Epitaxial wafer

Abstract

The present invention provides an epitaxial wafer which has a single crystal Si epitaxial layer (Si epitaxial layer) on a single crystal Si substrate. The Si epitaxial layer has a single crystal Si lattice spacing of 5.408 Å or less. A dopant in the single crystal Si substrate is diffused from the single crystal Si substrate into the Si epitaxial layer, while being reduced, and has a concentration profile locally higher on the Si epitaxial layer side than on the single crystal Si substrate side at the interface between the single crystal Si substrate and the Si epitaxial layer. The epitaxial wafer is a wafer for bonding. The Si epitaxial layer has a function as an etching stopping layer or a polishing stopping layer during thinning after bonding. Consequently, the present invention provides an epitaxial wafer which has a function as a stopping layer in an etching / polishing step during thinning after bonding especially in a silicon device manufacturing process.

Description

Epitaxial wafer

[0001] The present invention relates to an epitaxial wafer, and more particularly to an epitaxial wafer for fabricating a device having a junction structure.

[0002] In addition to miniaturization and structural changes (from planar to fin structures), wafer bonding has recently been used to improve device performance. For example, in the case of solid-state imaging devices, a wafer on which a photodiode is fabricated and a wafer on which a peripheral circuit is fabricated are separately prepared and then bonded together (Non-Patent Document 1). Furthermore, a structure has also been proposed and studied in recent years in which the power supply wiring, which was previously formed on the device surface via an insulating layer, is wired to a separate wafer and then bonded (Non-Patent Document 2).

[0003] In a bonded device in which wafers are bonded in this way, it is necessary to thin the wafers. To achieve this thinning with precision and without thickness variations, it is possible to provide an etching stop layer or to use SOI with a BOX film (oxide film) as the stop layer.

[0004] Among these, the use of SOI substrates has the advantage of good thickness uniformity and the presence of a BOX film, which acts as an effective stop layer. However, current 300 mm diameter SOI substrates are fabricated using a bonding method, which requires the use of two substrates. Therefore, using this SOI substrate requires the use of three or more wafers.

[0005] On the other hand, if a material or structure with a different etching rate is available, this layer can be used as an etching stop layer. Also, in thinning by CMP (Chemical Mechanical Polishing), the different etching rates are thought to make this layer effective as a polishing stop layer.

[0006] Based on this idea, it is conceivable to have layers of materials with different physical properties in the substrate (SOI with an oxide film is an example of this) or to grow layers with different resistances. However, simply growing layers with different resistances sequentially by epitaxial growth often results in a dull resistance profile, causing sagging and preventing the device from fulfilling its intended purpose.

[0007] For example, Patent Document 1 discloses a method for forming a gettering layer between a silicon wafer and an epitaxial film by adding carbon at a concentration of 1E18 to 1E20 atoms / cm. ３ and a method for producing an epitaxial wafer doped with the same carbon atoms. Patent Document 2 also describes that impurities segregate around and within carbon aggregates in a modified layer formed by implantation directly below an epitaxial layer, where the carbon is solid-dissolved. Another example (Patent Document 3) proposes a multilayer composite structure in which a silicon dioxide layer, a carbon-doped amorphous silicon layer in contact with the silicon dioxide layer, a dielectric layer in contact with the amorphous silicon layer, and a semiconductor element layer in contact with the dielectric layer are formed on the surface of a semiconductor substrate having a field resistivity of approximately 500 Ω cm.

[0008] JP 2013-051348 A JP 2018-142689 A JP 2017-526190 A

[0009] W. Hafez et. al. , “Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing”, Abst. of VLSI Symposium 2023, T6-1Y. Kikuchi et. al. , “Noise Performance Improvements of 2-Layer Transistor PixelStacked CMOS Image Sensor with Non-doped Pixel-FinFETs”, Abst. of VLSI Symposium 2023, T7-4

[0010] However, the techniques described in the above documents are insufficient in terms of the function as an etching stop layer and in terms of device fabrication.

[0011] The present invention has been made to solve the above problems, and an object of the present invention is to provide an epitaxial wafer that functions as a stop layer in the etching and polishing steps that are performed when thinning the wafer after bonding in the silicon device manufacturing process.

[0012] In order to achieve the above object, the present invention provides an epitaxial wafer having a single crystal silicon epitaxial layer on a single crystal silicon substrate, wherein the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less, and a dopant in the single crystal silicon substrate is diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer while decreasing in concentration, and has a concentration profile in which the dopant is locally higher on the single crystal silicon epitaxial layer side at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer than on the single crystal silicon substrate side, the epitaxial wafer being a wafer for bonding, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding.

[0013] Since the lattice spacing of the single crystal silicon in the single crystal silicon epitaxial layer is within the above-mentioned range, segregation can be achieved in the diffusion concentration profile of the dopant at the interface between the single crystal silicon epitaxial layer and the single crystal silicon substrate. Furthermore, such segregation can sharply change the dopant concentration at the interface. Therefore, the single crystal silicon epitaxial layer and the single crystal silicon substrate can have clearly different resistivities at the interface, making the single crystal silicon epitaxial layer an excellent stop layer for thinning. Furthermore, since the layer functioning as the etching stop layer or the like is a single crystal silicon epitaxial layer, this is particularly effective when a single crystal epitaxial layer for device fabrication is formed thereon. For example, in a layer formed by implantation of carbon ions rather than a single crystal silicon epitaxial layer as in the present invention, the ion implantation can cause damage to the crystal lattice and the generation of defects, which can adversely affect the device formation layer formed thereon. However, the present invention eliminates such concerns. Therefore, this epitaxial wafer is suitable for fabricating devices with junction structures, which are intended to be thinned by bonding. Moreover, the number of substrates required can be reduced compared to when the BOX layer of an SOI substrate is used as an etching stop layer, and the wafer can be fabricated relatively inexpensively.

[0014] In this case, the single crystal silicon epitaxial layer has a carbon concentration of 6×10 ２０ atoms / cm ３ That's it, 4 x 10 ２１ atoms / cm ３ It can be the following:

[0015] In this case, it is possible to more reliably increase the lattice strain while maintaining the single crystal structure, and it is possible to provide the above-mentioned dopant segregation.

[0016] The dopant in the single crystal silicon substrate may be boron.

[0017] Boron is a common dopant and is therefore convenient. + It may have a / p interface.

[0018] The epitaxial wafer of the present invention has an excellent function as an etching stop layer or a polishing stop layer, and can be used as an inexpensive and excellent bonding wafer that is also effective for device fabrication, and is therefore suitable for fabricating devices having a bonded structure.

[0019] 1 is a schematic diagram showing an example of an epitaxial wafer of the present invention. 2 is a graph showing an example of the relationship between the carbon concentration in single crystal silicon and the evaluation results of the lattice spacing by X-ray diffraction (XRD) and Vegard's law. Carbon concentration: 1E20 atoms / cm ３ 1 is a graph showing an example of a boron diffusion concentration profile in the case of carbon concentration: 3E20 atoms / cm ３ 1 is a graph showing an example of a boron diffusion concentration profile in the case of carbon concentration: 6E20 atoms / cm ３ 1 is a graph showing an example of a boron diffusion concentration profile in the case of carbon concentration: 8E20 atoms / cm ３ 10 is a graph showing an example of a diffusion concentration profile of boron in the case of

[0020] The present invention will be described in detail below with reference to the drawings as an example of an embodiment, but the present invention is not limited thereto. As mentioned above, there has been a demand for a bonding wafer having a layer that functions as an etching stop layer or the like and can be used for thinning, particularly for fabricating devices having a bonded structure. Therefore, the present inventors have conducted extensive research on such a bonding wafer.

[0021] For example, in Patent Document 1, sequential growth is performed using epitaxial technology, with a carbon-doped layer formed on a silicon substrate and an epitaxial layer formed on top of that. Patent Document 1 is also a gettering technology that originally focused on metals using carbon, but dopants such as boron are naturally also affected by this gettering layer, so for example, boron can be segregated to form a layer with a different resistivity and used as an etching stop layer. The carbon concentration in the carbon-doped layer at this time is 1E18 to 1E20 atoms / cm ３ However, as will be described later, in reality, the lattice constant of silicon hardly changes within this range, and the effect as an etching stop layer is insufficient.

[0022] Patent Document 2 describes a method for forming a gettering layer by implanting carbon through ion implantation. While metals are important targets for gettering, dopants such as boron are also affected by the gettering layer. Therefore, for example, boron can be segregated to form a layer with a different resistivity, which can be used as an etching stop layer. However, because this method relies on ion implantation technology, there are concerns about lattice damage and defect generation, even when the implanted species is carefully selected. These issues can adversely affect device fabrication.

[0023] In addition, in Patent Document 3, the layer is doped with carbon to form an amorphous layer. In this case, when sequential epitaxial growth is performed on a silicon substrate, for example, the presence of the amorphous layer poses a problem (issue) in that the layer grown thereon does not become single crystal.

[0024] The present inventors have identified these problems and conducted research to find a solution to the problem. As a result, they have conceived of an epitaxial wafer (having a silicon epitaxial layer on a single crystal silicon substrate) characterized in that (1) the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less, (2) dopants in the single crystal silicon substrate are diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer while decreasing, and have a concentration profile in which the dopant is locally higher on the single crystal silicon epitaxial layer side at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer than on the single crystal silicon substrate side, and (3) the epitaxial wafer is a wafer for bonding, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding. The present inventors have found that such a wafer can be an inexpensive and excellent wafer for bonding that has a good etching stop layer (or polishing stop layer) and has little adverse effect on device fabrication, and have completed the present invention.

[0025] That is, the present invention provides an epitaxial wafer having a single crystal silicon epitaxial layer on a single crystal silicon substrate, wherein the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less, and wherein a dopant in the single crystal silicon substrate is diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer while decreasing in concentration, and has a concentration profile in which the dopant is locally higher on the single crystal silicon epitaxial layer side at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer than on the single crystal silicon substrate side, the epitaxial wafer is a wafer to be bonded, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding.

[0026] An example of an epitaxial wafer of the present invention is shown in Figure 1. As shown in Figure 1, the epitaxial wafer 1 of the present invention is a wafer for bonding used in the fabrication of devices having bonded structures, and is intended to be thinned (by etching or polishing) after bonding. It is composed of a substrate 2, a first epitaxial layer (also referred to as a first EP layer) 3 on the substrate 2, and a second epitaxial layer (also referred to as a second EP layer) 4 on the first epitaxial layer 3.

[0027] Here, the substrate 2 is a single crystal silicon substrate. The substrate 2 is doped with a dopant. Here, an example is given in which the substrate 2 is doped with boron as the dopant (p-type), but this is not limiting. For example, the substrate 2 may be doped with Ga.

[0028] The first EP layer 3 is a single crystal silicon epitaxial layer. The lattice spacing (lattice constant) of the single crystal silicon in this first EP layer 3 is 5.408 Å or less. Compared to the lattice spacing of a typical single crystal silicon substrate, which is 5.43 Å, this is approximately 0.41% narrower (lattice distortion).

[0029] This lattice spacing can be evaluated by, for example, X-ray diffraction (XRD). An example of an apparatus that can be used for evaluation is the Smart Lab manufactured by Rigaku Corporation. Using this apparatus, the substrate was arranged in an out-of-plane configuration, and the lattice spacing (inter-lattice distance) was determined.

[0030] In order to generate the lattice distortion in the first EP layer 3, for example, a dopant (for lattice distortion) may be doped. Here, an example in which carbon is doped is given, but this is not limiting. Instead of carbon, another atom (e.g., Ge) may be doped as the dopant (for lattice distortion).

[0031] Here, the relationship between the concentration of carbon as a dopant (for lattice distortion) and the lattice spacing of single crystal silicon doped with that concentration of carbon is shown in Figure 2. More specifically, the lattice spacing at each carbon concentration in single crystal silicon doped with carbon at various concentrations was evaluated using X-ray diffraction (XRD) and Vegard's law. The plots in Figure 2 are the results of evaluation using XRD, and the dashed line graph is the result of evaluation using Vegard's law. Figure 2 also illustrates a range wider than the lattice spacing range in the present invention. Note that Vegard's law is an empirical rule that states that there is an approximate proportional relationship between the lattice constant of an alloy and the concentration of its constituent elements.

[0032] From this result, it is clear that the evaluation results of XRD and the evaluation results of Vegard's law are in good agreement, and the carbon concentration is 1E20 atoms / cm ３ It can be seen that the lattice spacing is affected only when the doping density exceeds 6E20 atoms / cm (the lattice spacing is about 5.425 to 5.428 Å). However, in the first EP layer 3 of the epitaxial wafer 1 of the present invention, 5.425 to 5.428 Å is insufficiently narrow, and as mentioned above, the lattice spacing must be 5.408 Å or less. In the case of carbon doping, the doping density is 6E20 atoms / cm. ３ By setting the doping concentration at or above, such a narrow lattice spacing can be achieved more reliably. Furthermore, although the lattice spacing narrows as the carbon concentration increases, in order to effectively prevent the carbon concentration from becoming too high and changing from single crystal to amorphous, in the present invention, the doping concentration is set to 4E21 atoms / cm. ３ The carbon concentration is preferably in the following range (lattice spacing is about 5.385 Å):

[0033] The agreement between the XRD evaluation results and the evaluation results according to Vegard's law suggests that carbon exists at substitutional sites in the single crystal silicon. In this regard, it has been confirmed separately by infrared absorption spectroscopy that carbon exists at substitutional sites.

[0034] 3-6 shows the actual boron concentration profile (diffusion from the substrate) of the epitaxial wafer obtained by varying the carbon concentration in the first EP layer 3. Here, a carbon-containing single crystal silicon epitaxial layer B was grown to a thickness of approximately 1 μm on a single crystal silicon substrate A, followed by epitaxial growth at 1050°C for another hour (single crystal silicon epitaxial layer C). The boron concentration of the epitaxial wafer from which the epitaxial layer C was removed was evaluated by secondary ion mass spectrometry (SIMS). The single crystal silicon epitaxial layer C was removed before evaluation in order to shorten the evaluation time by SIMS (and because the information of particular interest was near the interface between the single crystal silicon substrate A and the single crystal silicon epitaxial layer B).

[0035] The details of the single crystal silicon substrate A and the single crystal silicon epitaxial layers B and C are as follows: [Single crystal silicon substrate A] Boron-doped substrate: boron concentration is 7E14 atoms / cm ３ It is carbon-free and the carbon concentration is 7E15 atoms / cm ３ [Single crystal silicon epitaxial layer B] Carbon-doped layer: carbon concentration is 4 patterns (1E20 atoms / cm ３ ,3E20atoms / cm ３ ,6E20atoms / cm ３ ,8E20atoms / cm ３ ) [Single crystal silicon epitaxial layer C] Carbon non-doped layer

[0036] The apparatus used for the SIMS evaluation was a 7f manufactured by CAMECA Corp. Using this apparatus, the concentration profile of each element was measured from the surface of the sample to 2 μm.

[0037] 3 to 6, the carbon-doped region (single crystal silicon epitaxial layer B) extends from the surface to the dotted line (the interface between single crystal silicon epitaxial layer B and single crystal silicon substrate A) in the depth direction on the horizontal axis. The boron diffusion profile when no carbon is doped is also shown.

[0038] First, Figure 3 shows the carbon concentration of 1E20 atoms / cm ３ (From Fig. 2, the lattice spacing is about 5.425 to 5.428 Å), and Fig. 4 shows the carbon concentration of 3E20 atoms / cm ３ This is an example of the case where boron is diffused from the single crystal silicon substrate A into the single crystal silicon epitaxial layer B (carbon-doped layer) while decreasing in concentration (lattice spacing is approximately 5.418 to 5.42 Å). Overall, it can be seen that boron is being diffused from the single crystal silicon substrate A into the single crystal silicon epitaxial layer B (carbon-doped layer) while decreasing in concentration, but no segregation of boron is visible. All that can be seen is that boron is less diffused when the carbon is doped than when the carbon is not doped. Even near the interface, no significant change (sudden change) is observed in the concentration profile, and the concentration only decreases gradually toward the surface. Therefore, even if an etching process is performed from the single crystal silicon substrate A side toward the single crystal silicon epitaxial layer B side, no significant change in the etching rate at the interface is likely to occur, and the layer cannot fully function as an etching stop layer (or polishing stop layer).

[0039] Also, Figure 5 shows the carbon concentration of 6E20 atoms / cm ３ (lattice spacing is 5.408 Å), Fig. 6 shows the carbon concentration of 8E20 atoms / cm ３ (lattice spacing is 5.402 Å). These are examples of epitaxial wafers 1 of the present invention, with single crystal silicon substrate A corresponding to substrate 2 and single crystal silicon epitaxial layer B corresponding to first EP layer 3 (and single crystal silicon epitaxial layer C corresponding to second EP layer 4). In the case of these carbon concentrations, it is seen that boron is diffused from single crystal silicon substrate A into single crystal silicon epitaxial layer B (carbon-doped layer) while decreasing overall, but in the vicinity of the dotted line shown as the interface, the boron concentration on the carbon-doped layer side is locally higher than on the single crystal silicon substrate A side, and segregation is observed (the area indicated by the arrow in the graph).

[0040] Specifically, the combination of boron concentrations at the interface between the single crystal silicon epitaxial layer B (corresponding to the first EP layer 3) side and the single crystal silicon substrate A (corresponding to the substrate 2) side is 6.3E14 atoms / cm in FIG.３ / 1.9E14atoms / cm ３ and +4.4 Eatoms / cm across the interface. ３ The concentration difference is about 3.3 times higher. In Figure 6, the concentration is 6.4E14 atoms / cm ３ / 1.4E14atoms / cm ３ and +5.0E14 atoms / cm ３ The concentration difference is about 4.6 times higher.

[0041] In this way, by setting the lattice spacing of the single crystal silicon in the first EP layer 3 to 5.408 Å or less (in the case of carbon doping, 6E20 atoms / cm ３ At a carbon concentration of 0.1 or more, boron segregation as described above can be generated at the interface between the substrate 2 and the first EP layer 3. The presence of such segregation results in a sharp and clear change in resistivity across the interface. Therefore, when the epitaxial wafer 1 is bonded to another substrate or the like and a thinning process (etching or polishing) is performed from the substrate 2 side, the first EP layer 3 can fully fulfill its role (function) as an etching stop layer (or polishing stop layer).

[0042] Another advantage of the epitaxial wafer of the present invention is that it is inexpensive because fewer substrates are used than when, for example, the BOX layer of an SOI substrate is used as an etching stop layer.

[0043] Here, 6E20 atoms / cm ３ to 8E20 atoms / cm ３ However, the same function can be expected even when carbon is doped at a higher concentration. ３ The carbon concentration can be even higher, that is, 4E21 atoms / cm or more (lattice spacing is 5.393 to 5.402 Å or less), and even in this case, the function as an etching stop layer can be similarly effective. However, as mentioned above, the carbon concentration is 4E21 atoms / cm ３It is more preferable that the lattice spacing is about 5.385 Å or more.

[0044] The epitaxial wafer 1 of the present invention may include at least the substrate 2 and first EP layer 3 as described above. However, as shown in FIG. 1 , the second EP layer 4 may also be formed. This second EP layer 4 may be, for example, a single-crystal silicon epitaxial layer, and may be a layer on which devices are formed. Because the first EP layer 3 is a single-crystal silicon epitaxial layer, it is easy to form a good single-crystal epitaxial layer (second EP layer 4) of silicon or the like thereon. Therefore, this second EP layer 4 may be a layer suitable for device formation. In other words, the first EP layer 3 of the present invention has less (or significantly less) damage and defects to the crystal lattice than carbon-implanted layers (modified layers) formed in a substrate by ion implantation as in the prior art (e.g., Patent Document 2), and therefore can prevent adverse effects on device fabrication.

[0045] Furthermore, when formed by ion implantation, the film thickness is characterized by being very thin (for this reason, the modified layer in Patent Document 2 is evaluated using a 3D atom probe). On the other hand, the first EP layer 3 of the present invention can be easily adjusted to an appropriate thickness as an etching stop layer (or polishing stop layer) by adjusting the epitaxial growth time, etc. Therefore, the present invention is advantageous in this respect as well.

[0046] The epitaxial wafer 1 of the present invention and a device having a junction structure using the epitaxial wafer 1 can be manufactured, for example, as follows: First, a substrate 2 is prepared. For example, a single crystal silicon ingot manufactured by the CZ method or FZ method while doping with boron is sliced ​​with a wire saw, and the sliced ​​substrate is then subjected to grinding, lapping, etching, polishing, and other processes.

[0047] Then, a carbon-doped single-crystal silicon layer (first EP layer 3) is epitaxially grown using trimethylsilane, monomethylsilane, monosilane gas, or the like under reduced pressure in a low-pressure CVD apparatus. The temperature is not particularly limited, but deposition at a temperature in the range of 700°C to 900°C, preferably 730°C to 750°C, can result in an epitaxial layer with fewer defects. The carbon concentration is not particularly limited, but as mentioned above, it is controlled to an appropriate doping concentration so that the lattice spacing of the single-crystal silicon in the first EP layer 3 is 5.408 Å or less. In particular, a doping concentration of 6E20 atoms / cm is preferred. ３ Above, 4E21 atoms / cm ３ At this time, a boron diffusion concentration profile such as that shown in Figure 5-6 is obtained. That is, at the interface between the substrate 2 and the first EP layer 3, a high segregation of boron is obtained on the first EP layer 3 side, and the resistivity changes sharply across the interface.

[0048] Then, single crystal silicon not containing carbon is epitaxially grown on this (second EP layer 4), thereby completing the epitaxial wafer 1 of the present invention as shown in FIG.

[0049] Next, after forming desired devices on the second EP layer 4 of the epitaxial wafer 1 of the present invention, the epitaxial wafer 1 is bonded to another wafer on which devices and the like are formed to produce a bonded wafer. At this time, the second EP layer 4 side on which the devices are formed serves as the bonding surface.

[0050] Then, etching (or polishing) is performed on the bonded wafer from the substrate 2 (single crystal silicon substrate) side of the epitaxial wafer 1 portion to thin the surface. At this time, the etching (polishing) is performed while measuring the etching rate (polishing rate). The following describes an example of thinning by etching. Etching can be performed by wet etching, for example, and the etching solution for the substrate 2 (single crystal silicon substrate) can be a mixture of hydrofluoric acid and nitric acid, or an aqueous solution of sodium hydroxide or potassium hydroxide.

[0051] At this time, as shown in the boron diffusion concentration profile in Figure 5-6, the boron concentration in the substrate 2 near the interface with the first EP layer 3 gradually decreases toward the interface. Therefore, the etching rate in that region also gradually decreases toward the interface. Then, when the etching point reaches the interface, as described above, there is a sharp change in resistivity, and the resistivity increases rapidly, so the etching rate also increases rapidly. This change in etching rate indicates that the etching point has reached the interface, so the etching process is terminated at this point. In this way, the thinning process is completed, and a device having a junction structure can be fabricated.

[0052] The present invention will be described in more detail below with reference to examples of the present invention, but the present invention is not limited to these. (Example 1) Diameter 300 mm, (110) surface, boron doped (boron concentration: 7E14 atoms / cm ３ , carbon concentration: 7E15atoms / cm ３ A single crystal silicon substrate (substrate 2) having a resistivity of 10 Ω·cm was prepared. ４ ) and trimethylsilane gas (SiH(CH ３ ) ３ ) as a source gas, at a temperature of 700°C and a pressure of 10 Torr (1333 Pa), carbon was deposited on the single crystal silicon substrate at a density of 6E20 atoms / cm ３ A single crystal silicon epitaxial layer doped with a concentration of 1 μm was grown (first EP layer 3). ２ Cl ２ ) as a source material, silicon epitaxial growth was carried out at a temperature of 1050° C. for a growth time of 60 minutes (second EP layer 4). In this way, the epitaxial wafer of the present invention was manufactured.

[0053] Thereafter, the lattice spacing in the first EP layer 3 was evaluated by XRD, and the boron concentration was evaluated by SIMS. Since the purpose of this evaluation was to evaluate the substrate 2 and the first EP layer 3, the second EP layer 4 was removed by polishing before the evaluation in order to shorten the evaluation time. These evaluations were performed using the above-mentioned equipment.

[0054] As a result of the evaluation, the lattice spacing was found to be 5.408 .ANG.. Furthermore, a boron concentration profile similar to that in FIG. 5 was obtained, and boron segregation was confirmed on the first EP layer 3 side at the interface between the substrate 2 and the first EP layer 3.

[0055] (Example 2) The flow rate of trimethylsilane gas was changed to increase the carbon doping concentration in the first EP layer 3 to 8E20 atoms / cm ３ Except for this, an epitaxial wafer was manufactured and evaluated in the same manner as in Example 1. As a result of the evaluation, the lattice spacing was found to be 5.402 Å. In addition, a boron concentration profile similar to that shown in FIG. 6 was obtained, and boron segregation was confirmed on the first EP layer 3 side at the interface.

[0056] (Example 3) The flow rate of trimethylsilane gas was changed to dope carbon in the first EP layer 3 to 4E21 atoms / cm ３ Except for this, an epitaxial wafer was manufactured and evaluated in the same manner as in Example 1. As a result of the evaluation, the lattice spacing was found to be 5.385 Å. In addition, a boron concentration profile similar to that in Figures 5 and 6 was obtained, and boron segregation was confirmed on the first EP layer 3 side at the interface.

[0057] Comparative Example 1: A single crystal silicon substrate similar to that of Example 1 (boron concentration: 7E14 atoms / cm ３ , carbon concentration: 7E15atoms / cm ３) was prepared, and a single crystal silicon epitaxial layer was grown to a thickness of 1 μm in a low-pressure CVD apparatus at a temperature of 700°C and a pressure of 10 Torr (1333 Pa) using monosilane as the source gas. Next, as in Example 1, silicon epitaxial growth was performed using dichlorosilane gas as the source gas at a temperature of 1050°C for a growth time of 60 minutes. Thus, an epitaxial wafer was produced. Evaluation was then performed in the same manner as in Example 1. The evaluation revealed a lattice spacing of 5.43 Å. A boron concentration profile similar to that in Figure 3 was obtained, and no boron segregation was observed near the interface. The carbon concentration in the single crystal silicon epitaxial layer directly on the single crystal silicon substrate was 7E15 atoms / cm, the same as in the single crystal silicon substrate. ３ It was.

[0058] (Comparative Example 2) The flow rate of trimethylsilane gas was changed to increase the carbon doping concentration in the single crystal silicon epitaxial layer directly above the single crystal silicon substrate to 3E20 atoms / cm ３ Except for this, epitaxial wafers were manufactured and evaluated in the same manner as in Example 1. As a result of the evaluation, the lattice spacing was found to be 5.42 Å. In addition, a boron concentration profile similar to that shown in FIG. 4 was obtained, and no boron segregation was confirmed near the interface.

[0059] Furthermore, the epitaxial wafers (single crystal silicon substrate + single crystal silicon epitaxial layer + single crystal silicon epitaxial layer) produced in Examples 1-3 and Comparative Examples 1 and 2 were bonded to another wafer to produce a bonded wafer, which was then subjected to an etching process to attempt thinning. In the cases where the epitaxial wafers of Examples 1-3 were used, the etching rate began to gradually decrease as the etching process progressed, but there was a point where it suddenly increased. Therefore, the etching process was terminated at that point, assuming that the etching process had reached the interface. This enabled the production of bonded wafers that had been thinned using the carbon-doped layer as an etching stop layer. On the other hand, in the cases where the epitaxial wafers of Comparative Examples 1 and 2 were used, the etching rate continued to gradually decrease, and the interface could not be found, so the etching process was terminated midway.

[0060] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and that provides similar effects is included within the technical scope of the present invention.

Claims

1. An epitaxial wafer having a single crystal silicon epitaxial layer on a single crystal silicon substrate, wherein the single crystal silicon epitaxial layer has a single crystal silicon lattice spacing of 5.408 Å or less, and wherein dopants in the single crystal silicon substrate are diffused from the single crystal silicon substrate into the single crystal silicon epitaxial layer while decreasing in concentration, and wherein the dopant has a concentration profile at the interface between the single crystal silicon substrate and the single crystal silicon epitaxial layer such that the dopant is locally higher on the single crystal silicon epitaxial layer side than on the single crystal silicon substrate side, and wherein the epitaxial wafer is a wafer for bonding, and the single crystal silicon epitaxial layer functions as an etching stop layer or a polishing stop layer in thinning after bonding.

2. The single crystal silicon epitaxial layer has a carbon concentration of 6×10 ２０ atoms / cm ３ That's it, 4 x 10 ２１ atoms / cm ３ 2. The epitaxial wafer according to claim 1, wherein:

3. The epitaxial wafer according to claim 1 or 2, wherein the dopant in the single crystal silicon substrate is boron.

Images