Mask liner

Abstract

Methods and apparatus are provided for etching features in a substrate used in fabricating an electronic device. The substrate includes at least one layer of a material to be etched and a mask having a plurality of openings in a layer of mask material and a mask sidewall liner comprising a liner material on sidewalls of the openings in the layer of mask material. Compared to the mask material, the liner material as a greater etch selectivity with respect to the material to be etched under plasma etch conditions.

Description

Docket No. LAM1P059WO MASK LINER INCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes. BACKGROUND

[0002] In semiconductor fabrication, the miniaturization of feature size is a continuously driving challenge that impacts dry etch processes, such as processes that form high aspect ratio (HAR) features. Such features are commonly used in memory device fabrication such as DRAM capacitor fabrication and 3D NAND contacts.

[0003] The background provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background or presented as contextual information in the description, that may not otherwise qualify as prior art at the time of filing, is neither expressly nor impliedly admitted as prior art against the present disclosure. SUMMARY

[0004] One general aspect includes a method of etching features in a substrate used in fabricating an electronic device. The method includes (a) providing a substrate to an etch chamber, where the substrate may include at least one layer of material to be etched and a mask over at least one layer, where the mask includes (i) a layer of mask material, (ii) a plurality of openings in the layer of mask materials, and (iii) a mask sidewall liner comprising a liner material on sidewalls of the openings in the layer of mask material. The method further includes (b) etching the features in at least one layer, through the openings in the layer of mask material, by exposing the substrate to plasma etch conditions, where compared to the mask material, the liner material has a greater etch selectivity with respect to the material to be etched under the plasma conditions.

[0005] In some embodiments, one or more layers, together, form a mold stack.

[0006] In some embodiments, the method includes forming the mask sidewall liner on the sidewalls of the openings in the layer of mask material prior to (a). In some implementations,Docket No. LAM1P059WO forming sidewall liner includes (i) conformally depositing a layer of the liner material on the layer of mask material, including the plurality of openings, and (ii) removing substantially all the liner material at the bottoms of the plurality of openings.

[0007] In some embodiments, removing substantially all the liner material at the bottoms of the plurality of openings involves performing an anisotropic etch that exposes at least one layer of material to be etched.

[0008] In some embodiments, (i) conformally depositing the layer of the liner material on the layer of mask material and (ii) removing substantially all the liner material at the bottoms of the plurality of openings are performed in the same tool. In some embodiments, conformally depositing the layer of liner operation and the etching of the feature operations are performed in an etch chamber.

[0009] In some embodiments, the liner materials include a metal-organic composite, a metal- containing carbon, a metal carbide, a metal oxide, a silicide, a metal nitride, or any combination thereof.

[0010] In some embodiments, mask materials include amorphous carbon, polysilicon, metal- doped carbon, or any combination thereof, where the substrate includes a dielectric material.

[0011] In some embodiments, the plurality of openings in the layer of mask material is wider than a critical dimension (CD) of the features by approximately 2 times the thickness of the mask sidewall liner. In some cases, the thickness of the mask sidewall liner is about 1 nm to 10 nm.

[0012] In some embodiments, the method further involves, prior to forming the plurality of openings in the mask layer, forming a top mask layer over the mask; creating a plurality of top mask openings, which aligns with the plurality of openings in the layer of mask material, which the plurality of openings have not yet been formed; and forming a top mask liner on the sidewalls of the plurality of top mask openings. In some embodiments, the method further includes etching the plurality of openings in the layer of mask material, through the plurality of top mask openings.

[0013] In some embodiments, the top masks include silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

[0014] In some embodiments, etching the feature involves exposing the substrate to a plasma generated by a transformer-coupled plasma (TCP) power source.

[0015] In some embodiments, the plasma etch conditions include supplying the etch chamber with an etchant gas, which includes a fluorine-containing component and / ora chlorine- containing component, along with a carbon-containing component. In some implementations,Docket No. LAM1P059WO the fluorine-containing component includes HF, NF3, CF4, PF3, PF5, ClF3, ClF, IF7, SF6, SiF4, WF6, MoF6, RuF6, or any combination thereof. In some embodiments, the carbon-containing component includes a hydrocarbon and / or a hydrofluorocarbon. In some embodiments, the chlorine-containing component includes Cl2, BCl3, HCl, SiCl4, SiH2Cl2, SiHCl3, SiH3Cl or any combination thereof.

[0016] In some embodiments, plasma etch conditions involve an etch chamber having a pressure of about 2 to 400 mTorr. In some embodiments, plasma etch conditions involve a substrate having a temperature of about -100°C to 200°C.

[0017] In some embodiments, the feature has an aspect ratio of at least about 10:1, or at least 100:1.

[0018] In some embodiments, the features are at locations of capacitors or contacts for a memory device.

[0019] One general aspect includes an apparatus for etching features in a substrate. The apparatus may include an etch chamber configured to receive a substrate including at least one layer to be etched and a mask material above at least one layer; a plasma power source for providing plasma in the etch chamber; one or more gas inlets for providing an etchant gas and liner precursor to the etch chamber; a substrate support for supporting a substrate, where the substrate support includes or is associated with an electrode configured to provide a bias voltage to the substrate; and a controller configured to cause (a) forming a plurality of openings in the layer of mask material, (b) forming a mask sidewall liner on sidewalls of the openings in the layer of mask material, and (c) etching the features in at least one layer, through the openings in the layer of mask material by exposing the substrate to a plasm etch conditions. In some implementations, the apparatus further includes a plasma power source that may be a transformer coupled plasma (TCP) power source.

[0020] In some embodiments, at least one layer for the apparatus includes a dielectric material where the layer of mask material includes carbon or polysilicon.

[0021] In some embodiments, at least one layer comprises a primary mask layer, and the feature includes openings in the primary mask layer. In some embodiments, the layer of mask material includes a silicon nitride, a silicon oxide, a silicon oxynitride, or any combination thereof.

[0022] In some implementations, the controller in the apparatus is further configured to cause forming a liner on the sidewalls of the openings in the layer of mask material by causing (i) conformally depositing a layer of liner material on the layer of mask material, including the plurality of openings, and (ii) removing substantially all the liner material at the bottoms of theDocket No. LAM1P059WO plurality of openings. In some embodiments, (ii) involves performing an anisotropic etch that exposes at least one layer of the material to be etched. In some embodiments, (i) involves depositing the liner material where the liner material includes a metal-organic composite, a metal-containing carbon, a metal carbide, a metal oxide, a silicide, a metal nitride, or any combination thereof.

[0023] In some embodiments, the mask material includes amorphous carbon, polysilicon, metal-doped carbon, or any combination thereof, and where the substrate includes a dielectric material.

[0024] In some embodiments, the controller of the apparatus is configured to form a plurality of openings in the layer of mask material that is wider than the critical dimension (CD) of the features by approximately 2 times the thickness of the mask sidewall liner. In some embodiments, the thickness of the mask sidewall liner is about 1 nm to 10 nm.

[0025] In some embodiments, the controller of the apparatus is configured to cause plasma etch conditions where the plasma etch conditions involve supplying the etch chamber with an etchant gas, including a fluorine-containing component and a carbon-containing component. In some embodiments, plasma etch conditions involve etch chamber pressure of about 2 to 400 mTorr. In some embodiments, plasma etch conditions involve substrate temperature of about - 100°C to 200°C.

[0026] Any combination of the features mentioned in this section may be implemented together in the methods of this disclosure.

[0027] These and other features of the disclosure will be presented below, sometimes with reference to drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 illustrates an example of a patterned substrate with HAR features with a plurality of feature openings that can be etched according to certain embodiments.

[0029] Figures 2A – 2D illustrate example operations for etching the HAR features on a substrate having a mask layer. The sidewall profile exhibits CD expansion and bowCD.

[0030] Figure 2E shows a flow chart illustrating example operations for etching high aspect ratio features where etching is performed while applying sidewall passivation conditions, according to certain embodiments.

[0031] Figures 3A – 3D display schematic illustrations of a HAR feature etch process that involves forming a liner on a substrate having at least one layer of mask material.

[0032] Figure 3E provides a flow chart illustrating example operations in a high aspect ratioDocket No. LAM1P059WO etch process that involves forming a liner layer on a mask.

[0033] Figures 4A – 4E show schematic illustrations of the HAR feature etch process, which involves forming a liner layer on a substrate with two layers of mask material (top mask layer and primary mask layer).

[0034] Figure 4F depicts a process flow diagram illustrating example operations in a high aspect ratio etch process that involves two or more mask layers (e.g., a top mask layer and a primary mask layer) and forming a liner layer on a top mask layer.

[0035] Figure 5 presents a block diagram of an etch apparatus that may be used to etch HAR features.

[0036] Figure 6 presents a block diagram of a system including an etch apparatus. DETAILED DESCRIPTION Introduction and Context

[0037] Currently, high aspect ratio (HAR) etching of dielectric layers for forming contact molds, capacitor molds, etc., is conducted using a high-density carbon mask, boron or metal- doped carbon mask, or a polysilicon mask. The pattern on such mask is transferred to the dielectric layer(s) below. At least partly due to limited mask-substrate etch selectivity for HAR etching, the produces a faceted top on the mask. As a consequence, ions impinging on the faceted top scatter toward the substrate sidewalls, thereby inducing a bowed feature profile shape. The increased feature diameter due to such bowing is sometimes referred to as bow CD. Existing techniques of reducing bow CD include (a) modifying the dielectric etch conditions or etch process to partially passivate the feature sidewall using an ex-situ or in-situ formed “liner,” or (b) using a metal-doped mask to enhance etch selectivity. These approaches introduce limitations or tradeoffs such as bow CD reduction versus the bottom of the feature being unopened or feature shape twisting, etc. These approaches also lengthen the etch process time.

[0038] Current HAR etching of conductors such as carbon also introduces a passivation layer, such as a soft silicon oxide film, during etching, for bow protection. This passivation introduces similar tradeoffs regarding feature shape / profile and long etch process time.

[0039] Certain etch processes described herein may address one or more of the issues of current HAR etch technology. Certain etch processes described herein provide new ways to conduct HAR etching when fabricating 3DNAND, DRAM, or similar devices. The disclosed etch processes may minimize bow CD and provide high selectivity. In certain embodiments, the etch process employs a low sputtering yield hard film liner on mask sidewalls. In someDocket No. LAM1P059WO implementations, such sidewall liner is prepared after a mask open process, before HAR etching. The liner may be formed in many different ways, such as (a) ex-situ using a deposition tool, or (b) in-situ, post mask open, using an etch tool. If the liner is formed by conformal deposition, such deposition may be followed by a process to open the etch front of the underlying substrate layers by performing a punch etch of the bottom of the liner layer.

[0040] Liners may be applied to mask sidewalls in essentially any HAR etch process. For example, they may be applied to sidewalls of masks used to etch features non-mask, substrate layers such as dielectric layers used in memory device molds. Also, they may be applied to the sidewalls of top masks that are used to define the pattern in a primary mask such as a high- density carbon mask used in fabricating memory devices.

[0041] The HAR etch processes described herein may provide any one or more improvements over existing processes. For example, using a mask with a mask sidewall liner may significantly reduce the cost compared to using a metal-doped mask. Such processes also or alternatively enable HAR etching with reduced bow CD and deeper etch features with straighter profiles.

[0042] Generally, the HAR etch process may be used to create “features” such as trenches, vias, and other holes or openings, which may be characterized by their critical dimensions (CDs), sidewall profiles, aspect ratios, etc. The feature(s) may be formed on a substrate having one or more layer(s) thereon. The substrate may be a silicon wafer, e.g., a 200-mm wafer or a 300-mm wafer, which may have one or more layer(s) of material, such as dielectric, conducting, or semiconducting material deposited thereon. One example of a feature is a capacitor mold or contact hold in one or more layers disposed on a substrate.

[0043] An HAR etch process creates an etch pattern on a substrate such that a plurality of features is formed on the substrate. Figure 1 depicts an example of a patterned substrate 100 having a layer of substrate 103 (e.g., a dielectric layer) and a plurality of etched features 105 such as capacitor molds, vias, or other recessed features as described above. As depicted in Figure 1, the patterned substrate 100 may have a plurality of feature openings when viewed from or near the feature opening.

[0044] In some embodiments, the HAR features may be etched on a substrate that includes one or more layers, such as dielectric layers to be etched and one or more mask layers that define the pattern to be etched. Figure 2A illustrates the initial substrate stack 210 having blanket layers of primary mask materials on a substrate. As depicted in Figure 2A, stack 210 may include one or more mask layers, such as a top mask layer 211, a primary mask layer 213, and a substrate layer 215 to be etched. As shown, substrate layer 215 may have a primary maskDocket No. LAM1P059WO layer 213 disposed thereon and a top mask layer 211 provided on the primary mask layer 213.

[0045] In some cases, the substrate 215 may be a mold stack having one or more layers, such as that one or more dielectric layers. As examples, and further discussed below, the dielectric layer(s) may comprise silicon nitride and / or silicon oxide, or alternating layers of oxides and nitrides (ONON). In some embodiments, the primary mask layer 213 may be a conductive layer, e.g., a carbon-containing layer or a metal-doped layer. In some cases, the primary mask layer 213 may be a high-density carbon. In some embodiments, the top mask layer 211 may be a dielectric material, e.g., silicon oxide, silicon nitride, and silicon oxynitride.

[0046] As illustrated in Figure 2B, the top mask layer 211 may be developed, etched, or otherwise opened to form a pattern on the top mask layer 211. The process of forming a pattern on the mask layer is referred to as “mask open.” Utilizing the patterned top mask layer 211, the pattern is transferred to the underlying primary mask layer 213. To transfer the pattern, the primary mask layer 213 may be etched (a separate mask open operation). In some embodiments, the mask opening of the top mask layer 211 may be performed in a dielectric etch apparatus, or any other suitable etch apparatus.

[0047] In some cases, due to the limited mask-substrate etch selectivity for the HAR etching, mask-opening processes can create a faceted top on the mask. The faceted top may contribute to the scattering of the ions towards the substrate sidewalls during the etching process and creating a bowed feature profile, increasing the feature diameter. This is depicted in Figure 2C, where the mask opening of the top mask layer 211 has faceting 221. As a result, the upper portion of the mask opening of the primary mask layer 213 can have a bowed profile 223 in the primary mask layer 213 and / or a tapering 225 of the sidewalls of a feature. In some embodiments, the mask opening of the primary mask layer 213 is performed in a conductor etch apparatus, although any suitable apparatus may be used to etch the primary mask layer 213.

[0048] As shown in Figure 2D, the pattern of primary mask layer 213 is transferred or etched on the substrate layer 215 below. The substrate 215 may be etched in a dielectric etch apparatus, but any other suitable apparatus may be used. In some embodiments, the top mask layer 211 is removed or etched during this operation, and the primary mask layer 213 may exhibit faceting 231 due to the limited selectivity of the HAR etching process. In some cases, the faceting and / or bowed profile of the primary mask layer 213 is at least partially responsible for sidewall bowing, tapering, and / or other issues with features etched in substrate layer 215. As illustrated in Figure 2D, the HAR etch process introduces a bowed feature 233 and a tapered sidewall 235 profile shape in the substrate layer 215. In addition, features in the underlying substrate layerDocket No. LAM1P059WO 215 may be etched to a non-uniform depth. Current processes to address bow CD and sidewall taper frequently introduce other issues, such as twisting of the feature profile, undesired nucleation 217 on the feature sidewalls, and clogging the feature opening.

[0049] In certain conventionally employed embodiments, a high aspect ratio feature(s) may be etched in accordance with the process and operation illustrated in Figure 2E. Figure 2E depicts a process flow diagram illustrating example operations in a high aspect ratio etch process 200. The process 200 for etching a high aspect ratio feature(s) begins with an operation 201, which involves receiving a substrate having one or more layer(s) to be etched. The substrate may have a mask layer deposited over the layer(s) to be etched. In some embodiments, the substrate may have a top mask layer, a primary mask layer underlying the top mask layer, and a substrate layer to be etched. An example of such a substrate is illustrated in Figure 2A. The various layers of the substrate may be formed in various deposition apparatuses. In some embodiments, a deposition apparatus may be used to deposit various layers on the substrate. In some embodiments, the substrate layer(s) may be at least about 3 microns thick, at least about 7 microns thick, or at least about 10 microns thick. In some embodiments, the thickness of the mask layer(s) may be at least about 25%, at least about 30%, at least about 40%, at least about 50%, or at least about 60% of the thickness of the substrate layer(s) to be etched. In some embodiments, mask layer(s) may include a dielectric material such as silicon nitride or silicon oxide, or a conductive material such as carbon or doped metal.

[0050] In an operation 203, a mask-open operation is performed to define an etched pattern on the mask layer. In some embodiments, operation 203 involves one or more mask-open operations, depending on the number of mask layers in a substrate stack. For example, a substrate stack having two mask layers (e.g., a top mask layer and a primary mask layer, as depicted in Figure 2A) may have two mask-open operations. The first mask opening may be performed to define a pattern on the top mask layer. The second mask opening may be performed to transfer the pattern on the top mask layer to the underlying primary mask layer. In various implementations, in operation 203, bowed feature profiles and faceting may occur in the primary mask layer during the operation. In some embodiments, operation 203 may form a feature having a critical dimension at or near the feature bottom at least about 50 nm, at least about 70 nm, or at least about 100 nm. In some embodiments, operation 203 may form a feature having a feature depth of at least about 2 microns, at least about 3 microns, or at least about 7 microns.

[0051] In an operation 205, one or more layer(s) is etched through the mask pattern. The substrate having one or more layer(s) to be etched may be a mold stack, which may beDocket No. LAM1P059WO alternating layers of dielectric materials such as oxides, nitrides, or oxynitrides. The oxides may be silicon oxide, nitride may be silicon nitride, and oxynitrides may be silicon oxynitride. Operation 205 may be performed under the sidewall passivation conditions. For example, operation 205 may be performed where a metal precursor and / or a fluorocarbon is incorporated during the etch process. In some cases, the sidewall passivation involves forming a protective layer of metal deposit, which assists in maintaining the feature profile of the mask layers when etching the substrates. In some embodiments, the deposited passivation layer may not be conformal, or deposits unwanted passivation material at or near the etch front or opening, which can lead to various issues such as feature twisting, feature blocking, capping, etc. Liner-based HAR Etch Processes

[0052] In some embodiments, the HAR etch involves forming a liner layer on a mask. Figures 3A – 3D provide schematic illustrations of a HAR feature etch process that involves forming a liner on a substrate having at least one layer of mask material. As depicted in Figure 3A, a substrate 300 having at least one layer of material to be etched 320 and a mask 310 over the layer of material to be etched 320. As shown in Figure 3A, mask 310 may have a plurality of openings 312 in the layer of mask material used to form mask 310. The plurality of openings on mask 310 may be formed by any suitable mask opening process. In some embodiments, openings in mask 310 have a larger dimension, or feature width, compared to the target feature dimensions of an underlying layer 320. The mask layer may be deposited in any suitable deposition apparatus, and the dielectric etch tool may be used to form a pattern or plurality of feature openings on mask 310.

[0053] As depicted in Figure 3B, a layer of liner 330 is deposited on the horizontal surfaces and the sidewalls of mask 310. The layer of liner 330 may be conformally deposited in any suitable deposition tool. For example, the thickness of the liner 330 deposited on the horizontal surface may be substantially the same as the width of the liner 330 layer on the sidewalls of the feature. In various implementations, liner layer 330 material is a ‘hard’ material and has an etch selectivity such that underlying material 310 is selectively etched while the liner layer 330 material is not (or substantially less) etched.

[0054] As depicted in Figure 3C, the horizontal portions of the liner 330 may be removed without completely removing the liner 330 from the sidewalls. Removing liner material from horizontal surfaces, particularly at the bottom of the openings, without completely removing the liner from the sidewalls is referred to as “punch through.” In some embodiments, the liner 330 is etched in a conductor etch apparatus or any other suitable apparatus. The resulting openings 314, in which the openings in patterned mask 310 are narrowed by liner layer 330Docket No. LAM1P059WO have a CD that meets the target specification for the etch process.

[0055] As shown in Figure 3D, layer 320 may be etched through the patterned mask 310 and the liner 330 to form a plurality of features in layer 320. In various embodiments, layer 320 may have one or more layers of a dielectric material. In various embodiments, the etched feature in layer 320 may have reduced or eliminated bow CD and reduced or eliminated taper of the sidewalls. Moreover, the etched feature may have a more uniform feature depth across the different features. In various implementations, due to the high selectivity of liner 330 (vis- à-vis the material of layer 320), liner 330 materials remain largely intact during the etch process that forms features in layer 320.

[0056] In some embodiments, a high aspect ratio feature(s) may be etched in accordance with the process and operation illustrated in Figure 3E. Figure 3E depicts a process flow diagram illustrating example operations in a high aspect ratio etch process 350 that involves forming a liner layer on a mask. The process 350 for etching a high aspect ratio feature(s) begins with an operation 351. Operation 351 involves receiving a substrate having one or more layer(s) to be etched. The substrate has a mask layer over the layer(s) to be etched. In some embodiments, the mask layer deposited over the layer(s) to be etched is a primary mask layer.

[0057] In an operation 353, a mask-open operation is performed to define an etched pattern comprising a plurality of openings in the layer of mask material. In various embodiments, mask-opening in operation 353 forms mask openings that are wider than the target width of the feature to be etched in an underlying layer. For example, mask opening operation 353 may form mask openings that are wider than the mask opening that may have been formed during operation 203 in Figure 2E. In some embodiments, operations 351 and 353 are performed in the same apparatus or tool, which may be a deposition and / or etch tool.

[0058] In an operation 355, a mask sidewall liner layer is deposited. As illustrated in Figure 3B, the mask sidewall liner layer may be conformal with the topology of an underlying mask layer. In some embodiments, the mask sidewall liner layer is formed by depositing a conformal layer of the liner material on the layer of mask materials, including the plurality of openings, where the liner material may be deposited on the horizontal surfaces and sidewalls of the mask material having a plurality of openings. In some embodiments, liner material has a thickness of about 1-10 nm (i.e., reducing the critical dimension of the openings by about 2-20nm).

[0059] In an operation 357, the bottom of the liner layer is removed while leaving a liner on the sidewalls of the mask opening. As mentioned in the discussion of Figure 3C, the operation 357 is sometimes referred to as a “punch through” operation. In some embodiments, substantially all of the liner material at the bottoms of the plurality of openings is removed. ToDocket No. LAM1P059WO form the sidewall liners, liner material is removed from the horizontal surfaces without completely removing the liner material from the sidewalls of the mask material. In some embodiments, removing substantially all the liner material at the bottom of the plurality of mask openings involves performing an anisotropic etch that exposes at least one layer to be etched at the bottoms of the mask openings. In some embodiments, operations 355 and 357 are performed in the same chamber (e.g., the same conductor etch chamber).

[0060] In an operation 359, one or more layer(s) of material underlying the mask with liners are etched. In some embodiments, operation 359 involves etching the features in at least one layer through the openings in the layer of mask material by exposing the substrate to plasma etch conditions. In some embodiments, operation 359, etching is performed without applying sidewall passivation conditions. In various implementations, compared to the mask material, the liner material has a greater etch selectivity with respect to the material to be etched under the plasma etch conditions. Additional details of the plasma etch conditions are provided herein.

[0061] An example of a liner-based etch application is a mold etch process that uses a high- density carbon, doped carbon, or polysilicon mask, but with mask open critical dimension (CD) increased by about 2 to 30 nanometers. After the mask open operation, the process deposits a conformal liner material, which is more resistant to etching (e.g., harder) than the primary mask material. The liner coats the feature mask sidewall to a thickness of, e.g., about 2 to 10 nanometers. This reduces the mask open CD to the desired size for the pattern to be etched. Due to its low sputtering yield and chemical resistance, the mask sidewall liner material protects the primary mask material and resists faceting. The reduced faceting and ion scattering from the mask may also reduce the bow CD in the subsequent dielectric HAR etch. The liner may also improve overall mask selectivity. In some implementations, the liner is conformally deposited in-situ in a mask open etch tool (e.g., a conductor etch tool) after the mask open process. As an example, the process flow may include the following operations: mask open -> in-situ deposition of liner -> liner bottom punch through to open up an etch front. Each of these operations may be performed in a mask open tool. In another implementation, the liner deposition and the punch through are performed before an HAR dielectric etch in the dielectric etch chamber.

[0062] In some embodiments, the HAR etch employs two or more mask layers and forming a liner layer on at least one of these mask layers. Figures 4A – 4E show schematic illustrations of the HAR feature etch process that involves forming a liner layer on a substrate having two layers of mask material. As depicted in Figure 4A, a substrate 400 having at least one layer ofDocket No. LAM1P059WO material to be etched 412 and two mask layers, such as a primary mask layer 411 over the layer(s) of material to be etched 412 and a top mask layer 410 over the primary mask layer 411. As shown in Figure 4A, the top mask 410 has a plurality of openings 422 in the layer of top mask material 410. In some embodiments, the plurality of openings on the top mask 410 is formed by any suitable mask opening process. In some embodiments, openings 422 in the top mask 410 have a larger critical dimension or feature width compared to the target feature dimensions of any underlying primary mask layer 411 and / or the layers of substrates to be etched 412. The mask layers (top mask layer 410 and the primary mask layer 411) may be deposited in any suitable deposition apparatus, and the dielectric etch apparatus or tool may be used to form a pattern or plurality of feature openings on the top mask layer 410.

[0063] As depicted in Figure 4B, a layer of liner 413 is deposited on the horizontal surfaces and the sidewalls of the top mask 410. The layer of liner 413 may be deposited in any suitable deposition apparatus, and the deposited layer of liner 413 material may be conformal. For example, the thickness of the liner 413 deposited on the horizontal surfaces may be substantially the same as the width of the liner 413 layer on the sidewalls of the feature. As with layer 330 in the embodiment of Figure 3B, the liner material may be ‘hard’ with respect to the material of top mask 410. Hence, the etch of selectivity with respect to an underlying material to be etched is greater for the material of liner layer 413 than for the material of top mask 410. Thus, the etch selectivity of the liner material is such that the underlying material of mask 411 may be etched while the liner layer 413 material is substantially unetched.

[0064] As depicted in Figure 4C, the horizontal portions of the liner 413 are removed without completely removing the liner 413 from the sidewalls, i.e., punched through to remove the liner 413 material at the bottom of the plurality of openings 422 by performing an anisotropic etch process that exposes the top of primary mask layer 411. In some embodiments, the punch- through is performed in a conductor etch apparatus, but any other suitable apparatus may be used. Resulting “lined” openings 424 have a CD suitable for holes to be formed in the primary mask layer 411.

[0065] As shown in Figure 4D, the primary mask layer 411 is etched through the patterned top mask layer 410 and the liner 413 on the sidewalls of the top mask layer 410 to form a plurality of features (openings) in the underlying primary mask layer 411. In various embodiments, the etched feature in the primary mask layer 411 has reduced bow CD and / or reduced sidewall taper. In various implementations due to the high selectivity of the material of liner 413 with respect to the material of primary mask layer 411, liner 413 material remains largely intact during the etch process that forms an opening pattern in the primary mask layer 411.Docket No. LAM1P059WO

[0066] As depicted in Figure 4E, the underlying layer 412 is etched through the patterned primary mask layer 411 to form a plurality of features in layer 412. In various embodiments, the etched features in substrate layer 412 have reduced bow CD and / or reduced sidewall taper as a result of the relatively straight sidewall profile in the mask layer 411, which may be attributed to the use of liner 413. Moreover, the etched features in the mask layer 411 may have a more uniform feature depth across the different features. In general, the top mask layer and liner material (i.e., 410 and 413, respectively) are removed before etching the underlying layer 412. The top mask layer 410 and liner material 413 may be removed via a suitable wet etch process. In some embodiments, the top mask layer 410 and liner material 413 are removed in a tool that etches the primary mask layer 411.

[0067] In general, the same overall liner-based process sequences and tool choices that were described for etching the substrate layer(s) (e.g., a memory device mold stack) may also apply for etching the primary mask (e.g., etching a carbon hard mask). For example, the process may be applied to etch a carbon or polysilicon HAR mask. A top mask to etch a primary mask may contain, e.g., a silicon oxynitride (SION), as silicon oxide, or silicon nitride. A layer of such material, disposed over a high-density carbon layer, may be etched to define a mask pattern, but a suitable hard liner may be applied to the sidewalls of the top mask to minimize facet, reduce hole size, reduce bow CD (in features of the underlying carbon mask), and / or increase mask selectivity in the SION / oxide / nitride mask.

[0068] When two or more mask layers are present, a high aspect ratio feature(s) may be etched in accordance with the process and operations illustrated in Figure 4F. Figure 4F depicts a process flow diagram illustrating example operations in a high aspect ratio etch process 450 that involves two or more mask layers (e.g., a top mask layer and a primary mask layer) forming a liner layer on a top mask layer. The process 450 begins with an operation 451 that involves receiving a substrate having one or more layer(s) to be etched. The substrate also has two or more mask layer(s) over the layer(s) to be etched, including a top mask layer over at least one other mask layer.

[0069] In an operation 452, a mask-open operation is performed to define an etched pattern on the top mask layer. Operation 452 may form a plurality of openings in the top mask layer. In various embodiments, mask-opening operation in 452 forms mask openings that are wider than the target width of the feature to be etched in an underlying mask layer(s) and layer(s) to be etched. In some embodiments, operations 451 and 452 are performed in an etching tool such as a dielectric etching tool.

[0070] In an operation 453, a mask sidewall liner layer is deposited over the patterned top maskDocket No. LAM1P059WO layer. In various embodiments, the top mask sidewall liner layer is conformally deposited. In some embodiments, the mask sidewall liner layer is formed by depositing a conformal layer of the liner material on the layer of top mask material, including the plurality of openings, where the liner material may be deposited on the horizontal surfaces and sidewalls of the top mask material having a plurality of openings. In some embodiments, liner material has a thickness of about 1 to 20 nm (e.g., about 5 to 20 nm or about 10 nm in thickness).

[0071] In an operation 454, which is a punch through operation, the bottom of the sidewall liner layer is removed while leaving the liner on the sidewalls of the mask openings. In some embodiments, substantially all of the liner material at the bottoms of the plurality of openings is removed. The liner material is removed from the horizontal surfaces without completely removing the liner material from the sidewalls of the mask material. In some embodiments, removing substantially all the liner material at the bottom of the plurality of openings involves performing an anisotropic etch that exposes at least one layer to be etched. In some embodiments, operations 453 and 454 are performed in the same chamber (e.g., the same conductor etch chamber). In some embodiments, operation 453 is performed in a deposition tool, and operation 454 is performed in an etch tool.

[0072] In an operation 455, the primary mask layer(s) is etched. In some embodiments, operation 455 involves etching the feature in at least one layer of the primary mask layer through the openings in the top mask layer by exposing the substrate to plasma etch conditions without applying sidewall passivation conditions. In some embodiments, etch operation 455 is performed under conditions that do not substantially passivate sidewalls of openings being formed in the primary mask layer(s). In various implementations, compared to the top mask material, the liner material has a greater etch selectivity with respect to the primary mask material under the plasma etch conditions in operation 455.

[0073] In some embodiments, as depicted in an operation 456, a sidewall liner material may optionally be formed on the primary mask, as depicted in Figure 3E, in a manner similar to operations 355 and 357 of process 350.

[0074] In an operation 457, one or more layer(s) of material are etched through the primary mask pattern. In some embodiments, operation 457 involves etching the feature in at least one layer through the openings in the layer of primary mask material (and optionally top mask material if it is still remaining) by exposing the substrate to appropriate plasma etch conditions. In various implementations, operation 457 is performed without applying sidewall passivation conditions. In some embodiments, the sidewalls of the features are not substantially passivated during operation 457. Additional details of the plasma etch conditions are provided below.Docket No. LAM1P059WO Substrate, Mask, and Etch Feature Characteristics Substrate Layer Characteristics

[0075] As used herein the term substrate or substrate layer includes a silicon wafer or other support on which is provided one or more layers that are to be etched (or have been etched) in accordance with an etch process as described herein. In certain embodiments, the substrate layer(s) to be etched includes a dielectric such as a silicon nitride (SiNy), a silicon oxide (SiOx), a doped version of either of these, a multilayer stack of any of these, and the like.

[0076] For example, a dielectric substrate may include a mold stack for a DRAM device (e.g., thick layers of SiOx and thin layers of SiNy or vice versa) or a mold stack for a 3DNAND memory device (e.g., “ONON . . .” stacks of 10s or even 100s of alternating SiOx and SiNy layers). In another embodiment, the substrate includes alternating layers of silicon oxide and polysilicon.

[0077] In some embodiments, the disclosed liner-based etch process and associated apparatus are applicable to etching substrates that are not dielectrics. For example, the process may etch substrates comprising a conductor, such as a layer of carbon.

[0078] Any given substrate layer to be etched may have a thickness of about 10 nanometers to about 10000 nanometers. Mask Layer Characteristics

[0079] Mask materials may be chosen for etch selectivity versus the substrate material to be etched. Examples of mask layer materials for etching dielectric layers in a substrate include carbon (e.g., amorphous carbon characterized by its sp2-content), polysilicon, doped carbon, doped polysilicon, metal oxide, metal nitride, metal silicide, etc.

[0080] Examples of mask layer materials for etching conductor layers in a substrate include silicon oxides, silicon oxynitrides, silicon carbides, mixture of silicon nitride / oxide / carbides.

[0081] In certain embodiments, the thickness of a mask layer, prior to etch, is about 2 microns to 10 microns. Top Mask Layer Characteristics

[0082] For HAR etching, a second mask is often necessary to generate a pattern in the primary mask. For example, to etch dielectric layers in a mold stack, a high-density patterned carbon mask or a polysilicon mask may be employed, and a dielectric-containing top mask may be employed to etch the hole pattern in the carbon mask. Examples of materials for use in such top masks include silicon oxynitride (SiON), a silicon oxide (SiOx), or a silicon nitride (SiNy).

[0083] As illustrated with reference to Figures 4A-4E, many cases employing a second / top mask can employ a high selectivity liner in the top mask. In such cases, the mask open processDocket No. LAM1P059WO for the top mask produces extra wide CD openings in the top mask. A subsequently deposited mask sidewall liner reduces the openings to appropriate CDs.

[0084] In certain embodiments, the thickness of a top mask layer, prior to etch, is about 100nm to 600nm. Mask Sidewall Liner Characteristics

[0085] As indicated, a mask sidewall liner may be made from a material that provides high etch selectivity with respect to the underlying material to be etched. Typically, the etch selectivity of the liner material is greater than the etch selectivity of the primary mask material. For example, if a dielectric substrate layer is to be etched using a high-density carbon mask, the selectivity of the liner material with respect to the dielectric material may be greater than the selectivity of the high-density carbon mask material with respect to the dielectric material.

[0086] In certain embodiments, the etch selectivity of the liner material with respect to the underlying substrate material to be etched is at least about10:1.

[0087] In certain embodiments, the liner material is a metal, a metal-organic composite, a metal-containing carbon, a metal carbide, a metal oxide, a silicide, a metal nitride, or any combination thereof. Examples of liner elements, used alone or in a compound or dopant, include tungsten and its oxide / carbide / nitride compound alloys, molybdenum and its oxide / nitride / carbide compound alloys, ruthenium and its compound alloys, boron, aluminum and its compound alloys, , and the like.

[0088] In certain embodiments, the liner is deposited to a thickness that reduces the mask open CD to a CD appropriate for the etch process that follows. As examples, the deposited thickness of a liner may be about 2 to 20 nanometers or about 7 to 12 nanometers.

[0089] It should be understood that the liner is not a passivating layer as conventionally formed in HAR etch processes. Further, the liner is typically fully formed on the mask sidewalls before etching features in the underlying substrate layer(s). Substrate Feature Characteristics

[0090] In certain embodiments, the features etched in the substrate have an aspect ratio of at least about 10:1, or between about 10:1 and 100:1, or at least about 100:1.

[0091] In certain embodiments, the features etched in the substrate have a width (or diameter in the case of cylindrical features) of about 10 nm to 200 nm or about 40 nm to 100 nm.

[0092] In certain embodiments, the features etched in the substrate have an average depth of about 2 microns to about 20 microns or about 5 microns to 10 microns. Mask Feature Characteristics

[0093] In some embodiments, the mask is patterned with openings corresponding to theDocket No. LAM1P059WO locations, sizes, and shapes of the features to be etched in the underlying substrate layer(s). In certain embodiments, the openings in a primary mask have an aspect ratio of at least about 10:1, or between about 5:1 and 50:1, or at least about 20:1.

[0094] In certain embodiments, the mask opening width (or diameter) is nominally the same as or only slightly larger than the width of the feature to be etched in the underlying substrate. However, in embodiments employing a mask sidewall liner as disclosed herein, the mask opening width is increased by an amount of about two times the thickness of the mask sidewall liner. Thus, for example, the mask opening widths may be about 2 to 20 nanometers greater than a CD of the features to be etched. Etch and Deposition Conditions Liner Deposition Conditions

[0095] A mask sidewall liner may be deposited by any of various conventional or future- developed processes suitable for the liner material being deposited. Examples of such deposition processes include chemical vapor deposition (CVD) processes, including plasma- enhanced CVD processes, physical vapor deposition processes, atomic layer deposition (ALD) processes including thermal ALD and plasma-assisted ALD, and the like.

[0096] In some embodiments, the deposition of the mask sidewall liner begins by flowing one or more reactants into the reaction chamber. In the case of PECVD, the reactant delivery is accompanied by a plasma. The deposition process continues until the desired thickness of the liner layer is reached, at which point the plasma may be extinguished, and the reactant flow may be terminated.

[0097] For example, a liner may be a tungsten (W)-containing liner, which can be deposited thermally or plasma-enhanced using a tungsten hexafluoride (WF6) precursor, with or without a reducing agent such asH2or B2H6reducing agent. Bottom Punch Through Conditions

[0098] A bottom punch through process is used to remove the conformally deposited liner layer from regions over the mask openings. In some cases, the punch through process is performed using an anisotropic etch process.

[0099] For example, a metal oxide liner (e.g., tungsten-containing liner) can be removed from the regions over the mask opening using a chlorine-containing plasma (e.g., Cl2-based plasma). In various implementations, bias may be applied to anisotropically remove the liner material from the regions over the mask opening. Substrate Layer Etch Conditions

[0100] Substrate layers may be etched through masks with sidewall liners by using any ofDocket No. LAM1P059WO many types of etch processes. Such processes may be characterized by, for example, their process gas composition, temperature, pressure, plasma generation and biasing conditions, etc.

[0101] In certain embodiments, the substrate etch process does not employ process gas compounds or other specific conditions that are conventionally used to form a passivation layer during the etch process. For example, the etch processes may include no fluorocarbons, hydrofluorocarbons, or metal-containing compounds. Without focusing on forming a passivation layer, the process can avoid or mitigate problems such as feature clogging and twisting that are increasingly associated with passivation layers formed during HAR etch processes. Etch processes that are not focused on passivation are layers may be enabled when the mask has a liner. Etchant Chemistry

[0102] Etch processes disclosed herein may be partially characterized by, for example, their process gas composition.

[0103] In certain embodiments, the etchant process gas chemistry includes a fluorine source. Examples of fluorine source include hydrogen fluoride (HF), phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), chlorine monofluoride (ClF), iodine heptafluoride (IF7), sulfur hexafluoride (SF6), silicon tetrafluoride (SiF4), tungsten hexafluoride (WF6), molybdenum hexafluoride (MoF6), fluorine (F2), boron trifluoride (BF3), arsenic trifluoride (AsF3), xenon difluoride (XeF2) and ruthenium hexafluoride (RuF6).

[0104] In some embodiments, the etchant gas includes a chlorine-containing source. Examples of chlorine-containing sources include chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and monochlorosilane (SiH3Cl).

[0105] In some embodiments, the etchant gas includes a fluorine-containing and a chlorine- containing source. Examples include etchant gases that include chlorine trifluoride (ClF3) and chlorine monofluoride (ClF).

[0106] In some embodiments, the etchant gas includes a fluorine source, a chlorine source, and a carbon source.

[0107] In certain embodiments, the etchant chemistry includes a fluorine source and a carbon source. Examples of carbon sources include all volatile hydrocarbons (CxHy) and hydrofluorocarbons (CxHyFz, where z>0), e.g., CH2F2.

[0108] In certain embodiments, one or more additional gases may be included. Examples of such additional gases include hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogenDocket No. LAM1P059WO iodide (HI), chlorine (Cl2), carbon trifluoro iodide (CF3I), helium (He), and carbonyl sulfide (COS). In certain embodiments, the etch chemistry includes a reducing agent (e.g., molecular hydrogen) and / or an oxidizer (e.g., molecular oxygen)

[0109] In some implementations, the etchant chemistry includes hydrogen fluoride, phosphorus trifluoride (PF3), molecular hydrogen (H2), and nitrogen trifluoride (NF3). In some implementations, the etchant chemistry additionally includes a fluorocarbon such as carbon tetrafluoride (CF4) and / or a hydrofluorocarbon such as difluoromethane (CH2F2).

[0110] The components of the etchant process gas may be present in any of various ratios. As examples, etchant gases used to process a 300 mm wafer may have flow rates in the following ranges: NF3: 0-100sccm; CF4: 0-100 sccm; CH2F2: 0-100 sccm; HF: 0-1000 sccm; H2: 0-1000 sccm; PF3: 0-100sccm HCl: 0-200sccm HBr0-200sccm HI: 0-200sccm

[0111] In some implementations, non-reactive gases such as nitrogen (N2), argon (Ar), and / or helium (He) may be used to modulate plasma properties. Examples of the flow rates for a 300 mm wafer include the following: N20-500sccm Ar 0-500 sccm He 0-1000 sccm Temperature

[0112] In some embodiments, the temperature range of the substrate or the substrate support is about 80°C to 150°C. In some embodiments supporting cryogenic processing, the temperature of the substrate or the substrate support is about -100°C to 80°C or about -40°C to 0°C. In some embodiments, the etch process proceeds using both cryogenic and non-cryogenic temperature domains. Thus, the temperature may change or even alternate over the course of a feature etch. For example, part of a feature etch process may be run at -60°C, and then the process has a temperature equilibration step, and finally, the remaining part of the feature etch process is run at 40°C. In some implementations, the etch apparatus comprises a multiple-Docket No. LAM1P059WO channel chiller to change substrate temperature to utilize both cryogenic and non-cryogenic etching regime. Pressure

[0113] In some embodiments, the pressure in the plasma etch chamber is at least a partial vacuum. For example, the pressure may be about 1 to 1000 mT or about 2 to 200 mT.

[0114] Very low pressures, such as down to about 2 mT or even 1 mT, may facilitate deep, HAR etching. Such applications require a very narrow angular distribution of ions reaching the substrate surface. Ideally, all ions would reach the surface in a direction that is perpendicular to the plane of the surface. But, this is not possible because some ions contact gas molecules or atoms in the etch chamber. Any ions that contact molecules as they travel toward the substrate will deflect them and introduce some deviation from the ideal perfectly perpendicular ion angle distribution. Very low pressures reduce the occurrence of such collisions. Plasma generation

[0115] In certain embodiments, the plasma etch chamber comprises a plasma source generator and electrode (e.g., an inductively coupled plasma (ICP) electrode) and plasma bias generator and electrode (e.g., an electrode within or proximate a wafer pedestal, chuck, or other support). In certain embodiments, the plasma source is capacitively coupled (CCP). In the following example, plasma process conditions assume that the etch chamber includes both sources. It also assumes that these sources are pulsed, such that each cycle includes, at least, a high-power state (S1) and a lower power state (S0). Note that in some embodiments, a portion of or all of the etch process does not employ multi-state pulsing or even any pulsing. Power and frequency of the plasma source generator and electrode:

[0116] In certain embodiments, the plasma power and frequency for a plasma source generator falls within certain ranges, which are shown as examples below. Note that while the ranges assume a system that employs at least two states (S0 and S1), it extends single state embodiments and multi-state embodiments having three or more states. In the case of single state embodiments, the power and frequency ranges may correspond to the S1 ranges shown below. In the case of multi-state embodiments, the highest state may correspond to the S1 state values shown below. S0 frequency: about 10 to 100 MHz (e.g., about 13MHz to 60 MHz) S0 Power: about 0 to 700 W (e.g., about 100 to 500 W) S1 frequency: about 10 to 100 MHz (e.g., about 13MHz to 60 MHz) S1 Power: about .5-20kW (e.g., about 6-15kW)Docket No. LAM1P059WO Power and frequency of the plasma bias generator and electrode

[0117] In certain embodiments, the plasma power and frequency for a plasma bias generator falls within certain ranges, which are shown as examples below. As with the plasma source generator ranges described above, while the plasma bias ranges assume a system that employs at least two states (S0 and S1), it extends single state embodiments and multi-state embodiments having three or more states. In the case of single state embodiments, the power and frequency ranges may correspond to the S1 ranges shown below. In the case of multi-state embodiments, the highest state may correspond to the S1 state values shown below. S0 frequency: about 100 to 2000 kHz (e.g., 400 kHz) S0 Power: about 0 to 1000 W (e.g., about 1 to 400 W) S1 frequency: about 100 to 2000 MHz (e.g., 400 kHz) S1 Power: about 0 to 200,000 W (e.g., about 1 to 80 kW) Pulsing characteristics

[0118] As indicated, certain etch processes employ a plasma pulsing process. The pulsing may be characterized by various parameters. For example, the number of distinct pulse states may include two, three, four, or more. Pulsing may also be characterized by a duty cycle. As an example, the S1 duty cycle may be about 5 to 60%, assuming that S1 is the state with the highest power. The pulsing may also be characterized by a repetition rate, which in certain cases is about 100Hz to 20kHz.

[0119] In certain embodiments, the pulsing regime is supported in a commercially available plasma etch tool available from Lam Research of Fremont, CA. Examples of such tools include the Flex™, the Kiyo™, the Akara™, and the Vantex™. Multi-state Pulsing

[0120] As explained, plasma power may be pulsed, with each pulse cycle at least two states. The pulsing may be applied to the source RF power, the bias RF power, or both. In multi- state pulsing, each pulsed RF cycle has at least a first state, second state, and third state. In one example of a multi-state pulse scheme, the first state is defined by the source RF power having a first source RF power level and the bias RF power having a first bias RF power level, the second state is defined by the source RF power and the bias RF power having substantially zero power levels, and the third state is defined by the source RF power having a second source RF power level less than the first source RF power level, and the bias RF power having a substantially zero power level.

[0121] Incorporating an intermediate state in a multi-state RF pulsing scheme may over- come fundamental process development limits and barriers in existing etch technologies.Docket No. LAM1P059WO The intermediate state may be based on preferential trimming of the mask neck polymer in a low ion energy state, to facilitate a more aggressive high energy state (On / High state) and a more polymerizing passivation state (Off / Low state). Introducing such a low ion energy state with source power only helps to control the neck / mask shape. Combining this approach with on-off pulsing instead of level-to-level pulsing drives more polymer deposition on the top of the mask, passivating the top of the mask and controlling mask etch rate. This approach enables breaking the trade-off between mask neck / process margin versus selectivity.

[0122] An example four state pulsing scheme includes (a) an S1 state has the highest power (both source power and bias power), an S0 state that has zero plasma power from either source, an S3 state that has some source power but no bias power, and an S4 state that has a small amount of both Source and bias powers. Integration and Applications

[0123] The etch processes described herein may be employed to etch any of many different types of features. As indicated, such features may be etched using particular etch conditions comprising process gas chemistries (e.g., hydrogen-fluoride containing etchants), temperatures (e.g., cryogenic), plasma control (e.g., source or bias pulsing), and any combination thereof. The etched features may have shapes such as cylindrical, polygonal, trench, etc.

[0124] In certain embodiments, the feature etched in accordance with this disclosure has as an aspect ratio of at least about 10:1, at least about 20:1, at least about 50:1, or at least about 100:1. In some cases, the feature has an aspect ratio of about 20:1 to about 70:1.

[0125] In certain embodiments, a feature etched in accordance with this disclosure is used in a memory application such as fabrication of a DRAM array or 3D NAND memory device. In the context of DRAM fabrication, an etched feature may be used as a mold for a capacitor.

[0126] It should be understood that the disclosed etch processes and apparatus are not limited to etching mold stacks or other structures for memory devices. Disclosed etch processes and apparatus may be used to etch features or structures in 3D DRAM, or to etch high aspect ratio logic trench or holes. Etch and Deposition Tools

[0127] Deposition tool for forming blanket layers, including mask layers and optionally for forming mask sidewall liners. Examples of such tools include deposition reactors configured to perform chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition (thermal and plasma enhanced), epitaxial growth, and the like. In certain embodiments, the deposition tool is a Vector™ tool, a Striker™ tool,Docket No. LAM1P059WO an Altus™ tool, or a Halo™ tool available from Lam Research Corporation of Fremont, California. A Vector™ tool is commonly used for depositing carbon mask layers.

[0128] Dielectric etch tool for etching dielectric layers in the substrate or in a mask layer when the mask comprises a dielectric material. Examples of such dielectric etch tools include certain anisotropic dry etch tools that employ a biased plasma generator, such as a capacitively coupled plasma (CCP) reactor, a transformer coupled plasma (TCP) reactor, and the like. In certain embodiments, the dielectric etch tool is a Flex™ or a Vantex™ available from Lam Research Corporation of Fremont, California.

[0129] Conductor etch tool for etching conductor layers in a mask layer or in a substrate layer when the substrate comprises a conductor material. Examples of such conductor etch tools include certain anisotropic dry etch tools that employ a biased plasma generator, such as a CCP reactor, a TCP reactor, and the like. In certain embodiments, the conductor etch tool is a Kiyo™ or a Akara™ available from Lam Research Corporation of Fremont, California. Apparatus and System

[0130] Figure 5 illustrates a schematic diagram of a plasma processing system according to some embodiments. Figure 6 illustrates a schematic diagram of a control module for controlling the systems described in Figure 6 according to some embodiments.

[0131] Various implementations described herein may be performed in a plasma processing system. With reference to FIG. 5, an example plasma processing system or apparatus may include a chamber 601 having a gas injector / showerhead / nozzle 603 for distributing gases (605, 607, 609) (e.g. reactant and purge gases) or other chemistries (e.g., one or more etch chemistries such as hydrogen fluoride (HF), phosphoric trifluoride (PF3), nitrogen trifluoride (NF3), molecular hydrogen (H2), etc.) into the chamber 601, chamber walls 611, a chuck 613 for holding a substrate or wafer 615 to be processed which may include electrostatic electrodes for chucking and dechucking a wafer. The chuck 613 is heated and / or cooled for thermal control, enabling heating or cooling of the substrate 615 to a desired temperature during a substrate processing, such as etching the substrate having a mold stack. In some embodiments, the temperature of the substrate may be controlled between about -100 °C and up to 300 °C. In some implementations, the chuck 613 may include an electrode to be electrically charged using a plasma bias generator 617 to provide a bias RF power to the substrate in accordance with implementations of the disclosure.

[0132] In certain embodiments, a plasma source generator 619 is configured to supply source RF power to an electrode, e.g., an inductively coupled plasma electrode to generate a plasma 625 in the process space over the substrate 615. In some implementations, theDocket No. LAM1P059WO chamber walls are heated to support thermal management and efficiency. A vacuum source 627 provides a vacuum to evacuate gases from the chamber 601. The system or apparatus may include a system controller 629 for controlling some or all of the operations of the chamber or apparatus, such as modulating the chamber pressure, inert gas flow, source RF power, source frequency, reactive gas flow; bias RF power, bias frequency, temperature, vacuum settings; and other process conditions.

[0133] In some implementations, a system / apparatus may include more than one chamber for processing substrates.

[0134] FIG. 6 shows a control module 700 for controlling the systems described above, in accordance with implementations of the disclosure. For instance, the control module 700 may include a processor, memory and one or more interfaces. The control module 700 may be employed to control devices in the system based in part on sensed values. For example, the control module 700 may control one or more of valves 702, filter heaters 704, pumps 706, and other devices 708 based on the sensed values and other control parameters. The control module 700 receives the sensed values from, for example only, pressure manometers 710, flow meters 712, temperature sensors 714, and / or other sensors 716. The control module 700 may also be employed to control process conditions during reactant delivery and plasma processing. The control module 700 will typically include one or more memory devices and one or more processors.

[0135] The control module 700 may control activities of the reactant delivery system and plasma processing apparatus. The control module 700 executes computer programs including sets of instructions for controlling process timing, delivery system temperature, pressure differentials across the filters, valve positions, mixture of gases, chamber pressure, chamber temperature, wafer temperature, RF power levels, e.g., source RF power level and / or bias RF power level, wafer ESC or pedestal position, and other parameters of a particular process. The control module 700 may also monitor the pressure differential and automatically switch vapor reactant delivery from one or more paths to one or more other paths. Other computer programs stored on memory devices associated with the control module 700 may be employed in some implementations.

[0136] Typically, there will be a user interface associated with the control module 700. The user interface may include a display 718 (e.g. a display screen and / or graphical software displays of the apparatus and / or process conditions), and user input devices 720 such as pointing devices, keyboards, touch screens, microphones, etc.

[0137] Computer programs for controlling delivery of reactant, plasma processing and otherDocket No. LAM1P059WO processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program.

[0138] The control module parameters relate to process conditions such as, for example, filter pressure differentials, process gas composition and flow rates, substrate temperature, chamber pressure, plasma conditions such as RF power levels, e.g., source RF power levels and / or bias RF power level, and the RF frequency, e.g., source RF frequency and / or bias RF frequency, duty cycle, cooling gas pressure, and chamber wall temperature.

[0139] The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the inventive deposition processes. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code. Conclusion

[0140] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments are described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0141] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, structures, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Docket No. LAM1P059WO CLAIMS What is claimed is:

1. A method of etching features in a substrate used in fabricating an electronic device, the method comprising: (a) providing a substrate to an etch chamber, wherein the substrate comprises at least one layer of a material to be etched and a mask over the at least one layer, wherein the mask comprises (i) a layer of mask material, (ii) a plurality of openings in the layer of mask material, and (iii) a mask sidewall liner comprising a liner material on sidewalls of the openings in the layer of mask material; and (b) etching the features in the at least one layer, through the openings in the layer of mask material, by exposing the substrate to plasma etch conditions, wherein compared to the mask material the liner material has a greater etch selectivity with respect to the material to be etched under the plasma etch conditions.

2. The method of claim 1, further comprising, prior to (a), forming the mask sidewall liner on the sidewalls of the openings in the layer of mask material.

3. The method of claim 2, wherein forming the sidewall liner comprises: (i) conformally depositing a layer of the liner material on the layer of mask material, including the plurality of openings; and (ii) removing substantially all the liner material at bottoms of the plurality of openings.

4. The method of claim 3, wherein removing substantially all the liner material at bottoms of the plurality of openings comprises performing an anisotropic etch that exposes the at least one layer of a material to be etched.

5. The method of any of the foregoing claims, wherein the liner material comprises a metal-organic composite, a metal-containing carbon, a metal carbide, a metal oxide, a silicide, a metal nitride, or any combination thereof.

6. The method of any of the foregoing claims, wherein the mask material comprises amorphous carbon, polysilicon, metal-doped carbon, or any combination thereof, and wherein the substrate comprises a dielectric material.Docket No. LAM1P059WO 7. The method of any of the foregoing claims, wherein the plurality of openings in the layer of mask material are wider than a critical dimension (CD) of the features by approximately 2 times a thickness of the mask sidewall liner.

8. The method of any of the foregoing claims, further comprising: prior to forming the plurality of openings in the mask layer, forming a top mask layer over the mask; creating a plurality of top mask openings, which aligns the with plurality of openings in the layer of mask material, which plurality of openings have not yet been formed; and forming a top mask liner on the sidewalls of the plurality of top mask openings.

9. The method of claim 8, further comprising etching the plurality openings in the layer of mask material, through the plurality of top mask openings.

10. The method of claims 8 or 9, wherein the top mask comprises a silicon nitride, a silicon oxide, a silicon oxynitride, or any combination thereof.

11. The method of any of the foregoing claims, wherein etching the features comprises exposing the substrate to a plasma generated by a transformer-coupled plasma (TCP) power source.

12. The method of any of the preceding claims, wherein the plasma etch conditions comprise supplying the etch chamber with an etchant gas comprising (i) a fluorine-containing component and a carbon-containing component, or (ii) a chlorine-containing component and the carbon-containing component.

13. The method of claim 16, wherein the fluorine-containing component comprises HF, NF3, CF4, PF3, SF6, SiF4, WF6, MoF6, RuF6, PF5, ClF3, ClF, IF7, or any combination thereof.

14. The method of claims 12 or 13, wherein the carbon-containing component comprises a hydrocarbon or a hydrofluorocarbon.Docket No. LAM1P059WO 15. The method of claims 12 or 13, wherein the chlorine-containing component comprises Cl2, BCl3, HCl, SiCl4, SiH2Cl2, SiHCl3, or SiH3Cl.

16. The method of any of the preceding claims, wherein the plasma etch conditions comprise a pressure in the etch chamber of about 2 to 400 mTorr.

17. The method of any of the preceding claims, wherein the plasma etch conditions comprise a temperature of the substrate of about -100°C to 200°C.

18. The method of claim 1, wherein the features have an aspect ratio of at least about 10:

1.

19. An apparatus for etching features in a substrate, apparatus comprising: an etch chamber configured to receive a substrate comprising at least one layer to be etched and a layer of mask material above the at least one layer; a plasma power source for providing a plasma in the etch chamber; one or more gas inlets for providing an etchant gas and liner precursor to the etch chamber; a substrate support for supporting the substrate, wherein the substrate support comprises or is associated with an electrode configured to provide bias voltage to the substrate; and a controller configured to cause: (a) forming a plurality of openings in the layer of mask material, (b) forming a mask sidewall liner on sidewalls of the openings in the layer of mask material; and (c) etching the features in the at least one layer, through the openings in the layer of mask material, by exposing the substrate to plasma etch conditions.

20. The apparatus of claim 19 , wherein the controller is further configured to cause forming a liner on sidewalls of the openings in the layer of mask material by causing: (i) conformally depositing a layer of liner material on the layer of mask material, including the plurality of openings; and (ii) removing substantially all the liner material at bottoms of the plurality of openings.

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