Array substrate, display panel, and display apparatus

Abstract

An array substrate, a display panel, and a display apparatus. The array substrate of the present disclosure comprises: a base substrate; a plurality of pixel electrodes, arranged in an array on the base substrate; a plurality of data lines, extending along a portion of column gaps between the pixel electrodes; a plurality of gate lines, extending along row gaps between the pixel electrodes, two of the gate lines being included in the same row gap; and a plurality of common electrode lines, extending along gaps between the pixel electrodes, the common electrode lines and the data lines being arranged in the same layer and being spaced apart, each common electrode line comprising an abutment portion for supporting a spacer, and the orthographic projection of the abutment portion on the base substrate being located between the orthographic projections of the two gate lines on the base substrate.

Description

Array substrate, display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410944863.8, filed on July 15, 2024, entitled "Array Substrate, Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0004] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0006] On one hand, embodiments of this disclosure provide an array substrate, including:

[0007] Substrate;

[0008] Multiple pixel electrodes are arranged in an array on the substrate.

[0009] Multiple data lines extend at the partial column gaps of the pixel electrodes;

[0010] Multiple gate lines extend at the row gaps of the pixel electrodes, with two gate lines at the same row gap;

[0011] Multiple common electrode lines extend at the gaps between the pixel electrodes, and the common electrode lines are arranged on the same layer as the data lines and spaced apart. The common electrode lines include a base portion for supporting spacers, and the orthographic projection of the base portion on the substrate is located between the orthographic projections of the two gate lines on the substrate.

[0012] In some embodiments, the array substrate provided in this disclosure further includes a common electrode electrically connected to the plurality of common electrode lines, the common electrode including a first strip-shaped common electrode and a second strip-shaped common electrode that are intersected and integrally disposed; wherein...

[0013] The orthographic projection of the first strip common electrode on the substrate is located between the orthographic projections of the two gate lines on the substrate, and the second strip common electrode and the data line are alternately arranged at different column gaps of the pixel electrode.

[0014] In some embodiments, in the array substrate provided in the present disclosure, the plurality of common electrode lines include a first common electrode line, the first common electrode line being electrically connected to the first strip-shaped common electrode, and the orthographic projection of the first strip-shaped common electrode on the substrate at least partially overlapping the orthographic projection of the first common electrode line on the substrate.

[0015] In some embodiments, the array substrate provided in the present disclosure further includes a transition line disposed on the same layer as the plurality of gate lines, the transition line being connected between two adjacent first common electrode lines.

[0016] In some embodiments, the array substrate provided in this disclosure further includes a first insulating layer located between the layer containing the plurality of data lines and the layer containing the plurality of gate lines, and a second insulating layer located between the layer containing the plurality of data lines and the layer containing the common electrode; wherein,

[0017] The first insulating layer and the second insulating layer include a through-hole, wherein the orthographic projection of the first through-hole on the substrate overlaps with the orthographic projection of the adapter line on the substrate.

[0018] The second insulating layer includes a second via that is conductively connected to the first via, wherein the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the first strip common electrode on the substrate.

[0019] The first strip-shaped common electrode is electrically connected to the adapter cable through the first via, and the first strip-shaped common electrode line is electrically connected to the first common electrode line through the second via.

[0020] In some embodiments, in the array substrate provided in the present disclosure, the plurality of common electrode lines further include a second common electrode line, the second common electrode line being electrically connected to the second strip-shaped common electrode, and the orthographic projection of the second strip-shaped common electrode on the substrate at least partially overlapping the orthographic projection of the second common electrode line on the substrate.

[0021] In some embodiments, the array substrate provided in this disclosure further includes a second insulating layer located between the layer containing the plurality of data lines and the layer containing the common electrode. The second insulating layer includes a third via, and the second common electrode line is electrically connected to the second strip-shaped common electrode through the third via.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the pedestal portion on the substrate.

[0023] In some embodiments, in the array substrate provided in the present disclosure, the second strip-shaped common electrode includes a boss structure, the orthographic projection of the boss structure on the substrate covers the orthographic projection of the third via on the substrate and is located within the orthographic projection of the base portion on the substrate.

[0024] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transistors and a plurality of connection structures located at the row gaps of the pixel electrodes; wherein,

[0025] The orthographic projection of the connection structure on the substrate intersects with the orthographic projection of the second strip-shaped common electrode on the substrate;

[0026] Between two adjacent data lines, two transistors are provided at the same row gap of the pixel electrode; one of the transistors is electrically connected to the pixel electrode through the connection structure.

[0027] In some embodiments, the array substrate provided in this disclosure further includes a plurality of compensation structures located at the gaps between the pixel electrode rows. The compensation structures are electrically connected to the transistors that do not correspond to the connection structures, and the orthographic projection of the compensation structures on the substrate intersects with the orthographic projection of the second strip common electrode on the substrate. A portion of the connection structure and the compensation structure are arranged approximately symmetrically about the first strip common electrode on both sides of the two gate lines.

[0028] In some embodiments, the array substrate provided in the present disclosure further includes a first pattern on the same layer as the active layer of the transistor, wherein the orthographic projection of the first pattern on the substrate substantially coincides with the orthographic projection of the pattern of the layer containing the data line on the substrate.

[0029] In some embodiments, in the array substrate provided in the present disclosure, the common electrode further includes a plurality of third strip-shaped common electrodes, which are located at the same column gap as the data line of the pixel electrode.

[0030] In some embodiments, in the array substrate provided in the present disclosure, at least a portion of the third strip common electrode is located between two adjacent pixel electrodes arranged along the row direction.

[0031] In some embodiments, in the array substrate provided in the present disclosure, the third strip-shaped common electrode on one side of the data line is located between two adjacent pixel electrodes arranged along the row direction, and the third strip-shaped common electrode on the other side of the data line passes through the column gap of the pixel electrodes and intersects with the first strip-shaped common electrode.

[0032] In some embodiments, the array substrate provided in the present disclosure further includes a second pattern on the same layer as the pixel electrode, wherein the orthographic projection of the second pattern on the substrate generally coincides with the orthographic projection of the pattern of the layer containing the gate line on the substrate.

[0033] On the other hand, embodiments of this disclosure provide a display panel, including an array substrate and a counter substrate placed opposite each other; wherein,

[0034] The array substrate is the array substrate provided in the embodiments of this disclosure;

[0035] The opposing substrate includes a spacer, and the orthographic projection of the end of the spacer facing the array substrate onto the substrate overlaps with the orthographic projection of the pedestal portion onto the substrate.

[0036] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0037] Figure 1 is a schematic diagram of a structure of four sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0038] Figure 2 is a schematic diagram of another structure of four sub-pixels in the array substrate provided in the embodiment of this disclosure;

[0039] Figure 3 is a schematic diagram of another structure of four sub-pixels in the array substrate provided in the embodiment of this disclosure;

[0040] Figure 4 is a schematic diagram of another structure of four sub-pixels in the array substrate provided in the embodiment of this disclosure;

[0041] Figure 5 is a schematic diagram of another structure of four sub-pixels in the array substrate provided in the embodiment of this disclosure;

[0042] Figure 6 is a cross-sectional view along line a-a' in Figures 1, 3 and 5;

[0043] Figure 7 is a cross-sectional view along line b-b' in Figures 1, 2, and 4;

[0044] Figure 8 is a cross-sectional view along line c-c' in Figures 2 and 4;

[0045] Figure 9 is a cross-sectional view along line d-d' in Figures 3 and 5;

[0046] Figure 10 is a schematic diagram of the structure of the layer where the pixel electrodes are located in Figures 1 to 5;

[0047] Figure 11 is a schematic diagram of the structure of the layer containing the grid lines in Figures 1 to 5;

[0048] Figure 12 is a schematic diagram of the active layer in Figure 1;

[0049] Figure 13 is a schematic diagram of the structure of the layer where the data line is located in Figure 1;

[0050] Figure 14 is a schematic diagram of the structure of the layer where the vias are located in Figures 1, 3, and 5;

[0051] Figure 15 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 1;

[0052] Figure 16 is a schematic diagram of the structure of the layer where the data lines are located in Figures 2 and 4;

[0053] Figure 17 is a schematic diagram of the structure of the layer where the vias are located in Figures 2 and 4;

[0054] Figure 18 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 2;

[0055] Figure 19 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 4;

[0056] Figure 20 is a schematic diagram of the structure of the layer where the data lines are located in Figures 3 and 5;

[0057] Figure 21 is a schematic diagram of the structure of the layer where the common electrode is located in Figures 3 and 5;

[0058] Figure 22 is a schematic diagram of the active layer structure in Figures 2 and 4;

[0059] Figure 23 is a schematic diagram of the active layer structure in Figures 3 and 5;

[0060] Figure 24 is a schematic diagram of a display panel provided in an embodiment of this disclosure;

[0061] Figure 25 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;

[0062] Figure 26 is a schematic diagram of a display device provided in an embodiment of the present disclosure;

[0063] Figure 27 is a schematic diagram of another structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0065] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0066] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0067] Dual-gate pixels, in layman's terms, refer to a pixel architecture where the number of gate lines in the display area (AA) is doubled and the number of data lines is halved. This can reduce the amount of source drive circuitry (COF) by half, thereby saving costs.

[0068] However, in some embodiments, the base for supporting the spacer (PS) is located on the data line, and the transistor for charging the pixel electrode is located close to the data line. As a result, the base is close to the double metal layer of the transistor (the gate and source / drain overlap). When squeezed, the PS may slide to the double metal layer and get stuck, making it difficult to return to its original position. In addition, when the PS is squeezed, it may also slide to the pixel opening area and scratch the pixel opening area, affecting the display effect.

[0069] To at least improve the aforementioned technical problems existing in related technologies, this disclosure provides an array substrate. Figures 1 to 5 show schematic diagrams of the structure of four sub-pixels in the array substrate provided by this disclosure. Figure 6 is a cross-sectional view along line a-a' in Figures 1, 3, and 5; Figure 7 is a cross-sectional view along line b-b' in Figures 1, 2, and 4; Figure 8 is a cross-sectional view along line c-c' in Figures 2 and 4; Figure 9 is a cross-sectional view along line d-d' in Figures 3 and 5; Figure 10 is a schematic diagram of the structure of the layer containing the pixel electrodes in Figures 1 to 5; Figure 11 is a schematic diagram of the structure of the layer containing the gate lines in Figures 1 to 5; Figure 12 is a schematic diagram of the structure of the active layer in Figure 1; Figure 13 is a schematic diagram of the structure of the layer containing the data lines in Figure 1; Figure 14 is a schematic diagram of the structure of the layer containing the data lines in Figures 1, 2, and 4. 3. Figure 5 shows the structural schematic diagram of the layer containing the vias; Figure 15 shows the structural schematic diagram of the layer containing the common electrode in Figure 1; Figure 16 shows the structural schematic diagram of the layer containing the data lines in Figures 2 and 4; Figure 17 shows the structural schematic diagram of the layer containing the vias in Figures 2 and 4; Figure 18 shows the structural schematic diagram of the layer containing the common electrode in Figure 2; Figure 19 shows the structural schematic diagram of the layer containing the common electrode in Figure 4; Figure 20 shows the structural schematic diagram of the layer containing the data lines in Figures 3 and 5; Figure 21 shows the structural schematic diagram of the layer containing the common electrode in Figures 3 and 5; Figure 22 shows the structural schematic diagram of the active layer in Figures 2 and 4; and Figure 23 shows the structural schematic diagram of the active layer in Figures 3 and 5.

[0070] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 1 to 5 and Figures 10 to 15, may include:

[0071] Optionally, the substrate 101 includes a display area (AA) and a non-display area located on at least one side of the display area (AA). In some embodiments, the display area (AA) includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

[0072] Multiple pixel electrodes 102 are arranged in an array in the display area (AA). Optionally, the pixel electrodes 102 are block electrodes. In some embodiments, the pixel electrodes 102 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO).

[0073] Multiple data lines 103 extend at some of the column gaps of the pixel electrode 102, for example, the data lines 103 extend at the odd or even column gaps of the pixel electrode 102. In some embodiments, the material of the layer containing the data lines 103 (i.e., the source / drain metal layer) may include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The source / drain metal layer may be a single-layer structure or a stacked structure, for example, the source / drain metal layer may be a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0074] Multiple gate lines 104 extend at the row gaps of the pixel electrode 102. This disclosure can employ a dual-gate pixel architecture, where two gate lines 104 can be included at the same row gap, halving the number of data lines 103 and helping to reduce costs. In some embodiments, the material of the layer containing the gate lines 104 (i.e., the gate metal layer) can include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate metal layer can be a single-layer structure or a stacked structure, for example, the gate metal layer can be a single-layer structure composed of a molybdenum metal layer.

[0075] Multiple common electrode lines 105 extend at the gaps between pixel electrodes 102. Optionally, the common electrode lines 105 and data lines 103 are arranged in the same layer and spaced apart. The common electrode lines 105 include a base portion PS' for supporting spacers (PS). The orthographic projection of the base portion PS' on the substrate 101 is located between the orthographic projections of two gate lines 104 at the same row gap on the substrate 101. Optionally, the base portion PS' intersects with the column gap between the two data lines 103. In this disclosure, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for creating a specific pattern, and then using the same mask to form a patterning process in one step. That is, one patterning process corresponds to one mask (also called photomask). Depending on the specific pattern, the one patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0076] In the array substrate provided in the embodiments of this disclosure, the base portion PS' of the spacer (PS) is moved from the data line 103 to the common electrode line 104. On the one hand, this increases the distance between the spacer (PS) and the double-layer metal in the horizontal direction, preventing the spacer (PS) from sliding to the double-layer metal and getting stuck, making it difficult to recover. On the other hand, when the spacer (PS) is squeezed, the sliding distance in the horizontal and vertical directions is longer, while the oblique distance is shorter. The base portion PS' is located between the double gates, which can minimize and average the scratching effect of the spacer (PS) on the pixel opening area, which is beneficial to improving display uniformity.

[0077] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 1 to 5, 7, 10, 11, 13, 15, 16, and 18 to 21, may further include a common electrode 106 electrically connected to multiple common electrode lines 105. The common electrode 106 may be a slit electrode, and the portion of the common electrode 106 located between the slits may be labeled as a fourth strip-shaped common electrode 1064. The material of the common electrode 106 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO). The common electrode 106 may include a first strip-shaped common electrode 1061 and a second strip-shaped common electrode 1062 that are intersected and integrally disposed. The orthographic projection of the first strip-shaped common electrode 1061 on the substrate 101 is located between the orthographic projections of the two gate lines 104 on the substrate 101, and the second strip-shaped common electrode 1062 and the data line 103 are alternately disposed at different column gaps of the pixel electrode 102. The first strip common electrode 1061 and the second strip common electrode 1062 form an interleaved connection network, which can significantly improve the uniformity of the common voltage (VCOM), thereby improving image defects such as head-shaking patterns, lateral crosstalk, and waterfall caused by poor VOM uniformity, and improving product specifications.

[0078] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 1, 3, 5, 6, 11, 15, and 21, multiple common electrode lines 105 may include a first common electrode line 1051. The first common electrode line 1051 is electrically connected to a first strip-shaped common electrode 1061, and the orthographic projection of the first strip-shaped common electrode 1061 on the substrate 101 at least partially overlaps with the orthographic projection of the first common electrode line 1051 on the substrate 101. Optionally, the orthographic projection of the first strip-shaped common electrode 1061 on the substrate 101 is located within the orthographic projection of the first common electrode line 1051 on the substrate 101, and the orthographic projection of the first common electrode line 1051 on the substrate 101 is located between the orthographic projections of the two gate lines 104 on the substrate 101. The first common electrode line 1051 and the first strip-shaped common electrode 1061, which are of different layers and extend in the same direction, are connected in parallel, which can effectively reduce the overall trace resistance and improve the uniformity of VCOM.

[0079] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG1, FIG3, FIG5, FIG6, FIG11, FIG15 and FIG21, may further include a transition line 107 disposed on the same layer as the multiple gate lines 104. The transition line 107 is connected between two adjacent first common electrode lines 1051 to avoid the first common electrode lines 1051 from being short-circuited with the data lines 103 disposed on the same layer.

[0080] In some embodiments, the array substrate provided in this disclosure, as shown in FIG6, may further include a first insulating layer 108 located between the layer containing the multiple data lines 103 (i.e., the layer containing the common electrode line 105) and the layer containing the multiple gate lines 104 (i.e., the layer containing the adapter line 107), and a second insulating layer 109 located between the layer containing the multiple data lines 103 (i.e., the layer containing the common electrode line 105) and the layer containing the common electrode 106. The materials of the first insulating layer 108 and the second insulating layer 109 may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., and may be a single layer or a stacked layer. The first insulating layer 108 and the second insulating layer 109 may include a through-hole V1, the orthographic projection of the first via V1 on the substrate 101 overlapping the orthographic projection of the adapter line 107 on the substrate 101. In some embodiments, the orthographic projection of the first via V1 on the substrate 101 is located within the orthographic projection of the adapter line 107 on the substrate 101. The second insulating layer 109 also includes a second via V2 that is electrically connected to the first via V1, the orthographic projection of the second via V2 on the substrate 101 overlapping the orthographic projection of the first strip common electrode 1061 on the substrate 101. For example, the orthographic projection of the second via V2 on the substrate 101 is located within the orthographic projection of the first strip common electrode 1061 on the substrate 101. The first strip common electrode 1061 is electrically connected to the adapter line 107 through the first via V1, and the first strip common electrode line 1061 is electrically connected to the first common electrode line 1051 through the second via V2. The first via V1 and the second via V2 together form a stepped semi-via, which is conducive to the uniform diffusion of the alignment liquid (PI) in the display area (AA) and avoids black mura.

[0081] In some embodiments, as shown in FIG2, 7, 8, 16 and 18, the multiple common electrode lines 105 may further include a second common electrode line 1052. The second common electrode line 1052 is electrically connected to the second strip-shaped common electrode 1062, and the orthographic projection of the second strip-shaped common electrode 1062 on the substrate 101 at least partially overlaps with the orthographic projection of the second common electrode line 1052 on the substrate 101. For example, the orthographic projection of the second strip-shaped common electrode 1062 on the substrate 101 is located within the orthographic projection of the second common electrode line 1052 on the substrate 101. The second common electrode line 1052 and the data line 103 are alternately arranged at different column gaps of the pixel electrode 102. The first strip-shaped common electrode 1061 directly crosses the data line 103. This not only improves the uniformity of VCOM, but also ensures that the pixel load remains basically unchanged.

[0082] In some embodiments, as shown in FIG8, in the array substrate provided in the present disclosure, the second insulating layer 109 may include a third via V3, and the second common electrode line 1052 includes a boss structure 1052'. The boss structure 1052' is electrically connected to the second strip-shaped common electrode 1062 through the third via V3. Optionally, the orthographic projection of the third via V3 on the substrate 101 and the orthographic projection of the base portion PS' on the substrate 101 overlap at least partially. For example, the orthographic projection of the third via V3 on the substrate 101 is located within the orthographic projection of the base portion PS' on the substrate 101, and the orthographic projection of the boss structure 1052' on the substrate 101 covers the orthographic projection of the third via V3 on the substrate 101 and is located within the orthographic projection of the base portion PS' on the substrate 101, so as to avoid setting the boss structure 1052' that carries the third via V3 outside the base portion PS', thereby saving non-opening area space and improving pixel transmittance.

[0083] It is worth noting that in some embodiments, as shown in Figures 3, 5, 9 and 20, the second common electrode line 1052 can be omitted. In this case, the spacing between the two pixel electrodes 102 between the two data lines 103 can be reduced, thereby improving pixel transmittance.

[0084] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 1 to 5, 10, 11, 13, 15, 16, and 18 to 21, may further include a plurality of transistors 110, a plurality of connection structures 111, and a plurality of compensation structures 112 located at the row gaps of the pixel electrodes 102; wherein, two transistors 110 are provided at the same row gap between two adjacent data lines 103; one transistor 110 is electrically connected to the pixel electrode 102 through the connection structure 111, and the other transistor 110 is electrically connected to the compensation structure 111 and the pixel electrode 102, and the two pixel electrodes 102 electrically connected by the two transistors 110 are located in adjacent rows and adjacent columns. Optionally, the orthographic projections of the connection structure 111 and the compensation structure 112 on the substrate 101 intersect each other with the orthographic projections of the second strip-shaped common electrode 1062 on the substrate 101, and portions of the connection structure 111 and the compensation structure 112 are arranged approximately symmetrically about the first strip-shaped common electrode 1061 on both sides of the dual gate. This configuration ensures that the lateral capacitance of the connection structure 111 and the gate line 104 is approximately equal to the lateral capacitance of the compensation structure 112 and the gate line 104, and that the storage capacitance of the connection structure 111 and the second strip common electrode 1061 is approximately equal to the storage capacitance of the compensation structure 112 and the second strip electrode 1061. This results in the charging rates of different pixel electrodes 102 being approximately the same, which is beneficial for improving display quality.

[0085] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 1 to 5, 10, 15, 18, 19, and 21, the common electrode 106 may further include multiple third strip-shaped common electrodes 1063. The third strip-shaped common electrodes 1063 and the data line 103 are located at the same column gap of the pixel electrode 102. Optionally, at least some of the third strip-shaped common electrodes 1063 are located between two adjacent pixel electrodes 102 arranged along the row direction, for example, in Figures 1 to 21. 3. In Figures 10, 15, and 18, all third strip-shaped common electrodes 1063 are located between two adjacent pixel electrodes 102 arranged along the row direction. In Figures 4, 5, 10, 19, and 21, the third strip-shaped common electrode 1063 on one side of the data line 103 is located between two adjacent pixel electrodes 102 arranged along the row direction, and the third strip-shaped common electrode 1063 on the other side of the data line 103 penetrates the column gaps of the pixel electrodes 102 and intersects with the first strip-shaped common electrode 1061. On the one hand, the third strip-shaped common electrode 1063 penetrating the column gaps of the pixel electrodes 102 increases the density of the common electrode network, which can enhance the voltage uniformity of the common electrode network. On the other hand, the second strip-shaped common electrode 1062 and the third strip-shaped common electrode 1063 are connected in parallel, which can reduce the resistance of the vertical common electrode and reduce the voltage drop.

[0086] In some embodiments, in the array substrate provided in this disclosure, the active layer AC can share the same mask as the source / drain metal layer. In this case, as shown in Figures 12, 13, 16, 20, 22, and 23, the active layer AC may include a first electrode line corresponding to and directly contacting the data line 103, the common electrode line 105 (including the first common electrode line 1051 and / or the second common electrode line 1052), the first electrode S, and the second electrode D of the transistor 110, respectively. The orthogonal projections of the first patterns 103', 105' (including 1051' and / or 1052'), S', and D' on the substrate 101 can substantially coincide with the orthogonal projections of the data lines 103 and 105' (including the first common electrode line 1051 and / or the second common electrode line 1052) of the source and drain metal layers, the first electrode S of the transistor 110, and the second electrode D of the transistor 110 on the substrate 101.

[0087] In some embodiments, in the array substrate provided in the present disclosure, the layer where the pixel electrode 102 is located can share the same mask as the gate metal layer. Therefore, as shown in FIG10 and FIG11, the layer where the pixel electrode 102 is located can include second patterns 104', 107', G', 111', and 112' that correspond to and directly contact the gate line 104, the adapter line 107, the gate G of the transistor 110, the connection structure 111, and the compensation structure 112 of the gate metal layer, respectively. Optionally, the orthographic projection of the second patterns 104', 107', G', 111', and 112' on the substrate 101 can substantially coincide with the orthographic projection of the gate line 104, the adapter line 107, and the gate G of the transistor 110 on the substrate 101.

[0088] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the error allowance, it is within the protection scope of this disclosure.

[0089] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 1 to 5, 10, and 13 to 21, the first electrode S of transistor 110 can be integrally disposed with data line 103, and the second electrode D of transistor 110 can be electrically connected to pixel electrode 102 through transition electrode 113 of the layer where common electrode 106 is located. Optionally, transition electrode 113 is electrically connected to pixel electrode 102 and the second electrode D of transistor 110 through a fourth via V4. The fourth via V4 penetrates the first insulating layer 108 and the second insulating layer 109 at the overlap with pixel electrode 102, and penetrates the second insulating layer 109 at the overlap with the second electrode D of transistor 110. Other essential components in the array substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on the present disclosure.

[0090] Based on the same inventive concept, this disclosure provides a display panel. Figures 24 and 25 are schematic diagrams of a structure of the display panel provided in this disclosure. As shown in Figures 24 and 25, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 opposite to the array substrate 001. The counter substrate 002 includes spacers PS. The orthographic projection of the end of the spacers PS facing the array substrate 001 on the substrate 101 overlaps with the orthographic projection of the base portion PS' on the substrate 101. Optionally, the orthographic projection of the end of the spacers PS facing the array substrate 001 on the substrate 101 is located within the orthographic projection of the base portion PS' on the substrate 101. It should be noted that when not compressed, the spacer PS, as the main spacer (Main PS), can contact the array substrate 001, while the spacer PS, as the auxiliary spacer (Sub PS), has a certain gap with the array substrate 001. When compressed, the spacer PS, as the main spacer (Main PS), is compressed, and the spacer PS, as the auxiliary spacer (Sub PS), contacts the array substrate 001. Furthermore, since the principle by which this display panel solves the problem is similar to that of the array substrate described above, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be elaborated further. Optionally, PS can also be disposed on the array substrate; this is not limited here.

[0091] In some embodiments, as shown in Figures 24 and 25, in the display panel provided in the present disclosure, a liquid crystal layer 003 may be disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0092] Based on the same inventive concept, this disclosure provides a display device. Figures 26 and 27 are schematic diagrams of a structure of the display device provided in this disclosure. As shown in Figures 26 and 27, the display device provided in this disclosure may include the display panel PNL provided in this disclosure, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0093] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0094] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a television, monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0095] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0096] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, The display panel comprises: a substrate; a plurality of pixel electrodes arranged in an array on the substrate; a plurality of data lines extending at part of column gaps of the pixel electrodes; a plurality of gate lines extending at row gaps of the pixel electrodes, each row gap comprising two gate lines; a plurality of common electrode lines extending at the gaps of the pixel electrodes, the common electrode lines being arranged in the same layer as the data lines and being spaced apart from the data lines, the common electrode lines comprising abutment portions for supporting spacers, and a projection of the abutment portions on the substrate being located between projections of the two gate lines on the substrate.

2. The array substrate of claim 1, wherein, The display panel further comprises a common electrode electrically connected to the plurality of common electrode lines, the common electrode comprising a first strip-shaped common electrode and a second strip-shaped common electrode which are cross and integrally arranged; wherein a projection of the first strip-shaped common electrode on the substrate is located between the projections of the two gate lines on the substrate, and the second strip-shaped common electrode is alternately arranged with the data lines at different column gaps of the pixel electrodes.

3. The array substrate of claim 2, wherein, The plurality of common electrode lines comprises a first common electrode line, the first common electrode line is electrically connected to the first strip-shaped common electrode, and a projection of the first strip-shaped common electrode on the substrate at least partially overlaps with a projection of the first common electrode line on the substrate.

4. The array substrate of claim 3, wherein, The display panel further comprises a transfer line arranged in the same layer as the plurality of gate lines, the transfer line being connected between two adjacent first strip-shaped common electrodes.

5. The array substrate of claim 4, wherein, The display panel further comprises a first insulating layer between a layer where the plurality of data lines are located and a layer where the plurality of gate lines are located, and a second insulating layer between a layer where the plurality of data lines and the common electrode are located; wherein the first insulating layer and the second insulating layer comprise a first via hole arranged through, a projection of the first via hole on the substrate partially overlaps with a projection of the transfer line on the substrate; the second insulating layer comprises a second via hole arranged in conduction with the first via hole, a projection of the second via hole on the substrate partially overlaps with a projection of the first strip-shaped common electrode on the substrate; the first strip-shaped common electrode is electrically connected to the transfer line through the first via hole, and the first strip-shaped common electrode line is electrically connected to the first common electrode line through the second via hole.

6. The array substrate according to any one of claims 2 to 5, wherein, The plurality of common electrode lines further comprises a second common electrode line, the second common electrode line is electrically connected to the second strip-shaped common electrode, and a projection of the second strip-shaped common electrode on the substrate at least partially overlaps with a projection of the second common electrode line on the substrate.

7. The array substrate of claim 6, wherein, The display panel further comprises a second insulating layer between the layer where the plurality of data lines are located and the layer where the common electrode is located, the second insulating layer comprises a third via hole, and the second common electrode line is electrically connected to the second strip-shaped common electrode through the third via hole.

8. The array substrate of claim 7, wherein, A projection of the third via hole on the substrate at least partially overlaps with a projection of the abutment portion on the substrate.

9. The array substrate of claim 7 or 8, wherein, The second strip-shaped common electrode comprises a boss structure, a normal projection of the boss structure on the substrate substrate covers a normal projection of the third via on the substrate substrate and is located within a normal projection of the base on the substrate substrate.

10. The array substrate according to any one of claims 2 to 9, wherein, Further comprising a plurality of transistors and a plurality of connection structures at the row gaps of the pixel electrodes; wherein, The normal projection of the connection structure on the substrate substrate and the normal projection of the second strip-shaped common electrode on the substrate substrate intersect each other; Between the two adjacent data lines, two transistors are provided at the same row gap of the pixel electrode; one of the transistors is electrically connected to the pixel electrode through the connection structure.

11. The array substrate of claim 10, wherein, Further comprising a plurality of compensation structures at the row gaps of the pixel electrodes, the compensation structures are electrically connected to the transistors which do not correspond to the connection structures, and the normal projection of the compensation structures on the substrate substrate and the normal projection of the second strip-shaped common electrode on the substrate substrate intersect each other, and part of the connection structure and the compensation structure are arranged on both sides of the two gate lines about the first strip-shaped electrode.

12. The array substrate of claim 10 or 11, wherein, Further comprising a first pattern in the same layer as the active layer of the transistor, the normal projection of the first pattern on the substrate substrate and the normal projection of the pattern in the layer where the data line is located on the substrate substrate substantially coincide.

13. The array substrate according to any one of claims 2 to 12, wherein, The common electrode further comprises a plurality of third strip-shaped common electrodes, which are located at the same column gaps of the pixel electrodes as the data lines.

14. The array substrate of claim 13, wherein, At least part of the third strip-shaped common electrode is located between the two adjacent pixel electrodes arranged in the row direction.

15. The array substrate of claim 14, wherein, The third strip-shaped common electrode on one side of the data line is located between the two adjacent pixel electrodes arranged in the row direction, and the third strip-shaped common electrode on the other side of the data line penetrates the column gap of the pixel electrode and intersects the first strip-shaped common electrode.

16. The array substrate of any one of claims 1 to 15, wherein, Further comprising a second pattern in the same layer as the pixel electrode, the normal projection of the second pattern on the substrate substrate and the normal projection of the pattern in the layer where the gate line is located on the substrate substrate substantially coincide.

17. A display panel, wherein, Comprise an array substrate and a counter substrate opposite to each other; wherein, The array substrate is the array substrate according to any one of claims 1-16; The counter substrate comprises a spacer, and a normal projection of an end of the spacer towards the array substrate on the substrate substrate and a normal projection of the base on the substrate substrate overlap each other.

18. A display device, wherein, The display panel comprises the display panel according to claim 17, and a backlight module located on the light entering side of the display panel.

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