Chip stack and package structure and manufacturing method therefor

Abstract

Provided are a chip stack and package structure and a manufacturing method therefor. The manufacturing method for the chip stack and package structure comprises the following steps: providing a carrier substrate (1) and sequentially forming a first wiring layer (2) and first pillars (21) on the carrier substrate (1); forming, on the upper surface of the first wiring layer (2), a stacked structure (3) comprising stacked first and second stack structures (31, 32), wherein the first and second stack structures (31, 32) respectively comprise first chips (311) stacked in a misaligned manner and a first electrode pillar (312), and second chips (321) stacked in a misaligned manner and a second electrode pillar (322); providing a transfer board (4) having second pillars (41) formed on the bottom surface thereof, and electrically connecting the first and second pillars (21, 41) and removing the transfer board (4); forming a package layer (5) and thinning the package layer (5); forming a second wiring layer (6) on the upper surface of the package layer (5); and forming a protective layer (8) covering the exposed upper surface of the second wiring layer (6), removing the carrier board (1) and forming conductive bumps (24). The first and second chips (311, 321) in the stacked structure (3) each are stacked in a misaligned manner, and are bonded with the first and second wiring layers (2, 6) and the first and second pillars (21, 41), thereby reducing the process difficulty and the manufacturing costs while implementing interconnection between the chips.

Description

Chip stacked packaging structure and its fabrication method Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a chip stacking packaging structure and its manufacturing method. Background Technology

[0002] High-bandwidth memory (HBM) is widely used in high-performance graphics cards, GPU accelerators, and high-performance computing requiring large amounts of data transfer due to its large capacity and high bandwidth. It is typically formed by vertically stacking multiple dynamic random access memory (DRAM) chips to form a three-dimensional vertical stacked chip, as shown in Figure 1, which is a schematic diagram of the structure of an HBM memory chip, including the bottom DRAM chip 01, the stacked DRAM chip 02, the interconnect copper pillars 03, and the lead-out bumps 04. The DRAM chips in the HBM memory chip (i.e., the bottom DRAM chip 01 and the stacked DRAM chip 02) are generally interconnected and stacked through a combination of through silicon via (TSV) technology (i.e. the process of forming the interconnect copper pillars 03) and thermo-press bonding (TCB) or hybrid bonding. The vias in each DRAM chip are small in size and dense in density, which makes the fabrication and filling of the vias difficult, thus making the fabrication of the stacked chip difficult, with low yield and high cost.

[0003] Therefore, there is an urgent need to find a chip stacking packaging structure that reduces the difficulty and cost of stacked chip manufacturing while improving the yield of stacked chip manufacturing. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a chip stacking packaging structure and its manufacturing method, so as to solve the problems of high manufacturing difficulty, high manufacturing cost and low manufacturing yield of HBM memory chips in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a chip stacked packaging structure, comprising the following steps:

[0006] A carrier plate is provided, on the upper surface of the carrier plate a first wiring layer and a first pillar located on the upper surface of the first wiring layer;

[0007] A stacked structure comprising a first stacked structure and a second stacked structure are formed on the upper surface of the first wiring layer. The upper surface of the stacked structure is not lower than the upper surface of the first pillar. The first stacked structure includes at least two staggered stacked first chips and a first electrode pillar electrically connected to the first chip and the first wiring layer. The second stacked structure includes at least two staggered stacked second chips and a second electrode pillar extending along the stacking direction.

[0008] A transfer plate is provided with a bottom surface forming a second column that corresponds one-to-one with the first column, and the height of the second column is not less than the height of the stacked structure exceeding the first column. The bottom of the second column is fixedly electrically connected to the top of the first column and the transfer plate is removed.

[0009] An encapsulation layer is formed covering the stacked structure, the exposed surfaces of the first pillar and the second pillar, and the upper surface of the first wiring layer, and the encapsulation layer is thinned to expose the second pillar and the second electrode pillar;

[0010] A second wiring layer electrically connected to the second pillar and the second electrode pillar is formed on the upper surface of the encapsulation layer to obtain an encapsulation unit including the first pillar, the second pillar, the stacked structure, the encapsulation layer and the second wiring layer;

[0011] A protective layer is formed covering the exposed upper surface of the second wiring layer, the carrier plate is removed, and a conductive bump electrically connected to the first wiring layer is formed on the side of the first wiring layer opposite to the stacked structure.

[0012] Optionally, the number of the first chips in the first stacked structure is the same as the number of the second chips in the second stacked structure.

[0013] Optionally, the upper surface of the first stacked structure is not higher than the upper surface of the first pillar.

[0014] Optionally, the first chips in the first stacked structure are not completely identical; the second chips in the second stacked structure are not completely identical.

[0015] Optionally, before forming the protective layer and after forming the second wiring layer, the method further includes forming the package unit at least once on the upper surface of the second wiring layer.

[0016] Optionally, the package unit is formed on the upper surface of the second wiring layer adjacent to the first wiring layer. In the package unit on the upper surface of the second wiring layer, the first electrode post of the first stack structure is electrically connected to the second wiring layer adjacent to the first stack structure below.

[0017] Optionally, before forming the protective layer and after forming the second wiring layer, the method further includes the step of forming a third stacked structure electrically connected to the second wiring layer on the upper surface of the second wiring layer, and the protective layer covers the exposed surface of the third stacked structure.

[0018] Optionally, the third stacking structure includes at least two third chips stacked upwards in a staggered manner and a third electrode post electrically connected to each of the third chips. The third electrode post extends in a manner away from the stacking of the third chips and is electrically connected to the second wiring layer below the third stacking structure.

[0019] Optionally, the thickness of the third stacked structure is greater than the thickness of the first stacked structure.

[0020] The present invention also provides a chip stacking package structure, which is fabricated using the chip stacking package structure fabrication method described above.

[0021] As described above, the chip stacking packaging structure and its manufacturing method of the present invention improve the packaging structure by stacking multiple first chips and multiple second chips in a staggered manner to form a first stacking structure and a second stacking structure together to form a layered structure. A first electrode post electrically connected to the first chip is led from the staggered region along a direction away from the first chip stack to the first wiring layer, and a second electrode post electrically connected to the second chip is led from the staggered region along the second chip stack direction to the second wiring layer. These are then combined with the first post, the second post, the first wiring layer, and the second wiring layer. This achieves interconnection between chips in the three-dimensional stacked packaging structure without forming through-hole interconnect structures on the chips, reducing process difficulty, manufacturing costs, and improving the yield of the packaging structure. The first and second posts are fixedly electrically connected to achieve electrical connection between the first and second wiring layers, which are located above and below the layered structure, respectively. This limits the thickness of the layered structure to the sum of the process limits of the heights of the first and second posts, increasing the thickness of the layered structure and consequently increasing the number of chips that can be stacked in the layered structure, thus possessing high industrial application value. Attached Figure Description

[0022] Figure 1 shows a schematic diagram of the structure of an HBM memory chip.

[0023] Figure 2 shows a process flow diagram of the fabrication method of the chip stacked packaging structure of the present invention.

[0024] Figure 3 shows a cross-sectional view of the chip stacking package structure after the formation of the first wiring layer in the method of fabricating the chip stacking package structure of the present invention.

[0025] Figure 4 shows a cross-sectional view of the chip stacking packaging structure after the formation of the first pillar in the manufacturing method of the present invention.

[0026] Figure 5 shows a cross-sectional view of the chip stacked packaging structure after the stacked structure is formed, according to the method of manufacturing the chip stacked packaging structure of the present invention.

[0027] Figure 6 shows a cross-sectional view of the chip stacking packaging structure fabrication method of the present invention after the first pillar and the second pillar are electrically connected.

[0028] Figure 7 shows a schematic diagram of the removal of the transfer plate in the method for fabricating the chip stacked packaging structure of the present invention.

[0029] Figure 8 shows a cross-sectional view of the chip stacking packaging structure after the packaging layer is formed, according to the method of manufacturing the chip stacking packaging structure of the present invention.

[0030] Figure 9 shows a cross-sectional view of the chip stacking packaging structure fabrication method of the present invention after thinning the packaging layer.

[0031] Figure 10 shows a cross-sectional view of the chip stacking package structure fabrication method of the present invention after the formation of the second wiring layer.

[0032] Figure 11 shows a cross-sectional view of the chip stacking packaging structure fabrication method of the present invention after forming the third stacked structure.

[0033] Figure 12 shows a cross-sectional view of the chip stacking packaging structure of the present invention after the protective layer is formed.

[0034] Figure 13 shows a cross-sectional view of the chip stacking package structure fabrication method of the present invention after the formation of conductive bumps.

[0035] Reference numerals: 01 Bottom DRAM Chip; 02 Stacked DRAM Chips; 03 Interconnect Copper Pillars; 04 Lead-out Bumps; 1 Carrier Board; 2 First Wiring Layer; 21 First Pillar; 22 First Dielectric Layer; 23 First Interconnect Layer; 24 Conductive Bumps; 3 Stacked Structure; 31 First Stacked Structure; 311 First Chip; 312 First Electrode Pillar; 32 Second Stacked Structure; 321 Second Chip; 322 Second Electrode Pillar; 33 Third Stacked Structure; 331 Third Chip; 332 Third Electrode Pillar; 4 Relay Board; 41 Second Pillar; 5 Encapsulation Layer; 6 Second Wiring Layer; 61 Second Dielectric Layer; 62 Second Interconnect Layer; 7 Third Stacked Structure; 71 Third Chip; 72 Third Electrode Pillar; 8 Protective Layer. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Please refer to Figures 2 to 13. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the figures only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] Example 1

[0039] This embodiment provides a method for fabricating a chip stacked package structure. As shown in Figure 2, which is a process flow diagram of the method for fabricating the chip stacked package structure, the method includes the following steps:

[0040] S1: A carrier plate is provided, on the upper surface of the carrier plate a first wiring layer and a first pillar located on the upper surface of the first wiring layer;

[0041] S2: A stacked structure including a first stacked structure and a second stacked structure are formed on the upper surface of the first wiring layer. The upper surface of the stacked structure is not lower than the upper surface of the first pillar. The first stacked structure includes at least two staggered stacked first chips and a first electrode pillar electrically connected to the first chip and the first wiring layer. The second stacked structure includes at least two staggered stacked second chips and a second electrode pillar extending along the stacking direction.

[0042] S3: Provide a transfer plate with a bottom surface forming a second column corresponding to the first column, and the height of the second column is not less than the height of the stacked structure exceeding the first column. Fix the bottom of the second column to the top of the first column and remove the transfer plate.

[0043] S4: Form an encapsulation layer covering the stacked structure, the exposed surfaces of the first pillar and the second pillar, and the upper surface of the first wiring layer, and thin the encapsulation layer to expose the second pillar and the second electrode pillar;

[0044] S5: A second wiring layer electrically connected to the second pillar and the second electrode pillar is formed on the upper surface of the encapsulation layer to obtain an encapsulation unit including the first pillar, the second pillar, the stacked structure, the encapsulation layer and the second wiring layer;

[0045] S6: Form a protective layer covering the exposed upper surface of the second wiring layer, remove the carrier plate, and form a conductive bump electrically connected to the first wiring layer on the side of the first wiring layer opposite to the stacked structure.

[0046] Please refer to Figures 3 to 7 and perform steps S1, S2, and S3: Provide a carrier plate 1, form a first wiring layer 2 and a first pillar 21 located on the upper surface of the first wiring layer 2 on the carrier plate 1; form a stacked structure 3 on the upper surface of the first wiring layer 2, including a first stacked structure 31 and a second stacked structure 32 stacked sequentially, the upper surface of the stacked structure 3 is not lower than the upper surface of the first pillar 21, the first stacked structure 31 includes at least two staggered stacked first chips 311 and a first electrode pillar 312 electrically connecting the first chips 311 and the first wiring layer 2, the second stacked structure 32 includes at least two staggered stacked second chips 321 and a second electrode pillar 322 extending along the stacking direction; provide a transfer plate 4 with a bottom surface forming a second pillar 41 corresponding one-to-one with the first pillar 21, and the height of the second pillar 41 is not less than the height of the stacked structure 3 exceeding the first pillar 21, fix the bottom of the second pillar 41 to the top of the first pillar 21 and remove the transfer plate 4.

[0047] Specifically, the carrier board 1 is used as a process platform for fabricating the first wiring layer 2, which facilitates the transfer of the unpackaged structure to each process segment during the subsequent fabrication of the packaging structure. The carrier board 1 is made of materials including glass, ceramic, metal, organic polymer, semiconductor or other suitable materials.

[0048] Specifically, before forming the first wiring layer 2, the process also includes forming a first adhesive layer of a predetermined thickness on the upper surface of the carrier plate 1.

[0049] Specifically, the first adhesive layer can be obtained by sticking tape on the carrier plate 1, or by coating the carrier plate 1 with a polymer material and curing it. The first adhesive layer is a peelable material under specific conditions. By forming a first adhesive layer on the carrier plate 1 before forming the first wiring layer 2, it is easier to remove the carrier plate in the future.

[0050] Specifically, as shown in Figure 3, which is a cross-sectional structural diagram after the formation of the first wiring layer 2, the first wiring layer 2 includes at least one first dielectric layer 22 and at least one first interconnect layer 23, and the first pillar 21 is electrically connected to the first interconnect layer 23.

[0051] Specifically, the methods for forming the first dielectric layer 22 include chemical vapor deposition, physical vapor deposition, transfer molding, liquid encapsulation, vacuum lamination, spin coating, or other suitable methods; the methods for forming the first interconnect layer 23 include chemical vapor deposition, physical vapor deposition, sputtering, electroplating, electroless plating, or other suitable methods.

[0052] Specifically, as shown in Figure 4, which is a cross-sectional structural diagram after the formation of the first pillar 21, the formation of the first pillar 21 includes the following steps: forming a masking layer of a preset thickness on the upper surface of the first wiring layer, and patterning the masking layer to form a through hole in the masking layer; forming the first pillar 21 that fills the through hole.

[0053] Specifically, the masking layer is a commonly used photoresist layer, and the method for forming vias by patterning the masking layer is a commonly used photoresist patterning process, which will not be elaborated here.

[0054] Specifically, the first pillars 21 are arranged in a predetermined manner to facilitate subsequent interconnection between chips. The method for forming the first pillars 21 that fill the vias includes chemical vapor deposition, physical vapor deposition, evaporation, sputtering, electroplating, electroless plating, or other suitable methods.

[0055] Specifically, the height of the first pillar 21 is related to the thickness of the shielding layer, the size of the vias in the shielding layer (affecting the filling of the vias), and the via filling process. While ensuring the performance of the packaging structure, the height of the first pillar 21 can be selected according to the actual situation, and is not limited here. In this embodiment, since the thickest photoresist layer (shielding layer) currently used to fabricate conductive pillars can only reach 240 μm, the height of the first pillar 21 can only reach 220 μm.

[0056] Specifically, after forming the first pillar 21, the process also includes removing the masking layer. In this embodiment, since a photoresist layer is used as the masking layer, the removal of the masking layer also employs a commonly used photoresist stripping process.

[0057] Specifically, as shown in Figure 5, which is a cross-sectional view of the stacked structure 3, the stacked structure 3 is formed on the upper surface of the first wiring layer 2 by fixing the first electrode post 312 to the first wiring layer 2 electrically. The method for fixing the first electrode post 312 to the first wiring layer 2 electrically includes soldering, bonding, or other suitable methods. In this embodiment, soldering is used to fix the first electrode post 312 to the first wiring layer 2 electrically.

[0058] Specifically, while ensuring the performance of the packaging structure, the number, size, shape, and type of the first chip 311 in the first stacking structure 31 can be selected according to the actual situation, and are not limited here; the number, size, shape, and type of the second chip 321 in the second stacking structure 32 can be selected according to the actual situation, and are not limited here. In this embodiment, the first stacking structure 31 consists of two first chips 311 stacked together upwards, and its electrodes (i.e., the first electrode posts) extend downwards; the second stacking structure 32 consists of two second chips 321 stacked together upwards, and its electrodes (i.e., the second electrode posts) extend upwards.

[0059] Specifically, a first adhesive layer and a second adhesive layer are formed between two adjacent first chips 311 and between two adjacent second chips 321, respectively. The first adhesive layer firmly fixes the two adjacent first chips 311 together, and the second adhesive layer firmly fixes the two adjacent second chips 321 together. A third adhesive layer is formed between the first stacked structure 31 and the second stacked structure 32. The third adhesive layer firmly fixes the first chip 311 and the second chip 321 at the junction of the first stacked structure 31 and the second stacked structure 32 together.

[0060] Specifically, the methods for forming the first adhesion layer include die bond film (DAF) bonding, back gold alloying, or other suitable methods; the methods for forming the second adhesion layer include die bond film bonding, back gold alloying, or other suitable methods; and the methods for forming the third adhesion layer include die bond film bonding, back gold alloying, or other suitable methods.

[0061] Specifically, the method for forming each first electrode post 312 in the first stacked structure 31 includes electroplating, metal wire bonding, or other suitable methods; the method for forming each second electrode post 322 in the second stacked structure 32 includes electroplating, metal wire bonding, or other suitable methods.

[0062] Specifically, the first electrode post 312, which is electrically connected to the first chip 311 above the bottom first chip 311, is located on the lower surface of the area where the first chip 311 and the lower first chip 311 are offset (i.e., the area where the first chip 311 and the lower first chip 311 do not overlap). The first electrode post 312 can be formed after the formation of the stacked structure 3 or before the formation of the first stacked structure 31. The second electrode post 322, which is electrically connected to the second chip 321 below the top first chip 321, is located on the lower surface of the area where the second chip 321 and the upper second chip 321 are offset (i.e., the area where the second chip 321 and the upper second chip 321 do not overlap). The second electrode post 322 can be formed after the formation of the stacked structure 3 or before the formation of the second stacked structure 32.

[0063] As an example, the number of first chips 311 in the first stacked structure 31 is the same as the number of second chips 321 in the second stacked structure 32.

[0064] Specifically, while ensuring the performance of the packaging structure, the number of first chips 311 in the first stacked structure 31 can also be different from the number of second chips 321 in the second stacked structure 32.

[0065] As an example, the first chips 311 in the first stacked structure 31 are not completely identical; the second chips 321 in the second stacked structure 32 are not completely identical. Here, "not completely identical" refers to the chip size and chip type being not completely identical.

[0066] Specifically, while ensuring the performance of the packaging structure, the chip type and size of each first chip 311 in the first stacked structure 31 can be completely identical; the chip type and size of each second chip 321 in the second stacked structure 32 can also be completely identical; the chip type and size of the first chip 311 in the first stacked structure 31 can be the same as or different from the chip type and size of the second chip 321 in the second stacked structure 32. In this embodiment, the first chip 311 in the first stacked structure 31 and the second chip 321 in the second stacked structure 32 are both memory chips of the same size.

[0067] Specifically, while ensuring the performance of the packaging structure, the lower surfaces of each first electrode post 312 may or may not be flush; the upper surfaces of each second electrode post 322 may or may not be flush. Preferably, the lower surfaces of each first electrode post 312 are flush, and the upper surfaces of each second electrode post 322 are flush.

[0068] Specifically, while ensuring the performance of the packaging structure, the misalignment size between two adjacent first chips 311 in the first stacking structure 31 can be selected according to the actual situation; the misalignment size between two adjacent second chips 321 in the second stacking structure 32 can be selected according to the actual situation; the two adjacent first chips 311 can be stacked and misaligned in a spiral upward manner or stacked and misaligned in one direction; the two adjacent second chips 321 can be stacked and misaligned in a spiral upward manner or stacked and misaligned in one direction.

[0069] As an example, the upper surface of the first stacked structure 31 is not higher than the upper surface of the first pillar 21 to avoid the height of the first pillar 21 reaching the limit of the manufacturing process. When the height of the second stacked structure 31 exceeds the height of the first pillar 21, it will affect the interconnection between the subsequent first wiring layer 2 and the second wiring layer (see Figure 10 below).

[0070] Specifically, the first pillar 21 is spaced at a preset distance from the stacked structure 3. While ensuring the performance of the encapsulation structure, the distance between the first pillar 21 and the stacked structure 3 can be selected according to the actual situation.

[0071] Specifically, as shown in Figure 6, which is a cross-sectional structural diagram after the first column 21 and the second column 41 are fixedly electrically connected, the upper surface of the first stacked structure 31 can also be higher than the upper surface of the first column 2, provided that the height of the structure after the first column 21 and the second column 41 are electrically connected is greater than that of the stacked structure 3.

[0072] Specifically, a second adhesive layer is provided between the adapter plate 4 and the second post 41 to facilitate the peeling and reuse of the adapter plate 4 after the second post 41 is fixedly electrically connected to the first post 21.

[0073] Specifically, the second adhesive layer can be made of the same material as the first adhesive layer, or they can be different materials.

[0074] Specifically, the material of the adapter plate 4 includes glass, metal, organic polymer, or other suitable materials. In this embodiment, a glass plate is used as the adapter plate 4.

[0075] Specifically, the method for forming the second post 41 on the adapter plate 4 is the same as the method for forming the first post 21, and will not be described again here; after the top of the first post 21 and the bottom of the second post 41 are fixedly electrically connected, the upper surface of the second post 41 is not lower than the upper surface of the second electrode post 322. In this embodiment, the upper surface of the second post 41 is higher than the upper surface of the second electrode post 322 to facilitate the fixed electrical connection of the first post 21 and the second post 41 together.

[0076] Specifically, the method for fixing the first post 2 and the second post 41 to an electrical connection includes soldering, bonding, or other suitable methods. In this embodiment, the bottom of the second post 41 is soldered to the top of the first post 2.

[0077] Specifically, as shown in Figure 7, which is a schematic diagram of removing the transfer plate 4, the transfer plate 4 is usually removed by reducing or dissociating the adhesion of the second adhesive layer under specific conditions. For example, it can be removed by reducing the adhesion and dissociating the second adhesive layer under specific laser irradiation, ultraviolet light irradiation, or heat treatment at a specific temperature.

[0078] Referring again to Figures 8 to 13, perform steps S4, S5, and S6: form an encapsulation layer 5 covering the exposed surfaces of the stacked structure 3, the first pillar 21, and the second pillar 41, and the upper surface of the first wiring layer 2, and thin the encapsulation layer 5 to expose the second pillar 41 and the second electrode pillar 322; form a second wiring layer 6 on the upper surface of the encapsulation layer 5 that is electrically connected to the second pillar 41 and the second electrode pillar 322 to obtain an encapsulation unit including the first pillar 21, the second pillar 41, the stacked structure 3, the encapsulation layer 5, and the second wiring layer 6; form a protective layer 8 covering the exposed upper surface of the second wiring layer 6; remove the carrier plate 1 and form a conductive bump 24 electrically connected to the first wiring layer 2 on the side of the first wiring layer 2 facing away from the stacked structure 3.

[0079] Specifically, as shown in Figure 8, which is a cross-sectional structural diagram after the encapsulation layer 5 is formed, the upper surface of the encapsulation layer 5 is higher than the upper surface of the substrate 4. The methods for forming the encapsulation layer 5 include compression molding, transfer molding, liquid sealing, vacuum lamination, or other suitable methods.

[0080] Specifically, as shown in Figure 9, which is a cross-sectional view of the encapsulation layer 5 after thinning, the methods for thinning the encapsulation layer 5 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods. In this embodiment, chemical mechanical polishing is used to thin the encapsulation layer 5 from its upper surface.

[0081] Specifically, when the upper surface of the second pillar 41 is higher than the upper surface of the second electrode pillar 322, the second pillar 41 is simultaneously thinned when the encapsulation layer 5 is thinned to the upper surface of the second pillar 41, so that the encapsulation layer 5 exposes the second pillar 41 while simultaneously exposing the second electrode pillar 322. Furthermore, if required by the process, the second electrode pillar 322 can also be thinned simultaneously with the thinning of the second pillar 41 and the encapsulation layer 5, so that the height of the second electrode pillar 322 on the upper surface of the second chip 321 at the top layer of the second stacked structure 32 meets the process requirements.

[0082] Specifically, as shown in Figure 10, which is a cross-sectional structural diagram after the formation of the second wiring layer 6, the second wiring layer 6 includes at least one second dielectric layer 61 and at least one second interconnect layer 62, and the second pillar 41 and each second electrode pillar 322 are electrically connected to the second interconnect layer 62.

[0083] Specifically, the processes for forming the second dielectric layer 61 and the second interconnect layer 62 are the same as those for forming the first dielectric layer 22 and the first interconnect layer 23, and will not be described in detail here.

[0084] Specifically, while ensuring the performance of the packaging structure, the number of layers of the second dielectric layer 61 in the second wiring layer 6 can be the same as or different from the number of layers of the first dielectric layer 22 in the first wiring layer 2; the number of layers of the second interconnect layer 62 in the second wiring layer 6 can be the same as or different from the number of layers of the first interconnect layer 23 in the first wiring layer 2.

[0085] As an example, before forming the protective layer 8 and after forming the second wiring layer 6, the method further includes forming a package body unit at least once on the upper surface of the second wiring layer 6. That is, after forming the second wiring layer 6, based on the performance requirements of the package structure, the package body unit is repeatedly formed on the upper surface of the second wiring layer 6, and the number of times the package body unit is formed can be selected according to actual needs.

[0086] As an example, an encapsulation unit is formed on the upper surface of the second wiring layer 6 adjacent to the first wiring layer 2. In the encapsulation unit on the upper surface of the second wiring layer 6, the first electrode post 312 of the first stacked structure 31 is electrically connected to the second wiring layer 6 adjacent below the first stacked structure 31.

[0087] Specifically, when multiple stacked package units are formed above the bottom package unit, the chip type, number of chips and chip size in each stacked structure of two adjacent package units can be the same as or different from those in each stacked structure of the bottom package unit.

[0088] As an example, as shown in Figure 11, which is a cross-sectional view of the third stacked structure 7 after its formation, before the formation of the protective layer 8 and after the formation of the second wiring layer 6, the method further includes the step of forming the third stacked structure 7 electrically connected to the second wiring layer 6 on the upper surface of the second wiring layer 6, and the protective layer 8 covers the exposed surface of the third stacked structure 7.

[0089] As an example, the third stack structure 7 includes at least two third chips 71 stacked upwards in a staggered manner and a third electrode post 72 electrically connected to each third chip 71. The third electrode post 72 extends in a manner away from the stacking of the third chips 71 and is electrically connected to the second wiring layer 6 below the third stack structure 7.

[0090] Specifically, while ensuring the performance of the packaging structure, the number, size, shape and type of the third chip 71 in the third stacking structure 7 can be selected according to the actual situation, and are not restricted here; the size and shape of the staggered area between two adjacent third chips 71 in the third stacking structure 7 can be selected according to the actual situation; the size and shape of each third chip 71 in the third stacking structure 7 can be selected according to the actual situation; the third chips 71 in the third stacking structure 7 can be stacked staggered in a spiral upward shape, or they can be stacked staggered in one direction.

[0091] Specifically, a third adhesive layer is formed between any two adjacent third chips 71 in the third stack structure 7, which is used to stack and fix the two adjacent third chips 71 together in a staggered manner. The third adhesive layer has the same properties as the first adhesive layer and the second adhesive layer, which will not be described in detail here.

[0092] Specifically, the bottom surfaces of each third electrode post 72 are flush. In two adjacent staggered stacked third chips 71, the third electrode post 72 electrically connected to the upper third chip 71 is located below the staggered area of ​​the third chip 71, and the third electrode post 72 electrically connected to the bottom third chip 71 is located below the bottom surface of the third chip 71.

[0093] Specifically, the method for forming the third electrode post 72 is the same as the method for forming the first electrode post 312, and will not be described again here.

[0094] Specifically, the method for electrically connecting the third electrode post 72 to the second wiring layer 6 includes soldering, bonding, or other suitable methods.

[0095] As an example, the thickness of the third stacked structure 7 is greater than the thickness of the first stacked structure 31.

[0096] Specifically, since no interconnecting conductive pillars are required around the third stacked structure 7, the thickness of the third stacked structure 7 can be less than the thickness of the first stacked structure 31 while ensuring the performance of the packaging structure.

[0097] Specifically, if required by the packaging structure, before forming the protective layer 8 and after forming the second wiring layer 6, other chips or packages electrically connected to the second wiring layer 6 can also be formed on the upper surface of the second wiring layer 6.

[0098] Specifically, as shown in Figure 12, which is a cross-sectional structural diagram after the formation of the protective layer 8, the methods for forming the protective layer 8 include chemical vapor deposition, physical vapor deposition, compression molding, transfer molding, liquid encapsulation, vacuum lamination, or other suitable methods. In this embodiment, before forming the protective layer 8 and after forming the second wiring layer 6, a third stacked structure 7 is formed on the upper surface of the second wiring layer 6. The protective layer 8 that encapsulates the exposed surface of the third stacked structure 7 and the exposed upper surface of the second wiring layer 6 is the same as the encapsulation layer 5.

[0099] Specifically, the peeling process of the carrier plate is determined by the material properties of the first adhesive layer. For example, if the first adhesive layer is a high-temperature heat-release adhesive, the carrier plate can be removed through a high-temperature process, and there are no further restrictions on the peeling process.

[0100] Specifically, as shown in Figure 13, which is a cross-sectional view of the conductive bump 24 after it has been formed, the method of forming the conductive bump 24 includes reflow soldering, ball bonding or other suitable methods.

[0101] Specifically, by stacking multiple first chips 311 in a staggered manner to form a first stacking structure 31, and forming a first electrode post 312 on the side of the staggered area between two adjacent first chips 311 away from the stacking direction, and simultaneously stacking multiple second chips 321 in a staggered manner to form a second stacking structure 32, and forming a second electrode post 322 on the side of the staggered area between two adjacent second chips 321 along the stacking direction, the first stacking structure 31 and the second stacking structure 32 are stacked together, with the first electrode post 312 and the second electrode post 322 extending in opposite directions, and the stacked layer structure 3 is combined with the first wiring layer 2, the first post 21, the second post 41 and the second wiring layer 6, the interconnection between chips in the three-dimensional stacked packaging structure can be achieved without forming a through-hole interconnect structure on the chip, which reduces the process difficulty and the manufacturing cost of the packaging structure, and improves the yield of the packaging structure.

[0102] Specifically, since the stacked structure 3 is formed in the area between the first pillars 21, the structure after the first pillars 21 and the second pillars 41 are electrically connected, the first wiring layer 2 electrically connected to the first stacked structure 31 and the second wiring layer 6 electrically connected to the second stacked structure 32 can be the sum of the process limits of the stacked structure 3 to reach the height of the first pillars 21 and the second pillars 41, thereby increasing the thickness of the stacked structure 3 and thus increasing the number of chips that can be stacked in the stacked structure 3.

[0103] The chip stacking packaging structure fabrication method of this embodiment involves stacking multiple first chips 311 in a staggered manner, forming a first electrode post 312 on the side of the staggered area between two adjacent first chips 311 away from the stacking direction, and simultaneously stacking multiple second chips 321 in a staggered manner to form a second stacking structure 32. Then, a second electrode post 322 is formed on the side of the staggered area between two adjacent second chips 321 along the stacking direction. The first stacking structure 31 and the second stacking structure 32 are then stacked together, with the first electrode post 312 and the second electrode post 322 extending in opposite directions. The stacked layer structure 3 is then combined with the first wiring layer 2, the first post 21, the second post 41, and the second wiring layer 6. This method achieves interconnection between chips in a three-dimensional stacked packaging structure without forming through-hole interconnection structures on the chips, reducing the process difficulty and the manufacturing cost of the packaging structure, and improving the yield of the packaging structure. Furthermore, due to the structural limitations of the package unit, the thickness of the stacked structure is limited by the sum of the process limits of the heights of the first pillar 21 and the second pillar 41, which greatly increases the thickness of the stacked structure 3, thereby increasing the number of chips that can be stacked in the stacked structure 3.

[0104] Example 2

[0105] This embodiment provides a chip stacking package structure, as shown in Figure 13, which is a cross-sectional view of the chip stacking package structure. The chip stacking package structure is fabricated using the chip stacking package structure fabrication method described in Embodiment 1.

[0106] Specifically, the chip stacked packaging structure includes a first wiring layer 2, a package unit, a protective layer 8, and conductive bumps 24. The package unit includes a first pillar 21, a second pillar 41, a stacked structure 3, a package layer 5, and a second wiring layer 6. The first pillar is located on the upper surface of the first wiring layer 6 and is electrically connected to it. The stacked structure 3 includes a first stacked structure 31 and a second stacked structure 32 stacked sequentially. The first stacked structure 31 includes at least two staggered first chips 311 and a first electrode pillar 312 electrically connecting the first chips 311 to the first wiring layer 2. The second stacked structure 32 includes at least two staggered second chips 311. 21 and a second electrode post 322 extending along the stacking direction and electrically connected to the second wiring layer 6, the bottom of the second post 41 being fixedly electrically connected to the top of the first post 21, the encapsulation layer 5 covering the exposed surfaces of the first post 21, the second post 41 and the stacked structure 3 and the upper surface of the first wiring layer 6, the upper surface of the encapsulation layer 5 exposing the upper surfaces of the second post 41 and the second electrode post 322, the second wiring layer 6 covering the upper surface of the encapsulation layer 5 and electrically connected to the second post 41 and the second electrode post 322; the protective layer 8 covering the exposed upper surface of the second wiring layer 6; the conductive bump 24 located on the side of the first wiring layer 2 away from the package unit and electrically connected to the first wiring layer 2.

[0107] Specifically, the first wiring layer 2 includes at least one first dielectric layer 22 and at least one first interconnect layer 23, and the first pillar 21 is electrically connected to the first interconnect layer 23; the material of the first dielectric layer 22 includes epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorinated glass or other suitable materials; the material of the first conductive layer 23 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver or other suitable conductive materials.

[0108] Specifically, the material of the first pillar 21 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver or other suitable conductive materials; the material of the second pillar 41 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver or other suitable conductive materials.

[0109] Specifically, when the first column 2 and the second column 41 are welded together with solder, a welding layer is provided between the first column 2 and the second column 41. The material of the welding layer includes copper, aluminum, nickel, gold, silver, tin, titanium or other suitable welding materials.

[0110] Specifically, in the first stacked structure 31, a first adhesion layer is also provided between two adjacent first chips 311. When the two adjacent first chips 311 are fixed by a die-bonding adhesive film process, the material of the first adhesion layer is a die-bonding adhesive film. When the two adjacent first chips 311 are fixed by a back-gold alloying process, the first adhesion layer is an alloy layer formed by alloying semiconductor material and metal at the interface of the two adjacent first chips 311. In the second stacked structure 32, a second adhesion layer is also provided between two adjacent second chips 321. When the two adjacent second chips 321 are fixed by a die-bonding adhesive film process, the material of the second adhesion layer is a die-bonding adhesive film. When the two adjacent second chips 321 are fixed by a back-gold alloying process, the material of the second adhesion layer is a die-bonding adhesive film. When fixing two adjacent second chips 321, the second adhesive layer is an alloy layer made of semiconductor material and metal alloyed at the interface of the two adjacent second chips 321; a third adhesive layer is also provided at the interface between the first stacked structure 31 and the second stacked structure 32. When the die bond adhesive process is used to fix the adjacent first chip 311 and second chip 321 at the interface, the material of the third adhesive layer is die bond adhesive film. When the back gold alloying process is used to fix the adjacent first chip 31 and second chip 321 at the interface, the third adhesive layer is an alloy layer made of semiconductor material and metal alloyed at the interface between the adjacent first chip 311 and second chip 321.

[0111] Specifically, the lower surfaces of each first electrode post 312 are flush, and the material of the first electrode post 312 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver or other suitable conductive materials; the upper surfaces of each second electrode post 322 and the second post 41 are flush, and the material of the second electrode post 322 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver or other suitable conductive materials.

[0112] Specifically, as the number of stacked layers increases, the length of the first electrode post 312 gradually increases, while the length of the second electrode post 322 gradually decreases. While ensuring the performance of the packaging structure, the cross-sectional dimensions and shape of the first electrode post 312 can be selected according to actual conditions; similarly, the cross-sectional dimensions and shape of the second electrode post 322 can be selected according to actual conditions. Here, the cross-section refers to the surface parallel to the upper surface of the first wiring layer 11.

[0113] Specifically, the upper surface of the encapsulation layer 5 is flush with the upper surfaces of the second post 41 and the second electrode post 322. The material of the encapsulation layer 5 includes epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorinated glass, or other suitable materials.

[0114] Specifically, the second wiring layer 6 has at least one second dielectric layer 61 and at least one second interconnect layer 62. The second pillar 41 and each second electrode pillar 322 are electrically connected to the second conductive interconnect layer 62. The material of the second dielectric layer 61 includes epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorinated glass, or other suitable materials. The material of the second conductive interconnect layer 62 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver, or other suitable conductive materials.

[0115] Specifically, at least one package unit may be stacked above the second wiring layer 6 adjacent to the first wiring layer 11, or the stacking of package units may be omitted.

[0116] Specifically, when a package unit is stacked above the second wiring layer 6 adjacent to the first wiring layer 11, the first chip 311 in different package units can be the same or different, and the second chip 321 in different package units can be the same or different.

[0117] Specifically, the upper surface of the second wiring layer 6 is also provided with a third stacking structure 7, and a protective layer 8 covers the exposed surface of the third stacking structure 7. The third stacking structure 7 includes at least two third chips 71 stacked upwards in a staggered manner and a third electrode post 72 electrically connected to each third chip 71. The third electrode post 72 extends along the stacking method away from the third chips 71 and is electrically connected to the second wiring layer 6 below the third stacking structure 7.

[0118] Specifically, a third adhesive layer is provided between two adjacent third chips 71. When the two adjacent third chips 71 are fixed by die bonding film bonding process, the material of the third adhesive layer is die bonding film. When the two adjacent third chips 71 are fixed by back gold alloying process, the third adhesive layer is an alloy layer made of semiconductor material and metal alloyed at the interface of the two adjacent third chips 71.

[0119] Specifically, as the number of layers of the third chip 71 in the third stacked structure 7 increases, the height of the third electrode post 72 gradually increases. The material of the third electrode post 72 includes copper, aluminum, nickel, titanium, tungsten, copper, nickel, chromium, vanadium, gold, silver or other suitable conductive materials.

[0120] Specifically, while ensuring the performance of the packaging structure, the cross-sectional dimensions and shape of the third electrode post 72 can be selected according to the actual situation, and are not restricted here.

[0121] Specifically, the material of protective layer 8 includes epoxy resin, silicone, PI, PBO, BCB, silicon dioxide, phosphosilicate glass, fluorinated glass, or other suitable materials.

[0122] Specifically, the conductive bump 24 includes one of spherical and columnar shapes, or other suitable shapes; the material of the conductive bump 24 includes copper, aluminum, nickel, gold, silver, tin, titanium or other suitable materials.

[0123] Specifically, by stacking multiple first chips 311 and multiple second chips 321 in a staggered manner to form a first stacking structure 31 and a second stacking structure 32, and then stacking the first stacking structure 31 and the second stacking structure 32 together, the interconnection between the chips is achieved by combining the first electrode post 312 electrically connected to the first chip 311, the second electrode post 322 electrically connected to the second chip 321, the first wiring layer 2, the first post 21, the second post 41, and the second wiring layer 6. The first electrode post 312 electrically connected to the first chip 311 is led from the staggered region to the first wiring layer 11 in a direction away from the stacking of the first chip 311, and the second electrode post 322 electrically connected to the second chip 321 is led from the staggered region to the second wiring layer 6 in a direction away from the stacking of the second chip 321. The extension directions of the first electrode post 312 and the second electrode post 322 are opposite. The interconnection between the chips in the three-dimensional stacked packaging structure can be achieved without forming a through-hole interconnection structure on the chip, which reduces the process difficulty and the manufacturing cost of the packaging structure.

[0124] The chip stacking packaging structure of this embodiment improves the packaging structure by stacking multiple first chips 311 and multiple second chips 321 in a staggered manner to form a first stacking structure 31 and a second stacking structure 32, respectively. The first stacking structure 31 and the second stacking structure 32 are then stacked together. The first electrode post 312, which is electrically connected to the first chip 311, is led from the staggered region along the direction away from the stacking of the first chip 311 to the first wiring layer 11. The second electrode post 322, which is electrically connected to the second chip 321, is led from the staggered region along the stacking direction of the second chip 321 to the second wiring layer 6. The extension directions of the first electrode post 312 and the second electrode post 322 are opposite. Then, it is combined with the first post 21, the second post 41, the first wiring layer 2 and the second wiring layer 6. The interconnection between the chips in the three-dimensional stacked packaging structure can be realized without forming a through-hole interconnection structure on the chip, which reduces the process difficulty.

[0125] In summary, the chip stacking packaging structure and its fabrication method of the present invention improve the packaging structure by staggering multiple first chips and multiple second chips to form a first stacking structure and a second stacking structure, respectively. The first and second stacking structures are then stacked together to form a layered structure. A first electrode post electrically connected to the first chip is led from the staggered region along a direction away from the first chip stack to the first wiring layer, and a second electrode post electrically connected to the second chip is led from the staggered region along the second chip stack direction to the second wiring layer. The first and second electrode posts extend in opposite directions. Combined with the first post, second post, first wiring layer, and second wiring layer, interconnection between chips in the three-dimensional stacked packaging structure can be achieved without forming through-hole interconnect structures on the chips, reducing process difficulty, manufacturing costs, and improving the yield of the packaging structure. By using the fixed electrical connection between the first and second posts to achieve electrical connection between the first and second wiring layers, the thickness of the layered structure is limited by the sum of the process limits of the heights of the first and second posts, increasing the thickness of the layered structure and consequently increasing the number of chips that can be stacked in the layered structure. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0126] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a chip stack package structure, the method comprising: The method comprises the following steps: providing a carrier plate, a first wiring layer is formed on the upper surface of the carrier plate, and a first column is formed on the upper surface of the first wiring layer; a laminated structure comprising a first stack structure and a second stack structure stacked in sequence is formed on the upper surface of the first wiring layer, the upper surface of the laminated structure is not lower than the upper surface of the first column, the first stack structure comprises at least two first chips stacked in sequence and first electrode columns electrically connected to the first chips and the first wiring layer, and the second stack structure comprises at least two second chips stacked in sequence and second electrode columns extending in the stacking direction; a transfer plate is provided, the bottom surface of the transfer plate is formed with second columns corresponding to the first columns, the height of the second columns is not less than the height of the laminated structure beyond the first columns, the bottom of the second column is fixedly and electrically connected to the top of the first column, and the transfer plate is removed; a packaging layer is formed to cover the laminated structure, the first column, the second column, the exposed surface of the first wiring layer, and the upper surface of the first wiring layer, and the packaging layer is thinned to expose the second column and the second electrode column; a second wiring layer electrically connected to the second column and the second electrode column is formed on the upper surface of the packaging layer, so as to obtain a packaging body unit comprising the first column, the second column, the laminated structure, the packaging layer and the second wiring layer; a protective layer is formed to cover the exposed upper surface of the second wiring layer, the carrier plate is removed, and conductive bumps electrically connected to the first wiring layer are formed on the side of the first wiring layer away from the laminated structure.

2. The method of claim 1, wherein: The number of the first chips in the first stack structure is the same as the number of the second chips in the second stack structure.

3. The method of claim 1, wherein: The upper surface of the first stack structure is not higher than the upper surface of the first column.

4. The method of claim 1, wherein: Each of the first chips in the first stack structure is not completely the same, and each of the second chips in the second stack structure is not completely the same.

5. The method of claim 1, wherein: Before the protective layer is formed, after the second wiring layer is formed, the method further comprises the step of forming the packaging body unit on the upper surface of the second wiring layer at least once.

6. The method of claim 5, wherein: The upper surface of the second wiring layer adjacent to the first wiring layer is formed with the packaging body unit, and in the packaging body unit on the upper surface of the second wiring layer, the first electrode column of the first stack structure is electrically connected to the second wiring layer adjacent to the first stack structure below.

7. The method of claim 1, wherein: Before the protective layer is formed, after the second wiring layer is formed, the method further comprises the step of forming a third stack structure electrically connected to the second wiring layer on the upper surface of the second wiring layer, and the protective layer covers the exposed surface of the third stack structure.

8. The method of claim 7, wherein: The third stack structure comprises at least two third chips stacked in sequence upwardly and third electrode columns electrically connected to each of the third chips, the third electrode columns extend away from the third chips stacked in the method and are electrically connected to the second wiring layer below the third stack structure.

9. The method of claim 7, wherein: The thickness of the third stack structure is greater than the thickness of the first stack structure.

10. A chip stack package structure, characterized by, The chip stack packaging structure is made by the method of any one of claims 1-9.

Images