Digital-to-analog converters using clock signals and integrated circuit packages containing the same

Abstract

A digital-to-analogue converter (DAC) device includes an input terminal for receiving an input signal that includes m MSBs and n least significant bits LSBs. The device includes a coarse DAC that generates a first voltage from the m MSBs, utilizing resistors and switches coupled to a reference voltage. Coupled with a clock signal of a predetermined frequency, a pulse generator produces pulse signals, including a first pulse signal with a first average voltage and a second pulse signal with a second voltage approximately half of the first average voltage. A fine DAC generates a second voltage using then LSBs to select among the pulse signals. An output filter combines the first and second voltages to produce the final output signal. Integrated circuits containing DAC devices and packages containing the integrated circuits are also described.

Description

[0001] DIGITAL-TO-ANALOG CONVERTERS USING CLOCK SIGNALS AND INTEGRATED CIRCUIT PACKAGES CONTAINING THE SAME

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of priority to Provisional Application No. 63 / 834,385, titled “DIGITAL-TO-ANALOG CONVERTERS USING CLOCK SIGNALS,” filed on July 31, 2024, the contents of which are hereby incorporated by reference.

[0004] BACKGROUND

[0005] In high-speed data communication and signal processing, the efficiency and performance of digital-to-analog converters (DACs) often play an important role. DACs are integral components in numerous applications, including wireless communication, audio processing, and instrumentation, where they convert digital signals into analog form. With the rapid advancement of technology, there is an increasing demand for DACs that not only deliver high precision and speed but also operate at low power. This need is particularly pronounced in applications such as mobile devices, Internet of things (loT) devices, and high-density data centers, where power consumption directly impacts battery life, thermal management, and overall system efficiency. Low-power DACs help in reducing the heat generated, extending the operational lifespan of electronic devices, and enabling more compact and lightweight designs. Moreover, in large-scale deployments, such as in highspeed Serializer / Deserializer (SERDES) receivers used in data centers and communication infrastructure, multiple DAC instances are required, further amplifying the importance of low power consumption to manage the cumulative power draw.

[0006] Unfortunately, existing DACs are inadequate, as explained in further detail below. New and improved DACs are desired.

[0007] BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 A is a schematic diagram illustrating an example DAC device.

[0009] FIG. IB is a circuit diagram illustrating an example resistor ladder configuration for implementing coarse DAC 102.

[0010] FIG. 2A is a schematic diagram illustrating an example DAC device.

[0011] FIG. 2B is a circuit diagram illustrating components of an example DAC device.

[0012] FIG. 2C is a schematic diagram illustrating components for implementing an example fine

[0013] DAC. FIGS. 2D is a circuit diagrams illustrating components of an example DAC.

[0014] FIG. 3 is a circuit diagram illustrating an example resistor ladder configuration for implementing an example coarse DAC.

[0015] FIG. 4 is a plot illustrating output waves forms provided by an example pulse generator.

[0016] FIG. 5 is a plot illustrating an output range of an example DAC device.

[0017] FIG. 6 is a plot illustrating an output waveform of an example DAC device.

[0018] FIG. 7 is a plot comparing power consumption of a conventional DAC device and an example DAC device.

[0019] FIG. 8 is a schematic cross-sectional diagram illustrating a circuit package.

[0020] DETAILED DESCRIPTION

[0021] The following description describes digital -to-analog converters (DACs), integrated circuits that include DACs, and circuit packages including such integrated circuits. In certain examples, a DAC device includes an input terminal for receiving an input signal that includes an integer number, m, most significant bits (MSBs) and an integer number, zz, least significant bits LSBs. The device includes a coarse DAC that, during operation, generates a first voltage from the m MSBs, utilizing several resistors and switches coupled to a reference voltage. Coupled with a clock signal of a predetermined frequency, a pulse generator produces multiple pulse signals, including a first signal with a first average voltage and a second signal with a second voltage approximately half of the first average voltage. A fine DAC generates another voltage using the n LSBs to select among the multiple pulse signals. An output filter combines the first and second voltages to produce the final output signal.

[0022] DACs are used in many different applications, such as Serializer / Deserializer (SERDES) devices. The increasing demand for high-speed data communication has led to the widespread adoption of SERDES technology. SERDES receivers can facilitate efficient data transmission by converting serial data streams into parallel data formats for processing. One of the challenges in designing SERDES receivers is a need for high-performance DACs that meet specifications for power consumption, area efficiency, and scalability. As data rates increase, power efficiency becomes an increasingly important factor in the design of DACs for SERDES receivers. Existing DACs often consume significant power, which scales linearly with the number of DACs in an integrated circuit. In high-speed SERDES receivers, this can lead to excessive power consumption, limiting the overall efficiency and performance of the system. DACs in SERDES receivers often need a differential output configuration. Differential outputs can be necessary to reduce noise and interference, ensure signal integrity, and enhance the overall performance of the receiver. DACs with differential outputs can be advantageous as they provide better common-mode noise rejection and improve the robustness of the signal transmission compared to DAC outputs referenced to ground.

[0023] Many SERDES receivers, especially those operating in multi-phase configurations, use multiple DACs to function effectively. For example, a 4-phase receiver may need at least 12 DACs to handle parallel data processing requirements. The deployment of multiple DACs can further exacerbate the power and area challenges, as conventional DAC designs do not necessarily scale efficiently in terms of power consumption and chip area.

[0024] Conventional DAC technologies, including clocked comparator offset cancellation schemes and resistor string DACs, can face several limitations that hinder their efficiency and practicality in high-performance applications. A clocked comparator offset cancellation scheme involves a preamplifier to amplify the input signal and an offset amplifier driven by a DAC, with the differential voltage fed into a clocked comparator to convert analog voltages into digital signals. Despite these efforts to enhance performance, conventional solutions can suffer significant deficiencies.

[0025] A resistor string DAC, combined with a resistor string interpolator, can increase resolution without substantially increasing complexity. For instance, a 10-bit DAC configuration might utilize a 5b+5b approach, reducing the number of resistors in the DAC the from 1024 to 26.

[0026] However, a resistor string DAC can feature notable challenges. Firstly, the use of multiple resistors can occupy excessive chip area, which is not preferable for compact designs. Additionally, the main resistor string can be loaded by the interpolation string resistors, further complicating the design, and leading to inefficiencies. Large resistor values in the interpolating string, while reducing loading, can result in lower operational speeds, necessitating the use of buffers to alleviate this issue.

[0027] An alternative, resistor to resistor (R2R) DAC, offers better area efficiency by employing only two sets of resistors, minimizing the number of components. This configuration ensures a constant current independent of the DAC code and simplifies the digital logic compared to the complex multi-step one-hot decoders required by the interpolation DAC. Nonetheless, the R2R DAC also suffers from significant drawbacks. Both power consumption and area scale linearly with the number of DACs, making this approach unsuitable for applications requiring multiple DAC instances.

[0028] The example DAC designs described below can address one or more of these challenges, e.g., providing digitally scalable DAC designs that can be efficiently integrated into high-speed SERDES receivers. In various embodiments, the DACs described can operate with low power, reducing the overall power footprint of the SERDES receiver. DACs may be implemented to provide differential outputs, which can ensure high signal integrity and noise immunity. Various example DAC designs can allow for easy scaling with minimal increase in power consumption and chip area, enabling the deployment of multiple DAC instances without compromising performance.

[0029] When an element is referred to herein as being "connected" or "coupled" to another element, it is to be understood that the elements can be directly connected to the other element or have intervening elements present between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood that no intervening elements are present in the "direct" connection between the elements. However, the existence of a direct connection does not exclude other connections, in which intervening elements may be present.

[0030] In general, a "DAC device" is an electrical device that generates an analog output based on a digital input. Depending on the output, the analog output may be a differential output. As an example, a DAC device may be implemented using multiple DAC cores to achieve the desired performance and functionality. The term "DAC core" refers to a circuit providing the function of converting digital input signals into corresponding analog output signals. A DAC core may be implemented using resistor ladders, current sources, or switched capacitor networks, and can be combined with other DAC cores to form a more complex and capable DAC device.

[0031] Referring to FIG. 1 A, an example DAC device 100 includes an input terminal 101 for receiving an input signal. The input signal is a digital signal that includes m most significant bits (MSBs) and n least significant bits (LSBs). The DAC device 100 includes a coarse DAC 102 configured to generate a first voltage based on the m MSBs and a fine DAC 103 configured to general a second voltage based on the n LSBs. In some examples, m + n is 12 or less, e.g., m = 5 and n =4, or m = 4 and n = 5, or m = 5 and n = 5. The coarse DAC 102 is coupled to a voltage supply 104 (or, alternatively, a current source), described further below. The coarse D AC 102 includes multiple resistors and multiple switches, and it is coupled to a reference voltage provided by the voltage supply 104. The output of the coarse DAC 102, which may be single or differential, may be based on a number of the resistors selected. Typically, the number of resistors is set via a control module, which can be programmed to provide a desired performance of the DAC. In certain examples, the coarse DAC 102 includes 2m resistors arranged as a resistor ladder and m switches.

[0032] The DAC device 100 also includes a pulse generator 106 coupled to a clock 105. The clock 105 generates a clock signal at a predetermined frequency, such as 14 GHz. The pulse generator 106 utilizes this clock signal to generate multiple pulse signals. For example, the pulse generator 106 provides five output voltages by leveraging the clock signal and four additional pulse signals characterized by frequencies at 1 / 2, 1 / 4, 1 / 8, and 1 / 16 of the clock frequency (or pulse width). By multiplying the clock signal and the four pulse signals with a reference voltage (e.g., voltage V), five distinct binary average voltages are obtained at V, V / 2, V / 4, V / 8, and V / 16. This configuration allows for precise voltage tuning and control, making it adaptable for various applications. For instance, in some implementations, the pulse generator produces more or fewer pulse signals to achieve different levels of voltage granularity and control, depending on the specific needs of the system.

[0033] The fine DAC 103 generates a voltage using the n LSBs received from input 101 and the pulse signals received from pulse generator 106. In some examples, then LSBs and the pulse signals are processed using AND logic gates, which allows the TI LSBS to select appropriate pulse voltages, thereby achieving the desired voltage output from the fine DAC 103.

[0034] To ensure the final output signal is stable and free from high-frequency noise components introduced by the pulse signals, the output of the DAC is filtered using an RC filter. Therefore, a filter 107, which includes an output resistor and an output capacitor, is configured to provide a smooth output signal to output block 108. This filter combines the voltages provided by the coarse DAC 102 and the fine DAC 103 to produce a clean, stable output signal.

[0035] In various examples, the filter 107 is configured to optimize performance for specific applications. For example, the values of the output resistor and capacitor can be selected to achieve the desired cutoff frequency and ripple characteristics, ensuring the filter effectively mitigates any clock ripple present in the DAC output. It is to be appreciated that DAC device 100 can deliver precise, low-power analog output signals, making it suitable for high- performance applications such as SERDES receivers. These applications often use multiple DAC instances operating with high efficiency and minimal power consumption, and the described DAC device can meet these needs effectively.

[0036] Referring to FIG. IB, an example resistor ladder configuration for implementing a coarse DAC 102 includes multiple input lines (Inp<0> through Inp<9>) connected to a series of resistors arranged in a ladder network. In general, the voltage VOut depends on the number of resistors being selected by the input bits.

[0037] Each input line Inp<x> is connected to a switch (shown as an inverter symbol), which controls the connection to the corresponding resistor. The resistors in the ladder network are of two types: resistors with resistance R and resistors with resistance 2R. In operation, the input bits (Inp<0> through Inp<9>) determine which switches are activated, thereby selecting the corresponding resistors in the ladder. When a switch is activated by an input bit, the associated resistor is included in the path for generating the output voltage Vout. The output voltage Vout is derived from the voltage drop across the resistor network and is dependent on the combination of resistors selected by the input bits.

[0038] For instance, if the input bit Inp<0> is activated, the corresponding 2R resistor is included in the circuit. If both Inp<0> and Inp<l> are activated, the 2R resistor from Inp<0> and the combination of 2R and R resistors from Inp< 1> are included in the circuit, influencing the output voltage Vout accordingly. The voltage Vout is thus a function of the number and position of resistors selected by the input bits. It should be noted that the actual implementation can vary, and additional components or different configurations may be employed to optimize performance for specific applications.

[0039] Referring to FIG. 2A, another example DAC device 200 includes an input terminal for receiving an input signal that is composed of m (e.g., 4 in FIG. 2A) MSBs and n (e.g., 5 in FIG. 2A) LSBs. The DAC device 200 receives a clock input (Clk in) that provides a clock signal to a non-overlapping pulse generator 201. The clock signal is characterized by a predetermined frequency (e.g., 14 GHz). The pulse generator 201, utilizing the clock signal, generates pulse signals that are used to create intermediate voltages used in the fine DAC process. In the illustrated example, the pulse generator outputs five pulse signals corresponding to binary weights (e.g., frequencies at 1 / 2, 1 / 4, 1 / 8, and 1 / 16 of the clock frequency). The coarse DAC 202 receives them MSBs from the input signal and generates a first voltage. The coarse DAC includes a resistor ladder network and multiple switches to select the appropriate resistors based on the input bits. This configuration allows the coarse DAC to produce a voltage corresponding to the higher-order bits of the input signal, providing a coarse approximation of the final analog output.

[0040] The pulse adder 203 and adjustable voltage selector 204 are components of the fine DAC. The pulse adder 203 combines the pulse signals generated by the pulse generator 201, while the adjustable voltage selector 204 uses then LSBs to select specific pulse signals. In an embodiment, this selection is achieved through AND logic gates, which combine then LSBs with the pulse signals to produce a precise finely tuned voltage.

[0041] The final stage of the DAC device 200 involves filtering the combined output using a switch capacitor filter 205. In certain examples, filter 205 includes an output resistor and an output capacitor, configured to remove clock ripple and high-frequency noise from the signal. This filtering ensures that the differential output signals (e.g., op and on) are smooth and stable, suitable for high-precision applications.

[0042] Referring to FIG. 2B, example components of an example DAC device include a resistor ladder network 210 composed multiple resistors connected in series. Each resistor R1 is coupled to a switch controlled by the input bits (e.g., the MSBs) to select the appropriate voltage level. For example, the resistor ladder network is configured to generate a set of discrete voltage levels based on the selected resistors. An adj cent voltage selector 212, connected to the resistor ladder 210, is responsible for selecting voltage levels from the resistor ladder network. The selected adjacent voltages are fed into the fine interpolation module 214, which performs a fine-tuning process to generate a precise voltage output. The fine interpolation module 214 uses LSBs and pulse signals generated by the pulse generator to interpolate between the adjacent voltages. The finely interpolated voltage is then passed through an output filter 216, composed of a resistor R and a capacitor C. The RC filter 216 removes high- frequency noise and clock ripple introduced during the pulse generation and fine interpolation processes.

[0043] Referring to FIG. 2C, in certain implementations, the input signal, composed of MSBs and LSBs, is processed by two decoding mechanisms. The LSBs are first processed through a one-hot decoder 220 which takes the LSB and generates individual output signals where only one of the outputs is active at any given time. The output of the one-hot decoder 220 is fed into a two-hot decoder 222, which generates pairs of signals (even and odd) corresponding to voltage levels of the pulse generator, selected using the switches using the outputs of the two hot decoders to select the switches.

[0044] The MSBs (Code<4:0>) and pulse signals (Pulse<4:0>) are processed through AND logic gates in a pulse adder 224. The combination of these signals ensures that the precise voltage selection for fine DAC interpolation is achieved. The outputs from the AND logic gates are then ORed together to sum the contributions from the different pulse signals, refining the voltage output further.

[0045] Referring to FIG. 2D, in an example, the fine interpolation section receives the even and odd signals from the two-hot decoder 222 and the ev and od signals from the pulse adder 224. These signals control switches in a capacitor network 230, allowing for providing precise voltages. For example, the multiple tapping points of the resistor DAC voltage are interpolated with the switch capacitor network to produce an analog output (outp and outn).

[0046] Referring to FIG. 3, another example resistor ladder 300 for a coarse DAC includes a series of resistors, denoted as Ris, connected in series in sequence from a reference voltage at the top to ground at the bottom. Resistors Rls can be matched, ensuring uniform voltage drops across each segment of the ladder. This uniformity can be important for generating precise voltage steps that are proportional to the position in the ladder. Along the resistor ladder, multiple taps 302 are provided. These taps 302 allow for different voltage levels to be extracted based on the specific resistors included in the voltage path. For example, the voltage at each tap 302 is determined by the cumulative resistance from the top of the ladder to the specific tap point.

[0047] The lower end of the ladder is connected to a switch, controlled by the signal labeled "pd". This switch can selectively connect or disconnect the ladder to ground, effectively enabling or disabling the voltage generation process. In operation, the switch allows for dynamic control over the voltage levels output by the resistor ladder, enabling the selection of specific voltage steps required by the coarse DAC. In various embodiments, the coarse DAC utilizes the voltage levels generated by this resistor ladder network as the initial coarse approximation of the final analog output.

[0048] FIG. 4 is a plot showing example output waveforms provided by a pulse generator. The pulse generator receives a high-frequency clock signal, denoted as "elk" in the timing diagram. In this example, the clock signal operates at a frequency of 14 GHz, providing the fundamental timing for the generation of pulse signals. The non-overlapping pulse generator produces a series of pulse signals, each characterized by a specific width and timing such that no two pulses overlap. This non-overlapping characteristic can reduce signal interference and improve accurate digital-to-analog conversion. The pulse signals generated are shown in the timing diagram as "pulse_gate<4>", "pulse_gate<3>", "pulse_gate<2>", and "pulse_gate<l>". Each of these signals corresponds to a different division of the clock frequency. The average voltage of each pulse signal is proportional to the total pulse width. For example:

[0049] "pulse_gate<4>" has an average voltage proportional to V / 2. "pulse_gate<3>" has an average voltage proportional to V / 4. "pulse_gate<2>" has an average voltage proportional to V / 16. "pulse_gate<l>" has an average voltage proportional to V / 32.

[0050] This proportionality allows the DAC to generate voltage levels based on the selected pulse signals, which are useful for fine interpolation. The loading of multiple DACs is configured to ensure that the pulse generator can drive multiple DAC cores without degradation in signal quality or timing accuracy.

[0051] FIG. 5 is a plot illustrating output range of an example DAC device as illustrated in FIG. 1 A. In various implementations, the DAC voltage range is about half of the supply voltage. The plot shows how the DAC output voltage (y-axis) varies as a function of the digital input code, which ranges from 0 to 500 numbers of settings. Ideally, the output voltage increases linearly with the DAC code, demonstrating the precise digital-to-analog conversion capability of the device. The plot includes multiple lines representing the DAC output voltage under different process, voltage, temperature (PVT) conditions. These conditions account for variations in manufacturing processes, supply voltage fluctuations, and temperature changes, which can affect the performance of the DAC. Despite these variations, the DAC output maintains a consistent and predictable behavior, with the output voltage varying from approximately +Z-323 mV to + / - 469 mV around the ideal linear response. This demonstrates the robustness of the DAC design in maintaining accuracy and linearity under diverse operating conditions. The linearity of the output voltage with respect to the DAC code can be important for high-precision applications. The plot shows that the DAC device adheres closely to the expected linear behavior, with minimal deviation across different PVT scenarios.

[0052] FIG. 6 is a plot illustrating output waveform of an exemplary DAC device. The Y-axis represents the DAC output voltage (DAC O / P), measured in millivolts (mV), while the X-axis represents time in microseconds (ps). The plot displays the output voltage of the DAC device over a short period, highlighting the ripple present in the output signal. The ripple is characterized by the periodic oscillations superimposed on the steady-state output voltage. For example, the settling time constant of the output waveform is shown, indicating the time it takes for the output signal to stabilize after a change in the input signal. In various examples, an integration filter (e.g., with a resistor and capacitor) at the output is used to reduce the ripple and smooth the signal. For example, the effectiveness of the filter is evident in the gradual settling of the waveform towards a stable value, as seen in the plot. The initial portion of the plot shows the output voltage starting at 37 mV and then rising to 37.75 mV. The presence of ripple is seen as small periodic variations around the average output voltage. As time progresses, the ripple amplitude remains relatively consistent, indicating the inherent characteristics of the DAC's output filtering mechanism. It is to be appreciated that the integration filter can help ensure that the output signal settles to a stable value, reducing the impact of high-frequency noise and ripple.

[0053] FIG. 7 is a plot illustrating power consumption comparison of a conventional DAC device and an example of DAC device 100. In FIG. 7, the X-axis represents the number of DAC instances, ranging from 1 to 12. The Y-axis represents the power consumption in milliwatts (mW). The plot includes two curves: one for the conventional DAC (R2R) and one for the proposed time-domain DAC. The conventional DAC's power consumption increases linearly with the number of DACs, shown by the upward- si oping curve marked with triangles. This indicates that as more DACs are added, the total power consumption grows linearly by approximately 1 mW per DAC. The disclosed DAC, depicted by the curve marked with squares, shows a linear increase albeit at a much shallower gradient, e.g., about 0.1 mW per DAC. In other words, the power consumption increases at a slower rate compared to the conventional DAC.

[0054] An advantage of the disclosed DAC is its low power consumption, especially when scaling the number of DAC instances. DAC circuitry can be shared among all the DACs, with only the DAC core being separate. This shared design can substantially reduce the overall power consumption of a DAC circuit. In an example that utilizes 12 DAC instances, the DAC implementation can provide approximately 90% power savings compared to a conventional DAC.

[0055] In general, the DAC devices described above can be useful in a variety of applications, including, for example, in analogue-mixed-signal (AMS) electronics for copackaged optics systems. Examples of such systems are described, for example, in U.S. Application No. 19 / 279,985, titled “APPARATUS AND SYSTEMS FOR PHOTONIC INTERCONNECTS,” filed on July 24, 2025, the entire contents of which is incorporated herein by reference.

[0056] FIG. 8 is a schematic diagram that shows an example package 500 that is part of a photonic network. Here, package 500 is connected to a light source 600 via optical fiber(s) 601. Package 500, as shown, includes first die 510 and a second die 520 both mounted on a photonic integrated circuit (PIC) 530. Die 510 is an electrical integrated circuit (EIC) composed of a general part 510B that may include various processing, storage, and communication functions, and an AMS part 510A that includes analog / mixed-signal circuits for interfacing with PIC 530. Similarly, die 520 is an EIC that includes a general part 520B and an AMS part 520A. The package 500 further includes a substrate 540 which supports the PIC 530. The dies 510 and 520 are bonded, e.g., flip-chip bonded, to the top surface of the PIC 530.

[0057] The PIC 530 includes optical modulators MODI and MOD2 and photodetectors PD1 and PD2. The modulators can be electro-absorption modulators (EAMs), micro-ring resonators, or Mach-Zehnder interferometric modulators. A first waveguide 533 forms an optical path between MODI and PD2 and a second waveguide 534 forms an optical path between MOD2 and PD1. The PIC 530 also includes a grating coupler GC which couples light from light source 600 into the PIC via a fiber array unit FAU. Waveguides 535 and 536 form optical paths from the grating coupler GC to MODI and MOD2, respectively. The AMS part 510A of first die 510 includes a driver (DRV1) and a transimpedance amplifier (TIA1). AMS part 520A of second die 520 includes a driver (DRV2) and a transimpedance amplifier (TIA2).

[0058] During operation, the light source 600 delivers light to the PIC 530 via the optical fiber(s) 601. The waveguides 535 and 536 deliver light to the modulators MODI and MOD2, respectively. Modulator MODI modulates the light it receives with information from driver DRV1 and transmits the modulated light to photodetector PD2 via waveguide 533. Photodetector PD2 converts the received light to an electrical signal for second die 520. Similarly, modulator MOD2 modulates light it receives with information from driver DRV2 and transmits the modulated light to photodetector PD1 via waveguide 534. Photodetector PD1 converts the received light to an electrical signal for first die 510. Jointly with a serializer (not shown) in first die 510, driver DRV1, transimpedance amplifier TIA2, and a deserializer (not shown) in second die 520, modulator MODI, waveguide 533, and photodetector PD1 form a data channel from first die 510 to second die 520.

[0059] PIC 530 includes a first interconnect region, a second interconnect region, and an offset region. The first interconnect region includes a bondpad pattern located over MODI and PD1 that matches a bondpad pattern on first die 510 located under DRV1 and TIA1 or is otherwise configured to form an electrical interconnection between the respective components. The second interconnect region includes a bondpad pattern located over PD2 and MOD2 that matches a bondpad pattern on second die 520 located under TIA2 and DRV2 or is otherwise configured to form an electrical interconnection between the respective components. Bondpads of the bondpad pattern on first die 510 are physically and electrically connected with bondpads of the bondpad pattern in the first interconnect region by copper posts 525, and bondpads on the bondpad pattern on the second integrated circuit are physically and electrically connected with two or more bondpads of the bondpad pattern in the second interconnect region by copper posts 526. Bondpads on first die 510 may be located more than 100 microns (100 pm) from the edge of first die 510. Bondpads on second die 520 may be located more than 100 microns (100 pm) from the edge of second die 520. The distance between the (lower) surface of first die 510 and the (top) surface of PIC 530 is less than 2 mm and in many cases less than 50 microns. The distance between the (lower) surface of second die 520 and the (top) surface of PIC 530 is less than 2 mm and in many cases less than 50 microns.

[0060] Driver DRV1 converts the digital signal to an analog electrical signal suitable for driving a photonic modulator and delivers the analog electrical signal to modulator MODI in PIC 530. Modulator MODI sends light modulated with the information to be transmitted to photodetector PD2 via waveguide 533. Photodetector PD2 converts the modulated light to a current signal, and delivers the current signal to transimpedance amplifier T1A2, which amplifies the signal and converts it to a voltage signal for suitable for digital interface I / F2. Interface I / F2 converts the voltage to a digital signal suitable for processing in general part 520B of second die 520. Similarly, information to be transmitted from general part 520B of second die 520 to general part 510B of first die 510 travels via I / F2, DRV2, MOD2, waveguide 534, photodetector PD1, transimpedance amplifier TIA1, and interface I / F I .

[0061] Each AMS module 510A and 510B includes a DAC device 511 and 521, respectively. The DAC devices can be the same as those described above. The AMS modules 510A and 510B also include a phase locked loop 512 and 522, respectively, that provide clock signals to the DAC devices 511 A and 51 IB, respectively. The output of the DAC devices 511 and 521 can be used as a reference signal for the drivers and / or TIAs, and / or for other purposes, e.g., calibrating circuits in the AMS modules.

[0062] In addition to the AMS modules, each die 510 and 520 can include a microcontroller which sets the number of resistors used in the DACs. The microcontroller can provide the input signal to the DAC.

[0063] Use of the DACs described here allow the components of the AMS modules, e.g., the drivers, to be small and positioned close to the modulators, e.g., within 200 micrometers (pm). For example, the compact design of the DAC, featuring a combination of coarse and fine DAC stages can allow the drivers to occupy minimal space in the AMS electronics of the dies. This compactness can facilitate positioning the drivers within 200 pm of the modulator. Positioning the driver close to the driver can increase signal transmission efficiency and reduce latency and loss. The dual-stage design of the DAC described here, incorporating both coarse and fine DACs, can provide various advantages to packages using photonic networking, such the system shown in FIG. 8. The fine tunability and accuracy achieved through this design can improve precision of the analog signals driving the modulators, enhancing the overall performance and fidelity of a photonic networking system. Additionally, or alternatively, the small footprint of the DAC-based drivers allows them to be placed in close proximity to the modulators, e.g., within 200 pm. This proximity can reduce signal degradation and latency, contributing to the more efficient and reliable operation of the system. The compact and efficient DAC design supports high-density integration, making it suitable for advanced photonic systems where space and performance are important.

[0064] While FIG. 8 shows an example of a package configured for photonic networking between two dies mounted on a common PIC, other implementations are possible. For example, photonic networking between packages using photonic links similar to those described here is possible. In such cases, the packages can be linked by one or more optical fibers which link modulators in one package with photodetectors in another, and vice versa. Other implementations, including additional detail of both the EICs and PICs are described in U.S. Application No. 19 / 279,985, incorporated above. Multiple packages can be networked to provide a multi-node computing system with sufficient memory, processing, bandwidth, and energy efficiency constraints for effective operation of artificial intelligence (Al) and / or machine learning (ML) models. Some example benefits are described herein with reference to various features and functionalities provided by the computing system as described. It will be appreciated that benefits explicitly described with reference to one or more examples described herein are provided by way of example and are not intended to be an exhaustive list of all possible benefits of a computing system that features the described DACs.

[0065] For example, circuit packages, such as package 500, and connections thereof may enable the construction of complex topologies of compute and memory nodes that can best serve a specific application. In a simple example, a set of photonic channels connect memory circuit packages with memory nodes (e.g., memory resources) to one or more compute circuit packages with compute nodes. The compute circuit packages, and memory circuit packages can be connected and configured in any number of network topologies which may be facilitated through the use of one or more photonic channels include optical fibers. This may provide the benefit of relieving distance constraints between nodes (compute and / or memory), and, for example, the memory circuit packages can physically be placed arbitrarily far from the compute circuit packages (within the optical budget of the photonic channels).

[0066] Network topologies may provide significant speed and energy savings. For example, photonic transport of data is typically more efficient than an equivalent high-bandwidth electrical interconnect in an EIC of the circuit package itself. By implementing one or more photonic channels, the electrical cost of transmitting data may be significantly reduced. Additionally, photonic channels are typically much faster than electrical interconnects, and thus the use of photonic channels permits the grouping and topology configurations of memory and compute circuit packages that best serve the bandwidth, and connectivity needs of a given application. Indeed, the architectural split of memory and compute networks allows each to be optimized for the magnitude of data, traffic patterns, and bandwidth of each network applications. A further added benefit is that of being able to control the power density of the system by spacing memory and compute circuit packages to optimize cooling efficiency, as the distances and arrangements are not dictated by electrical interfaces.

[0067] Compute and memory nodes and fabric of communication links including the modulators and electrical interconnects described above provide a distributed data processing environment, which may be referred to as a fabric-based environment, on which programs can be run. A compute node or memory node in such an environment will generally have installed on it a software stack that runs on one or more processors of the node to provide an operating environment, which may be referred to as a layer, on which program software deployed to the node can run.

[0068] The compute and memory nodes of a particular environment can be homogeneous, i.e., all the compute nodes are basically the same and all the memory nodes are basically the same, or they can be heterogeneous.

[0069] A compute node has one or more processors that can perform data processing operations, e.g., by executing program instructions, by performing operations implemented in hardware or firmware, by routing a data packet through the electrical interface, or otherwise. The processors can include, for example, CPUs, accelerators of various kinds, e.g., GPUs (graphics processing units), TPUs (tensor processing units), DPUs (data processing units), or programmed FPGAs (field-programmable gate arrays) or other special purpose ASICs (application specific integrated circuits), or by a combination of two or more of them.

[0070] A compute node generally has or is directly connected electrically to local memory, e.g., HBM, DDR, LI and L2 caches, registers and the like.

[0071] A memory node, while it may have processors to run software and may have other characteristics of a compute node, has as its primary purpose in a fabric-based environment the purpose of providing access to data, specifically, for example, for use by compute processes running on compute nodes, and to enable other nodes to read and write data over photonic channels connecting the memory node to the other nodes. The memory devices a memory node has for storing data can be of one or more types. They are connected through respective memory controllers, message routers, and photonic interfaces through which other nodes read and write data by sending messages to ports implemented on the memory node.

[0072] Compute and memory nodes can have memory devices of one or more kinds, including, for example, flash memory, read-only memory, random-access memory (RAM), static RAM, dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) based DRAM, or high bandwidth memory (HBM) memory, or a combination of two or more of them.

[0073] Unidirectional photonic links have a photonic transmitter at one end and a photonic receiver at the other end linked by an optical waveguide, e.g., a semiconductor waveguide or an optical fiber.

[0074] Generally, a photonic channel used in a fabric-based environment is a bidirectional photonic channel, which has at least two unidirectional photonic links that transmit in opposite directions, providing, for example, for the transmission of messages in one direction and acknowledgements in the other.

[0075] In some implementations, the nodes of a fabric-based environment include routers to route data from one node, directly or through intermediary nodes, to another. Generally, data is transferred in messages over photonic or electrical channels in response to programs executing on the nodes or to operations of memory controllers or similar devices, for example. Such messages can be sent point-to-point, when the two nodes have links directly connect them, or through routers on one or more intermediary nodes that route messages according to addressing data that is part of the messages.

[0076] In some implementations, a compute node will have multiple ports, electrical or photonic or both, each directly connected by a link or channel, e.g., bidirectional channel, to a respective other node; and the messages sent by the compute node will be routed to the messages’ target nodes by a router on the compute node that directs the messages to the appropriate port on the compute node. When a data message is received over a port, the router on the receiving node will examine the message header to determine the destination node in the fabric, either the node itself or another node, and process the message accordingly.

[0077] The addressing of messages through the fabric-based environment can be implemented in a variety of ways. In some implementations, multiple methods are implemented in the same fabric-based environment. In some addressing methods, messages carry the actual address of the message destination, and routers in the fabric implement what in effect are routing tables to transmit messages toward their destination addresses. In some implementations, the routing tables are updated dynamically in response to information about device failures or losses of connections, for example. In other addressing methods, messages are routed by relative addresses, i.e., addresses expressed as directional steps from the current node. Modeling nodes as points on a 2D, 3D, or higher dimensional grid, a target destination can be represented in a message header as a number of steps, which may be positive, negative, or zero, in each of the dimensions. When a message has been transmitted, the receiving node can update the message header of the message to account for the steps taken by the message from the sender in each dimension, with the result that the message header now contains a relative address relative to the receiving node. In other addressing methods, a combination of direct and relative addresses is used.

[0078] Memory nodes can be interconnected by photonic links, e.g., in the form of bidirectional photonic channels, to form a memory fabric. The memory fabric can be part of a server and generally includes multiple nodes in one or more packages. A package can include hundreds of nodes extending in multiple dimensions. A fabric made up of multiple packages can have hundreds of thousands of nodes or more, connected by photonic channels in a 2D, 3D, or higher dimensional memory fabric when the nodes have a sufficient number of photonic ports.

[0079] Generally, a fabric-based environment is implemented using packages of nodes, e.g., package 500 described above. In general, a package, sometimes called a System in Package (SiP), includes multiple nodes that are interconnected potentially both at an electrical layer of the package and on an interconnection substrate, e.g., a PIC, and which can be enclosed in a single casing. Each of the nodes in a package can have electrical connections, photonic connections, or both to other nodes within the package. Connections within a package are referred to as intra-chip connections, with the substrate being considered a chip. Connections between nodes in different packages are referred to as inter-chip connections.

[0080] In an environment with multiple packages, some, or all of the nodes in one package have inter-chip photonic connections to nodes in one or more other packages. Generally, these inter-chip photonic connections are made by bidirectional photonic channels.

[0081] Generally, a program that runs on a fabric-based environment will be made up of program modules, each constructed to run on one of the nodes of the environment. Generally, each module includes instructions to invoke the services of the software stack on which it is running or of the underlying physical devices of the node, to load and store data, locally or remotely, to perform computing and control operations, and to communicate and coordinate with other modules of the program running on the same node or on other nodes on which the program has also been deployed.

[0082] Each of the one or more modules that make up a program can be coded separately for a respective particular kind of node. Or a large program can be broken up automatically, e.g., by a compiler, into separately deployable components to run on the nodes of a fabric-based environment. The environment and the resources available in its nodes and the characteristics of its connections, are described by a physical topology, to define, for example, the target for which the compiler is generating executable code.

[0083] A program or the modules of a program can generally be programmed using any suitable procedural, interpreted, or declarative language, or combinations of them, from which executable or interpretable code is automatically generated, e.g., by a compiler, to run on some run-time environment, for example, on some node hardware or some software layer or layers installed on the hardware.

[0084] A physical topology generally describes the locations of the nodes, any intra-chip connections, and inter-chip connections each node has to other nodes. In some fabric-based environments, nodes are implemented in packages, and the location of a node may also include the package in which it is found. A physical topology may be stored in a topology file that defines an environment for a compiler or for deployment management software.

[0085] Program modules and components of the software stack will generally be deployed to nodes through electrical links from a control computer, which may be one of the nodes of the fabric-based environment programmed to perform this function, or which may be a separate control computer. These links can be direct or indirect, and may be provided by an electrical bus, e.g., a PCIe (Peripheral Component Interconnect Express) bus. In some implementations, the photonic links of the fabric-based environment may also be used to deploy modules and components to nodes.

[0086] Executable code can be deployed to nodes directly, or, for example, in containers which can be managed by a container management or orchestration system.

[0087] A fabric-based environment will generally include one or more nodes that are connected, or can be connected dynamically, to devices external to the fabric. External devices can include devices, for example, to provide human interaction for programs running on the fabric, or to provide data to, or to receive results from, such programs.

[0088] The fabric-based environment can be or be part of a general computing environment for executing programs. The computing environment can include or be associated with a compilation environment. The compilation environment takes a program input, e.g., an input machine learning model, and transforms it into machine-readable form by executing a compiler and a code generator. An input machine learning model can be provided in the form of a TensorFlow model, for example.

[0089] The application code generated by the compiler and code generator is, in some implementations, provided to a runtime environment running on the nodes of the computing environment. The runtime environment provides services to the running application code on the computing environment. In some implementations, the nodes of the computing environment include firmware that performs hardware-related operations, e.g., monitoring and driving hardware components of the computing environment, used by the runtime environment and the application code.

[0090] The application and runtime environment run on the compute nodes and use, if and as requested by the application, the resources of the fabric-based environment, including, for example, the compute nodes, memory nodes, memory devices, links and channels, routers, and ports.

[0091] As discussed herein in detail, the present disclosure includes a number of practical applications having features described herein that provide benefits and / or solve problems associated with providing a multi-node computing system with sufficient memory, processing, bandwidth, and energy efficiency constraints for effective operation of Al and / or ML models. Some example benefits are discussed herein in connection with various features and functionalities provided by the computing system as described.

[0092] For example, the various circuit packages described herein, and connections thereof may enable the construction of complex topologies of compute and memory nodes that can best serve a specific application. In a simple example, a set of photonic channels connect memory circuit packages with memory nodes (e.g., memory resources) to one or more compute circuit packages with compute nodes. The compute circuit packages, and memory circuit packages can be connected and configured in any number of network topologies which may be facilitated through the use of one or more photonic channels include optical fibers. This may provide the benefit of relieving distance constraints between nodes (compute and / or memory), and, for example, the memory circuit packages can physically be placed arbitrarily far from the compute circuit packages (within the optical budget of the photonic channels).

[0093] The various network topologies may provide significant speed and energy savings. For example, photonic transport of data is typically more efficient than an equivalent high- bandwidth electrical interconnect in an E1C of the circuit package itself. By implementing one or more photonic channels, the electrical cost of transmitting data may be significantly reduced. Additionally, photonic channels are typically much faster than electrical interconnects, and thus the use of photonic channels permits the grouping and topology configurations of memory and compute circuit packages that best serve the bandwidth, and connectivity needs of a given application. Indeed, the architectural split of memory and compute networks allows each to be optimized for the magnitude of data, traffic patterns, and bandwidth of each network applications. A further added benefit is that of being able to control the power density of the system by spacing memory and compute circuit packages to optimize cooling efficiency, as the distances and arrangements are not dictated by electrical interfaces.

[0094] The following numbered paragraphs are non-limiting examples of various embodiments of the present disclosure.

[0095] 1. A digital -to-analog converter (DAC) device including an input terminal for receiving an input signal, the input signal comprising m most significant bits (MSBs) and n least significant bits (LSBs); a coarse DAC configured to generate a first voltage based on them MSBs, the coarse DAC including a plurality of resistors and a plurality of switches and being coupled to a reference voltage; a pulse generator coupled to a clock signal and configured to generate a plurality of pulse signals, the clock signal being characterized by a predetermined frequency, the plurality of pulse signals including a first pulse signal and a second pulse signal, the first pulse signal being characterized by a first average voltage, the second pulse signal being characterized by a second voltage, the second voltage being about half of the first average voltage, the first average voltage being associated with the predetermined frequency of the clock signal; a fine DAC configured to generate a second voltage using then LSBs and the plurality of pulse signals, then LSBs being used to select the plurality of pulse signals; and a filter including an output resistor and an output capacitor, the filter being configured to provide an output signal based on a sum of the first voltage and the second voltage.

[0096] 2. The DAC device of claim 1, wherein the coarse DAC includes 2m resistors configured in series.

[0097] 3. The DAC device of paragraph 1, wherein the plurality of pulse signals includes 2n pulse signals.

[0098] 4. The DAC device of paragraph 1, wherein the coarse DAC includes a one-hot decoder and a two-hot decoder.

[0099] 5. The DAC device of paragraph 4, wherein the two-hot decoder generates an even signal and an odd signal.

[0100] 6. The DAC device of paragraph 5, wherein the even signals and the odd signal are coupled to the plurality of switches for selecting resistors.

[0101] 7. The DAC device of paragraph 1, wherein m is a whole number greater than 7.

[0102] 8. The DAC device of paragraph 1, further including an OR circuit for adding the first voltage and the second voltage.

[0103] 9. The DAC device of paragraph 1, wherein the fine DAC includes an AND circuit configured with the n LSBs and the plurality of pulse signals as inputs.

[0104] 10. The DAC device of paragraph 1, wherein the plurality of pulse signals includes n pulse signals.

[0105] 11. The DAC device of paragraph 1, wherein the fine DAC is configured to multiply the n LSBs and the plurality of pulse signals.

[0106] 12. The DAC device of paragraph 1, wherein the coarse DAC further includes a capacitor network for interpolating voltages associated with the plurality of resistors.

[0107] 13. The DAC device of paragraph 1, wherein the plurality of resistors is configured a resistor ladder.

[0108] 14. The DAC device of paragraph 1, wherein the second voltages includes a clock ripple, the filtering being configured to remove the clock ripple.

[0109] 15. The DAC device of paragraph 1, wherein the second voltage includes a plurality of pulses.

[0110] 16. A digital -to-analog converter (DAC) device including: an input terminal receiving an input signal, the input signal including m most significant bits (MSBs) and n least significant bits (LSBs); a coarse DAC configured to generate a first voltage based on the m MSBs, the coarse DAC including a resistor ladder circuit and a plurality of switches and being coupled to a reference voltage, the coarse DAC further including a two-hot decoder for generating even signals and odd signals based on the m MSBs, the even signals and the odd signals being coupled to the plurality of switches; a pulse generator coupled to a clock signal and configured to generate a plurality of pulse signals using the clock signals, the clock signal being characterized by a predetermined frequency, the plurality of pulse signals including a first pulse signal and a second pulse signal; a fine DAC configured to generate a second voltage using the n LSBs and the plurality of pulse signals, the n LSBs being used to select the plurality of pulse signals; and a filter including an output resistor and an output capacitor, the filter being configured to provide an output signal based on a sum of the first voltage and the second voltage.

[0111] 17. The DAC device of paragraph 16, wherein the filter includes a cutoff filter characterized by a predetermined cutoff frequency.

[0112] 18. A digital-to-analog converter (DAC) device including: an input terminal receiving an input signal, the input signal including m most significant bits (MSBs) and n least significant bits (LSBs); a coarse DAC configured to generate a first voltage based on the m MSBs; a pulse generator coupled to a clock signal and configured to generate a n pulse signals, the clock signal being characterized by a predetermined frequency, the plurality of pulse signals including a first pulse signal and a second pulse signal, the first pulse signal being characterized by a first average voltage, the second pulse signal being characterized by a second voltage, the second voltage being about half of the first average voltage, the first average voltage being associated with the predetermined frequency of the clock signal; a fine DAC configured to generate a second voltage using the n LSBs and them pulse signals as inputs to an AND circuit, the n LSBs being used to select m pulse signals; and a filter including an output resistor and an output capacitor, the filter being configured to provide an output signal based on a sum of the first voltage and the second voltage.

[0113] 19. The DAC device of paragraph 18, wherein the coarse DAC includes a resistor ladder and a plurality of switches.

[0114] 20. The DAC device of paragraph 19, wherein the coarse DAC further includes a decoder for generating signals to select resistors using the plurality of switches and m MSBs.

[0115] 21. An integrated circuit including: an analogue-mixed-signal (AMS) module including a driver for generating a signal for driving a modulator in a photonic integrated circuit (PIC), a transimpedance amplifier (TIA) for receiving a signal from a photodetector in the PIC, a phase locked loop (PLL), and the DAC device of paragraph 1, wherein the PLL provides the clock signal to the DAC device.

[0116] 22. A package including: the integrated circuit of paragraph 21; and a photonic integrated circuit including the modulator and the photodetector, the modulator being electrically connect to the driver in the integrated circuit and the photodetector being electrically connected to the TIA in the integrated circuit.

[0117] 23. An integrated circuit including: an analogue-mixed-signal (AMS) module including a driver for generating a signal for driving a modulator in a photonic integrated circuit (PIC), a transimpedance amplifier (TIA) for receiving a signal from a photodetector in the PIC, a phase locked loop (PLL), and the DAC device of paragraph 16, wherein the PLL provides the clock signal to the DAC device.

[0118] 24. A package including: the integrated circuit of paragraph 23; and a photonic integrated circuit including the modulator and the photodetector, the modulator being electrically connect to the driver in the integrated circuit and the photodetector being electrically connected to the TIA in the integrated circuit.

[0119] 25. An integrated circuit including: an analogue-mixed-signal (AMS) module including a driver for generating a signal for driving a modulator in a photonic integrated circuit (PIC), a transimpedance amplifier (TIA) for receiving a signal from a photodetector in the PIC, a phase locked loop (PLL), and the DAC device of paragraph 18, wherein the PLL provides the clock signal to the DAC device.

[0120] 26. A package including: the integrated circuit of paragraph 25; and a photonic integrated circuit including the modulator and the photodetector, the modulator being electrically connect to the driver in the integrated circuit and the photodetector being electrically connected to the TIA in the integrated circuit.

[0121] A number of embodiments are described. Other embodiments are in the following claims.

[0122] What is claimed is:

Claims

CLAIMS1. A digital -to-analog converter (DAC) device comprising: an input terminal for receiving an input signal, the input signal comprising m most significant bits (MSBs) and n least significant bits (LSBs); a coarse DAC configured to generate a first voltage based on them MSBs, the coarse DAC comprising a plurality of resistors and a plurality of switches and being coupled to a reference voltage; a pulse generator coupled to a clock signal and configured to generate a plurality of pulse signals, the clock signal being characterized by a predetermined frequency, the plurality of pulse signals comprising a first pulse signal and a second pulse signal, the first pulse signal being characterized by a first average voltage, the second pulse signal being characterized by a second voltage, the second voltage being about half of the first average voltage, the first average voltage being associated with the predetermined frequency of the clock signal; a fine DAC configured to generate a second voltage using then LSBs and the plurality of pulse signals, then LSBs being used to select the plurality of pulse signals; and a filter comprising an output resistor and an output capacitor, the filter being configured to provide an output signal based on a sum of the first voltage and the second voltage.

2. The DAC device of claim 1, wherein the coarse DAC comprises 2m resistors configured in series.

3. The DAC device of claim 1, wherein the plurality of pulse signals comprises 2n pulse signals.

4. The DAC device of claim 1, wherein the coarse DAC comprises a one-hot decoder and a two-hot decoder.

5. The DAC device of claim 4, wherein the two-hot decoder generates an even signal and an odd signal.

6. The DAC device of claim 5, wherein the even signals and the odd signal are coupled tothe plurality of switches for selecting resistors.

7. The DAC device of claim 1, wherein mis a whole number greater than 7.

8. The DAC device of claim 1, further comprising an OR circuit for adding the first oltage and the second voltage.9 The DAC device of claim 1, wherein the fine DAC comprises an AND circuit configured with the n LSBs and the plurality of pulse signals as inputs.10 The DAC device of claim 1, wherein the plurality of pulse signals comprises n pulse signals.11 The DAC device of claim 1, wherein the fine DAC is configured to multiply the n LSBs and the plurality of pulse signals.12 The DAC device of claim 1, wherein the coarse DAC further comprises a capacitor network for interpolating voltages associated with the plurality of resistors.13 The DAC device of claim 1, wherein the plurality of resistors is configured a resistor ladder.14 The DAC device of claim 1, wherein the second voltages comprises a clock ripple, he filtering being configured to remove the clock ripple.15 The DAC device of claim 1, wherein the second voltage comprises a plurality of pulses.16 A digital -to-analog converter (DAC) device comprising: an input terminal receiving an input signal, the input signal comprising m most significant bits (MSBs) and n least significant bits (LSBs); a coarse DAC configured to generate a first voltage based on the m MSBs, the coarseDAC comprising a resistor ladder circuit and a plurality of switches and being coupled to a reference voltage, the coarse DAC further comprising a two-hot decoder for generating even signals and odd signals based on the m MSBs, the even signals and the odd signals being coupled to the plurality of switches; a pulse generator coupled to a clock signal and configured to generate a plurality of pulse signals using the clock signals, the clock signal being characterized by a predetermined frequency, the plurality of pulse signals comprising a first pulse signal and a second pulse signal; a fine DAC configured to generate a second voltage using the n LSBs and the plurality of pulse signals, the n LSBs being used to select the plurality of pulse signals; and a filter comprising an output resistor and an output capacitor, the filter being configured to provide an output signal based on a sum of the first voltage and the second voltage.

17. The DAC device of claim 16, wherein the filter comprises a cutoff filter characterized by a predetermined cutoff frequency.

18. A digital -to-analog converter (DAC) device comprising: an input terminal receiving an input signal, the input signal comprising m most significant bits (MSBs) and n least significant bits (LSBs); a coarse DAC configured to generate a first voltage based on the m MSBs; a pulse generator coupled to a clock signal and configured to generate a n pulse signals, the clock signal being characterized by a predetermined frequency, the plurality of pulse signals comprising a first pulse signal and a second pulse signal, the first pulse signal being characterized by a first average voltage, the second pulse signal being characterized by a second voltage, the second voltage being about half of the first average voltage, the first average voltage being associated with the predetermined frequency of the clock signal; a fine DAC configured to generate a second voltage using the n LSBs and them pulse signals as inputs to an AND circuit, the n LSBs being used to select m pulse signals; and a filter comprising an output resistor and an output capacitor, the filter being configured to provide an output signal based on a sum of the first voltage and the second voltage.

19. The DAC device of claim 18, wherein the coarse DAC comprises a resistor ladder and a plurality of switches.

20. The DAC device of claim 19, wherein the coarse DAC further comprises a decoder for generating signals to select resistors using the plurality of switches and m MSBs.

21. An integrated circuit comprising: an analogue-mixed-signal (AMS) module comprising a driver for generating a signal for driving a modulator in a photonic integrated circuit (PIC), a transimpedance amplifier (TIA) for receiving a signal from a photodetector in the PIC, a phase locked loop (PLL), and the DAC device of claim 1, wherein the PLL provides the clock signal to the DAC device.

22. A package comprising: the integrated circuit of claim 21; and a photonic integrated circuit comprising the modulator and the photodetector, the modulator being electrically connect to the driver in the integrated circuit and the photodetector being electrically connected to the TIA in the integrated circuit.

23. An integrated circuit comprising: an analogue-mixed-signal (AMS) module comprising a driver for generating a signal for driving a modulator in a photonic integrated circuit (PIC), a transimpedance amplifier (TIA) for receiving a signal from a photodetector in the PIC, a phase locked loop (PLL), and the DAC device of claim 16, wherein the PLL provides the clock signal to the DAC device.

24. A package comprising: the integrated circuit of claim 23; and a photonic integrated circuit comprising the modulator and the photodetector, the modulator being electrically connect to the driver in the integrated circuit and the photodetector being electrically connected to the TIA in the integrated circuit.

25. An integrated circuit comprising: an analogue-mixed-signal (AMS) module comprising a driver for generating a signal for driving a modulator in a photonic integrated circuit (PIC), a transimpedance amplifier (TIA) for receiving a signal from a photodetector in the PIC, a phase locked loop (PLL), and the DAC device of claim 18,22wherein the PLL provides the clock signal to the DAC device.

26. A package comprising: the integrated circuit of claim 25; and a photonic integrated circuit comprising the modulator and the photodetector, the modulator eing electrically connect to the driver in the integrated circuit and the photodetector being electrically connected to the TIA in the integrated circuit.

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