Device, arrangement, and method for coupling signals to a quantum processing circuit

Abstract

A device (101) for coupling signals to a quantum processing circuit (102) comprises a block of dielectric material having a first surface (103) and a second surface (104). Each through via in a first array of through vias extends from the first surface (103) to the second surface (104) of the block. A first slot (106) in the first surface (103) cuts partially through at least a subset of the through vias (105) in the first array of through vias, leaving an uncut portion (404) of each of the through vias (105) extending intact from the first surface (103) to the second surface (104).

Description

DEVICE , ARRANGEMENT , AND METHOD FOR COUPLING SIGNALS TOA QUANTUM PROCESSING CIRCUITTECHNICAL FIELD

[0001] The following disclosure is generally related to hardware solutions for information processing . In particular, the disclosure is related to hardware and methods that can be used to establish signal paths to and / or from a quantum processing circuit , a normal operating temperature of which is in the cryogenically cooled domain .BACKGROUND

[0002] In the following, quantum processing is used as an example of a discipline that benefits from the abi lity to route a large number of electric signals to and from chips and other circuit elements that are under cryogenically cooled conditions during their normal operation . However, the following disclosure is also applicable to other kinds of information processing .

[0003] For quantum processing to be possible , the quantum proces sing circuits must be cooled to very low temperatures , such as close to or even below 10 millikelvins . This is accomplished by thermally coupling the quantum processing circuits to a high-performance cooling apparatus inside a cryostat . While some types of quantum proces sing, such as the use of spin qubits , may allow operating at temperatures at 1 K or above , the temperatures involved are still cold enough to require the use of cryostats , which then leads to certain challenges related to the hardware used .

[0004] Quantum processing circuits , such as those that include the actual qubits , are often built in the form of chips where the circuit elements appear as quasi two- dimensional patterns on at least one planar surface and, at least in some cases , on one or more intermediate layers of a substrate . Bl ind vias , buried vias , and / or through vias in the substrate may be used to route electric signals between surfaces and / or intermediate layers . Challenges arise when a large number of electric signals should be routed between the chip and other circuit elements . In particular, as the number and density of qubits in quantum processing circuits increase , there will be a need to route a large number of electric signals between a cryogenically cooled chip and higher temperature levels , even up to the room-temperature environment of the cryostat .

[0005] A known way to route electric signals between a chip and its surroundings is wire bonding, in which individual bonding wires are each metallurgically attached between a bonding pad on a visible ( top) surface of the chip and a corresponding connection pad on a surrounding surface . Another known way is bump bonding, in which small , initially spherical pieces of conductive material become squeezed between bonding pads on a bottom surface of the chip and a substrate on which the chip is placed . Ball grid arrays (BGA' s ) are conceptual ly similar to bump bonding but they usually refer to connections on a slightly larger scale , like mounting a completed integrated circuit onto a printed circuit board .

[0006] The known approaches to the routing of electric signals give rise to a variety of problems . As the numberof required signal routes becomes large , it may be difficult to fit enough bonding wires or bumps to the available limited space . Differences in the coefficients of thermal expansion of different materials create problems because the dimensions of the structural entities change to a variable extent . Quantum processing frequently involves signals that must be carefully shielded against crosstalk and electromagnetic interference , which limits the applicability of all techniques in which properly grounded shielding structures cannot follow the actual signal line throughout its whole length .SUMMARY

[0007] This summary is provided to introduce a selection of concepts in a s implif ied form that are further described below in the detailed description . This summary is not intended to identify key features or essential features of the claimed subj ect matter, nor is it intended to be used to limit the scope of the claimed subj ect matter .

[0008] It is an obj ective to provide a device and an arrangement for coupling signals to a quantum processing circuit so that a large number of signals could be conveyed in a relatively small space . Another obj ective is to ensure that the approach taken to construct the device and arrangement is flexible enough to be scaled for larger and smal ler numbers of s ignals . Yet another obj ective is to provide a method for manufacturing a device of said kind .

[0009] According to a first aspect , there is provided a device for coupling signals to a quantum processing circuit . The device comprises a block of dielectric material with a first surface and, on an opposite side ofthe block, a second surface . Each through via in a first array of through vias extends from the first surface to the second surface of the block . A first slot in the first surface cuts partial ly through at least a subset of the through vias in the first array of through vias , leaving an uncut portion of each of the through vias ( 105 ) extending intact from the first surface ( 103 ) to the second surface ( 104 ) .

[0010] According to an embodiment , the first slot is one of a first plurality of slots in the first surface . The first array of through vias may then be one of a second plurality of arrays of through vias , each through via in the second plurality of arrays of through vias extending from the first surface to the second surface . Each s lot in the first plurality of s lots may cut partially through at least a subset of the through vias of at least one array of through vias in the second plurality . This involves at least the advantage that a very large number of signals may be coupled .

[0011] According to an embodiment , in addition to the first array of through vias , the device comprises at least a second array of through vias , each through via in the first and second arrays extending from the first surface to the second surface . The first slot may then leave the uncut portion of each of the through vias of the first array of through vias extending intact from the first surface to the second surface on a first side of the first slot . The first slot may cut partially through at least a subset of the through vias of the second array of through vias , leaving the uncut portion of each of the through vias of the second array of through vias extending intact from the first surface tothe second surface on a second s ide of the first slot , opposite to the first side . This involves at least the advantage that a relatively large number of connections may be built around a single slot .

[0012] According to an embodiment , the first and second arrays of through vias comprise at least one pair of through vias so that one through via of the pair belongs to the first array of through vias , the other through via of the pair belongs to the second array of through vias , and the through vias of the pair face each other across the first slot . This involves at least the advantage that differential signals may be conveyed with low susceptibility to interference .

[0013] According to an embodiment , at least said first array of through vias i s a linearly organi zed array of through vias . This involves at least the advantage that a linear slot can be used, which may make at least some of the manufacturing steps easier .

[0014] According to an embodiment , at least the first slot is a linear slot . This involves at least the advantage that a dicing saw or some other relatively straightforwardly applicable tool can be used to make such slots .

[0015] According to an embodiment , at least a subset of said through vias are superconductive through vias . This involves at least the advantage that the generation of waste heat may be kept in control , allowing the solution to be used in systems that require maintaining extremely low temperatures .

[0016] According to a second aspect , there is provided an arrangement for coupling signals to a quantum processing circuit . The arrangement comprises a device ofthe kind described above , an electrically insulating first carrier, and conductors supported by the first carrier . The first carrier is flat and fixed, by a first end thereof , to the first slot . At least a first subset of the conductors supported by the first carrier are conductively connected to a corresponding subset of the through vias in the first array of through vias .

[0017] According to an embodiment , the first carrier comprises layers of electrically insulating material in a stack . Each conductor in the first subset of conductors may then be between a first outer layer and an intermediate layer in the stack . The first outer layer may comprise openings at locations where each respective conductor of the first subset of conductors is adj acent to a respective through via in the first array of through vias . This involves at least the advantage that a structurally solid and functionally versatile arrangement can be provided .

[0018] According to an embodiment , each conductor of a second subset of the conductors supported by the first carrier is between a second outer layer and the intermediate layer in the stack . The second outer layer may then comprise openings at locations where each respective conductor of the second subset of conductors is adj acent to a respective through via in the device . Thi s involves at least the advantage that a relatively large number of connections can be made using a single carrier .

[0019] According to an embodiment , at least one conductor of the first subset of conductors and a respective at least one conductor of the second subset of conductors are similarly routed through a maj ority oftheir length on opposite sides of the intermediate layer , forming a pair of conductors for routing a dif ferential signal . This involves at least the advantage that susceptibility to interference can be reduced .

[0020] According to an embodiment , the arrangement comprised a shielding conductor layer on at least one surface of the first carrier . This involves at least the advantage that shielding against electromagnetic interference can be improved .

[0021] According to an embodiment , said shielding conductor layer is patterned at the first end of the first carrier to prevent said shielding conductor layer from making short circuits between through vias in said first array of through vias . Thi s involves at least the advantage that appropriate use of the through vias for routing signals can be ensured .

[0022] According to an embodiment , the device comprises a first plurality of slots in its first surface . The first carrier may then be one of a second plurality of electrically insulating carriers of conductors . Each carrier of the second plurality may be flat and f ixed, by a respective first end thereof , to a respective slot of the first plurality . At least one subset of conductors supported by each carrier of the second plural ity may be conductively connected to a corresponding subset of the through vias in the respective array of through vias partially cut through by the respective slot . This involves at least the advantage that spatial connection density can be made relatively high .

[0023] According to an embodiment , the arrangement comprises at least one thermali zing block of thermally conductive material fixed, at a separating distance fromthe device , to a surface of at least one of the one or more carriers of conductors comprised in the arrangement . This involves at least the advantage that thermali zation can be accomplished at an intermediate point along signal connections .

[0024] According to an embodiment , at a contact area or contact areas between the thermali zing block and the respective one or more carriers , to the surface or surfaces of which the thermal i zing block is fixed, at least a portion of a constituting material of the respective one or more carriers may be replaced with a thermal conductor material with higher thermal conductivity than the constituting material . This involves at least the advantage that a more effective thermali zing contact can be made to inner layers of a layered carrier than if the contact was only to the outermost surface of the carrier .

[0025] According to an embodiment , the thermal conductor material may connect at least one conductor supported by the respective carrier to the thermali zing block . This involves at least the advantage that a more effective thermali zing contact can be made to such a conductor than if the contact was only to the outermost surface of the carrier .

[0026] According to a third aspect , there is provided a quantum processing system comprising at least one arrangement of the kind described above .

[0027] According to a fourth aspect , there is provided a method for manufacturing a device for use to couple signals to a quantum processing circuit . The method comprises providing a block of dielectric material having a first surface and, on an oppos ite side of the block,a second surface . The method comprises forming a f irst array of through vias through the block of dielectric material , each through via in the first array of through vias extending from the first surface to the second surface , and forming a f irst s lot in the f irst surface so that the first slot cuts partially through each of the through vias in the first array of through vias , leaving an uncut portion of each of the through vias extending intact from the first surface to the second surface .BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings , which are included to provide a further understanding of the disclosure and constitute a part of this specification, illustrate practical embodiments and together with the description help to explain the principles of the disclosure . In the drawings : figure 1 illustrates an arrangement for coupling signals to a quantum processing circuit , figure 2 illustrates a device for coupling signals to a quantum processing circuit , figure 3 illustrates a device for coupling signals to a quantum processing circuit , figure 4a illustrates a cross section of a device like that in figs 2 and 3 , figure 4b illustrates the concepts of a cut portion and uncut portion of a through via, figure 5 illustrates a device for coupling signals to a quantum processing circuit , figure 6 illustrates a step in assembling an arrangement , figure 7 illustrates a step in assembling an arrangement ,figure 8 illustrates a step in assembling an arrangement , figure 9 illustrates a step in assembling an arrangement , figure 10 illustrates a step in assembling an arrangement , and figure 11 illustrates a device for coupling signals to a quantum processing circuit .DETAILED DESCRIPTION

[0029] In the following description, reference is made to the accompanying drawings , which form part of the disclosure , and in which are shown, by way of illustration, specific aspects in which the present disclosure may be placed . I t i s understood that other aspects may be utilised, and structural or logical changes may be made without departing from the scope of the present disclosure . The following detailed description, therefore , is not to be taken in a limiting sense , as the scope of the present disclosure is defined in the appended claims .

[0030] For instance , it is understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa . For example , if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or il lustrated in the f igures . On the other hand, for example , if a specific apparatus is described based on functional units , a corresponding method may include a step performing the described functionality, even if such step is not explicitly described or illustrated inthe figures . Further, it is understood that the features of the various example aspects described herein may be combined with each other, unless specifically noted otherwise .

[0031] Fig . 1 is a side view showing a device 101 for coupling signals to a quantum processing circuit 102 . The same device can be used regardless of the direction in which the signals propagate, so it could be called a device for coupling signals to and / or from a quantum processing circuit . For simplicity, only the shorter expression is used here without meaning any loss of generality compared to the longer, more accurate expression . In fig . 1 there are also other elements , whi le figs 2 and 3 show only the device 101 in two axonometric views .

[0032] The device 101 comprises a block of dielectric material . The block has a f irst surface 103 (here : the top surface ) and, on an opposite side of the block, a second surface 104 (here : the bottom surface ) parallel to the first surface 103 . The first surface 103 is seen in fig . 2 and the second surface 104 is seen in fig . 3 . In this example , the first and second surfaces are planar surfaces parallel to each other, but this is j ust an example and not a requirement .

[0033] The device comprises at least one array of through vias 105 . In conformity with the common use of terms on this technical f ield, a through via is a conductive or superconductive structure extending through a substrate from one surface of the substrate to another surface of the substrate . A through via may be made for example by making a hole through the substrate and subsequently filling the hole , or at least plating thewal ls of the hole , with electrically conductive or superconductive material . A material is considered superconductive if it is capable of becoming superconductive at temperatures below a known critical temperature that is not lower than those commonly achieved with cryogenic cooling systems used to cool quantum processing circuits . Examples of superconductive materials that can be used to make superconductive through vias in the sense considered here include , but are not limited to , tungsten, aluminium, and titanium .

[0034] Through vias may be, for example , signal vias or grounded vias . Signal vias may be used as parts of respective signal paths , while grounded vias can be used for shielding, for avoiding resonance modes , and / or for mechanical connection . For the purposes of the present description, the concept of through vias covers both signal vias and grounded vias .

[0035] In figs . 1 , 2 , and 3 , the arrays of through vias are linearly organi zed . A linearly organi zed array of through vias means two or more through vias located so that their longitudinal axes lie in a common plane . Consequently, the through vias of a linearly organi zed array follow each other in a straight line across the block of dielectric material . In the exemplary embodiment shown in figs . 2 and 3 , there are a total of eight linearly organi zed arrays of through vias of the kind introduced above . Each such linearly organi zed array consists of eight through vias arranged in a straight line from the front left to the back right of the block of dielectric material in figs . 2 and 3 . A linearly organi zed array of through vias may be called a line of vias for compact reference .

[0036] The device compri ses at least one slot 106 in the first surface 103 . In the example shown in figs . 1 - 3 , there are a total of four slots in the first surface 103 , and each of these is a linear slot . Each slot 106 cuts partially through at least a subset of the through vias 105 in at least one line or array of vias . Cutting partially through a through via means that an uncut portion of the respective through via is left extending intact from the first surface 103 to the second surface 104 of the block of dielectric material . The top end of each such uncut portion of a partially through-cut through via i s seen as a respective semi-circle on the first surface 103 of the block in fig . 2 .

[0037] In a more general case , the relations between slots and arrays of vias may be described as follows . The at least one slot 106 is one of a first plurality of (here : four) s lots in the first surface 103 . The at least one array of through vias is one of a second plurality of (here : eight ) arrays of through vias , each through via in the arrays of through vias extending from the first surface 103 to the second surface 104 . Each slot in the first plurality of slots cuts partially through at least a subset of the through vias 105 of at least one arrays of through vias (here : two arrays of through vias ) 105 in the second plurality .

[0038] Any slot in the f irst surface of the block of dielectric material may be limited by its ends like the slots seen in figs . 2 and 3 , so that it does not extend to any edge of the block of dielectric material . Alternatively, any slot may extend to an edge of the block of dielectric material at one or both of its ends .

[0039] I f there are a plurality of slots in the first surface of the block of dielectric material , they may all be equal in si ze and parallel to each other, like in figs . 2 and 3 . Alternatively, there may be slots of different si zes and / or orientations in the first surface .

[0040] Fig . 4a shows a cross-section of the block of dielectric material along an imaginary plane shown with reference designator 201 in figs . 2 and 3 . The fact that at least one of the slots , like slot 106 for example , cuts through two arrays of through vias may be described more formally as follows . The slot 106 cuts partially through at least a subset of the through vias 401 of the first array of through vias , leaving the uncut portion of each of the through vias401 of the first array of through vias extending intact from the first surface 103 to the second surface 104 on a f irst side of the first slot 106 . The same slot 106 cuts partially through at least a subset of the through vias402 of a second array of vias , leaving the uncut portion of at least a subset of the through vias 402 of the second line of through vias extending intact from the first surface 103 to the second surface 104 on a second side of the first slot 106 , opposite to the first side . Fig . 4b is an axono- metric explanatory drawing illustrating the concepts of a cut portion 403 and an uncut portion 404 of a through via, here through via 402 , in more detail , said through via being one of the through via of the subset of through vias being cut at least partially by the slot 106 .

[0041] Figs . 2 and 3 show the plurality of through vias appearing in a completely regular, rectangularly organi zed 8 x 8 pattern . Thi s i s not a requirement , asthere could be different numbers of through vias in different arrays , and the through vias in different arrays are not necessarily at regular or similar distances between the ends of the respective slots . However, certain advantages may be gained by designing the device 101 so that the s lots are linear and paral lel , and cut acros s the whole first surface of the block of dielectric material . As an example , such slots are relatively easy to make using a dicing saw similar to those used to cut semiconductor chips out of a wafer . Other methods for making slots in the block of dielectric material include but are not limited to laser ablation and selective chemical etching .

[0042] Further additional advantages may be gained by having, in at least some of the cases , two of the through vias located in a particular configuration with respect to each other across the respective slot . Such a s ituation may be formally described as follows . A first array of through vias and a second array of through vias may comprise at least one pair of through vias401 and 402 so that one through via401 of the pair belongs to the first array of through vias , the other through via402 of the pair belongs to the second array of through vias , and the through vias401 and 402 of the pair face each other across the respective slot 106 .

[0043] In the example embodiment of figs . l -4a, all through vias are placed so that each of them is a member of a pair of the kind described above . Additionally, the through vias of each pair face each other perpendicularly across the respective slot . It is also possible to have the through vias of a pair face each other obliquely across the respective slot . This would be thecase if , for example, the through vias of the so-called second array above ( those that include the through via 402 of fig . 4 ) would be moved linearly in the linear direction of the slot 106 by less than the constant distance between two adj acent through vias in the array .

[0044] A device of the kind described above may be advantageously used as a part of an arrangement for coupling signals to a quantum processing circuit 102 . As shown in fig . 1 , such an arrangement comprises at least one device 101 of the kind described above . Additionally, the arrangement comprises an electrically insulating first carrier 107 of conductors , as well as conductors 501 ( see fig . 5 ) supported by the first carrier 107 . The first carrier 107 is flat and fixed, by a first end thereof , to a first linear slot 106 in the block of dielectric material . Being characteri zed as flat means that considering three orthogonal directions , the f irst carrier 107 has a dimension in one direction ( thickness ) that is significantly smaller than its dimensions in the two other directions ( length, width) . A flat first carrier 107 may be planar like a rigid printed circuit board for example , but it may also be curved in at least one direction, like a bent flexible circuit board for example .

[0045] At least a f irst subset of the conductors 501 supported by the first carrier 107 are conductively connected to a corresponding subset of the through vias 105 or 401 in the first array of vias . The conductors 501 supported by the carrier 107 may comprise electrically conductive and / or superconductive material . For compactness in reference , they are only called conductors in this text . Also , their connections to respectivethrough vias are described as conductive , which as a term covers here both ohmic conductivity and superconductivity .

[0046] An advantageous form of a carrier and conductors supported by the carrier i s described in more detail in the following . The following description refers to figs . 6 to 8 , which also illustrate steps of a method for constructing an arrangement of the kind described above .

[0047] Fig . 6 is an axonometric partial cross section in which the lower part of the drawing shows a block of dielectric material cut along an imaginary plane that cuts through a pair of through vias 401 and 402 that face each other perpendicularly across a linear slot 106. The upper part of the drawing shows a carrier 107 , which is not yet in place in fig . 6 but directly above the slot 106 to which it will become fixed by its first end (here : lower end) . Also the carrier 107 is shown cut along the same imaginary plane as the block of dielectric material in fig . 6 .

[0048] The carrier 107 shown in fig . 6 comprises layers 601 , 602 , and 603 of electrical ly insulating material in a stack . A first subset of conductors 501 consists of conductive tracks between a f irst outer layer 601 and an intermediate layer 602 in the stack . The first outer layer 601 comprises openings 502 at locations where each respective conductor 501 of the first subset of conductors is adj acent to a respective through via 105 in the first array of through vias . Each such conductor coming adj acent to a respective through via is seen more clearly in fig . 7 , in which the carrier 107 is fixed to the slot by its first end .

[0049] Taking advantage of the layered structure of the carrier 107 , there may be a second subset of conductors carried by the carrier 107 and located between the second outer layer 603 and the intermediate layer 602 in the stack of layers . Taken the viewing angle in fig . 6 , the conductors of the second subset are not visible except the one an edge of which is seen as a thicker line between the second outer layer 603 and the intermediate layer 602 . In the embodiment shown here , also the second outer layer 603 comprises openings at locations where each respective conductor of the second subset of conductors is adj acent to a respective through via in the block of dielectric material .

[0050] As such, it would not be necessary to make the carrier 107 shown in fig . 6 comprise layers of electrically insulating material in a stack or have the conductors between an outer layer and an intermediate layer in the carrier . It would be possible to make the carrier comprise only a single electrically insulating layer, on a surface of which ( or on the two surfaces of which) the conductors would be carried . However, for reasons that become clear below, the layered structure described here is advantageous in various ways .

[0051] The visible conductor that is figuratively cut by the cross-section plane in fig . 6 ends in a connection patch 604 visible in the respective opening of the first outer layer 601 . According to an advantageous embodiment , this conductor is an example of one among the first subset of conductors for which there is a respective conductor of the second subset so that the two conductors are similarly routed, like parallel and coincident for example , through a maj ority of their lengthon opposite sides of the intermediate layer 602 . This way, the two conductors form a pair of conductors that is particularly suitable for routing a differential signal , for example . The connection patch of the other conductor of the pair is at the location shown with reference designator 605 .

[0052] Fig . 8 shows an example of how conductors carried by the carrier 107 may be conductively connected to a corresponding subset of the through vias . The example describes here involves soldering with a conductive or superconductive solder . Reference designator 801 shows the solder j oint with which the connection patch that was shown with reference designator 604 in fig . 6 is connected to those parts of the through via 401 that were accessible on ( and close to ) the wall surface of the slot 106. Reference designator 802 shows the solder j oint with which the connection patch that was shown with reference designator 605 in fig . 6 is connected to those parts of the through via 402 that were accessible on ( and close to ) the wall surface of the slot 106 .

[0053] One or more surfaces of the carrier 107 may comprise a shielding conductor layer . In f igs . 6 to 8 , the whole visible surface of the first surface layer 601 ( or at least a significant portion of that surface ) may comprise an essentially continuous shielding conductor layer . While the term conductor layer i s used here for compactness , the layer in question may ( additionally or alternatively) comprise superconductive material for optimally effective shielding against electromagnetic interference in a cryogenically cooled environment .

[0054] I f one or more shielding conductor layers are provided, care should be taken not to allow any part ofthe shielding conductor layer make unintentional short circuits between any through vias in the block of dielectric material . For this purpose , any shielding conductor layer may be patterned at the ( first ) end of the ( first ) carrier . Fig . 6 shows some examples of possible patterning . Shown with reference designator 607 is a shortened portion of the material of the shielding conductor layer between two openings in the first outer layer 601 . Shown with reference designator 608 is a shortened portion of the material of the shielding conductor layer that is additionally isolated from the edges of its adj acent openings by narrowing . Reference designator 609 shows a portion of the outer surface of the outer layer 601 with material of the shielding conductor layer removed to a height that will remain above the surface of the block of dielectric material in the assembled configuration .

[0055] At least in some embodiments it may be advantageous to provide one or more conductive or superconductive connections between a shielding conductor layer and one or more of the through vias in the block of dielectric material . In fig . 8 , an example of such a connection is shown as the solder j oint 803 between the shielding conductor layer and the through via that was shown with reference designator 105 in some of the previous drawings .

[0056] Along the edge of the slot in the block of dielectric material , the example shown in figs . 6 to 8 has a regular, alternating pattern of conductive or superconductive connections ( i ) between a connector supported by the carrier and the respective through via and ( ii ) between the shielding conductor layer and therespective through vias . Thi s i s not a requirement , as there may be two or more adj acent connections of one such kind without any connection of the other kind in between .

[0057] The solder j oints described above may be mechanically strong enough to keep the carrier 107 attached in place in the slot 106 . I f even better mechanical strength is aimed at , further means may be provided for attaching the carrier by the end thereof to the slot . A non-limiting example of such further means is glue that could be spread on the bottom surface of the slot and / or on the end surface of the carrier before j oining these two together .

[0058] In the examples above , and in figs . 6 to 8 , only one carrier and its attachment to the respective slot in the block of dielectric material are shown . As already mentioned above in the description of figs . 2 to 4 , the block of dielectric material may comprise a plurality of slots in its first surface 103 . As also mentioned, if there are a plurality of slots , these are not necessarily of the same size and do not necessarily have the same orientation . Also , there is no need for any s lot in the f irst surface 103 to be a linear slot . The carrier described above may be one of a plurality of electrically insulating carriers of conductors . Each such carrier may then be flat and fixed, by a respective first end thereof , to a respective slot across the surface of the block of dielectric material . On each such carrier, at least a subset of the conductors supported by the carrier can be conductively or superconductively connected to a corresponding subset of the through vias in the respective array of through vias partially cutthrough by the respective slot . In fig . 1 the number of carriers is four, but it can be smaller or larger .

[0059] In quantum processing systems it i s often important to minimi ze the thermal loading of the cool ing system that under operation maintains the coldest parts of the system at their base temperature , which may be in the order of about 10 millikelvins . In particular, it should be poss ible to provide one or more so-called thermali zation points along the signal connections that couple signals to and / or from the quantum processing circuit operating at the base temperature . A thermalization point means a thermally conductive coupling to an actively cooled part of the cryostat that is used to establish and maintain the cryogenically cooled conditions at which parts of the quantum processing system are to operate .

[0060] One advantageous way of creating a thermali zation point is shown in fig . 1 . The arrangement shows at least one thermali zing block 108 of thermally conductive material . A material is considered thermally conductive for the purposes of making thermally conductive couplings in cryogenically cooled conditions if its thermal conductivity is for example at least 100 W / (m*K) at or above 10 K, at least 10 W / (m*K) at 1 K, at least 1 W / (m*K) at 0 . 1 K, or at least 0 . 1 W / (m*K) at 0 . 01 K . A widely used but non-limiting example of a thermally conductive material is copper .

[0061] The thermali zing block 108 is fixed, at a separating distance from the device 101 , to a surface of at least one of the carriers 107 of conductors that are comprised in the arrangement . In the example embodiment of f ig . 1 , in which there are four carriers , there arefive thermali zing blocks , all at the same separating distance from the device 101 . Three of the five thermali zing blocks are each located between respective two of the carriers , while the fourth and fifth thermali zing blocks are located leftmost and rightmost in the hori zontally oriented stack of thermali zing blocks . The area at which a thermali zing block is in contact with the respective carrier may be called the contact area for short .

[0062] Fig . 1 does not show separately any actively cooled part of the surrounding cryostat or any thermally conductive coupling from any of the thermalizing blocks 108 and such an actively cooled part , as these are outside the scope of the present description . A person skilled in the art of cryogenic cool ing knows a large variety of ways of providing thermally conductive couplings of this kind . A non-limiting example is to fix a pliable element such as a braid of copper or silver between the elements that should be thermally coupled together .

[0063] I f the conductors are superconductive , they may contribute very little to any thermal conductivity in the longitudinal direction of the carriers . The bulk material of the carriers , in turn, should have as low thermal conductivity as possible to minimi ze any heat flow along the carriers towards the coldest parts . In cryogenic technology, low thermal conductivity may be for example less than 50 W / (m*K) at 100 K, less than 5 W / (m*K) at 10 K, less than 0 . 75 W / (m*K) at 1 K, less than 0 . 075 W / (m*K) at 0 . 1 K, and less than 0 . 0075 W / (m*K) at 0 . 01 K . One consequence thereof is that if a carrier has the general structure shown in figs . 6 to 8 , withlayers of (electrically insulating) bulk material in a stack and with electric conductors located between an outer layer and an intermediate layer in the stack, simply placing thermali zing blocks against the outer surfaces of such a carrier would not create a very ef fective thermali zation point on the conductors .

[0064] An improvement over such a non-optimal thermali zation solution is shown in f igs . 9 and 10 . As al ready shown in figs . 6 to 8 , openings in the outer layers 601 and 603 are provided at a certain distance from the end of the carrier that is to be fixed to the slot in the block of dielectric material . One such opening is singled out with reference designator 606 . The openings coincide with the locations of the conductors , so that for example a part of the conductor 501 is seen to cut across the opening 606 . The intermediate layer 602 does not have a corresponding opening at the same place so that it remains there supporting the visible section of the conductor 501 .

[0065] Fig . 9 shows how at last a portion of the constituting material of the carrier 107 i s replaced with a thermal conductor material 901 that has a higher thermal conductivity than the constituting (bulk) material of the carrier . In practice , one may fi ll the openings 606 with moldable material that has , once cured, a higher thermal conductivity than the bulk material of the carrier . To avoid disturbing the propagation of signals along the respective conductors , the thermal conductor material 901 should be electrically insulating . One such material is known by its brand name Stycast , available from Henkel Adhesives at the time of writing this text .

[0066] Fig . 10 shows how a thermali zation block 108 may be pres sed against the surface of the carrier at a height that coincides with the openings 606 seen in figs . 6 to 8 . As the drawing is once again a partial cross-section, at the cutting plane it is seen how the thermali zation block 108 comes also into mechanical contact with the exposed surface of the thermal conductor material 1001 .

[0067] Openings in the surface layer filled with Stycast or some similar material could be used regardless of whether such an opening coincides with a connector by location . A "blind" opening that only provided access to a mere patch of the surface of an intermediate layer of the carrier could in any case improve the thermal conductivity - and thereby the thermali zing effect - between the intermediate layer and the actively cooled part of the cryostat to which there is a thermally conductive coupling from the thermali zation block . In an embodiment li ke that of f igs . 6 to 9 , the thermal conductor material 901 connects also the connector carried by the respective carrier to the thermali zing block, providing an effective thermali zation point to the conductor .

[0068] Fig . 11 is a side view of a part of an electrically insulating carrier 1101 according to an embodiment . As a dif ference to the embodiments shown in the earlier drawings , the carrier 1101 in fig . 11 has openings at its side surface at three different distances from the lower end of the carrier . By filling these openings with Stycast or some similar material and by providing the respective thermali zing blocks , one may provide three different levels of thermalization .Alternatively, one may provide a more efficient coupling to a single level of thermali zation . All three levels have the same regular line of openings , but this is not a requirement ; different levels could have different numbers of openings that could be placed differently . For example , a checkerboard pattern of openings could be used to improve the overal l mechanical integrity of the carrier, as no individual thermali zation level would have the carrier mechanically weakened with a complete line of openings across its both surfaces .

[0069] Another advanced feature in the embodiment of fig . 11 is the provision of so-called fencing vias that separate adj acent conductors from each other . For example, via 1102 is part of the vertical column of fencing vias to the left of the leftmost visible conductor 1104 , while via 1103 is part of the vertical column of fencing vias to the right of it . Assuming that all vias shown in f ig . 11 are ( super ) conductive vias through the carrier 1101 , and also assuming that both outer surfaces of the carrier 1101 have respective essentially continuous shielding ( super ) conductor layers , connected to each other by the fencing vias whilepossibly patterned at the first end as described earlier, the connector 1104 and its mirrored twin (not shown) on the other surface of the intermediate layer of the carrier 1101 constitute an efficiently shielded pair for conveying differential signals .

[0070] Another advanced feature in the embodiment of fig . 11 is the provi sion of intermediate cuts 1105 at that end of the carrier 1101 that is to be fixed to a slot in a block of dielectric material . As the coeffi cients of thermal expansion may be different between thematerial of the carrier and the material of the dielectric block, slotting the lower edge of the carrier may help to reduce any shear forces that could otherwise tend to load the attachment .

[0071] Fig . 12 is a top view of a device according to an embodiment , showing the first surface of a block 1201 of dielectric material . In the embodiment of fig . 12 , through vias in the block 1201 of dielectric material are arranged in three linearly organi zed arrays . A slot 1202 in the first surface of the block 1201 is linear in this embodiment but does not extend across the whole first surface . The slot 1202 cuts partially through the through vias in the leftmost and central arrays of through vias . In these arrays , the through vias do not form pairs that would face each other perpendicularly across the slot 1202 . Rather, the two arrays of through vias form a staggered configuration in which, considered in the longitudinal direction of the slot 1202 , a through via in one of the arrays is at halfway between two adj acent through vias in the other array . Such an arrangement may enable a very tight packing of through vias , particularly if the slot therebetween can be made very narrow .

[0072] Fig . 13 is a top view of a device according to an embodiment , showing the first surface of a block 1301 of dielectric material . In the embodiment of fig . 13 , through vias in the block 1301 of dielectric material are arranged in four linearly organi zed arrays , two of which are mutually aligned in the middle column of through vias in fig . 13 . A first slot 1302 in the first surface of the block 1301 is linear in thi s embodiment and extends , at one end thereof , to an edge of the block1301 . The s lot 1302 cuts partial ly through a subset of the through vias in the leftmost array of through vias and through all through vias in the top middle array . A second slot 1303 cuts partially through another subset of the through vias in the leftmost array of through vias and through all through vias in the bottom middle array . Similar to the embodiment of fig . 12 , there is one array of through vias that is not cut at all by any of the slots . Such uncut through vias may be used for other purposes , like for coupling conductive ( or superconductive ) areas or tracks on the first surface of the dielectric block to conductive ( or superconductive ) areas or tracks on the second surface of the dielectric block .

[0073] Fig . 14 illustrates further variations of how slots and through vias may be located in a device of the kind described above . As shown in fig . 14 , the array ( s ) of through vias need not be linearly organi zed; the slot ( s ) need not be linear , and if there are more than one slot , such slots need not be parallel to each other . Through vias and other conductive or superconductive couplings may be located in various ways at those parts of the block 1401 of dielectric material that does not have slots . Also, there may be other kinds of couplings formed in or on the block 1401 of dielectric material . An example of the last-mentioned is the conductive or superconductive pattern 1402 that comprises a coupling patch at an edge of the block 1401 of dielectric material and a conductor track from there to one of the through vias .

[0074] Fig . 15 illustrates an example embodiment of an arrangement for coupling signals to a quantumprocessing circuit 102 . The purpose of fig . 15 is to illustrate some possible variations to the embodiments described earlier . For example , the first surface 103 of the block 101 of dielectric material does not need to be planar and does not need to be parallel to the second surface 104 . Also , if there are several flat carriers of conductors in the arrangement , these need not all belong to a common group that would have a common set of thermali zation blocks . Neither do such carriers of conductors need to all be oriented parallel to each other .

[0075] Fig . 1 shows how the device 101 may be connected to a quantum proces sing circuit 102 for example through bump bonding or through a ball grid array . One of the schematically shown bonding bumps is singled out with reference designator 109 in fig . 1 . Superconductive material s such as indium should be used for these connections if the overall nature of signal connections requires superconductivity . The lower end of each through via in the device constitutes a possible connection patch for making a signal connection to or from the quantum processing circuit 102 .

[0076] At the distant end ( s ) of the carrier ( s ) , meaning the upper end ( s ) in fig . 1 , the connections may continue using any known technology such as wires and cables coupled to the conductors on the carrier ( s ) through some suitable means . Examples of connectors and cabling are schematically shown as 110 and 111 respectively . It may be noted that while the electrically insulating carriers 107 have been shown in the drawings as being planar and rigid, this is not a requirement as they can be made of materials known from the technologyof flexible printed circuit boards . Thi s means that at that end where the signal couplings continue with cables 111 there may be considerably more space than at the other end, as at least some of the carriers may bend sideways , making the plurality of carriers fan out to the sides if necessary . I f thermali zation blocks are used at a plurality of levels , these may be thicker towards the upper end, supporting the fan-out shape of the bunch of carriers .

[0077] Materials for the parts of the arrangement deserve some consideration, in particular from the viewpoint of compatibility with each other and with cryogenically cooled conditions . Cooling the coldest parts of a quantum processing system to their initial room temperature to the operating temperature in the order of only some millikelvins will involve relatively large changes in physical dimensions due to thermal contraction . It is advantageous to make the device 101 of a material that has its coefficient of thermal expansion as close to that of the quantum proces sing circuit 102 as possible . This requirement can be relaxed somewhat , however , if the signal couplings ( see the bonding bump 109 for example ) between the two can be made in a way that allows some mutual displacement in the hori zontal direction . I f a substrate of the quantum processing circuit 102 is silicon for example , also the device 101 could be made of sil icon ( l ike crystal line or polymorphous silicon for example ) or some other material having its coefficient of thermal expansion in the corresponding range , like aluminium nitride for example . For a quantum processing circuit based on a sapphire substrate , the device 101 could be similarly made ofsapphire or of some ceramic material that has its coefficient of thermal expansion close to that of sapphire .

[0078] Examples of materials that could be used as a bulk material for the carriers include substrate materials for vacuum-compliant printed circuit boards , such as ceramic-filled or glass microfibre filled PTFE (polytetrafluorethylene ) composites available from manufacturers such as Rogers Corporation, as well as some epoxy laminates available from the company Park Advanced Circuitry Materials at the time of writing this text . More commonly used printed circuit board materials may also be used at least if the vacuum pumping system of the quantum process ing system may be relied upon to handle the small amount of outgassing that may occur and / or if the parts of the device can be suitably pre-treated for better compliancy with vacuum conditions , by pre-baking for example . Conductors on the carriers may be made of any conductive or superconductive material commonly used in lithographic processes to produce conductor traces on substrates of the kind mentioned above .

[0079] Devices and arrangements according to the description above have multiple advantages compared to previously known ways of making connections to and from quantum processing circuits . Conventional wire bonding, for example , has its l imitations when it comes to density and number of connections that can be made : trying to make a very large number ( >100 ) of bonded connections would require making the quantum processing circuit large enough to have long edges that could accommodate all the required bonding pads . A large circuit means long on-chip signal lines that are vulnerable to interference and crosstalk and make impedance matchingcomplicated. Bump bonding or BGAs using flip-chip technology may take advantage of two-dimensional arrays of connection points, but protecting the traces on the connectivity chip against interference and crosstalk may again become complicated.

[0080] With solutions like those described above, the density of connection points between the device 101 and the quantum processing circuit 102 can be estimated by comparing to densities of superconducting through vias that can be achieved with known technology. At the time of writing this text, Kyocera corporation has announced their capability of producing arrays of the so-called CC200 vias with 0.635 millimetres spacing between via centres. Similarly at the time of writing this text, it is plausible that a basic unit consisting of one qubit, two tuneable couplers, and one readout resonator on the quantum processing circuit, known as the unit cell, could reserve a 2 x 2 millimetres area. Each such unit cell may be estimated to require four signals: one signal for the microwave drive and three signals for flux. In and out signals for readout could be multiplexed among 10 qubits, resulting in a calculatory 0.2 signals per unit cell. Each of the signals listed above may be assumed to be a differential signal that requires two through vias in the block of dielectric material. Placing 4.2 x 2 = 8.4 through vias on a square area of 2 x 2 mm gives a required density of 2.1 such vias on each square millimetre. This, in turn, is achieved by placing the vias in a square grid with 0.690 mm pitch, which is clearly achievable at least with the CC200 via technology mentioned above.

[0081] The array of connection points between the device 101 and the quantum proces sing circuit 102 may thus have essentially the same dens ity as the points at which signals should be inj ected to and / or collected from the basic circuit elements of the quantum processing circuit . This means that lateral routing in the quantum processing circuit may be avoided to a large extent , making it simpler to avoid interference and crosstalk .

[0082] The solution described above may be characteri zed as fully lithographic up to the point where the cable connections come to the upper end ( s ) of the carrier ( s ) . This means that there may be little need to handle individual signal connectors , which makes constructing large quantum processing systems easier and faster . Unit cost per signal can be assumed to be lower than if individual UHV-compatible coaxial cables were used, and the solution is compatible with semiconductor circuit assembling techniques such as BGAs and bump bonding that allow integration in three dimensions . Thermal loading to the coldest parts of the quantum processing system is minimal , as all connections can be made to have extremely low ( or non-exi stent ) ohmic resistance and as all conductors can be effectively thermali zed at multiple points . The solution is particularly well suited for coupling shielded differential signals such as flux signals to the quantum processing circuit .

[0083] While one may need to use tooling techniques such as laser ablation to produce the final form of the carrier ( s ) , the possibility of keeping the middle layer of a three-layer carrier material intact of fers an advantage from the viewpoint of mechanical stability .

Claims

CLAIMS1. A device (101) for coupling signals to a quantum processing circuit (102) , the device comprising :- a block of dielectric material having a first surface (103) and, on an opposite side of the block, a second surface (104) ,- a first array of through vias (105) , each such through via extending from the first surface (103) to the second surface (104) of the block, and- a first slot (106) in the first surface (103) ; wherein the first slot (106) cuts partially through at least a subset of the through vias (105) in the first array of through vias, leaving an uncut portion (404) of each of the through vias (105) extending intact from the first surface (103) to the second surface(104) .

2. A device according to claim 1, wherein:- the first slot (106) is one of a first plurality of slots in the first surface (103) ,- the first array of through vias (105) is one of a second plurality of arrays of through vias (105) , each through via in the second plurality of arrays of through vias extending from the first surface (103) to the second surface (104) , and- each slot (106) in the first plurality of slots cuts partially through at least a subset of the through vias (105) of at least one array of through vias (105) in the second plurality.

3. A device according to any of claims 1 or2, wherein:- in addition to the first array of through vias(105) , the device comprises at least a second array of through vias (401) , each through via in the first and second arrays extending from the first surface (103)to the second surface (104) ,- the first slot (106) leaves the uncut portion (404) of each of the through vias (105) of the first array of through vias extending intact from the first surface (103) to the second surface (104) on a first side of the first slot (106) , and- the first slot (106) cuts partially through at least a subset of the through vias (105) of the second array of through vias (401) , leaving the uncut portion (404) of each of the through vias (401) of the second array of through vias extending intact from the first surface (103) to the second surface (104) on a second side of the first slot (106) , opposite to the first side .

4. A device according to claim 3, wherein:- the first and second arrays of through vias (105,401) comprise at least one pair of through vias (401,402) so that-- one through via (401) of the pair belongs to the first array of through vias, -- the other through via (402) of the pair belongs to the second array of through vias, and -- the through vias (401, 402) of the pair face each other across the first slot (106) .

5. An arrangementf or coupling signals to a quantum processing circuit (102) , the arrangement comprising :- a device (101) according to any of claims 1 to 4,- an electrically insulating first carrier (107) , and- conductors (501) supported by the first carrier (107) ; wherein the first carrier (107) is flat and fixed, by a first end thereof, to the first slot (106) , and wherein at least a first subset of the conductors (501) supported by the first carrier (107) areconductively connected to a corresponding subset of the through vias (105) in the first array of through vias .

6. An arrangement according to claim 5, wherein :- the first carrier (107) comprises layers (601, 602, 603) of electrically insulating material in a stack,- each conductor (501) in the first subset of conductors is between a first outer layer (601) and an intermediate layer (602) in the stack, and- the first outer layer (601) comprises openings (502) at locations where each respective conductor (501) of the first subset of conductors is adjacent to a respective through via (105) in the first array of through vias.

7. An arrangement according to claim 6, wherein :- each conductor of a second subset of the conductors supported by the first carrier (107) is between a second outer layer (603) and the intermediate layer (602) in the stack, and- the second outer layer (603) comprises openings at locations where each respective conductor of the second subset of conductors is adjacent to a respective through via in the device (101) .

8. An arrangement according to claim 7, wherein :- at least one conductor of the first subset of conductors and a respective at least one conductor of the second subset of conductors are similarly routed through a majority of their length on opposite sides of the intermediate layer (602) , forming a pair of conductors for routing a differential signal.

9. An arrangement according to any of claims 5 to 8, comprising a shielding conductor layer on at least one surface of the first carrier (107) .

10. An arrangement according to any of claims 5 to 9, wherein:- the device (101) comprises a first plurality of slots in its first surface (103) ,- the first carrier (107) is one of a second plurality of electrically insulating carriers of conductors; wherein each carrier of the second plurality is flat and fixed, by a respective first end thereof, to a respective slot of the first plurality, and wherein at least one subset of conductors supported by each carrier of the second plurality are conductively connected to a corresponding subset of the through vias in the respective array of through vias partially cut through by the respective slot.

11. An arrangement according to any of claims 5 to 10, comprising at least one thermalizing block (108) of thermally conductive material fixed, at a separating distance from the device (101) , to a surface of at least one of the one or more carriers (107) of conductors comprised in the arrangement.

12. An arrangement according to claim 11, wherein at a contact area or contact areas between the thermalizing block (108) and the respective one or more carriers (107) , to the surface or surfaces of which the thermalizing block (108) is fixed, at least a portion of a constituting material of the respective one or more carriers (107) is replaced with a thermal conductor material (901) with higher thermal conductivity than the constituting material.

13. An arrangement according to claim 12, wherein the thermal conductor material (901) connectsat least one conductor supported by the respective carrier to the thermalizing block (108) .

14. A quantum processing system comprising at least one arrangement according to any of claims 5 to 13.

15. A method for manufacturing a device (101) for use to couple signals to a quantum processing circuit (102) , the method comprising:- providing a block of dielectric material having a first surface (103) and, on an opposite side of the block, a second surface (104) ,- forming a first array of through vias (105) through the block of dielectric material, each through via in the first array of through vias extending from the first surface (103) to the second surface (104) , and- forming a first slot (106) in the first surface(103) so that the first slot (106) cuts partially through each of the through vias (105) in the first array of through vias, leaving an uncut portion (404) of each of the through vias (105) extending intact from the first surface (103) to the second surface(104) .

Images