Linear adder circuit

Abstract

This linear adder circuit comprises unit cells (10-1, 10-2) and collector resistors (RCP, RCN). Each unit cell is formed from a differential pair (1-1, 1-2) comprising a first transistor (Q1P, Q2P) and a second transistor (Q1N, Q2N), an emitter degeneration resistor (RE1P, RE1N, RE2P, RE2N), and a current source (IEE1, IEE2). The collector resistor (RCP) is connected to the collector of the second transistor (Q1N, Q2N) that outputs a normal-phase output signal (VOUT_P), and the collector resistor (RCN) is connected to the collector of the first transistor (Q1P, Q2P) that outputs an inverted-phase output signal (VOUT_N).

Description

Linear Addition Circuit

[0001] The present invention relates to a linear addition circuit having a function of linearly adding a plurality of wideband analog signals.

[0002] Recent high-speed, high-capacity communication systems have begun to handle wideband baseband signals (analog signals containing multilevel information). Therefore, there is an increasing need for measuring instruments used for testing communication devices and verifying systems to handle wideband analog signals. In particular, measuring instruments used in optical communication systems are now required to handle ultra-wideband baseband and analog signals with frequencies of tens of GHz or more. This has led to an increasing demand for various functions to process wideband baseband and analog signals. Specifically, amplifiers, distributors, linear adders, and subtracters are required.

[0003] Conventionally, a multiplexer using resistors R100 to R102 as shown in FIG. 14 has been known as a means for realizing a wideband analog signal addition function (Non-Patent Document 1). ０ When configuring a multiplexer, the values ​​of resistors R100 to R102 are Z ０ 14, however, there are problems in that attenuation of signal strength is unavoidable and it is difficult to ensure isolation between ports.

[0004] On the other hand, an adder circuit as shown in Fig. 15 is also commonly known (Non-Patent Document 2). This adder circuit is composed of an operational amplifier A200 and resistors R200 to R202. However, due to limitations in the operating speed of the operational amplifier itself, the adder circuit of Fig. 15 is not suitable for realizing an addition function over an ultra-wide frequency range such as several tens of GHz.

[0005] Furthermore, most baseband signals in current communications are differential signals, so it is preferable to implement the addition function using a fully differential, wideband configuration for communications applications.

[0006] Atsushi Hirohata, "Chapter 6: Types and Usage of Dividers / Combiners: Key Parts for Dividing / Combining High-Frequency Signals," Transistor Technology, December 2004, pp. 172-173, <https: / / toragi.cqpub.co.jp / wp-content / uploads / p172-173-3.pdf> Enger, "Part 3: The Science of Circuits! Introduction to Op-Amp Arithmetic, Chapter 1: Op-Amp Arithmetic Circuits Starting with Addition," Transistor Technology, December 2022, p. 102, <https: / / toragi.cqpub.co.jp / wp-content / uploads / p102-18.pdf>

[0007] The present invention has been made to solve the above-mentioned problems, and has as its object to provide a fully differential linear adder circuit that can linearly add a plurality of wideband analog signals.

[0008] A linear adder circuit according to the present invention comprises a plurality of unit cells arranged in parallel, each receiving a different differential input signal as an input, and first and second collector resistors provided between a first power supply voltage and the plurality of unit cells, each unit cell comprising a differential pair including a first transistor receiving a positive-phase input signal of the differential input signals at its base and a second transistor receiving a negative-phase input signal of the differential input signals at its base, emitter degeneration resistors connected to the emitters of the first and second transistors, and current sources provided between the emitters of the first and second transistors and the second power supply voltage, and the first collector resistor is connected to the collectors of the plurality of second transistors that output positive-phase output signals of the differential output signals, and the second collector resistor is connected to the collectors of the plurality of first transistors that output negative-phase output signals of the differential output signals.

[0009] According to the present invention, it is possible to add two or more wideband analog signals at high speed and linearly, and it is possible to control the voltage gain of the response by selecting the value of the collector resistance, etc., and it is possible to ensure sufficient strength (amplitude) of the analog signal after addition. Furthermore, in this invention, each port is separated via a transistor, so that isolation between the ports can be sufficiently ensured. Furthermore, since the present invention has a fully differential configuration, it is possible to realize a circuit suitable for processing differential baseband signals commonly used in communications.

[0010] FIG. 1 is a circuit diagram showing the configuration of a linear adder circuit according to a first embodiment of the present invention. FIGS. 2A to 2C are diagrams showing example waveforms of differential input signals and differential output signals. FIG. 3 is a circuit diagram showing the configuration of a linear adder circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of a linear adder circuit according to a third embodiment of the present invention. FIG. 5 is a circuit diagram showing the configuration of a linear adder circuit according to a fourth embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration of a linear adder circuit according to a fifth embodiment of the present invention. FIG. 7 is a circuit diagram showing another configuration of a linear adder circuit according to the fifth embodiment of the present invention. FIG. 8 is a circuit diagram showing another configuration of a linear adder circuit according to the fifth embodiment of the present invention. FIG. 9 is a circuit diagram showing another configuration of a linear adder circuit according to the fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing the configuration of a linear adder circuit according to a sixth embodiment of the present invention. FIG. 11 is a circuit diagram showing another configuration of a linear adder circuit according to the sixth embodiment of the present invention. FIG. 12 is a circuit diagram showing another configuration of a linear adder circuit according to the sixth embodiment of the present invention. FIG. 13 is a circuit diagram showing another configuration of a linear adder circuit according to the sixth embodiment of the present invention. 14 is a circuit diagram showing the configuration of a multiplexer, and FIG. 15 is a circuit diagram showing the configuration of an adder.

[0011] 1 is a circuit diagram showing the configuration of a linear adder circuit according to a first embodiment of the present invention. The linear adder circuit receives a positive-phase input signal V ＩＮ１ _ Ｐ A bipolar transistor Q1P receives an input signal V ＩＮ１ _ ＮA differential pair 1-1 is composed of a bipolar transistor Q1N to which a positive phase input signal V is input, and a base ＩＮ２ _ Ｐ A bipolar transistor Q2P is input to the base of which is connected to an inverted input signal V ＩＮ２ _ Ｎ A differential pair 1-2 is formed by a bipolar transistor Q2N to which the input is input, and an emitter degeneration resistor R Ｅ１Ｐ , R Ｅ１Ｎ and an emitter degeneration resistor R whose one end is connected to the emitters of the transistors Q2P and Q2N. Ｅ２Ｐ , R Ｅ２Ｎ and one end is resistor R Ｅ１Ｐ , R Ｅ１Ｎ The other end is connected to the power supply voltage V ＥＥ A constant current source I connected to ＥＥ１ and one end is resistor R Ｅ２Ｐ , R Ｅ２Ｎ The other end is connected to the power supply voltage V ＥＥ A constant current source I connected to ＥＥ２ One end is the power supply voltage V ＣＣ , and the other end is connected to the positive phase output signal V ＯＵＴ _ Ｐ A collector resistor R connected to the collectors of the two transistors Q1N and Q2N that output ＣＰ One end is the power supply voltage V ＣＣ , and the other end is connected to the inverted output signal V ＯＵＴ _ Ｎ A collector resistor R connected to the collectors of the two transistors Q1P and Q2P that output ＣＮ It consists of:

[0012] Differential pair 1-1 and emitter degeneration resistor R Ｅ１Ｐ , R Ｅ１Ｎ and constant current source I ＥＥ１ The differential pair 1-2 and the emitter degeneration resistor R Ｅ２Ｐ , R Ｅ２Ｎ and constant current source I ＥＥ２In this way, the linear addition circuit of this embodiment is configured such that two unit cells 10-1 and 10-2 are arranged in parallel, and the collectors of the transistors that output signals of the same polarity in the two unit cells 10-1 and 10-2 are connected to the same collector resistor.

[0013] In particular, in this embodiment, the constant current source I ＥＥ１ , I ＥＥ２ Current value I ＥＥ and emitter degeneration resistance R Ｅ１Ｐ , R Ｅ１Ｎ , R Ｅ２Ｐ , R Ｅ２Ｎ Resistance value R Ｅ is set. ＥＥ R Ｅ >V ＩＮ１ _ ｍａｘ -V ＩＮ１ _ ｍｉｎ ...(1) I ＥＥ R Ｅ >V ＩＮ２ _ ｍａｘ -V ＩＮ２ _ ｍｉｎ ... (2)

[0014] Here, V ＩＮ１ _ ｍａｘ is the differential input signal V ＩＮ１ _ Ｐ , V ＩＮ１ _ Ｎ The maximum voltage level of V ＩＮ１ _ ｍｉｎ is the differential input signal V ＩＮ１ _ Ｐ , V ＩＮ１ _ Ｎ is the minimum voltage level of ＩＮ２ _ ｍａｘ is the differential input signal V ＩＮ２ _ Ｐ , V ＩＮ２ _ Ｎ The maximum voltage level of V ＩＮ２ _ ｍｉｎ is the differential input signal V ＩＮ２ _ Ｐ , V ＩＮ２ _ Ｎ The right side of equation (1) is the minimum value of the voltage level of the differential input signal VＩＮ１ _ Ｐ , V ＩＮ１ _ Ｎ The right side of equation (2) represents the voltage amplitude of the differential input signal V ＩＮ２ _ Ｐ , V ＩＮ２ _ Ｎ In this way, in this embodiment, the current value I ＥＥ and resistance value R Ｅ The product of these is set to be greater than the amplitude of the differential input signal.

[0015] The differential input signal V ＩＮ１ (V ＩＮ１ _ Ｐ , V ＩＮ１ _ Ｎ ) and V ＩＮ２ (V ＩＮ２ _ Ｐ , V ＩＮ２ _ Ｎ ) are linearly converted into collector currents proportional to the voltages (collector currents corresponding to the mutual conductances of the transistors Q1P, Q1N, Q2P, and Q2N). Furthermore, the two converted signals are converted into collector currents proportional to the voltages of the collector resistors R Ｃ (R ＣＰ , R ＣＮ ) are linearly added, and the voltage drops by an amount corresponding to the total amount of current after addition, resulting in a differential output signal V ＯＵＴ (V ＯＵＴ _ Ｐ , V ＯＵＴ _ Ｎ ) is output.

[0016] Furthermore, this embodiment is characterized in that the operating states of the transistors Q1P, Q1N, Q2P, and Q2N are set to satisfy equations (3) and (4) in order to minimize the parasitic capacitance of the transistors Q1P, Q1N, Q2P, and Q2N, particularly the base-collector capacitance, and to suppress dynamic fluctuations in the base-collector capacitance. ＩＮ１ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ ... (3) V ＩＮ２ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ ...(4)

[0017] Here, V ＯＵＴ _ ｍｉｎ is the differential output signal V ＯＵＴ _ Ｐ , V ＯＵＴ _ Ｎ is the minimum value of the voltage level of the transistors Q1P, Q1N, Q2P, and Q2N. In other words, equations (3) and (4) indicate that the transistors Q1P, Q1N, Q2P, and Q2N operate with the base voltage level always lower than the collector voltage level. This feature minimizes the base-collector capacitance of the transistors Q1P, Q1N, Q2P, and Q2N, and also suppresses dynamic fluctuations in the base-collector capacitance, thereby achieving faster addition processing, wider bandwidth, and suppression of dynamic distortion.

[0018] Since the linear adder circuit of this embodiment has a fully differential configuration, it is possible to perform subtraction processing of two differential input signals by inverting the polarity of one of the differential input signals and inputting it. In other words, the circuit of this embodiment can be used not only as a linear adder circuit but also as a linear subtractor circuit.

[0019] As a supplement, to clarify the definition of each voltage level, the differential input signal V ＩＮ１ (V ＩＮ１ _ Ｐ , V ＩＮ１ _ Ｎ ), V ＩＮ２ (V ＩＮ２ _ Ｐ , V ＩＮ２ _ Ｎ ) and the differential output signal V ＯＵＴ (V ＯＵＴ _ Ｐ , V ＯＵＴ _ Ｎ ) are shown in Figures 2A-2C. Here, two differential input signals V ＩＮ１ , V ＩＮ２ 10 shows the case where sine waves of the same frequency and phase are input.

[0020] 3 is a circuit diagram showing the configuration of a linear addition circuit according to a second embodiment of the present invention. ＥＥ Constant current source I ＥＥ１ , I ＥＥ２In contrast to this, in this embodiment, the current value is I ＥＥ / 2 constant current source I ＥＥ１Ｐ , I ＥＥ１Ｎ , I ＥＥ２Ｐ , I ＥＥ２Ｎ Two current sources are provided for each differential pair. ＥＥ１Ｐ is the voltage between the emitter of transistor Q1P and the power supply voltage V ＥＥ and a current source I ＥＥ１Ｎ is the voltage between the emitter of transistor Q1N and the power supply voltage V ＥＥ The current source I ＥＥ２Ｐ is the voltage between the emitter of transistor Q2P and the power supply voltage V ＥＥ and a current source I ＥＥ２Ｎ is the voltage between the emitter of transistor Q2N and the power supply voltage V ＥＥ It is set between.

[0021] In the first embodiment, the emitter degeneration resistor R Ｅ１Ｐ , R Ｅ１Ｎ , R Ｅ２Ｐ , R Ｅ２Ｎ In contrast to this, in this embodiment, the resistance value is 2R Ｅ The emitter degeneration resistance R Ｅ１ , R Ｅ２ One emitter degeneration resistor R Ｅ１ is provided between the emitter of the transistor Q1P and the emitter of the transistor Q1N, and an emitter degeneration resistor R Ｅ２ is provided between the emitter of the transistor Q2P and the emitter of the transistor Q2N. Ｅ１ and constant current source I ＥＥ１Ｐ , I ＥＥ１Ｎ The differential pair 1-2 and the emitter degeneration resistor R Ｅ２ and constant current source I ＥＥ２Ｐ , I ＥＥ２Ｎ and form a unit cell 10a-2.

[0022] In this embodiment, by configuring the circuit so as to satisfy the conditions described in the first embodiment, i.e., equations (1) to (4), it is possible to achieve the same functions and performance as in the first embodiment.

[0023] [Third embodiment] Next, a configuration for improving the speed performance of the circuits of the first and second embodiments will be described. Fig. 4 is a circuit diagram showing the configuration of a linear adder circuit according to a third embodiment of the present invention. The circuit of this embodiment differs from the circuit of the first embodiment in that the upper stage of the differential pair transistors, i.e., the collectors of the transistors Q1P, Q1N, Q2P, and Q2N and the collector resistor R ＣＰ , R ＣＮ Cascode transistors Q-1P, Q-1N, Q-2P, and Q-2N are added between them.

[0024] The bases of the transistors Q-1P, Q-1N, Q-2P, and Q-2N are connected to a bias voltage V ＣＡＳ The collectors of the transistors Q-1P and Q-2P are connected to the collector resistor R ＣＮ The collectors of the transistors Q-1N and Q-2N are connected to the collector resistor R ＣＰ The emitters of the transistors Q-1P, Q-1N, Q-2P, and Q-2N are connected to the collectors of the transistors Q1P, Q1N, Q2P, and Q2N. The differential pair 1-1 and the emitter degeneration resistor R Ｅ１Ｐ , R Ｅ１Ｎ and constant current source I ＥＥ１ The transistors Q-1P and Q-1N constitute a unit cell 10b-1. The differential pair 1-2 and the emitter degeneration resistor R Ｅ２Ｐ , R Ｅ２Ｎ and constant current source I ＥＥ２ and transistors Q-2P and Q-2N form a unit cell 10b-2.

[0025] This embodiment is characterized in that, in addition to the formulas (1) to (4), the formulas (5) to (7) are further satisfied. ＩＮ１ _ ｍａｘ <V ＣＡＳ -V ＢＥＯＮ ... (5) V ＩＮ２ _ ｍａｘ <V ＣＡＳ -V ＢＥＯＮ... (6) V ＣＡＳ <V ＯＵＴ _ ｍｉｎ ... (7)

[0026] Here, V ＢＥＯＮ is the on-voltage of transistors Q-1P, Q-1N, Q-2P, and Q-2N. Equations (5) and (6) indicate that transistors Q1P, Q1N, Q2P, and Q2N operate in a state where the collector voltage is always higher than the base voltage. Furthermore, equation (7) indicates that transistors Q-1P, Q-1N, Q-2P, and Q-2N are also designed to operate in a state where the collector voltage is always higher than the base voltage.

[0027] In this embodiment, by adding transistors Q-1P, Q-1N, Q-2P, and Q-2N and satisfying equations (5) and (6), the output terminal (V ＯＵＴ _ Ｐ , V ＯＵＴ _ Ｎ ) can be reduced, the impedance seen from the output terminal to the circuit side can be increased, and an even faster response time can be achieved in the addition process.

[0028] 5 is a circuit diagram showing the configuration of a linear adder circuit according to a fourth embodiment of the present invention. This embodiment shows a configuration in which cascode transistors Q-1P, Q-1N, Q-2P, and Q-2N are added to the circuit of the second embodiment. The differential pair 1-1 and the emitter degeneration resistor R Ｅ１ and constant current source I ＥＥ１Ｐ , I ＥＥ１Ｎ The transistors Q-1P and Q-1N constitute a unit cell 10c-1. The differential pair 1-2 and the emitter degeneration resistor R Ｅ２ and constant current source I ＥＥ２Ｐ , I ＥＥ２Ｎ and transistors Q-2P and Q-2N form a unit cell 10c-2.

[0029] In this configuration, by configuring the addition of transistors Q-1P, Q-1N, Q-2P, and Q-2N so as to satisfy the above equations (5) to (7), it is possible to obtain the same functions and performance as in the third embodiment.

[0030] 6 is a circuit diagram showing the configuration of a linear adder circuit according to a fifth embodiment of the present invention. The circuit of this embodiment is the same as the circuit of the first embodiment except for the constant current source I ＥＥ１ , I ＥＥ２ variable current source I ＥＥ１Ｖ , I ＥＥ２Ｖ It has been replaced by V. ＣＳ１ , V ＣＳ２ is the variable current source I ＥＥ１Ｖ , I ＥＥ２Ｖ is the external control voltage.

[0031] Similarly, the constant current source I ＥＥ１Ｐ , I ＥＥ１Ｎ , I ＥＥ２Ｐ , I ＥＥ２Ｎ variable current source I ＥＥ１ＰＶ , I ＥＥ１ＮＶ , I ＥＥ２ＰＶ , I ＥＥ２ＮＶ The replaced configuration is shown in Figure 7. ＣＳ１Ｐ , V ＣＳ１Ｎ , V ＣＳ２Ｐ , V ＣＳ２Ｎ is the variable current source I ＥＥ１ＰＶ , I ＥＥ１ＮＶ , I ＥＥ２ＰＶ , I ＥＥ２ＮＶ The external control voltage is the constant current source I ＥＥ１ , I ＥＥ２ variable current source I ＥＥ１Ｖ , I ＥＥ２Ｖ The configuration in which the constant current source I ＥＥ１Ｐ , I ＥＥ１Ｎ , I ＥＥ２Ｐ , I ＥＥ２Ｎ variable current source I ＥＥ１ＰＶ , I ＥＥ１ＮＶ , I ＥＥ２ＰＶ , I ＥＥ２ＮＶ The configuration in which the above is replaced is shown in FIG.

[0032] In this way, by replacing the constant current source with a variable current source in the first to fourth embodiments, the left sides of equations (1) and (2) can be made variable, and the linear response range can be adjusted according to the analog input signal being handled.

[0033] Sixth Embodiment In the first to fifth embodiments, a linear adder circuit that adds two analog signals has been described. However, the present invention is not limited to a two-input configuration, and by expanding the number of parallel circuits based on differential pairs to two or more, it is also possible to configure an adder circuit for a number of wideband analog signals corresponding to the number of parallel circuits.

[0034] In the first embodiment, a configuration in which m (m is an integer equal to or greater than 3) unit cells 10-1 to 10-m are connected in parallel is shown in FIG. 10. The circuit in FIG. 10 receives m differential input signals V ＩＮ１ (V ＩＮ１ _ Ｐ , V ＩＮ１ _ Ｎ ), V ＩＮ２ (V ＩＮ２ _ Ｐ , V ＩＮ２ _ Ｎ ), ..., V ＩＮｍ (V ＩＮｍ _ Ｐ , V ＩＮｍ _ Ｎ ) is added.

[0035] In the second embodiment, a configuration in which m unit cells 10a-1 to 10a-m are connected in parallel is shown in Fig. 11. In the third embodiment, a configuration in which m unit cells 10b-1 to 10b-m are connected in parallel is shown in Fig. 12. In the fourth embodiment, a configuration in which m unit cells 10c-1 to 10c-m are connected in parallel is shown in Fig. 13.

[0036] In the configurations of FIGS. 10 to 13, formulas (1) and (2) are generalized to give formula (8), and formulas (3) and (4) are generalized to give formula (9). ＥＥ R Ｅ >V ＩＮＸ _ ｍａｘ -V ＩＮＸ _ ｍｉｎ ... (8) V ＩＮＸ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ ...(9)

[0037] V ＩＮＸ _ ｍａｘ is the differential input signal V ＩＮＸ _ Ｐ , VＩＮＸ _ Ｎ The maximum voltage level of V ＩＮＸ _ ｍｉｎ is the differential input signal V ＩＮＸ _ Ｐ , V ＩＮＸ _ Ｎ (X is an integer between 1 and m). In the configurations of FIGS. 12 and 13, equations (5) and (6) can be generalized to obtain equation (10). V ＩＮＸ _ ｍａｘ <V ＣＡＳ -V ＢＥＯＮ ...(10)

[0038] 10 and 11, the circuit constants of each unit cell can be set so that they satisfy the formulas (8) and (9). In the configurations of Figures 12 and 13, the circuit constants of each unit cell can be set so that they satisfy the formulas (7) to (10).

[0039] 10 to 13, the constant current source I ＥＥ１ , I ＥＥ２ , I ＥＥ１Ｐ , I ＥＥ１Ｎ , I ＥＥ２Ｐ , I ＥＥ２Ｎ variable current source I ＥＥ１Ｖ , I ＥＥ２Ｖ , I ＥＥ１ＰＶ , I ＥＥ１ＮＶ , I ＥＥ２ＰＶ , I ＥＥ２ＮＶ may be replaced with .

[0040] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0041] (Supplementary Note 1) A linear adder circuit of the present invention comprises a plurality of unit cells arranged in parallel, each receiving a different differential input signal as an input, and first and second collector resistors provided between a first power supply voltage and the plurality of unit cells, each unit cell comprising a differential pair consisting of a first transistor receiving a positive-phase input signal of the differential input signals at its base and a second transistor receiving a negative-phase input signal of the differential input signals at its base, emitter degeneration resistors connected to the emitters of the first and second transistors, and current sources provided between the emitters of the first and second transistors and a second power supply voltage, the first collector resistor being connected to the collectors of the plurality of second transistors that output positive-phase output signals of differential output signals, and the second collector resistor being connected to the collectors of the plurality of first transistors that output negative-phase output signals of the differential output signals.

[0042] (Supplementary Note 2) In the linear addition circuit according to Supplementary Note 1, the current value of the current source is I ＥＥ , the resistance value of the emitter degeneration resistor is R Ｅ , the maximum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍａｘ , the minimum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍｉｎ , the minimum value of the voltage level of the differential output signal is V ＯＵＴ _ ｍｉｎ Then, each unit cell is I ＥＥ R Ｅ >V ＩＮＸ _ ｍａｘ -V ＩＮＸ _ ｍｉｎ , V ＩＮＸ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ Meet the following.

[0043] (Supplementary Note 3) In the linear addition circuit described in Supplementary Note 1, each unit cell further includes third and fourth transistors provided between the first and second collector resistors and the first and second transistors, and having bases to which a bias voltage is input, the third transistor having a collector connected to the second collector resistor and an emitter connected to the collector of the first transistor, and the fourth transistor having a collector connected to the first collector resistor and an emitter connected to the collector of the second transistor.

[0044] (Supplementary Note 4) In the linear addition circuit according to Supplementary Note 3, the current value of the current source is I ＥＥ , the resistance value of the emitter degeneration resistor is R Ｅ , the maximum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍａｘ , the minimum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍｉｎ , the minimum value of the voltage level of the differential output signal is V ＯＵＴ _ ｍｉｎ , the bias voltage is V ＣＡＳ , the on-voltage of the third and fourth transistors is V ＢＥＯＮ Then, each unit cell is I ＥＥ R Ｅ >V ＩＮＸ _ ｍａｘ -V ＩＮＸ _ ｍｉｎ , V ＩＮＸ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ , V ＩＮＸ _ ｍａｘ <V ＣＡＳ -V ＢＥＯＮ , V ＣＡＳ <V ＯＵＴ _ ｍｉｎ Meet the following.

[0045] 1-1 to 1-m... differential pairs, 10-1, 10a-1, 10b-1, 10c-1, 10-2, 10a-2, 10b-2, 10c-2 to 10-m, 10a-m, 10b-m, 10c-m... unit cells, Q1P, Q1N, Q2P, Q2N, Q-1P, Q-1N, Q-2P, Q-2N... transistors, R Ｅ１ , R Ｅ１Ｐ , RＥ１Ｎ , R Ｅ２ , R Ｅ２Ｐ , R Ｅ２Ｎ ...emitter degeneration resistance, R ＣＰ , R ＣＮ ...collector resistance, I ＥＥ１ , I ＥＥ１Ｐ , I ＥＥ１Ｎ , I ＥＥ２ , I ＥＥ２Ｐ , I ＥＥ２Ｎ ...constant current source, I ＥＥ１Ｖ , I ＥＥ１ＰＶ , I ＥＥ１ＮＶ , I ＥＥ２Ｖ , I ＥＥ２ＰＶ , I ＥＥ２ＮＶ ...variable current source.

Claims

1. A linear addition circuit comprising: a plurality of unit cells arranged in parallel, each receiving a different differential input signal; and first and second collector resistors provided between a first power supply voltage and the plurality of unit cells, wherein each unit cell comprises: a differential pair consisting of a first transistor to the base of which a positive-phase input signal of the differential input signals is input; and a second transistor to the base of which an inverted phase input signal of the differential input signals is input; emitter degeneration resistors connected to the emitters of the first and second transistors; and current sources provided between the emitters of the first and second transistors and a second power supply voltage, wherein the first collector resistor is connected to the collectors of the plurality of second transistors which output positive-phase output signals of the differential output signals, and the second collector resistor is connected to the collectors of the plurality of first transistors which output inverted phase output signals of the differential output signals.

2. In the linear addition circuit according to claim 1, the current value of the current source is I ＥＥ , the resistance value of the emitter degeneration resistor is R Ｅ , the maximum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍａｘ , the minimum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍｉｎ , the minimum value of the voltage level of the differential output signal is V ＯＵＴ _ ｍｉｎ Then, each unit cell is I ＥＥ R Ｅ >V ＩＮＸ _ ｍａｘ -V ＩＮＸ _ ｍｉｎ , V ＩＮＸ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ A linear addition circuit characterized by satisfying the following.

3. A linear addition circuit according to claim 1, wherein each unit cell further comprises third and fourth transistors provided between the first and second collector resistors and the first and second transistors, and having bases to which a bias voltage is input; the third transistor has a collector connected to the second collector resistor and an emitter connected to the collector of the first transistor; and the fourth transistor has a collector connected to the first collector resistor and an emitter connected to the collector of the second transistor.

4. The linear addition circuit according to claim 3, wherein the current value of the current source is I ＥＥ , the resistance value of the emitter degeneration resistor is R Ｅ , the maximum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍａｘ , the minimum value of the voltage level of the differential input signal is V ＩＮＸ _ ｍｉｎ , the minimum value of the voltage level of the differential output signal is V ＯＵＴ _ ｍｉｎ , the bias voltage is V ＣＡＳ , the on-voltage of the third and fourth transistors is V ＢＥＯＮ Then, each unit cell is I ＥＥ R Ｅ >V ＩＮＸ _ ｍａｘ -V ＩＮＸ _ ｍｉｎ , V ＩＮＸ _ ｍａｘ <V ＯＵＴ _ ｍｉｎ , V ＩＮＸ _ ｍａｘ <V ＣＡＳ -V ＢＥＯＮ , V ＣＡＳ <V ＯＵＴ _ ｍｉｎ A linear addition circuit characterized by satisfying the following.

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