Display device driver IC inspection system

Abstract

This display device driver IC inspection system is used for a display device having a plurality of display elements and provided for inspecting a driver IC for driving the plurality of display elements. The display device driver IC inspection system comprises, on a wafer, a plurality of driver ICs arranged in a matrix for each inspection block. Each of the plurality of driver ICs has a clock signal input terminal to which a clock signal is input, a signal input terminal to which a test signal for inspecting the driver IC is input, a clock signal output terminal from which the clock signal is output, a signal output terminal from which the test signal is output, and a test mode switching circuit. The plurality of driver ICs arranged in a row include adjacent first and second driver ICs. The clock signal output terminal of the first driver IC is connected to the clock signal input terminal of the second driver IC. The signal output terminal of the first driver IC is connected to the signal input terminal of the second driver IC.

Description

Display driver IC inspection system

[0001] The present invention relates to a test system for a display driver IC.

[0002] Japanese Patent Application Laid-Open No. 2003-144222 discloses a technique relating to a test system for conducting electrical tests on semiconductor chips formed on a semiconductor wafer.

[0003] Japanese Patent Application Laid-Open No. 2001-210685

[0004] As the size of semiconductor chips decreases, the number of semiconductor chips formed on one semiconductor wafer increases. In such an inspection system, if a test is performed by contacting a probe such as a tester with each semiconductor chip, the time required for inspection may become longer as the number of semiconductor chips increases.

[0005] An object of the present invention is to provide a system for inspecting display driver ICs that can reduce the inspection time.

[0006] An inspection system for display device driver ICs according to one aspect of the present disclosure is used in a display device having a plurality of display elements, and is an inspection system for driver ICs for driving the plurality of display elements, and has a plurality of driver ICs formed in a matrix on a wafer for each inspection block, and each of the plurality of driver ICs has a clock signal input terminal to which a clock signal is input, a signal input terminal to which a test signal for inspecting the driver IC is input, a clock signal output terminal to output the clock signal, a signal output terminal to output the test signal, and a test mode switching circuit, and the plurality of driver ICs arranged in a column direction include adjacent first driver ICs and second driver ICs, and the clock signal output terminal of the first driver IC is connected to the clock signal input terminal of the second driver IC, and the signal output terminal of the first driver IC is connected to the signal input terminal of the second driver IC.

[0007] FIG. 1 is a plan view schematically showing a wafer of an inspection system according to a first embodiment. FIG. 2 is a plan view schematically showing multiple driver ICs, a first test circuit, and a second test circuit in an inspection block of the wafer. FIG. 3 is an explanatory diagram illustrating the connection configuration of multiple driver ICs, a first test circuit, and a second test circuit in an inspection block. FIG. 4 is a block diagram showing an example configuration of a driver IC. FIG. 5 is an explanatory diagram comparing example configurations of a test signal, a test start signal, and a test release signal input to a driver IC with example configurations of image data, pixel data, and control signals input in normal mode. FIG. 6 is a plan view schematically showing a display device according to a second embodiment. FIG. 7 is a plan view showing pixels of the display device according to the second embodiment. FIG. 8 is a circuit diagram showing a driver IC, multiple driver ICs, and multiple light-emitting elements. FIG. 9 is an explanatory diagram illustrating the connection configuration of a driver IC, multiple driver ICs, and a test circuit in test mode. FIG. 10 is a timing chart showing clock signals and image data input and output to the driver IC in display mode. FIG. 11 is an explanatory diagram illustrating an example configuration of image data transmitted and received by pixel ICs. FIG. 12 is an explanatory diagram for explaining a method for rewriting identification information.

[0008] Modes (embodiments) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] First Embodiment FIG. 1 is a plan view schematically showing a wafer of an inspection system according to a first embodiment. FIG. 2 is a plan view schematically showing a plurality of driver ICs, a first test circuit, and a second test circuit in an inspection block of the wafer. An inspection system 10 of this embodiment inspects a plurality of driver ICs 50 formed on a wafer 100 and determines whether the driver ICs are good or bad. After being diced into individual pieces, the driver ICs 50 formed on the wafer 100 are used in a display device 1 (see FIGS. 6 and 7 ) to drive a plurality of light-emitting elements 3 (display elements) included in the display device 1.

[0010] 1 and 2, a wafer 100 on which driving ICs 50 are formed has a plurality of inspection blocks 101 partitioned in a matrix. In FIGS. 1 and 2, the boundaries of the inspection blocks 101 are schematically indicated by dashed lines. The wafer 100 is, for example, a silicon wafer. However, the wafer 100 is not limited to this, and other semiconductor materials may also be used.

[0011] As shown in FIG. 2, the test block 101 is provided with a plurality of driver ICs 50, a first test circuit 102, a second test circuit 103, connection pads 104 and 105, a clock signal supply wiring 106, and a signal supply wiring 107.

[0012] In the first embodiment, the first direction D1 and the second direction D2 are parallel to the surface of the wafer 100. The first direction D1 is perpendicular to the second direction D2. However, the first direction D1 may intersect the second direction D2 without being perpendicular thereto. The third direction D3 is a direction perpendicular to the first direction D1 and the second direction D2. The third direction D3 corresponds to, for example, the normal direction of the wafer 100. Note that, hereinafter, a plan view refers to the positional relationship when viewed from the third direction D3.

[0013] The driving ICs 50 are, for example, micro ICs, and are very small, with each side measuring approximately 100 μm or less. The driving ICs 50 are formed in a matrix for each inspection block 101. In other words, the driving ICs 50 are arranged in a first direction D1 and a second direction D2.

[0014] In the following description, the multiple driver ICs 50 arranged in the second direction D2 in the inspection block 101 may be referred to as a driver IC row 50C. The driver IC rows 50C are arranged in the first direction D1. Each driver IC row 50C includes a first driver IC 50-1, a second driver IC 50-2, ..., an n-th driver IC 50-n. As shown in FIG. 2, each driver IC row 50C includes six driver ICs 50 (n=6). However, the shape, size, and number of driver ICs 50 in the inspection block 101 (the number of driver ICs 50 in each driver IC row 50C and the number of driver IC rows 50C arranged in the first direction D1) are merely examples and can be changed as appropriate.

[0015] In one driver IC column 50C, the multiple driver ICs 50 arranged in the second direction D2 are connected in series by clock signal supply wiring 106 and signal supply wiring 107. The clock signal supply wiring 106 supplies a clock signal CLK to the multiple driver ICs 50 in the driver IC column 50C. The signal supply wiring 107 supplies a test signal DAT to the multiple driver ICs 50 in the driver IC column 50C. The clock signal supply wiring 106 and the signal supply wiring 107 connect two driver ICs 50 adjacent to each other in the second direction D2. Furthermore, the clock signal supply wiring 106 and the signal supply wiring 107 are each provided independently between two driver ICs 50 adjacent to each other in the second direction D2.

[0016] In other words, the multiple clock signal supply wirings 106 are provided between two adjacent driver ICs 50 in the second direction D2, and are spaced apart from each other for each driver IC 50. Similarly, the multiple signal supply wirings 107 are provided between two adjacent driver ICs 50 in the second direction D2, and are spaced apart from each other for each driver IC 50. As a result, the first driver IC 50-1 and the second driver IC 50-2 to the n-th driver IC 50-n arranged in the second direction D2 are connected in series. Note that the clock signal supply wirings 106 and the signal supply wirings 107 are not provided between driver IC columns 50C adjacent to each other in the first direction D1, and therefore the clock signal CLK and the test signal DAT are not transmitted or received.

[0017] The first test circuit 102 is arranged on one side of the driving IC column 50C (the plurality of driving ICs 50 arranged in the second direction D2) in the second direction D2. The second test circuit 103 is arranged on the other side of the driving IC column 50C (the plurality of driving ICs 50 arranged in the second direction D2) in the second direction D2. The first test circuit 102 and the second test circuit 103 are provided corresponding to the plurality of driving IC columns 50C arranged in the first direction D1. In other words, in the inspection block 101, the plurality of driving IC columns 50C are arranged between the first test circuit 102 and the second test circuit 103 in the second direction D2.

[0018] A plurality of connection pads 104 are connected to the first test circuit 102. A plurality of connection pads 105 are connected to the second test circuit 103. In the test system 10 of this embodiment, probe pins of an external test device 120 (see FIG. 3 ) come into contact with the connection pads 104, 105 formed on the wafer 100, the test device 120 is connected to the test block 101 of the wafer 100, and the test system 10 tests a plurality of driver ICs 50.

[0019] Next, the details of the method for testing the driving ICs 50 in the testing system 10 of this embodiment will be described with reference to Figures 3 to 5. Figure 3 is an explanatory diagram for explaining the connection configuration of multiple driving ICs, a first test circuit, and a second test circuit in a testing block.

[0020] 3, the first test circuit 102 has an interface 102a and a test signal generation circuit 102b. The interface 102a is electrically connected to, for example, connection pads 104, and connects to an external testing device 120. The test signal generation circuit 102b generates a test signal DAT based on a control signal from the testing device 120. The first test circuit 102 also has a clock signal output terminal 111 and a signal output terminal 112. The clock signal output terminal 111 outputs a clock signal CLK. The signal output terminal 112 outputs the test signal DAT.

[0021] Each of the multiple driver ICs 50 has a clock signal input terminal 51, a signal input terminal 52, a clock signal output terminal 53, a signal output terminal 54, and a test mode switching circuit 65a. A clock signal CLK is input to the clock signal input terminal 51. A test signal DAT is input to the signal input terminal 52. The clock signal output terminal 53 outputs the clock signal CLK. The signal output terminal 54 outputs the test signal DAT.

[0022] The test mode switching circuit 65a switches between a test mode and a normal mode of the driving IC 50 in response to the test signal DAT (see FIG. 5). In the test mode of the driving IC 50, the inspection system 10 inspects the plurality of driving ICs 50. In the normal mode, when the driving IC 50 is mounted on the display device 1, the driving IC 50 has the function of driving the plurality of light-emitting elements 3 and displaying on the display device 1.

[0023] The test mode switching circuit 65a can switch the driving IC 50 into test mode in response to an input test start signal ST (see FIG. 5). Furthermore, the test mode switching circuit 65a releases the driving IC 50 from test mode when a test release signal EN (see FIG. 5) having a predetermined pattern is input. Specifically, the test mode switching circuit 65a switches between the signal path for test pattern data TP and the signal path for image data DT within the driving IC 50 between test mode and normal mode. The switching of signal paths will be described later with reference to FIG. 4.

[0024] Of the drive IC column 50C (plurality of drive ICs 50 arranged in the second direction D2), the clock signal input terminal 51 of the first drive IC 50-1 located on one side in the second direction D2 is connected to the clock signal output terminal 111 of the first test circuit 102 via the clock signal supply wiring 106 (see FIG. 2). In addition, the signal input terminal 52 of the first drive IC 50-1 is connected to the signal output terminal 112 of the first test circuit 102 via the signal supply wiring 107.

[0025] The clock signal output terminal 53 of the first driver IC 50-1 is connected to the clock signal input terminal 51 of the second driver IC 50-2 adjacent to the first driver IC 50-1 via a clock signal supply wiring 106 (see FIG. 2). The signal output terminal 54 of the first driver IC 50-1 is connected to the signal input terminal 52 of the second driver IC 50-2 adjacent to the first driver IC 50-1 via a signal supply wiring 107.

[0026] Of the driver IC row 50C (plurality of driver ICs 50 arranged in the second direction D2), the clock signal output terminal 53 of the nth driver IC 50-n in the final row (i.e., the driver IC 50 located on the other side of the second direction D2) is connected via clock signal supply wiring 106 (see FIG. 2) to the clock signal input terminal 113 of the second test circuit 103. In addition, the signal output terminal 54 of the nth driver IC 50-n is connected via signal supply wiring 107 to the signal input terminal 114 of the second test circuit 103.

[0027] The clock signal CLK output from the first test circuit 102 is sequentially transmitted in series (serial) to the first driver IC 50-1, the second driver IC 50-2, ..., the n-th driver IC 50-n via the clock signal supply wiring 106. Furthermore, the test signal DAT output from the first test circuit 102 is sequentially transmitted in series (serial) to the first driver IC 50-1, the second driver IC 50-2, ..., the n-th driver IC 50-n via the signal supply wiring 107.

[0028] The second test circuit 103 (or the inspection device 120) receives the test signal DAT output from the driver IC column 50C and compares it with a preset reference value to determine whether the multiple driver ICs 50 in the driver IC column 50C are pass or fail. Specifically, the second test circuit 103 has an interface 103a and a test signal judgment circuit 103b. The interface 103a is electrically connected to, for example, connection pads 105 (see FIG. 2 ) and connects to the external inspection device 120. The test signal judgment circuit 103b compares the test signal DAT received from the n-th driver IC 50-n in the final stage with a preset reference value to determine whether the driver IC column 50C is pass or fail. The second test circuit 103 outputs the judgment result of the test signal judgment circuit 103b to the inspection device 120.

[0029] The second test circuit 103 does not have to have the test signal determination circuit 103b. In this case, the second test circuit 103 may output the test signal DAT from the n-th driver IC 50-n in the final stage to the inspection device 120, and the inspection device 120 may determine whether the driver IC row 50C is a good product or a defective product.

[0030] In this way, the inspection system 10 of this embodiment inspects the multiple driver ICs 50 for each inspection block 101 (for each of the multiple driver ICs 50 sandwiched between the first test circuit 102 and the second test circuit 103). Furthermore, in the inspection system 10 of this embodiment, if all driver ICs 50 in one driver IC column 50C in the inspection block 101 are pass-through, the entire driver IC column 50C is determined to be pass-through. Furthermore, if at least one driver IC 50 in one driver IC column 50C is defective, the entire driver IC column 50C including the defective driver IC 50 is determined to be defective.

[0031] As a result, in this embodiment, the time required to inspect the plurality of driving ICs 50 formed on the wafer 100 can be reduced compared to when inspecting each of the plurality of driving ICs 50 individually.

[0032] 4 is a block diagram showing an example of the configuration of the driver IC 50. As shown in FIG. 4, the driver IC 50 includes buffer circuits 61 and 62, flip-flop circuits 63 and 64, a control circuit 65, a PWM control circuit 66, a memory circuit 67, and a light-emitting element drive circuit 68 (display element drive circuit).

[0033] The driving IC 50 has external connection terminals, such as a clock signal input terminal 51, a signal input terminal 52, a clock signal output terminal 53, and a signal output terminal 54, as well as a power supply terminal 55, a reference potential terminal 56, and connection terminals 57, 58, and 59. At least one light-emitting element 3 (display element) is connected to each of the connection terminals 57, 58, and 59, and when used as a display device 1, the driving IC 50 has the function of displaying an image using the plurality of light-emitting elements 3 (display elements) connected to the connection terminals 57, 58, and 59. The power supply terminal 55, the reference potential terminal 56, and the connection terminals 57, 58, and 59 are used when the driving IC 50 is mounted on the display device 1, and details of these terminals will be described later in the second embodiment ( FIG. 8 ).

[0034] FIG. 4 also illustrates the signal path of the test signal DAT in the test mode of the driving IC 50 and the signal path of the image data DT in the normal mode, and the detailed operations of the buffer circuits 61 and 62, the flip-flop circuits 63 and 64, the control circuit 65, the PWM control circuit 66, the memory circuit 67, and the light-emitting element drive circuit 68 will be described later in the second embodiment.

[0035] The test mode switching circuit 65a (see FIG. 3) of the driving IC 50 is included in, for example, the control circuit 65. However, without being limited to this, the test mode switching circuit 65a (see FIG. 3) may be provided in the driving IC 50 as a circuit separate from the control circuit 65.

[0036] In a normal mode in which the driver IC 50 drives the light-emitting elements 3 when mounted on the display device 1, image data DT input to the signal input terminal 52 is supplied to a flip-flop circuit 63 and a control circuit 65, as indicated by arrows A1 and A2. The image data DT supplied to the control circuit 65 is then supplied to a memory circuit 67, a PWM control circuit 66, and a display element drive circuit to drive the light-emitting elements 3 (display elements). The image data DT is then subjected to predetermined processing in the control circuit 65, and is output from the signal output terminal 54 via a buffer circuit 62 and a flip-flop circuit 64, as indicated by arrows A3 and A4.

[0037] In a test mode in which the driving ICs 50 are formed on the wafer 100, a test signal DAT input from the signal input terminal 52 is supplied to the flip-flop circuit 63 and the control circuit 65, as indicated by arrows A1 and A2. The test signal DAT supplied to the control circuit 65 is then supplied from the control circuit 65 to the memory circuit 67, the PWM control circuit 66, and the light-emitting element drive circuit 68, in that order, as indicated by arrows B1, B2, B3, B4, and B5, before returning to the control circuit 65. The test signal DAT returned to the control circuit 65 via each circuit is then output from the signal output terminal 54 via the buffer circuit 62 and the flip-flop circuit 64, as indicated by arrows A3 and A4.

[0038] 4, the driver IC 50 has a plurality of switch elements for switching the signal path of the test signal DAT. The test mode switching circuit 65a controls the on / off of the plurality of switch elements to form the signal paths indicated by arrows B1, B2, B3, B4, and B5.

[0039] As described above, the driver IC 50 can switch signal paths between the test mode and the normal mode, thereby enabling proper testing of each circuit within the driver IC 50. Furthermore, the driver IC 50 shares terminals used for inputting and outputting the clock signal CLK and the test signal DAT in the test mode and terminals used for inputting and outputting the clock signal CK and the image data DT in the normal mode. This allows the driver IC 50 to prevent an increase in the number of terminals.

[0040] FIG. 5 is an explanatory diagram for comparing examples of the configurations of the test signal, test start signal, and test release signal input to the driving IC with examples of the configurations of the image data, pixel data, and control signals input in normal mode.

[0041] As shown in FIG. 5, the test signal DAT includes a test start signal ST, test pattern data TP, and a test cancel signal EN.

[0042] The test start signal ST is, for example, data consisting of M consecutive "0" bits. Here, let N be the number of bits in the pixel data DTp included in the image data DT input for image display. Let K be the number of bits in the control signal Vsync, which controls the start of transmission of one frame of image data DT. The control signal Vsync is data consisting of K consecutive "0" bits. The number of bits K in the control signal Vsync is greater than the number of bits N in the pixel data DTp (K>N). The number of bits M in the test start signal ST is greater than the number of bits N in the image data DT. Furthermore, the number of bits M in the test start signal ST is smaller than the number of bits K in the control signal Vsync. In other words, the number of bits M in the test start signal ST satisfies the relationship N<M<K. This prevents erroneous transition to test mode due to image data DT input in normal mode. Alternatively, even if erroneous transition to test mode occurs, normal mode can be restored in the next frame. The test release signal EN is implemented, for example, by issuing the test start signal ST again during test mode.

[0043] For example, the pixel data DTp of the image data DT is 17 bits, the data start signal Start of the pixel data DTp is set to "0", and the data end signal Stop is set to "1". In this case, the image data DT can have a maximum of 18 consecutive "0" bits. Therefore, data with consecutive "0" bits of number M, which is larger than number N of bits, can be assigned as the test start signal ST.

[0044] The configurations and bit numbers of the test start signal ST, test pattern data TP, and test release signal EN included in the test signal DAT shown in FIG. 5 are merely examples, and any data different from the image data DT may be used.

[0045] Second Embodiment Fig. 6 is a plan view schematically showing a display device according to a second embodiment. The inspection system 10 according to the first embodiment described above has been configured to inspect a plurality of driver ICs 50 formed on a wafer, but the present invention is not limited to this. In the second embodiment, an example will be described in which inspection of a plurality of driver ICs 50 is performed in a state in which the plurality of driver ICs 50 are mounted as a display device 1.

[0046] 6, the display device 1 includes a substrate 21, a plurality of pixels PX, driver ICs (Integrated Circuits) 11A and 11B, test circuits 103A and 103B, clock signal supply wiring 12, signal supply wiring 13, and a host 201. The host 201 is a host IC, a host CPU, or the like.

[0047] The substrate 21 is an insulating substrate made of glass, a film-like resin, etc. The substrate 21 is a substrate on which a driver IC 50 for driving each pixel PX and a plurality of light-emitting elements 3 (see FIG. 2) are mounted.

[0048] In the following description, the Dx direction and the Dy direction are directions parallel to the surface of the substrate 21. The Dx direction is perpendicular to the Dy direction. However, the Dx direction may intersect the Dy direction without being perpendicular thereto. The Dz direction is a direction perpendicular to the Dx direction and the Dy direction. The Dz direction corresponds to, for example, the normal direction of the substrate 21. Note that in the second embodiment, a plan view refers to a positional relationship when viewed from the Dz direction.

[0049] 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that is arranged to overlap with a plurality of pixels PX and displays an image. The peripheral area GA is an area that does not overlap with the plurality of pixels PX and is arranged outside the display area AA.

[0050] A plurality of pixels PX are arranged in a matrix in the display area AA of the substrate 21. That is, the plurality of pixels PX are arranged in both the Dx direction and the Dy direction. The plurality of pixels PX arranged in the Dy direction are connected in series via clock signal supply wiring 12 and signal supply wiring 13. Furthermore, a plurality of sets of the plurality of serially connected pixels PX are arranged in the Dx direction. In the following description, the plurality of serially connected pixels PX may be referred to as a pixel group PX-G. Furthermore, the plurality of driver ICs 50 included in the pixel group PX-G correspond to the driver IC column 50C in the first embodiment described above.

[0051] The pixel group PX-G (plurality of pixels PX connected in series) is arranged in the Dy direction in the order of pixel PX-1, pixel PX-2, pixel PX-3, ..., pixel PX-(n-2), pixel PX-(n-1), and pixel PX-n. Of the pixel group PX-G (plurality of pixels PX connected in series), pixel PX-1 located at one end in the Dy direction is connected to driver ICs 11A and 11B. Furthermore, clock signal supply wiring 12 and signal supply wiring 13 are not provided between plural pixels PX adjacent to each other in the Dx direction, and therefore transmission and reception of various signals is not performed.

[0052] The driver ICs 11A and 11B are circuits that control the display of the display device 1. The driver ICs 11A and 11B are provided in the peripheral area GA of the substrate 21. The driver ICs 11A and 11B supply a clock signal CK and image data DT (see FIG. 8) to each of the pixel groups PX-G. The driver ICs 11A and 11B also supply the clock signal CK and image data DT in synchronization with each other to the multiple pixel groups PX-G arranged in the Dx direction. Note that a detailed connection configuration of the driver ICs 11A and 11B and the multiple pixels PX will be described later with reference to FIG. 8.

[0053] The driver ICs 11A and 11B include the function of the first test circuit 102 in the first embodiment. The test circuits 103A and 103B include the function of the second test circuit 103 in the first embodiment. The driver ICs 11A and 11B are arranged in one peripheral area GA in the Dy direction of the pixel group PX-G (driver IC column 50C). The test circuits 103A and 103B are arranged in the other peripheral area GA in the Dy direction of the pixel group PX-G (driver IC column 50C).

[0054] The driver ICs 11A and 11B are arranged next to each other in the Dx direction. The driver IC 11A controls the display of a plurality of pixels PX located on the left side of the center of the display area AA in the Dx direction, among the plurality of pixels PX. The driver IC 11B controls the display of a plurality of pixels PX located on the right side of the center of the display area AA in the Dx direction, among the plurality of pixels PX. The driver IC 11A and the driver IC 11B control the pixel group PX-G in synchronization with each other. However, this is not limited thereto, and the display device 1 may have one driver IC 11 or three or more driver ICs 11.

[0055] The test circuits 103A and 103B are arranged adjacent to each other in the Dx direction. The test circuit 103A receives the test signal DAT from the pixel group PX-G (driver IC column 50C) located to the left of the center of the display area AA in the Dx direction, among the pixel groups PX-G (driver IC columns 50C), and determines whether the pixel group PX-G (driver IC column 50C) is a good product or a bad product. The test circuit 103B receives the test signal DAT from the pixel group PX-G (driver IC column 50C) located to the right of the center of the display area AA in the Dx direction, and determines whether the pixel group PX-G (driver IC column 50C) is a good product or a bad product. However, the present invention is not limited to this, and the display device 1 may have one test circuit or three or more test circuits.

[0056] FIG. 7 is a plan view showing pixels of a display device according to the second embodiment. As shown in FIG. 7, one pixel PX includes multiple pixels SPX and a driving IC 50. For example, the pixel PX includes pixels SPX-R, SPX-G, and SPX-B. The pixel SPX-R displays the primary color red as the first color. The pixel SPX-G displays the primary color green as the second color. The pixel SPX-B displays the primary color blue as the third color. As shown in FIG. 7, in one pixel PX, the pixels SPX-R, SPX-G, and SPX-B are aligned in the Dx direction. Note that the first color, second color, and third color are not limited to red, green, and blue, respectively, and any color, such as a complementary color, can be selected. Hereinafter, when there is no need to distinguish between the pixels SPX-R, SPX-G, and SPX-B, they will simply be referred to as pixel SPX.

[0057] Each pixel SPX has a light-emitting element 3, a cathode electrode 31, and an anode electrode 32. The display device 1 displays an image by emitting different light from each of the light-emitting elements 3R, 3G, and 3B in the pixels SPX-R, SPX-G, and SPX-B. That is, the light-emitting elements 3R, 3G, and 3B are display elements of the display device 1, and are self-emitting elements that emit red light, green light, and blue light, respectively.

[0058] The light-emitting element 3 is an inorganic light-emitting diode (LED) chip having a size of approximately 3 μm or more and 300 μm or less in plan view, and is called a micro LED. A display device 1 having a micro LED in each pixel is also called a micro LED display device. Note that the "micro" in micro LED does not limit the size of the light-emitting element 3.

[0059] The plurality of light-emitting elements 3 may emit light of four or more different colors. The arrangement of the plurality of pixels SPX is not limited to the configuration shown in Fig. 7 . For example, one pixel SPX among the plurality of pixels SPX may be adjacent to another pixel SPX in the Dy direction. The plurality of pixels SPX may also be arranged in a triangular lattice pattern.

[0060] A driver IC 50 is provided for each pixel PX. In the example shown in FIG. 7 , one driver IC 50 is provided for three pixels SPX. The driver IC 50 is connected to the cathode electrode 31 (cathode of the light-emitting element 3) of each pixel SPX via wiring 14. The driver IC 50 is also connected to the anode electrode 32 (anode of the light-emitting element 3) of each pixel SPX via wiring 15. The driver IC 50 controls the flow of a predetermined current to each light-emitting element 3 based on control signals (clock signal CK and image data DT) from the driver ICs 11A and 11B, causing the light-emitting element 3 to emit light.

[0061] 7 shows a configuration in which one driver IC 50 is connected to three light-emitting elements 3, but this is not limiting, and one driver IC 50 may be connected to at least one light-emitting element 3. Alternatively, one driver IC 50 may be connected to four or more light-emitting elements 3. Furthermore, the driver IC 50 is not limited to a configuration in which it is provided for each pixel PX, and one driver IC 50 may be provided for a plurality of pixels PX (for example, two adjacent pixels PX).

[0062] 7, the plurality of light-emitting elements 3 are mounted on a common substrate 21 together with the driving IC 50. However, the present invention is not limited to this, and the plurality of light-emitting elements 3 may be mounted on a mounting substrate different from the substrate 21. In this case, the plurality of light-emitting elements 3 are mounted on the substrate 21 together with the mounting substrate, and the driving IC 50 is electrically connected to the plurality of light-emitting elements 3 through the mounting substrate.

[0063] 8 is a circuit diagram showing a driver IC, multiple driver ICs, and multiple light-emitting elements. As shown in FIG. 8, the display device 1 has multiple light-emitting elements 3 (display elements), multiple driver ICs 50, and a driver IC 11. The multiple driver ICs 50 include a first driver IC 50-1, a second driver IC 50-2, and a third driver IC 50-3 connected in series. The first driver IC 50-1, the second driver IC 50-2, and the third driver IC 50-3 are provided corresponding to pixels PX-1, PX-2, and PX-3, respectively (see FIG. 6).

[0064] For ease of understanding, FIG. 8 shows three rows and two columns of driving ICs (pixels PX) among the multiple driving ICs (pixels PX). In the following description, when there is no need to distinguish between the first driving IC 50-1, the second driving IC 50-2, and the third driving IC 50-3, they will simply be referred to as driving ICs 50. When there is no need to distinguish between the driver ICs 11A and 11B, they will simply be referred to as driver ICs 11. When there is no need to distinguish between the clock signal supply wirings 12-1, 12-2, 12-3, and 12-4, they will simply be referred to as clock signal supply wiring 12. When there is no need to distinguish between the signal supply wirings 13-1, 13-2, 13-3, and 13-4, they will simply be referred to as signal supply wiring 13.

[0065] In the test mode, the clock signal input terminals 51, signal input terminals 52, clock signal output terminals 53, and signal output terminals 54 of the multiple driver ICs 50 input and output a clock signal CLK and a test signal DAT, similar to the first embodiment described above. Also, as shown in FIG. 8 , in the normal mode (the display mode of the display device 1), a clock signal CK is input to the clock signal input terminal 51. Image data DT is input to the signal input terminal 52. The clock signal output terminal 53 outputs the clock signal CK. The signal output terminal 54 outputs image data DT. In other words, the clock signal input terminals 51, signal input terminals 52, clock signal output terminals 53, and signal output terminals 54 of the multiple driver ICs 50 are shared between the test mode and the normal mode. The normal mode of the display device 1 will be described with reference to FIG. 8 . The test mode of the display device 1 (driver ICs 50) will be described with reference to FIG. 9 .

[0066] The clock signal input terminal 51 of the first driver IC 50-1 is connected to the driver IC 11 via a clock signal supply wiring 12-1. The signal input terminal 52 of the first driver IC 50-1 is connected to the driver IC 11 via a signal supply wiring 13-1. The multiple clock signal supply wirings 12-1, 12-2, 12-3, and 12-4 are provided independently between two driver ICs 50 adjacent to each other in the Dy direction. Similarly, the multiple signal supply wirings 13-1, 13-2, 13-3, and 13-4 are provided independently between two driver ICs 50 adjacent to each other in the Dy direction.

[0067] The clock signal output terminal 53 of the first driver IC 50-1 is connected to the clock signal input terminal 51 of the second driver IC 50-2 via the clock signal supply wiring 12-2. The signal output terminal 54 of the first driver IC 50-1 is connected to the signal input terminal 52 of the second driver IC 50-2 via the signal supply wiring 13-2.

[0068] The clock signal output terminal 53 of the second driver IC 50-2 is connected to the clock signal input terminal 51 of the third driver IC 50-3 via the clock signal supply wiring 12-3. The signal output terminal 54 of the second driver IC 50-2 is connected to the signal input terminal 52 of the third driver IC 50-3 via the signal supply wiring 13-3.

[0069] In other words, the multiple clock signal supply wirings 12 are provided between two adjacent drive ICs 50 in the Dy direction, and are spaced apart for each drive IC 50. Similarly, the multiple signal supply wirings 13 are provided between two adjacent drive ICs 50 in the Dy direction, and are spaced apart for each drive IC 50. As a result, the first drive IC 50-1, second drive IC 50-2, and third drive IC 50-3 arranged in the Dy direction are connected in series.

[0070] The clock signal CK output from the driver IC 11 is sequentially transmitted in series to the first driver IC 50-1, the second driver IC 50-2, and the third driver IC 50-3 via the clock signal supply wiring 12. Furthermore, the image data DT output from the driver IC 11 is sequentially transmitted in series to the first driver IC 50-1, the second driver IC 50-2, and the third driver IC 50-3 via the signal supply wiring 13.

[0071] As a result, the display device 1 of this embodiment can increase the bandwidth (frequency) of the transmitted clock signal CK and image data DT compared to when multiple driver ICs 50 are connected in parallel to a common clock signal supply wiring 12 and a common signal supply wiring 13. In other words, the display device 1 can suppress voltage fluctuations and delays in the clock signal CK and image data DT due to the wiring resistance of the clock signal supply wiring 12 and the signal supply wiring 13. This allows the phase relationship between the clock signal CK and the image data DT to be maintained. Therefore, the display device 1 of this embodiment can achieve good display characteristics even when the number of serially connected pixels PX is increased. For example, the display device 1 can be applied to full HD displays, 4K displays, and displays with even greater pixel counts.

[0072] Note that the clock signal supply wiring 12 and the signal supply wiring 13 are not provided between adjacent driver ICs 50 in the Dx direction, and the clock signal CK and the image data DT are not transmitted or received between them. The driver IC 11 outputs the clock signal CK and the image data DT in synchronization with the plurality of driver ICs 50 (plurality of pixel groups PX-G) arranged in the Dx direction.

[0073] The plurality of driver ICs 50 further include a power supply terminal 55, a reference potential terminal 56, and connection terminals 57, 58, and 59 (see FIG. 4 ). The power supply terminal 55 is connected to the driver IC 11 via a power supply potential supply wiring 17. As a result, the driver IC 11 supplies a power supply potential PVDD to the plurality of driver ICs 50 through the power supply terminal 55 and the power supply potential supply wiring 17. The power supply potential supply wiring 17 is also connected to the anodes of the light-emitting elements 3 (3R, 3G, and 3B). The driver IC 11 supplies the power supply potential PVDD to the anodes of the light-emitting elements 3 (3R, 3G, and 3B) through the power supply potential supply wiring 17.

[0074] The plurality of driving ICs 50 and the plurality of light-emitting elements 3 are connected in parallel to the power supply potential supply wiring 17. In other words, the power supply potential supply wiring 17 is provided in common to the plurality of driving ICs 50 and the plurality of light-emitting elements 3 arranged in the Dy direction. In addition, in Fig. 8, the power supply potential supply wiring 17 is provided in common to the plurality of driving ICs 50 and the plurality of light-emitting elements 3 in two columns aligned in the Dx direction. However, this is not limited thereto, and the power supply potential supply wiring 17 may be provided in common to one column or three or more columns of the plurality of driving ICs 50 and the plurality of light-emitting elements 3.

[0075] The reference potential terminal 56 is connected to the driver IC 11 via the reference potential supply wiring 18. As a result, the driver IC 11 supplies a reference potential GND to the plurality of driver ICs 50 via the reference potential terminal 56 and the reference potential supply wiring 18. The reference potential GND is, for example, a ground potential. However, the reference potential GND is not limited to this, and may be a predetermined fixed potential different from the ground potential.

[0076] The reference potential supply wiring 18 is provided in common to the plurality of driver ICs 50 arranged in the Dy direction. In other words, the plurality of driver ICs 50 are connected in parallel to the reference potential supply wiring 18. In Fig. 8, the reference potential supply wiring 18 is provided in common to two columns of driver ICs 50 arranged in the Dx direction. However, the present invention is not limited to this, and the reference potential supply wiring 18 may be provided in common to one column or three or more columns of driver ICs 50.

[0077] The connection terminals 57, 58, and 59 are connected to the cathodes of the light-emitting elements 3R, 3G, and 3B, respectively. The cathodes of the light-emitting elements 3R, 3G, and 3B are connected to the reference potential GND via the drive transistors inside the light-emitting element drive circuit 68 (see FIG. 4) by operation of the light-emitting element drive circuit 68 of the drive IC 50. As a result, the light-emitting elements 3R, 3G, and 3B are each forward-bias driven and emit light.

[0078] 9 is an explanatory diagram illustrating the connection configuration of a driver IC, multiple driver ICs, and a test circuit in test mode. As shown in FIG. 9, the driver IC 11 is arranged on one side of a driver IC column 50C (multiple driver ICs 50 arranged in the Dy direction) in the Dy direction. The driver IC 11 includes a test signal generation circuit 11c. In test mode, the driver IC 11 outputs a clock signal CK from a clock signal output terminal 11a to the multiple driver ICs 50, and outputs a test signal DAT from a signal output terminal 11b to the multiple driver ICs 50.

[0079] The test circuits 103A and 103B are arranged on the other side in the Dy direction of the drive IC column 50C (the plurality of drive ICs 50 arranged in the Dy direction). Similar to the second test circuit 103 described above, the test circuits 103A and 103B include interfaces 103Aa and 103Ba and test signal determination circuits 103Ab and 103Bb. In the test mode of the display device 1 of this embodiment, an external inspection device 120A is electrically connected to the test circuits 103A and 103B via the interfaces 103Aa and 103Ba, and the display device 1 inspects the plurality of drive ICs 50.

[0080] The connection configuration of the multiple driver ICs 50 in the driver IC column 50C is as described in FIG. 8 , and a repeated description will be omitted. In the test mode of the display device 1 of the second embodiment, the driver IC 11 outputs a clock signal CLK and a test signal DAT to the driver IC column 50C. The multiple driver ICs 50 in the driver IC column 50C sequentially transmit the clock signal CLK and the test signal DAT in series. The test circuits 103A and 103B compare the test signal DAT received from the nth driver IC 50-n in the final stage with a preset reference value to determine whether the driver IC column 50C is a non-defective product. The test circuits 103A and 103B may not include the test signal determination circuits 103Ab and 103Bb, and may instead output the test signal DAT to an external inspection device 120A. With the above configuration, in the second embodiment, the test mode can be performed with multiple driver ICs 50 mounted on the display device 1.

[0081] Next, an example of operation of the driving IC 50 in the normal mode (display mode of the display device 1) will be described with reference to Fig. 4 and Fig. 10. Fig. 10 is a timing chart showing clock signals and image data input and output to and from the driving IC in the display mode.

[0082] 4, the buffer circuit 61 is connected between the clock signal input terminal 51 and the clock signal output terminal 53. As a result, the clock signal CK input to the clock signal input terminal 51 of the driver IC 50 is output from the clock signal output terminal 53 via the buffer circuit 61. The buffer circuit 61 corrects for voltage fluctuations in the clock signal CK caused by the resistance of the clock signal supply wiring 12, wiring within the driver IC 50, and the like, and outputs the clock signal CK. As a result, even in a configuration in which multiple driver ICs 50 are connected in series, the clock signal CK is transmitted successfully all the way to the final driver IC 50 (the nth driver IC 50-n).

[0083] The flip-flop circuit 63 is connected between the clock signal input terminal 51, the signal input terminal 52, and the control circuit 65. The buffer circuit 62 and the flip-flop circuit 64 are connected in series between the control circuit 65 and the signal output terminal 54.

[0084] The flip-flop circuit 63 receives the clock signal CK from the clock signal input terminal 51 and the image data DT from the signal input terminal 52, and outputs the image data DT to the control circuit 65 at a timing according to the clock signal CK.

[0085] The control circuit 65 controls the lighting of the light-emitting elements 3 connected to the drive IC 50 based on the image data DT input through the signal input terminal 52 and the flip-flop circuit 63. The control circuit 65 performs predetermined processing on the input image data DT and outputs the processed image data to the buffer circuit 62.

[0086] The control circuit 65 performs predetermined processing on the input image data DT and outputs the result to the storage circuit 67, and also controls the PWM control circuit 66 and the light-emitting element drive circuit 68 based on the input image data DT. The storage circuit 67 stores the image data DT input from the control circuit 65. The PWM control circuit 66 determines the lighting periods of the plurality of light-emitting elements 3 corresponding to the gradation based on the image data DT acquired from the control circuit 65, and generates a PWM control signal.

[0087] The light-emitting element drive circuit 68 drives the plurality of light-emitting elements 3 connected to the connection terminals 57 , 58 , and 59 of the drive IC 50 based on the PWM control signal obtained from the PWM control circuit 66 .

[0088] Specifically, the light-emitting element drive circuit 68 may be configured to include, for example, multiple switch elements that switch the connection state between the cathode of the light-emitting element 3 and the reference potential terminal 56. For example, the light-emitting element drive circuit 68 may be configured to include multiple switch elements that switch the connection (on) and disconnection (off) between the cathode of the light-emitting element 3 and the reference potential GND based on a PWM control signal. During a predetermined period when the cathode of the light-emitting element 3 is connected to the reference potential GND, current flows through the light-emitting element 3, causing it to light up. Furthermore, during a period when the cathode of the light-emitting element 3 is not connected to the reference potential GND, the light-emitting element 3 is turned off. By varying the on and off periods based on the PWM control signal, the light-emitting element 3 can express a gradation corresponding to the image data DT. As described above, the multiple light-emitting elements 3 connected to the drive IC 50 are driven using PWM (Pulse Width Modulation) based on the image data DT acquired by the control circuit 65.

[0089] The buffer circuit 62 corrects and outputs the voltage fluctuation and delay time of the image data DT caused by the resistance of the signal supply wiring 13 and wiring in the driver IC 50. The delay time is corrected by adjusting the delay time so that the delay time of the data after predetermined processing of the image data DT is not shorter than the delay time caused by the buffer circuit 61 provided for the clock signal CK.

[0090] The flip-flop circuit 64 receives the clock signal CK supplied from the clock signal input terminal 51 through the buffer circuit 61, and the image data DT from the signal input terminal 52 via the flip-flop circuit 63, the control circuit 65, and the buffer circuit 62. The flip-flop circuit 64 outputs the image data DT to the signal output terminal 54 at a timing according to the clock signal CK.

[0091] Figure 10 shows a clock signal CK (IN) input to a clock signal input terminal 51, image data DT (IN) input to a signal input terminal 52, a clock signal CK (OUT) output from a clock signal output terminal 53, and image data DT (OUT) output from a signal output terminal 54.

[0092] 10, the clock signal CK(OUT) output from the clock signal output terminal 53 is slightly delayed with respect to the clock signal CK(IN) due to the operation of the buffer circuit 61. For example, the delay of the clock signal CK(OUT) is the difference between time t2 and time t1 shown in FIG. 10. This delay is very small and does not cause any substantial problems.

[0093] The flip-flop circuits 63 and 64 output the image data DT at the rising (or falling) timing of the clock signal CK. That is, the image data DT is output from each of the flip-flop circuits 63 and 64 with a delay of one bit relative to the clock signal CK.

[0094] Specifically, as shown in Fig. 10, the image data DT includes a plurality of image data DT(a), DT(b), DT(c), and DT(d). Note that the image data DT(a), DT(b), DT(c), and DT(d) are shown schematically for ease of understanding. The configuration example of the image data DT is shown in Fig. 5.

[0095] Focusing on image data DT(a) of the image data DT, the image data DT(a) is input to the signal input terminal 52 a predetermined time after time t1 when the clock signal CK(IN) is input to the clock signal input terminal 51. In the first-stage flip-flop circuit 63, the image data DT(a) is output at the rising edge of the clock signal CK(IN) (time t3). In other words, the image data DT(a) is delayed by one bit relative to the clock signal CK(IN).

[0096] In the second-stage flip-flop circuit 64, the image data DT(a) is output at the rising edge of the clock signal CK(OUT) (time t6). As a result, compared with the timing relationship between the input clock signal CK(IN) and the image data DT(IN), the image data DT(OUT) is output with a delay of a total of two bits relative to the clock signal CK(OUT).

[0097] As described above, in the driver IC 50, the buffer circuits 61, 62 and flip-flop circuits 63, 64 cause the image data DT(OUT) output from the signal output terminal 54 to be delayed by a predetermined number of bits (e.g., 2 bits) relative to the clock signal CK(OUT) output from the clock signal output terminal 53. However, the timing relationship (delay time) between the clock signal CK(OUT) and the image data DT(OUT) is substantially the same for each of the multiple driver ICs 50. This allows the display device 1 to display images well even in a configuration where horizontal synchronization is not achieved (e.g., where there is no gate drive signal in an active matrix system).

[0098] In test mode, the buffer circuits 61 and 62 and the flip-flop circuits 63 and 64 operate in the same manner as in the normal mode described above, and the test signal DAT is output to the next-stage driver IC 50 with a predetermined bit delay in response to the clock signal CLK. However, as described in the first embodiment, the test mode switching circuit 65a of the control circuit 65 causes the test signal DAT to travel along the path indicated by arrows B1 to B5. Therefore, the timing relationship between the clock signal CLK and the test signal DAT differs from the timing relationship between the clock signal CK and the image data DT shown in FIG. 10. In test mode, multiple driver ICs 50 in the driver IC column 50C are tested collectively, so even if the delay with respect to the clock signal CLK is longer than in normal mode, it does not significantly affect the determination of whether the driver IC column 50C is good or bad. In test mode, the control circuit 65 does not need to perform predetermined processing on the test signal DAT (e.g., rewriting the identification information V in the image data DT).

[0099] Next, a method for processing image data DT by the control circuit 65 will be described with reference to FIGS. 11 and 12 . FIG. 11 is an explanatory diagram illustrating an example of the configuration of image data transmitted and received by the pixel IC. As shown in FIG. 11 , the pixel data DTp included in the image data DT includes multiple pieces of lighting information L for lighting multiple light-emitting elements 3, and identification information V corresponding to the lighting information L. For example, the pixel data DTp is 17 bits long, including 16 bits of lighting information L and 1 bit of identification information V. The lighting information L is, for example, a 16-bit PWM value, which is set for each of the multiple pieces of pixel data DTp according to the gradation of each pixel PX. Note that the PWM value is not limited to 16 bits and can be changed as appropriate according to the gradation of the pixel PX.

[0100] The control circuit 65 acquires lighting information L corresponding to each light-emitting element 3 connected to the driving IC 50 from among the plurality of lighting information L corresponding to the plurality of serially connected pixels PX, based on the identification information V. More specifically, the image data DT includes pixel data DTp (identification information V and lighting information L) corresponding to each light-emitting element 3 of the plurality of serially connected driving ICs 50 (first driving IC 50-1 to nth driving IC 50-n).

[0101] The control circuit 65 of the first driver IC 50-1 acquires, from the plurality of pieces of lighting information L, lighting information L corresponding to each of the light-emitting elements 3R, 3G, and 3B connected to the first driver IC 50-1, based on the identification information V. The control circuit 65 of the second driver IC 50-2 acquires, from the plurality of pieces of lighting information L, lighting information L corresponding to each of the light-emitting elements 3R, 3G, and 3B connected to the second driver IC 50-2, based on the identification information V. The serially connected driver ICs 50 sequentially acquire lighting information L, and the control circuit 65 of the nth driver IC 50-n in the final stage acquires, from the plurality of pieces of lighting information L, lighting information L corresponding to each of the light-emitting elements 3R, 3G, and 3B connected to the nth driver IC 50-n, based on the identification information V.

[0102] Fig. 12 is an explanatory diagram illustrating a method for rewriting identification information. Note that, for ease of understanding, Fig. 12 shows only the identification information V of the image data DT. However, the image data DT includes lighting information L corresponding to each of the identification information V. Fig. 12 also illustrates a configuration in which the image data DT includes n pieces of identification information V(1), V(2), V(3), ..., V(n-1), V(n) corresponding to n pixels PX connected in series.

[0103] As shown in Figure 12, in the image data DT input to the first driving IC 50-1 in the first row, all of the identification information V(1), V(2), V(3), ..., V(n-1), V(n) is set to "1" in advance.

[0104] The control circuit 65 of the first driver IC 50-1 first retrieves pixel data DTp (lighting information L) whose identification information V is "1" from the input image data DT. Then, the control circuit 65 of the first driver IC 50-1 transmits the retrieved pixel data DTp (lighting information L) based on the initial identification information V(1) to the memory circuit 67.

[0105] The control circuit 65 of the first driving IC 50-1 rewrites the identification information V(1) corresponding to the acquired lighting information L from "1" to "0." Then, the control circuit 65 of the first driving IC 50-1 outputs the image data DT having the rewritten identification information V from the signal output terminal 54.

[0106] The control circuit 65 of the second driver IC 50-2 in the next stage retrieves pixel data DTp (lighting information L) corresponding to the identification information V(2) whose identification information V is "1" first among the input image data DT. In other words, the control circuit 65 of the second driver IC 50-2 does not retrieve pixel data DTp corresponding to the identification information V(1) whose identification information V is "0". The control circuit 65 of the second driver IC 50-2 transmits the pixel data DTp (lighting information L) retrieved based on the second identification information V(2) to the memory circuit 67.

[0107] The control circuit 65 of the second driving IC 50-2 rewrites the identification information V(2) corresponding to the acquired lighting information L from "1" to "0." Then, the control circuit 65 of the second driving IC 50-2 outputs the image data DT having the rewritten identification information V from the signal output terminal 54.

[0108] The third driver IC 50-3 to the n-th driver IC 50-n sequentially retrieve pixel data DTp (lighting information L) based on the identification information V and rewrite the identification information V. The n-th driver IC 50-n in the final stage retrieves pixel data DTp (lighting information L) corresponding to the identification information V(n) whose identification information V is "1" first from among the input image data DT.

[0109] The control circuit 65 of the n-th driver IC 50-n rewrites the identification information V(n) corresponding to the acquired lighting information L from "1" to "0", and the capture of the image data DT for one frame (1F) is completed.

[0110] As described above, image data DT including multiple pixel data DTp is serially transmitted between multiple serially connected pixels PX (driver ICs 50), and the drive IC 50 of each pixel PX retrieves the pixel data DTp corresponding to that pixel PX from the image data DT. At this time, the drive IC 50 performs a process of rewriting only the identification information V, and transmits the remaining information, such as the lighting information L, the data start signal Start, and the data end signal Stop, to the next pixel PX (driver IC 50) without changing it.

[0111] The identification information V may be provided for each of the pixel data DTp(R), DTp(G), and DTp(B) corresponding to RGB, or the identification information V may be provided for the pixel data DTp(R) arranged first, and the pixel data DTp(G) and DTp(B) may be acquired based on the identification information V of the pixel data DTp(R). In this case, one bit corresponding to the identification information V of each of the pixel data DTp(G) and DTp(B) may be used for another purpose.

[0112] As described above, even if the display device 1 is configured without horizontal synchronization (for example, without a gate drive signal in an active matrix system), it can import pixel data DTp corresponding to pixel PX from the image data DT based on the identification information V, and can display an image well.

[0113] The display device 1 according to the second embodiment is an inorganic EL display using inorganic light-emitting diodes (micro LEDs) as display elements. However, the present invention is not limited to this, and the display device 1 may be, for example, a liquid crystal display device using liquid crystals as display elements. The display device 1 may also be an organic EL display using organic light-emitting diodes (OLEDs) as display elements. The display device 1 may also be an electrophoretic display (EPD), or may even be a transparent display that displays an image on a transparent display surface.

[0114] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure naturally fall within the technical scope of the present disclosure. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-described embodiments and modifications.

[0115] 1 Display device 3, 3R, 3G, 3B Light-emitting element 12, 106 Clock signal supply wiring 13, 107 Signal supply wiring 14, 15 Wiring 21 Substrate 10 Inspection system 11, 11A, 11B Driver IC 50 Driver IC 50-1 First driver IC 50-2 Second driver IC 50-3 Third driver IC 50C Driver IC row 51 Clock signal input terminal 52 Signal input terminal 53 Clock signal output terminal 54 Signal output terminal 65 Control circuit 65a Test mode switching circuit 100 Wafer 101 Inspection block 102 First test circuit 103 Second test circuit 104, 105 Connection pads CK, CLK Clock signal DAT Test signal DT Image data PX Pixel PX-G Pixel group V Identification information

Claims

1. An inspection system for driver ICs used in a display device having multiple display elements and for driving the multiple display elements, comprising: a plurality of driver ICs formed in a matrix on a wafer for each inspection block; each of the multiple driver ICs having a clock signal input terminal to which a clock signal is input, a signal input terminal to which a test signal for inspecting the driver IC is input, a clock signal output terminal to output the clock signal, a signal output terminal to output the test signal, and a test mode switching circuit; the multiple driver ICs arranged in a column direction include adjacent first and second driver ICs; the clock signal output terminal of the first driver IC is connected to the clock signal input terminal of the second driver IC; and the signal output terminal of the first driver IC is connected to the signal input terminal of the second driver IC.

2. An inspection system for display driver ICs as described in claim 1, comprising: a first test circuit arranged on one side of the plurality of driver ICs arranged in the column direction; and a second test circuit arranged on the other side of the plurality of driver ICs arranged in the column direction, wherein the first driver IC is located on the first test circuit side of the plurality of driver ICs arranged in the column direction, the clock signal input terminal and the signal input terminal of the first driver IC are connected to the first test circuit, and the clock signal output terminal and the signal output terminal of the driver IC located on the second test circuit side of the plurality of driver ICs arranged in the column direction are connected to the second test circuit.

3. The inspection system for display driver ICs according to claim 1, wherein the test mode switching circuits of the plurality of driver ICs are capable of switching to the test mode in response to an input test start signal.

4. The inspection system for display driver ICs according to claim 2, further comprising a plurality of connection pads formed on said wafer and connected to said first test circuit and said second test circuit, respectively.

5. An inspection system for display device driver ICs as described in claim 3, wherein when the number of bits of image data input to drive the plurality of display elements in the plurality of driver ICs is N, the test start signal is data consisting of consecutive "0"s with a number M of bits that is greater than the number N of bits of the image data.

6. The inspection system for a display driver IC according to claim 5, wherein the number of bits M of the test start signal is smaller than the number of cycles of transmission of the image data.

7. The inspection system for display driver ICs according to claim 1, wherein the test mode switching circuits of the plurality of driver ICs cancel the test mode in response to a test cancel signal having a predetermined pattern.

8. The inspection system for display device driver ICs according to claim 1, wherein each of the plurality of driver ICs has a flip-flop circuit, a control circuit, a memory circuit, and a display element driver circuit; in normal mode, a signal input from the signal input terminal is supplied to the memory circuit and the display element driver circuit, drives the display element, and is output from the signal output terminal; and in test mode, a test signal input from the signal input terminal is output from the signal output terminal via the flip-flop circuit, the control circuit, the memory circuit, the display element driver circuit, and the control circuit.

9. The inspection system for display device driver ICs according to claim 1, wherein the plurality of driver ICs have connection terminals connected to at least one display element, and when used as the display device, have the function of displaying an image using the plurality of display elements connected to the connection terminals.

Images