Motor drive device and motor drive system

Abstract

In a motor drive device, a control clock signal is generated on the basis of a position detection signal obtained by detecting the position of a rotor of a three-phase motor with a first angular amount as a minimum unit. On the basis of the control clock signal and the position detection signal, an electrical angle indicating the position of the rotor with a second angular amount smaller than the first angular amount as a minimum unit is estimated and updated as a control electrical angle, and a drive control signal for the coil of each phase is generated on the basis of the control electrical angle. The detection electrical angle based on the position detection signal is compared with the control electrical angle at the generation timing of a unique signal in the position detection signal, and the update cycle of the control electrical angle is adjusted according to the difference between them.

Description

Motor drive device and motor drive system

[0001] The present disclosure relates to a motor drive device and a motor drive system.

[0002] A motor drive device is used to control the drive of a three-phase motor (see, for example, Patent Document 1). The motor drive device appropriately drives the coils of each phase by estimating the electrical angle indicating the rotor position from a rotor position detection signal obtained based on the output signal of a Hall element or the like.

[0003] Japanese Patent Application Laid-Open No. 2020-206438

[0004] However, there may be a case where an error occurs between the estimated electrical angle and the electrical angle detected based on the position detection signal. Appropriate measures are required to deal with the occurrence of the error.

[0005] A motor drive device according to one aspect of the present disclosure is a motor drive device configured to drive a three-phase motor having U-phase, V-phase, and W-phase coils, the motor drive device including: a control electrical angle setting circuit configured to generate a control clock signal having a frequency corresponding to a rotational speed of the rotor based on a position detection signal obtained by detecting a rotor position of the three-phase motor in a first angular amount minimum unit; estimate, as a control electrical angle, an electrical angle indicating the rotor position in a second angular amount minimum unit that is smaller than the first angular amount based on the control clock signal and the position detection signal; and update the control electrical angle based on the control clock signal. and a drive control signal generation circuit configured to generate a drive control signal for supplying a phase voltage corresponding to the control electrical angle to a coil of each phase based on the control electrical angle, wherein the three-phase motor is driven based on the drive control signal, and a singular signal is generated each time the electrical angle indicating the rotor position in the position detection signal changes by the first angle amount, and the control electrical angle setting circuit compares the detected electrical angle indicated by the position detection signal with the control electrical angle at the timing when the singular signal is generated, and when there is an error between the detected electrical angle and the control electrical angle, adjusts the update cycle of the control electrical angle in accordance with the error.

[0006] FIG. 1 is a schematic diagram of a motor structure according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating the relationship between the magnetic poles of a rotor and three position detection units according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating the relationship between output signals of the three position detection units and the rotor position (phase) according to an embodiment of the present disclosure. FIG. 4 is a configuration diagram of a motor drive system according to an embodiment of the present disclosure. FIG. 5 is an external perspective view of a motor drive device according to an embodiment of the present disclosure. FIG. 6 is a waveform diagram of phase voltages of U phase, V phase, and W phase according to an embodiment of the present disclosure. FIG. 7 is a waveform diagram of three inter-phase voltages according to an embodiment of the present disclosure. FIG. 8 is an internal block diagram of a drive control circuit according to an embodiment of the present disclosure. FIG. 9 is a diagram illustrating how a control electrical angle is updated in response to a control clock signal according to an embodiment of the present disclosure. FIG. 10 is an internal block diagram of a control electrical angle setting circuit according to an embodiment of the present disclosure. FIG. 11 is a waveform diagram of three clock signals according to an embodiment of the present disclosure. FIG. 12 is a diagram illustrating how the period of a clock signal is set based on the period of a position detection signal according to an embodiment of the present disclosure. FIG. 13 is a timing chart illustrating a period during which the basic update process is continuously executed according to an embodiment of the present disclosure. FIG. 14 is a timing chart illustrating switching between the basic update process and the acceleration update process for updating the control electrical angle according to an embodiment of the present disclosure. FIG. 15 is a timing chart illustrating switching between the basic update process and the deceleration update process for updating the control electrical angle according to an embodiment of the present disclosure. FIG. 16 is a timing chart according to a reference configuration. FIG. 17 is a timing chart according to an embodiment of the present disclosure. FIG. 18 is a diagram illustrating how acceleration update process and deceleration update process are performed based on the U-phase position detection signal and the W-phase position detection signal according to an embodiment of the present disclosure. FIG. 19 is a flowchart illustrating processing related to a fall edge of the V-phase position detection signal according to a first example of the present disclosure. FIG. 20 is a flowchart illustrating processing related to a rising edge of the V-phase position detection signal according to a first example of the present disclosure. FIG. 21 is a flowchart illustrating processing related to a target edge of the position detection signal according to a first example of the present disclosure.FIG. 22 relates to a second example belonging to an embodiment of the present disclosure and is a diagram for explaining a method for determining the period of a clock signal in the second operation mode.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the referenced drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of brevity, in this specification, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated. For example, the high-side transistor referred to by "MH[" (see FIG. 4) described below may be written as a high-side transistor MH or abbreviated as a transistor MH, but they all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. IC is an abbreviation for Integrated Circuit. Ground refers to a reference conductor having an electric potential of 0 V (zero volts) as a reference, or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground.

[0009] A level refers to the level (height) of the electric potential, and for any given signal or voltage, a high level has a higher electric potential than a low level. For any given signal or voltage, a rising edge refers to a transition from a low level to a high level, and a falling edge refers to a transition from a high level to a low level. A rising edge timing refers to the timing at which a rising edge occurs, and a falling edge timing refers to the timing at which a falling edge occurs.

[0010] For any transistor configured as a FET (field effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET can be considered to be short-circuited to the source. Hereinafter, the on state and off state of any transistor may be simply referred to as on and off.

[0011] For any signal having a high or low signal level, the period during which the signal level is high is called a high level period, and the period during which the signal level is low is called a low level period.

[0012] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0013] If two arbitrary voltages to be compared are voltages v1 and v2, "v1>v2" indicates that voltage v1 is higher than voltage v2, "v1<v2" indicates that voltage v1 is lower than voltage v2, and "v1=v2" indicates that the value of voltage v1 is the same as the value of voltage v2. The same applies to other equations that include physical quantities other than voltage.

[0014] FIG. 1 is a schematic diagram of the structure of a motor 1 according to an embodiment of the present disclosure. The motor 1 is a three-phase brushless motor and includes a stator having three-phase armature windings and a rotor 3 having permanent magnets. The motor 1 may be a surface permanent magnet motor or an interior permanent magnet motor. The three-phase armature windings provided in the motor 1 are composed of a U-phase armature winding coil 2u, a V-phase armature winding coil 2v, and a W-phase armature winding coil 2w. In this embodiment, rotation of the motor 1 specifically refers to rotation of the rotor 3. The motor 1 may have any number of poles. In this embodiment, the direction of rotation of the rotor 3 is assumed to be constant.

[0015] The motor 1 is equipped with a position detector 4 for detecting the position of the rotor 3. The position detector 4 includes a U-phase position detection unit 4u, a V-phase position detection unit 4v, and a W-phase position detection unit 4w. Each position detection unit (4u, 4v, 4w) includes a Hall element and a signal processing circuit that amplifies and digitizes the output signal of the Hall element. Each position detection unit (4u, 4v, 4w) may be a Hall IC formed in the form of an integrated circuit. Here, the position detector 4 is considered to be provided on the motor 1, but it is also possible to consider the position detector 4 as being provided separately from the motor 1. Note that each position detection unit (4u, 4v, 4w) may have a Hall element but not a signal processing circuit that amplifies and digitizes the output signal of the Hall element. In this case, the signal processing circuit may be provided in a device that receives the output signal of the Hall element (a drive IC 100 described below; see FIG. 4). In the following, unless otherwise specified, it is assumed that each position detection unit (4u, 4v, 4w) has a signal processing circuit.

[0016] The position of the rotor 3 detected by the position detector 4 is the magnetic pole position of the rotor 3 and represents the phase of the rotor 3 when the rotor 3 rotates. In this embodiment, unless otherwise specified, the phase of the rotor 3 refers to the phase in electrical angle, and angles such as 60° and 120° represent angles in electrical angle. As shown in Fig. 2, the position detection units 4u, 4v, and 4w are arranged at positions that are shifted from each other by 120° electrical angle.

[0017] 3 shows the waveforms of the position detection signals HALL_u, HALL_v, and HALL_w. The position detection unit 4u outputs a signal corresponding to the direction of the magnetic field applied to the Hall element (Hall element in unit 4u) from the permanent magnet of the rotor 3 as the position detection signal HALL_u. The position detection unit 4v outputs a signal corresponding to the direction of the magnetic field applied to the Hall element (Hall element in unit 4v) from the permanent magnet of the rotor 3 as the position detection signal HALL_v. The position detection unit 4w outputs a signal corresponding to the direction of the magnetic field applied to the Hall element (Hall element in unit 4w) from the permanent magnet of the rotor 3 as the position detection signal HALL_w. Each position detection signal is a binary signal having a high or low signal level. In other words, the phase of the rotor 3 is detected in 180° increments by each position detection unit. As described above, the position detection units 4u, 4v, and 4w are arranged at positions that are shifted from one another by an electrical angle of 120°, and therefore the phase of the rotor 3 is detected by the units 4u, 4v, and 4w in increments of 60° (i.e., detection is performed in increments of 60°).

[0018] Here, when the rotor 3 is rotating in a predetermined direction, the phase of the rotor 3 when a rising edge occurs in the position detection signal HALL_u is 0°, and the phase of the rotor 3 when a fall edge occurs in the position detection signal HALL_u is 180°. The phase of the rotor 3 when a rising edge occurs in the position detection signal HALL_v is 240°, the phase of the rotor 3 when a fall edge occurs in the position detection signal HALL_v is 60°, the phase of the rotor 3 when a rising edge occurs in the position detection signal HALL_w is 120°, and the phase of the rotor 3 when a fall edge occurs in the position detection signal HALL_w is 300°. 360° is equivalent to 0° in terms of the phase of the rotor 3.

[0019] Fig. 4 shows the configuration of a motor drive system having a motor 1. The motor drive system is configured with the motor 1 and a drive IC 100, which is an example of a motor drive device. Note that the rotor 3 is not shown in Fig. 4.

[0020] 5 is an external perspective view of a drive IC 100 according to an embodiment of the present disclosure. The drive IC 100 is an electronic component (semiconductor device) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed to the outside of the drive IC 100 from the housing. The drive IC 100 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the drive IC 100 and the type of housing for the drive IC 100 shown in FIG. 5 are merely examples, and can be designed as desired.

[0021] The external terminals provided on the drive IC 100 include terminals OUTu, OUTv, and OUTw. In the motor 1, the coils 2u, 2v, and 2w are star-connected. That is, the first end of the coil 2u, the first end of the coil 2v, and the first end of the coil 2w are connected to the external terminals OUTu, OUTv, and OUTw, respectively, and the second ends of the coils 2u, 2v, and 2w are commonly connected at a neutral point NP. However, a delta connection may also be adopted for the coils 2u, 2v, and 2w. The external terminals OUTu, OUTv, and OUTw may also be referred to as output terminals.

[0022] The drive IC 100 includes a position detection signal acquisition circuit 10, a drive control circuit 20, a pre-driver 30, and an inverter circuit 40. The inverter circuit 40 includes a half-bridge circuit 40u for a U phase, a half-bridge circuit 40v for a V phase, and a half-bridge circuit 40w for a W phase.

[0023] Each of the half-bridge circuits 40u, 40v, and 40w includes a high-side transistor MH and a low-side transistor ML connected in series between a wiring to which a power supply voltage VPWR is applied and ground. The transistors MH and ML are configured as N-channel MOSFETs. The power supply voltage VPWR has a predetermined positive DC voltage value (e.g., 12 V, 24 V, or 48 V).

[0024] More specifically, in each of the half-bridge circuits 40u, 40v, and 40w, the drain of the transistor MH is connected to a first power supply terminal to which the power supply voltage VPWR is applied, and receives the power supply voltage VPWR. The source of the transistor MH and the drain of the transistor ML are commonly connected at a node ND, and the source of the transistor ML is connected to ground, which functions as a second power supply terminal. The source of each transistor ML may be connected to ground via a current detection resistor (the current detection resistors are not shown in FIG. 1 ). The node ND in each of the half-bridge circuits 40u, 40v, and 40w is connected to the output terminals OUTu, OUTv, and OUTw, respectively. Therefore, the node ND in each of the half-bridge circuits 40u, 40v, and 40w is connected to the first ends of the coils 2u, 2v, and 2w via the output terminals OUTu, OUTv, and OUTw, respectively. The voltages applied to the output terminals OUTu, OUTv, and OUTw, which correspond to the voltages at the first ends of the coils 2u, 2v, and 2w, are denoted by Vu, Vv, and Vw, respectively. The voltages Vu, Vv, and Vw are referred to as phase voltages or terminal voltages.

[0025] A signal output from the position detector 4 is input to the position detection signal acquisition circuit 10 through three external terminals provided on the drive IC 100, and position detection signals HALL_u, HALL_v, and HALL_w are acquired by the position detection signal acquisition circuit 10. In the case where the position detector 4 itself outputs position detection signals HALL_u, HALL_v, and HALL_w, the position detection signals HALL_u, HALL_v, and HALL_w from the position detector 4 are input to the position detection signal acquisition circuit 10. As described above, each position detection unit (4u, 4v, 4w) may have a Hall element but may not have a signal processing circuit that amplifies and digitizes the output signal of the Hall element. In this case, the signal processing circuit is provided in the position detection signal acquisition circuit 10, and the position detection signals HALL_u, HALL_v, and HALL_w are generated in the position detection signal acquisition circuit 10 based on the output signals of the position detection units (4u, 4v, 4w). The position detection signals HALL_u, HALL_v, and HALL_w are supplied from the position detection signal acquisition circuit 10 to the drive control circuit 20.

[0026] The drive control circuit 20 generates and outputs a drive control signal DRVu for the half-bridge circuit 40u, a drive control signal DRVv for the half-bridge circuit 40v, and a drive control signal DRVw for the half-bridge circuit 40w based on the position detection signals HALL_u, HALL_v, and HALL_w. For example, a torque command signal specifying the torque to be generated in the motor 1 may be provided to the drive control circuit 20. In this case, the drive control circuit 20 generates the drive control signals DRVu, DRVv, and DRVw so that the motor 1 generates the torque specified by the torque command signal. Alternatively, for example, a rotational speed command signal specifying the rotational speed of the motor 1 may be provided to the drive control circuit 20. In this case, the drive control circuit 20 generates the drive control signals DRVu, DRVv, and DRVw so that the motor 1 rotates at the rotational speed specified by the rotational speed command signal. Each of the drive control signals DRVu, DRVv, and DRVw is a binary signal and takes a value of "1" or "0."

[0027] The pre-driver 30 controls the state of each half-bridge circuit by controlling the gate potential of each transistor in the half-bridge circuits 40u, 40v, and 40w according to the drive control signals DRVu, DRVv, and DRVw. In any one of the half-bridge circuits 40u, 40v, and 40w, a state in which the transistor MH is on and the transistor ML is off is referred to as an output high state, and a state in which the transistor MH is off and the transistor ML is on is referred to as an output low state. Assuming that the on-resistances of the transistors MH and ML are zero, for example, in the half-bridge circuit 40u, in the output high state, the power supply voltage VPWR is applied to the output terminal OUTu via the high-side transistor MH, and in the output low state, the ground potential is applied to the output terminal OUTu via the low-side transistor ML (ignoring transient states). The same applies to the half-bridge circuits 40v and 40w.

[0028] The pre-driver 30 performs a U-phase driving operation to control the gate potentials of the transistors MH and ML of the half-bridge circuit 40u so that the half-bridge circuit 40u has a high output state during a period when the drive control signal DRVu has a value of "1" and a low output state during a period when the drive control signal DRVu has a value of "0". Similarly, the pre-driver 30 performs a V-phase driving operation to control the gate potentials of the transistors MH and ML of the half-bridge circuit 40v so that the half-bridge circuit 40v has a high output state during a period when the drive control signal DRVv has a value of "1" and a low output state during a period when the drive control signal DRVv has a value of "0". Similarly, the pre-driver 30 performs a W-phase driving operation that controls the gate potentials of the transistors MH and ML of the half-bridge circuit 40w so that the half-bridge circuit 40w is in an output high state during the period when the drive control signal DRVw has a value of "1" and so that the half-bridge circuit 40w is in an output low state during the period when the drive control signal DRVw has a value of "0".

[0029] The drive control circuit 20 outputs PWM signals as drive control signals DRVu, DRVv, and DRVw. PWM stands for pulse width modulation. PWM signals are binary signals with a predetermined PWM frequency, alternating between values ​​of "1" and "0." Each drive control signal (DRVu, DRVv, DRVw) that constitutes a PWM signal is a binary signal with a variable pulse width. The pulse width of a PWM signal refers to the length of time during which the PWM signal has a value of "1" in each cycle of the PWM signal. For a given PWM signal, the ratio of the time during which the PWM signal has a value of "1" to the sum of the time during which the PWM signal has a value of "1" and the time during which the PWM signal has a value of "0" is called the output duty. The output duty of the drive control signal DRVu is particularly referred to as the U-phase output duty, the output duty of the drive control signal DRVv is particularly referred to as the V-phase output duty, and the output duty of the drive control signal DRVw is particularly referred to as the W-phase output duty.

[0030] The half-bridge circuit 40u pulse-width modulates the power supply voltage VPWR in accordance with the drive control signal DRVu, and the voltage obtained by this pulse-width modulation is applied to a first end of the coil 2u as a phase voltage Vu. The phase voltage Vu is a square-wave switching voltage that has the potential of the power supply voltage VPWR during the period when the drive control signal DRVu has a value of "1" and has ground potential during the period when the drive control signal DRVu has a value of "0" (transient states are ignored). The half-bridge circuit 40v pulse-width modulates the power supply voltage VPWR in accordance with the drive control signal DRVv, and the voltage obtained by this pulse-width modulation is applied to a first end of the coil 2v as a phase voltage Vv. The phase voltage Vv is a square-wave switching voltage that has the potential of the power supply voltage VPWR during the period when the drive control signal DRVv has a value of "1" and has ground potential during the period when the drive control signal DRVv has a value of "0" (transient states are ignored). The half-bridge circuit 40w pulse-width modulates the power supply voltage VPWR in accordance with the drive control signal DRVw, and the voltage obtained by this pulse-width modulation is applied to the first end of the coil 2w as the phase voltage Vw. The phase voltage Vw is a rectangular-wave switching voltage that has the potential of the power supply voltage VPWR while the drive control signal DRVw has a value of "1" and has the ground potential while the drive control signal DRVw has a value of "0" (however, a transient state is ignored).

[0031] The pre-driver 30 and the inverter circuit 40 form an output stage circuit that supplies phase voltages Vu, Vv, and Vw based on the drive control signals DRVu, DRVv, and DRVw to the coils 2u, 2v, and 2w. In this embodiment, it is assumed that the inverter circuit 40 is built into the drive IC 100, but the inverter circuit 40 may be a circuit provided outside the drive IC 100. In addition to the inverter circuit 40, the pre-driver 30 may also be provided outside the drive IC 100. When the output stage circuit is provided outside the drive IC 100, it can be considered that the drive IC 100 and the output stage circuit form a motor drive device.

[0032] In this embodiment, three-phase modulation is performed by the drive IC 100 as an example. However, two-phase modulation may also be performed by the drive IC 100. FIG. 6 shows the waveforms of the phase voltages Vu, Vv, and Vw when three-phase modulation is performed by the drive IC 100. The phase voltage Vu is actually pulse-width modulated at a period that is sufficiently shorter than the period of the phase voltage Vu. However, for convenience of illustration, FIG. 6 shows a filtered voltage of the phase voltage Vu (a signal component of the actual phase voltage Vu from which signal components above the PWM frequency have been removed). The same applies to the phase voltages Vv and Vw, and also to the waveforms shown in FIG. 7 (described later). 6 are equivalent to the waveforms of the output duties of the U-phase, V-phase, and W-phase, respectively, and are also equivalent to the filtered signals of the drive control signals DRVu, DRVv, and DRVw (signal components at frequencies higher than the PWM frequency have been removed from the signal components of the actual drive control signals DRVu, DRVv, and DRVw). The phase voltage Vv lags behind the phase voltage Vu by 240°, and the phase voltage Vw lags behind the phase voltage Vu by 120°.

[0033] 7 shows the waveforms of three inter-phase voltages. The three inter-phase voltages consist of an inter-phase voltage Vu_w representing the phase voltage Vu viewed from the phase voltage Vw, an inter-phase voltage Vw_v representing the phase voltage Vw viewed from the phase voltage Vv, and an inter-phase voltage Vv_u representing the phase voltage Vv viewed from the phase voltage Vu. The inter-phase voltages Vu_w, Vw_v, and Vv_u each have a sinusoidal waveform, and the phases of the inter-phase voltages Vu_w, Vw_v, and Vv_u are shifted from one another by 120 electrical degrees.

[0034] 8 shows an internal block diagram of the drive control circuit 20. The drive control circuit 20 includes a control electrical angle setting circuit 21 (hereinafter, may be referred to as the setting circuit 21) and a drive control signal generation circuit 22 having a waveform data table 22a. The setting circuit 21 includes a control clock generation circuit 23 and an electrical angle estimation circuit 24. In the following description, the position detection signal HALL refers to the position detection signals HALL_u, HALL_v, and HALL_w.

[0035] A position detection signal HALL is input to a setting circuit 21. A control clock generation circuit 23 generates a control clock signal CLKc having a frequency corresponding to the rotational speed of the rotor 3 based on the position detection signal HALL and supplies the control clock signal CLKc to an electrical angle estimation circuit 24. Any clock signal including the control clock signal CLKc is a rectangular wave signal having alternating high and low levels. The position detection signal HALL is obtained by detecting the position of the rotor 3 in units of an angle amount ANG1. In this embodiment, the angle amount ANG1 is 60°. That is, the detection resolution of the rotor 3 position using the position detection signal HALL is 60° (see FIG. 3).

[0036] The electrical angle estimation circuit 24 estimates the electrical angle, which indicates the position of the rotor 3 in units of angle amount ANG2, as the control electrical angle θc based on the control clock signal CLKc and the position detection signal HALL. The angle amount ANG2 can be any value smaller than the angle amount ANG1, such as 2°, 1°, or 0.5°. Hereinafter, in this embodiment, the angle amount ANG2 is assumed to be 1°. In estimating the control electrical angle θc, the electrical angle estimation circuit 24 updates the control electrical angle θc. The update of the control electrical angle θc is performed in synchronization with the control clock signal CLKc. In updating the control electrical angle θc, the electrical angle estimation circuit 24 cyclically updates the control electrical angle θc within a range of 0° or more and less than 360° based on the control clock signal CLKc. That is, as shown in FIG. 9 , in updating the control electrical angle θc, the electrical angle estimation circuit 24 adds 1° to the control electrical angle θc each time a specific edge occurs in the control clock signal CLKc. When the specific edge occurs in the control clock signal CLKc while the control electrical angle θc is 359°, the control electrical angle θc is set to 0°. Here, the specific edge is assumed to be a rising edge. However, the specific edge may also be a falling edge. The control electrical angle θc is a control electrical angle indicating the phase of the rotor 3 recognized by the drive control circuit 20. Ideally, it coincides with the actual electrical angle of the rotor 3, but there may be a deviation. The control electrical angle θc is supplied to the drive control signal generation circuit 22. The adjustment signal SS supplied from the electrical angle estimation circuit 24 to the control clock generation circuit 23 will be described later.

[0037] The drive control signal generation circuit 22 refers to waveform table data 22a based on the control electrical angle θc and generates a drive control signal DRVu for supplying a phase voltage Vu corresponding to the control electrical angle θc to the coil 2u, a drive control signal DRVv for supplying a phase voltage Vv corresponding to the control electrical angle θc to the coil 2v, and a drive control signal DRVw for supplying a phase voltage Vw corresponding to the control electrical angle θc to the coil 2w. The drive control signals DRVu, DRVv, and DRVw generated here are supplied to the pre-driver 30, and the pre-driver 30 and the inverter circuit 40 are driven in accordance with the drive control signals DRVu, DRVv, and DRVw, whereby the phase voltages Vu, Vv, and Vw corresponding to the control electrical angle θc are supplied to the coils 2u, 2v, and 2w.

[0038] The waveform table data 22a stores command values ​​for the output duties of the U-phase, V-phase, and W-phase for each possible value of the control electrical angle θc. That is, the command values ​​for the output duties of the U-phase, V-phase, and W-phase when the control electrical angle θc is X° (hereinafter, for convenience, referred to as command value X°) are stored. * The waveform table data 22a stores the command value X. Here, X represents an arbitrary integer value between 0 and 359. When the control electrical angle θc is X°, the drive control signal generation circuit 22 calculates the command value X * is read from the waveform table data 22a, and the command value X * As a result, phase voltages Vu, Vv, Vw as shown in FIG. 6 are supplied to the coils 2u, 2v, 2w, respectively, in accordance with the position (phase) of the rotor 3.

[0039] 10 shows an internal block diagram of the control clock generation circuit 23. The control clock generation circuit 23 includes three clock generation circuits 231 to 233 and a selector 234. The clock generation circuit 231 generates and outputs a clock signal CLK1. The clock generation circuit 232 generates and outputs a clock signal CLK2. The clock generation circuit 233 generates and outputs a clock signal CLK3. The selector 234 selects one of the clock signals CLK1, CLK2, and CLK3 as the control clock signal CLKc in response to the adjustment signal SS from the electrical angle estimation circuit 24 and outputs it.

[0040] FIG. 11 shows the waveforms of the clock signals CLK1 to CLK3. Although FIG. 11 shows clock signals CLK1 to CLK3 each having a 50% duty cycle, the duty cycles of the clock signals CLK1 to CLK3 are arbitrary. Clock signal CLK1 is a basic clock signal, and the control clock generation circuit 23 generally sets clock signal CLK1 to control clock signal CLKc. Clock signal CLK2 has a higher frequency than clock signal CLK1. Therefore, during the period when clock signal CLK2 is set to control clock signal CLKc, the update cycle of the control electrical angle θc is shorter than during the period when clock signal CLK1 is set to control clock signal CLKc (the control electrical angle θc is updated at a relatively faster rate). For this reason, clock signal CLK2 can also be referred to as an acceleration clock signal or an advance clock signal. Clock signal CLK3 has a lower frequency than clock signal CLK1. Therefore, during the period when the clock signal CLK3 is set to the control clock signal CLKc, the update cycle of the control electrical angle θc is longer (the control electrical angle θc is updated at a relatively slower speed) than during the period when the clock signal CLK1 is set to the control clock signal CLKc. For this reason, the clock signal CLK3 can also be referred to as a deceleration clock signal or a retard clock signal.

[0041] The cycle length Tp1 represents the length of one cycle of the clock signal CLK1. The cycle length Tp2 represents the length of one cycle of the clock signal CLK2. The cycle length Tp3 represents the length of one cycle of the clock signal CLK3. Here, the interval between two adjacent rising edges of the clock signal CLK1 is regarded as one cycle, but the interval between two adjacent falling edges of the clock signal CLK1 may also be regarded as one cycle. The same applies to the clock signals CLK2 and CLK3. "Tp2<Tp1<Tp3" holds. Also, "Tp2=Tp1×k A " and "Tp3 = Tp1 × k B " where k A and k B is a predetermined coefficient, and "0<k A < 1 < k B ". The coefficient k A The coefficient k has a value corresponding to the frequency difference between the clock signals CLK1 and CLK2. B has a value according to the frequency difference between the clock signals CLK1 and CLK3. For example, "(k A , k B ) = (0.625, 1.6)". The coefficient k A is the coefficient k B The coefficient k is set to match the inverse of A and k B However, it is preferable to set each value of "0<k A < 1 < k B " as long as coefficient k A and k B The drive IC 100 is provided with an oscillator (not shown) that generates a master clock signal having a frequency sufficiently higher than the frequencies of the clock signals CLK1 to CLK3, and the control clock generation circuit 23 can generate the clock signals CLK1 to CLK3 by dividing the master clock signal by three division ratios. A and k B is determined by the relationship between the three division ratios.

[0042] For the sake of concreteness, the period from the time when a rising edge occurs in the position detection signal HALL_u to just before the time when the next rising edge occurs in the position detection signal HALL_u will be referred to as one frame. Therefore, the length of one frame corresponds to the length of one cycle of the position detection signal HALL_u. With reference to FIG. 12 , a certain frame during the period in which the rotor 3 continuously rotates in a fixed direction is denoted as frame FR[i], and frame FR[i] is considered to be the i-th frame (where i represents any natural number). The frame following frame FR[i] is frame FR[i+1], and the frame following frame FR[i+1] is frame FR[i+2]. Generally speaking, the (i+j)th frame is frame FR[i+j] (where j represents any integer).

[0043] The control clock generation circuit 23 determines the cycle length Tp1 by dividing the length of two cycles of the position detection signal HALL_u by a predetermined division number. In this case, the cycle length Tp1 is determined from a moving average of the length of two cycles of the position detection signal HALL_u. In this embodiment, the control electrical angle θc is updated in increments of 1° as described above, while the length of two cycles of the position detection signal HALL_u corresponds to an electrical angle of 720°. Therefore, the division number is 720. Here, the cycle length Tp1 is determined based on a length of 720° of electrical angle, but this is merely a numerical example. The cycle length Tp1 may also be determined based on other lengths, such as a length of 360° of electrical angle or a length of 1080° of electrical angle.

[0044] The control clock generation circuit 23 determines the cycle length Tp1 for a given frame of interest based on the lengths of the two frames immediately preceding the frame of interest. Therefore, for example, the control clock generation circuit 23 determines the cycle length Tp1 for frame FR[i+2] so that the cycle length Tp1 for frame FR[i+2] satisfies "Tp1 = T[i, i+1] / 720." T[i, i+1] represents the sum of the lengths of frames FR[i] and FR[i+1]. Similarly, the control clock generation circuit 23 determines the cycle length Tp1 for frame FR[i+3] so that the cycle length Tp1 for frame FR[i+3] satisfies "Tp1 = T[i+1, i+2] / 720." T[i+1, i+2] represents the sum of the lengths of frames FR[i+1] and FR[i+2].

[0045] <Basic Update Process> The setting circuit 21 (control electrical angle setting circuit 21) in FIG. 8 basically performs the following basic update process as the process for updating the control electrical angle θc (see FIG. 9). FIG. 13 shows a timing chart of a period during which the basic update process is continuously executed. In the basic update process, the clock signal CLK1 is set as the control clock signal CLKc. In other words, the basic update process is a process for updating the control electrical angle θc that is performed with the clock signal CLK1 set as the control clock signal CLKc.

[0046] The setting circuit 21 performs a zero-set process to generate a rising edge in the clock signal CLK1 at the timing of the rising edge of the position detection signal HALL_u in any frame during the rotation period of the rotor 3 and to set the control electrical angle θc to 0°. After the zero-set process, the setting circuit 21 performs a basic update process as a process for updating the control electrical angle θc, and continues to perform the basic update process unless an angle estimation error, which will be described later, is detected.

[0047] <Angle Estimation Error> The angle estimation error will now be described. The electrical angle represented by the position detection signal HALL (the electrical angle indicating the position of the rotor 3) is referred to as the detected electrical angle and is referred to as "θd" as necessary. As shown in FIG. 3 , the detected electrical angle θd is 0° at the rising edge timing of the position detection signal HALL_u and 180° at the falling edge timing of the position detection signal HALL_u. The detected electrical angle θd is 240° at the rising edge timing of the position detection signal HALL_v and 60° at the falling edge timing of the position detection signal HALL_v. The detected electrical angle θd is 120° at the rising edge timing of the position detection signal HALL_w and 300° at the falling edge timing of the position detection signal HALL_w.

[0048] Ideally, at the rising edge timing of each of the position detection signals HALL_u, HALL_v, and HALL_w and at the falling edge timing of each of the position detection signals HALL_u, HALL_v, and HALL_w, the difference between the detected electrical angle θd and the control electrical angle θc is within the resolution of the control electrical angle θc. However, due to error factors such as fluctuations in the rotational speed of the rotor 3 or installation errors of the position detection units 4u, 4v, and 4w, the difference between the detected electrical angle θd and the control electrical angle θc may exceed the resolution of the control electrical angle θc. The resolution of the control electrical angle θc corresponds to the angle amount ANG2 (1° in this embodiment). The electrical angle estimation circuit 24 can determine that an angle estimation error has occurred when the difference between the detected electrical angle θd and the control electrical angle θc exceeds the resolution of the control electrical angle θc.

[0049] The electrical angle estimation circuit 24 determines whether or not there is an angle estimation error at the timing of the rising edge of each of the position detection signals HALL_u, HALL_v, and HALL_w and at the timing of the falling edge of each of the position detection signals HALL_u, HALL_v, and HALL_w. If the electrical angle estimation circuit 24 determines that there is no angle estimation error, it does not output the adjustment signal SS (see FIG. 8 ) to the control clock generation circuit 23. If the electrical angle estimation circuit 24 determines that there is an angle estimation error, it outputs an active acceleration command signal SSacc or an active deceleration command signal SSdec as the adjustment signal SS to the control clock generation circuit 23 for the required time, thereby setting the clock signal CLK2 or the clock signal CLK3 to the control clock signal CLKc for the required time. The acceleration command signal SSacc and the deceleration command signal SSdec are binary signals having a high level or a low level. Here, it is assumed that a high-level acceleration command signal SSacc is an active acceleration command signal SSacc, and a high-level deceleration command signal SSdec is an active deceleration command signal SSdec. The acceleration command signal SSacc and the deceleration command signal SSdec never have a high level at the same time.

[0050] During the period when the adjustment signal SS is not output, the acceleration command signal SSacc and the deceleration command signal SSdec are maintained at a low level. During the period when the adjustment signal SS is not output (i.e., during the period when the acceleration command signal SSacc and the deceleration command signal SSdec are both at a low level), the control clock generation circuit 23 sets the clock signal CLK1 to the control clock signal CLKc. Therefore, during the period when the adjustment signal SS is not output, the above-mentioned basic update process (see FIG. 13) is executed as the process for updating the control electrical angle θc.

[0051] <Acceleration Update Process> A high level of the acceleration command signal SSacc is a signal instructing the clock signal CLK2 to be set as the control clock signal CLKc. Therefore, during the high level period of the acceleration command signal SSacc, the control clock generation circuit 23 sets the clock signal CLK2 as the control clock signal CLKc. During the high level period of the acceleration command signal SSacc, the acceleration update process is executed as a process for updating the control electrical angle θc. In the acceleration update process, the clock signal CLK2 is set as the control clock signal CLKc. In other words, the acceleration update process is a process for updating the control electrical angle θc that is performed with the clock signal CLK2 set as the control clock signal CLKc.

[0052] An example of the acceleration update process will be described with reference to FIG. 14 . In the example of FIG. 14 , at time t1, which is the fall edge timing of the position detection signal HALL_v, the control electrical angle θc is 57°, which is 3° behind the detected electrical angle θd at the same time. For the sake of concreteness, assuming "Tp2 = Tp1 × 0.625" (see FIG. 11 ), setting the clock signal CLK2 as the control clock signal CLKc accelerates the advance of the control clock signal CLKc by 0.375° per cycle of the control clock signal CLKc compared to when the clock signal CLK1 is set as the control clock signal CLKc. Therefore, the electrical angle estimation circuit 24 begins outputting a high-level acceleration command signal SSacc at time t1 to eliminate the 3° delay. As a result, the control clock signal CLKc switches from the clock signal CLK1 to the clock signal CLK2 at time t1. Since "3 / 0.375=8", after time t1, when eight rising edges occur in the control clock signal CLKc (time t2), the electrical angle estimation circuit 24 generates a falling edge in the acceleration command signal SSacc. Therefore, in the example of Figure 14, the acceleration update process is performed from time t1 to time t2, and the basic update process is performed before time t1 and after time t2.

[0053] As a simpler method, the following error reduction method α1 may be adopted. In the error reduction method α1, when the setting circuit 21 detects that the control electrical angle θc lags behind the detected electrical angle θd at time t1, the absolute difference between the control electrical angle θc and the detected electrical angle θd at time t1 is determined as the acceleration set value m (m=3 in the example of FIG. 14 ). At the same time, the output of a high-level acceleration command signal SSacc is started from time t1, thereby switching the control clock signal CLKc from the clock signal CLK1 to the clock signal CLK2 at time t1. After time t1, although different from the situation shown in FIG. 14 , when rising edges occur in the control clock signal CLKc the number of times equal to the acceleration set value m (i.e., m times), the electrical angle estimation circuit 24 generates falling edges in the acceleration command signal SSacc, thereby switching the control clock signal CLKc back from the clock signal CLK2 to the clock signal CLK1. In either method, the clock signal CLK2 is set to the control clock signal CLKc for a time period corresponding to the delay of the control electrical angle θc from the detected electrical angle θd, thereby reducing the error between the detected electrical angle θd and the control electrical angle θc. The accelerated update process can be modified in various ways as long as it reduces the error.

[0054] <Deceleration Update Process> The high-level deceleration command signal SSdec is a signal that commands the setting of the clock signal CLK3 as the control clock signal CLKc. Therefore, during the high-level period of the deceleration command signal SSdec, the control clock generation circuit 23 sets the clock signal CLK3 as the control clock signal CLKc. During the high-level period of the deceleration command signal SSdec, the deceleration update process is executed as a process for updating the control electrical angle θc. In the deceleration update process, the clock signal CLK3 is set as the control clock signal CLKc. In other words, the deceleration update process is a process for updating the control electrical angle θc that is performed in a state in which the clock signal CLK3 is set to the control clock signal CLKc.

[0055] An example of the deceleration update process will be described with reference to FIG. 15 . In the example of FIG. 15 , at time t3, which is the rising edge timing of the position detection signal HALL_v, the control electrical angle θc is 243°, which is 3° ahead of the detected electrical angle θd at the same time. For the sake of concreteness, assuming "Tp3 = Tp1 × 1.6" (see FIG. 11 ), setting the clock signal CLK3 as the control clock signal CLKc slows the advance of the control clock signal CLKc by 0.6° per cycle of the control clock signal CLKc compared to when the clock signal CLK1 is set as the control clock signal CLKc. Therefore, the electrical angle estimation circuit 24 begins outputting a high-level deceleration command signal SSdec at time t3 to eliminate the 3° advance. As a result, the control clock signal CLKc switches from the clock signal CLK1 to the clock signal CLK3 at time t3. Since "3 / 0.6=5", after time t3, when five rising edges occur in the control clock signal CLKc (time t4), the electrical angle estimation circuit 24 generates a falling edge in the deceleration command signal SSdec. Therefore, in the example of FIG. 14, the deceleration update process is performed from time t3 to time t4, and the basic update process is performed before time t3 and after time t4.

[0056] As a simpler method, the following error reduction method α2 may be adopted. In the error reduction method α2, when the setting circuit 21 detects that the control electrical angle θc is ahead of the detected electrical angle θd at time t3, the absolute difference between the control electrical angle θc and the detected electrical angle θd at time t3 is determined as the deceleration set value n (n=3 in the example of FIG. 15 ). At the same time, the control circuit 21 starts outputting a high-level deceleration command signal SSdec from time t3, thereby switching the control clock signal CLKc from the clock signal CLK1 to the clock signal CLK3. After time t3, different from the situation shown in FIG. 15 , when rising edges occur in the control clock signal CLKc the number of times equal to the deceleration set value n (i.e., n times), the electrical angle estimation circuit 24 generates falling edges in the deceleration command signal SSdec, thereby switching the control clock signal CLKc back from the clock signal CLK3 to the clock signal CLK1. In either method, the clock signal CLK3 is set to the control clock signal CLKc for a period of time corresponding to the advance of the control electrical angle θc relative to the detected electrical angle θd, thereby reducing the error between the detected electrical angle θd and the control electrical angle θc. The deceleration update process can be modified in various ways as long as it reduces the error.

[0057] <Comparison with Reference Configuration> FIG. 16 shows a timing chart for the reference configuration. In FIG. 16, it is assumed that the rising edge timing and falling edge timing of the position detection signal HALL_v are shifted in opposite directions from the ideal timing due to factors such as deviation of the installation position of the position detection unit 4v from the ideal position (the same applies to FIG. 17 described later). The drive IC for the reference configuration is referred to as the reference drive IC. Unlike the drive IC 100 according to the present embodiment, the reference drive IC always maintains a constant update period for the control electrical angle θc, and at the rising edge timing of the position detection signal HALL_u, the control electrical angle θc is forcibly set to 0° regardless of the value of the control electrical angle θc immediately before that timing. In FIG. 16, waveforms 911 to 913 represent the waveforms of the position detection signals HALL_u, HALL_v, and HALL_w, respectively, in the reference drive IC. 16, waveforms 914 to 916 respectively represent the waveforms of the control electrical angle θc, the output duty of the U-phase, and the phase current of the U-phase (the current flowing through the coil 2u) in the reference drive IC. In FIG. 16, a diagram 917 indicates that the update cycle of the control electrical angle θc in the reference drive IC is constant.

[0058] At times corresponding to dashed circles 921 to 923 in Figure 16, the rising edge of the position detection signal HALL_u triggers the forcible setting of the control electrical angle θc to 0°, regardless of the value of the immediately preceding control electrical angle θc. As a result, at times corresponding to dashed circles 921 to 923, the U-phase output duty changes discontinuously, causing the U-phase phase current to change discontinuously. In the waveform of the U-phase phase current shown in Figure 16, discontinuous changes occur in the U-phase phase current at the portions indicated by dashed circles 931 to 933. Discontinuities in the phase current can increase vibration and noise in the motor 1.

[0059] FIG. 17 shows a timing chart of the drive IC 100 according to this embodiment. In FIG. 17, waveforms 611 to 613 represent the waveforms of the position detection signals HALL_u, HALL_v, and HALL_w, respectively, in the drive IC 100. In FIG. 17, waveforms 614 to 616 represent the waveforms of the control electrical angle θc, the output duty of the U-phase, and the phase current of the U-phase (the current flowing through the coil 2u), respectively, in the drive IC 100. In FIG. 17, a composite figure 617 consisting of a white area, a hatched area, and a dotted area represents changes in the update period of the control electrical angle θc of the drive IC 100. Within the composite figure 617, the basic update process is performed in the white area, the acceleration update process is performed in the hatched area, and the deceleration update process is performed in the dotted area. By performing the acceleration update process or the deceleration update process as needed, discontinuities do not occur in the output duty and phase current of the U-phase (the same applies to the V-phase and W-phase), thereby reducing vibration and noise of the motor 1.

[0060] 17 , it is assumed that an angle estimation error is detected only at the rising edge and falling edge timing of the position detection signal HALL_v, and therefore the update processing of the control electrical angle θc is temporarily set to the acceleration update processing or the deceleration update processing in response to the rising edge or falling edge of the position detection signal HALL_v. However, an angle estimation error may be detected at the rising edge or falling edge timing of the position detection signal HALL_u, in which case the update processing of the control electrical angle θc is temporarily set to the acceleration update processing or the deceleration update processing in response to the rising edge or falling edge of the position detection signal HALL_u. Similarly, an angle estimation error may be detected at the rising edge or falling edge timing of the position detection signal HALL_w, in which case the update processing of the control electrical angle θc is temporarily set to the acceleration update processing or the deceleration update processing in response to the rising edge or falling edge of the position detection signal HALL_w. The same applies when angle estimation errors are detected at the rising edge and falling edge timing of two or more of the position detection signals HALL_u, HALL_v, and HALL_w.

[0061] FIG. 18 is a timing chart showing an example in which an angle estimation error is detected at each edge of the position detection signals HALL_u and HALL_w. In FIG. 18, the solid polygonal line 631 represents the actual waveform of the U-phase output duty, and the dashed polygonal line 632, which partially overlaps with the solid polygonal line 631, represents the ideal waveform of the U-phase output duty. In FIG. 18, time t11 is the ideal fall edge timing of the position detection signal HALL_u. In FIG. 18, the fall edge of the position detection signal HALL_u actually occurs before time t11, and the acceleration update process is performed by an amount corresponding to the difference between time t11 and the actual fall edge timing of the position detection signal HALL_u. In FIG. 18, time t12 is the ideal rise edge timing of the position detection signal HALL_w. FIG. 18 illustrates how the rising edge of the position detection signal HALL_w actually occurs after time t12, and the deceleration update process is performed by an amount corresponding to the difference between time t12 and the actual rising edge timing of the position detection signal HALL_w.

[0062] Below, several specific operational examples, application techniques, modified techniques, etc. related to the drive IC 100 or motor drive system will be described in multiple embodiments. The matters described above in this embodiment apply to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments shown below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can be combined).

[0063] <<First Embodiment>> A first embodiment will be described. In the first embodiment, a detailed method for setting the control electrical angle θc will be described.

[0064] For the sake of concreteness, hereinafter, the detected electrical angle θd at the rising edge timing of the position detection signal HALL_u, the detected electrical angle θd at the falling edge timing of the position detection signal HALL_v, the detected electrical angle θd at the rising edge timing of the position detection signal HALL_w, the detected electrical angle θd at the falling edge timing of the position detection signal HALL_u, the detected electrical angle θd at the rising edge timing of the position detection signal HALL_v, and the detected electrical angle θd at the falling edge timing of the position detection signal HALL_w will be referred to as detected electrical angles θd[0], θd

[60] , θd

[120] , θd

[180] , θd

[240] , and θd

[300] , respectively. The detected electrical angles θd[0], θd

[60] , θd

[120] , θd

[180] , θd

[240] , and θd

[300] are 0°, 60°, 120°, 180°, 240°, and 300°, respectively.

[0065] In addition, hereinafter, the control electrical angle θc at the rising edge timing of the position detection signal HALL_u, the control electrical angle θc at the falling edge timing of the position detection signal HALL_v, the control electrical angle θc at the rising edge timing of the position detection signal HALL_w, the control electrical angle θc at the falling edge timing of the position detection signal HALL_u, the control electrical angle θc at the rising edge timing of the position detection signal HALL_v, and the control electrical angle θc at the falling edge timing of the position detection signal HALL_w will be referred to as control electrical angles θc_UR, θc_VF, θc_WR, θc_UF, θc_VR, and θc_WF, respectively. Ideally (if there is no angle estimation error), the control electrical angles θc_UR, θc_VF, θc_WR, θc_UF, θc_VR, and θc_WF are 0°, 60°, 120°, 180°, 240°, and 300°, respectively.

[0066] The electrical angle estimation circuit 24 includes a counter (not shown) that counts the count value CVAL, and sets the acceleration command signal SSacc or the deceleration command signal SSdec to a high level for a required time using the counter. In the following description, initializing the count value CVAL refers to the process of setting the count value CVAL to zero. The angle amount TH shown below is a predetermined angle amount in electrical angle units, and satisfies "ANG2<TH<ANG1." For example, the angle amount TH is 30°, but may be a value other than 30°. As described above, in this embodiment, the angle amount ANG1 is 60°, which corresponds to the resolution of the position detection signal HALL, and the angle amount ANG2 is the control electrical angle θ C The resolution is 1°, which corresponds to the resolution of 1°. Unless otherwise specified, it is assumed that the basic update process is executed in the setting circuit 21, and the processing contents related to the rise edge or fall edge of the position detection signal HALL_u, HALL_v, or HALL_w will be described.

[0067] ---Fall Edge of HALL_v (60°)--- The process related to the fall edge of the position detection signal HALL_v will be described. Figure 19 is a flowchart of the process related to the fall edge of the position detection signal HALL_v. The drive control circuit 20 can operate in a first operating mode (the significance of the first operating mode will be described later). While the drive control circuit 20 is operating in the first operating mode, a fall edge occurs in the position detection signal HALL_v in step S10. The electrical angle estimation circuit 24 determines whether the following equations (1A), (1B), and (1C) are satisfied at the fall edge timing of the position detection signal HALL_v by comparing the control electrical angle θc (i.e., the control electrical angle θc_VF) with the detected electrical angle θd

[60] . If there is no sudden change in the rotational speed of the rotor 3, one of equations (1A), (1B), and (1C) will be satisfied at the fall edge timing of the position detection signal HALL_v. If none of these conditions are met, the system transitions to a second operation mode (step S18), which will be described later. θd

[60] -ANG2≦θc_VF≦θd

[60] (1A) θd

[60] -TH<θc_VF<θd

[60] -ANG2 (1B) θd

[60] <θc_VF<θd

[60] +TH (1C)

[0068] In case CS_1A where formula (1A) is satisfied at the timing of the falling edge of the position detection signal HALL_v (Y in step S11), the electrical angle estimation circuit 24 determines that there is no angle estimation error (step S12), and thereafter does not output the adjustment signal SS to the control clock generation circuit 23 at least until the timing of the rising edge of the position detection signal HALL_w. Therefore, the basic update process continues to be executed (step S13), and the state returns to the state before step S10.

[0069] In case CS_1B, where equation (1B) is true at the fall edge of the position detection signal HALL_v (Y in step S14), the electrical angle estimation circuit 24 determines that there is an angle estimation error and determines that the control electrical angle θc lags behind the detected electrical angle θd by a delay |θd

[60] - θc_VF| at the fall edge of the position detection signal HALL_v (step S15). |θd

[60] - θc_VF| corresponds to the magnitude of the angle estimation error and represents the absolute value of the difference between the detected electrical angle θd

[60] and the control electrical angle θc_VF. In case CS_1B, the setting circuit 21 performs an acceleration update process for an acceleration control time Tacc_VF corresponding to the delay |θd

[60] - θc_VF| from the fall edge of the position detection signal HALL_v, and then returns the update process for the control electrical angle θc to the basic update process (step S15). After the update process of the control electrical angle θc is returned to the basic update process, the state returns to the state before step S10. The acceleration control time Tacc_VF is expressed by the following equation (1D): Tacc_VF=Tp2×|θd

[60] −θc_VF| / (1−k A ) ...(1D)

[0070] In actuality, in case CS_1B, when the electrical angle estimation circuit 24 determines that there is an angle estimation error at the timing of the falling edge of the position detection signal HALL_v, it initializes the counter value CVAL and generates a rising edge in the acceleration command signal SSacc, thereby switching the update processing of the control electrical angle θc from the basic update processing to the acceleration update processing, and thereafter adds 1 to the count value CVAL every time a rising edge occurs in the control clock signal CLKc. In case CS_1B, the electrical angle estimation circuit 24 defines the acceleration length control value Cacc_VF and calculates the value "|θd

[60] -θc_VF| / (1-k A In the example of FIG. 14, the delay amount |θd

[60] −θc_VF| is 3° (the control electrical angle θc_VF is 57°), and “(1−k A )=0.375", and therefore the acceleration length control value Cacc_VF is 8. Note that if the right side of equation (1E) includes a decimal, the acceleration length control value Cacc_VF may be obtained by rounding off or discarding the decimal part of the value on the right side of equation (1E). After the acceleration update process is started, when the count value CVAL reaches the acceleration length control value Cacc_VF, the electrical angle estimation circuit 24 generates a fall edge in the acceleration command signal SSacc and stops outputting the adjustment signal SS, thereby returning the update process of the control electrical angle θc from the acceleration update process to the basic update process. In other words, when the duration in which the clock signal CLK2 is set to the control clock signal CLKc reaches the product of the cycle length Tp2 of the clock signal CLK2 and the acceleration length control value Cacc_VF (corresponding to the right side of equation (1D)), the control clock signal CLKc is returned to the clock signal CLK1. Cacc_VF=|θd

[60] -θc_VF| / (1-k A ) ... (1E)

[0071] In case CS_1C, where equation (1C) is satisfied at the fall edge timing of the position detection signal HALL_v (Y in step S16), the electrical angle estimation circuit 24 determines that there is an angle estimation error and determines that the control electrical angle θc leads the detected electrical angle θd by the lead amount |θd

[60] - θc_VF| at the fall edge timing of the position detection signal HALL_v (step S17). In case CS_1C, the setting circuit 21 performs deceleration update processing for a deceleration control time Tdec_VF corresponding to the lead amount |θd

[60] - θc_VF| from the fall edge timing of the position detection signal HALL_v, and then returns the update processing of the control electrical angle θc to the basic update processing (step S17). After the update processing of the control electrical angle θc is returned to the basic update processing, the state returns to the state before step S10. The deceleration control time Tdec_VF is expressed by the following equation (1F): Tdec_VF=Tp3×|θd

[60] −θc_VF| / (k B -1) ... (1F)

[0072] In actuality, in case CS_1C, when the electrical angle estimation circuit 24 determines that there is an angle estimation error at the timing of the falling edge of the position detection signal HALL_v, it initializes the counter value CVAL and generates a rising edge in the deceleration command signal SSdec, thereby switching the update process of the control electrical angle θc from the basic update process to the deceleration update process. Thereafter, 1 is added to the count value CVAL every time a rising edge occurs in the control clock signal CLKc. In case CS_1C, the electrical angle estimation circuit 24 defines the deceleration length control value Cdec_VF and calculates the value "|θd

[60] -θc_VF| / (k B Unlike the example of FIG. 14, if the advance amount |θd

[60] −θc_VF| is 3° (the control electrical angle θc_VF is 63°), and B−1)=0.6", then the deceleration length control value Cdec_VF is 5. If the right side of equation (1G) includes a decimal, the deceleration length control value Cdec_VF can be obtained by rounding off or discarding the decimal part of the value on the right side of equation (1G). After the deceleration update process is started, when the count value CVAL reaches the deceleration length control value Cdec_VF, the electrical angle estimation circuit 24 generates a fall edge in the deceleration command signal SSdec and stops outputting the adjustment signal SS, thereby returning the update process of the control electrical angle θc from the deceleration update process to the basic update process. In other words, when the duration in which the clock signal CLK3 is set to the control clock signal CLKc reaches the product of the period length Tp3 of the clock signal CLK3 and the deceleration length control value Cdec_VF (corresponding to the right side of equation (1F)), the control clock signal CLKc is returned to the clock signal CLK1. Cdec_VF=|θd

[60] −θc_VF| / (k B -1) ... (1G)

[0073] When the above-described error reduction methods α1 and α2 are used, the acceleration control time Tacc_VF for case CS_1B is expressed by the following formula (1D_a), and the deceleration control time Tdec_VF for case CS_1C is expressed by the following formula (1F_a). Tacc_VF=Tp2×|θd

[60] −θc_VF| ... (1D_a) Tdec_VF=Tp3×|θd

[60] −θc_VF| ... (1F_a)

[0074] ---Rising Edge of HALL_v (240°)--- Processing related to the rising edge of the position detection signal HALL_v will now be described. FIG. 20 is a flowchart of processing related to the rising edge of the position detection signal HALL_v. The drive control circuit 20 can operate in a first operating mode (the meaning of the first operating mode will be described later). While the drive control circuit 20 is operating in the first operating mode, a rising edge occurs in the position detection signal HALL_v in step S20. The electrical angle estimation circuit 24 compares the control electrical angle θc (i.e., the control electrical angle θc_VR) with the detected electrical angle θd

[240] at the timing of the rising edge of the position detection signal HALL_v to determine whether the following equations (2A), (2B), and (2C) hold. If there is no sudden change in the rotational speed of the rotor 3, any one of equations (2A), (2B), and (2C) will hold at the timing of the rising edge of the position detection signal HALL_v. If none of these conditions are met, the system transitions to a second operation mode (step S28), which will be described later. θd

[240] -ANG2≦θc_VR≦θd

[240] (2A) θd

[240] -TH<θc_VR<θd

[240] -ANG2 (2B) θd

[240] <θc_VR<θd

[240] +TH (2C)

[0075] In case CS_2A where formula (2A) is satisfied at the timing of the rising edge of the position detection signal HALL_v (Y in step S21), the electrical angle estimation circuit 24 determines that there is no angle estimation error (step S22), and thereafter does not output the adjustment signal SS to the control clock generation circuit 23 at least until the timing of the falling edge of the position detection signal HALL_w. Therefore, the basic update process continues to be executed (step S23), and the state returns to the state before step S20.

[0076] In case CS_2B, where equation (2B) is satisfied at the rising edge of the position detection signal HALL_v (Y in step S24), the electrical angle estimation circuit 24 determines that an angle estimation error exists and determines that the control electrical angle θc lags behind the detected electrical angle θd by a delay |θd

[240] - θc_VR| at the rising edge of the position detection signal HALL_v (step S25). |θd

[240] - θc_VR| corresponds to the magnitude of the angle estimation error and represents the absolute value of the difference between the detected electrical angle θd

[240] and the control electrical angle θc_VR. In case CS_2B, the setting circuit 21 performs acceleration update processing for an acceleration control time Tacc_VR corresponding to the delay |θd

[240] - θc_VR| from the rising edge of the position detection signal HALL_v, and then returns the update processing of the control electrical angle θc to the basic update processing (step S25). After the update process of the control electrical angle θc is returned to the basic update process, the state returns to the state before step S20. The acceleration control time Tacc_VR is expressed by the following equation (2D): Tacc_VR=Tp2×|θd

[240] −θc_VR| / (1−k A ) ...(2D)

[0077] In actuality, in case CS_2B, when the electrical angle estimation circuit 24 determines that there is an angle estimation error at the timing of the rising edge of the position detection signal HALL_v, it initializes the counter value CVAL and generates a rising edge in the acceleration command signal SSacc, thereby switching the update processing of the control electrical angle θc from the basic update processing to the acceleration update processing, and thereafter adds 1 to the count value CVAL every time a rising edge occurs in the control clock signal CLKc. In case CS_2B, the electrical angle estimation circuit 24 defines the acceleration length control value Cacc_VR and calculates the value "|θd

[240] -θc_VR| / (1-k A Unlike the example of FIG. 15, if the delay amount |θd

[240] −θc_VR| is 3° (the control electrical angle θc_VR is 237°), and “(1−K A)=0.375", the acceleration length control value Cacc_VR is 8. Note that if the right side of equation (2E) includes a decimal, the acceleration length control value Cacc_VR may be obtained by rounding off or discarding the decimal part of the value on the right side of equation (2E). After the acceleration update process is started, when the count value CVAL reaches the acceleration length control value Cacc_VR, the electrical angle estimation circuit 24 generates a fall edge in the acceleration command signal SSacc and stops outputting the adjustment signal SS, thereby returning the update process of the control electrical angle θc from the acceleration update process to the basic update process. In other words, when the duration in which the clock signal CLK2 is set to the control clock signal CLKc reaches the product of the cycle length Tp2 of the clock signal CLK2 and the acceleration length control value Cacc_VR (corresponding to the right side of equation (2D)), the control clock signal CLKc is returned to the clock signal CLK1. Cacc_VR=|θd

[240] -θc_VR| / (1-k A ) ... (2E)

[0078] In case CS_2C, where equation (2C) is satisfied at the rising edge of the position detection signal HALL_v (Y in step S26), the electrical angle estimation circuit 24 determines that there is an angle estimation error and that the control electrical angle θc leads the detected electrical angle θd by the lead amount |θd

[240] -θc_VR| at the rising edge of the position detection signal HALL_v (step S27). In case CS_2C, the setting circuit 21 performs deceleration update processing for a deceleration control time Tdec_VR corresponding to the lead amount |θd

[240] -θc_VR| from the rising edge of the position detection signal HALL_v, and then returns the update processing of the control electrical angle θc to the basic update processing (step S27). After the update processing of the control electrical angle θc is returned to the basic update processing, the state returns to the state before step S20. The deceleration control time Tdec_VR is expressed by the following equation (2F): Tdec_VR=Tp3×|θd

[240] −θc_VR| / (k B -1) ... (2F)

[0079] In actuality, in case CS_2C, when the electrical angle estimation circuit 24 determines that there is an angle estimation error at the timing of the rising edge of the position detection signal HALL_v, it initializes the counter value CVAL and generates a rising edge in the deceleration command signal SSdec, thereby switching the update process of the control electrical angle θc from the basic update process to the deceleration update process. Thereafter, 1 is added to the count value CVAL every time a rising edge occurs in the control clock signal CLKc. In case CS_2C, the electrical angle estimation circuit 24 defines the deceleration length control value Cdec_VR and calculates the value "|θd

[240] -θc_VR| / (k B In the example of FIG. 15, the advance amount |θd

[240] −θc_VR| is 3° (the control electrical angle θc_VR is 243°), and “(k B −1)=0.6″, and therefore the deceleration length control value Cdec_VR is 5. Note that, when the right side of equation (2G) includes a decimal, the deceleration length control value Cdec_VR can be obtained by rounding off or discarding the decimal part of the value on the right side of equation (2G). After the deceleration update process is started, the electrical angle estimation circuit 24 generates a fall edge in the deceleration command signal SSdec and stops outputting the adjustment signal SS when the count value CVAL reaches the deceleration length control value Cdec_VR, thereby returning the update process of the control electrical angle θc from the deceleration update process to the basic update process. In other words, when the duration in which the clock signal CLK3 is set to the control clock signal CLKc reaches the product of the period length Tp3 of the clock signal CLK3 and the deceleration length control value Cdec_VR (corresponding to the right side of equation (2F)), the control clock signal CLKc is returned to the clock signal CLK1. Cdec_VR=|θd

[240] −θc_VR| / (k B -1) ... (2G)

[0080] When the above-described error reduction methods α1 and α2 are used, the acceleration control time Tacc_VR for case CS_2B is expressed by the following formula (2D_a), and the deceleration control time Tdec_VR for case CS_2C is expressed by the following formula (2F_a). Tacc_VR=Tp2×|θd

[240] −θc_VR| ... (2D_a) Tdec_VR=Tp3×|θd

[240] −θc_VR| ... (2F_a)

[0081] ---Target Edges of HALL (Generalized)--- The processing related to the rising and falling edges of the position detection signals HALL_u and HALL_w is similar to the processing related to the rising or falling edge of the position detection signal HALL_v. The processing related to these six edges will be generalized and explained below. FIG. 21 is a flowchart of the processing related to the target edges of the position detection signal HALL. The target edges of the position detection signal HALL are either the rising or falling edges of the position detection signal HALL_u, the rising or falling edges of the position detection signal HALL_v, or the rising or falling edges of the position detection signal HALL_w.

[0082] The target edges of the position detection signal HALL are the rising edge and falling edge of the position detection signal HALL_u at the timings when the rising edge and falling edge of the position detection signal HALL_u occur. The target edges of the position detection signal HALL are the rising edge and falling edge of the position detection signal HALL_v at the timings when the rising edge and falling edge of the position detection signal HALL_v occur. The target edges of the position detection signal HALL are the rising edge and falling edge of the position detection signal HALL_w at the timings when the rising edge and falling edge of the position detection signal HALL_w occur. The target edge timing of the position detection signal HALL is the timing at which the target edge of the position detection signal HALL occurs. The control electrical angle θc and the detected electrical angle θd at the target edge timing of the position detection signal HALL are denoted as the control electrical angle θc_x and the detected electrical angle θd_x, respectively.

[0083] The drive control circuit 20 can operate in a first operation mode (the meaning of the first operation mode will be described later). While the drive control circuit 20 is operating in the first operation mode, a target edge occurs in the position detection signal HALL in step S30. The electrical angle estimation circuit 24 compares the control electrical angle θc (i.e., the control electrical angle θc_x) with the detection electrical angle θd_x at the target edge timing of the position detection signal HALL to determine whether the following equations (3A), (3B), and (3C) hold. If there is no sudden change in the rotational speed of the rotor 3, any one of equations (3A), (3B), and (3C) will hold at the target edge timing of the position detection signal HALL. If none of these equations hold, the operation mode transitions to a second operation mode (step S38), which will be described later. When the target edge of the position detection signal HALL is the rising edge of the position detection signal HALL_u and the control electrical angle θc_x is 180° or more, θc_x in the equations (3A), (3B), and (3C) is regarded as the control electrical angle θc (e.g., 357°, 358°, or 359°) at the timing of the rising edge of the position detection signal HALL_u minus 360°: θd_x-ANG2≦θc_x≦θd_x (3A) θd_x-TH<θc_x<θd_x-ANG2 (3B) θd_x<θc_x<θd_x+TH (3C)

[0084] In case CS_3A where formula (3A) is satisfied at the target edge timing of the position detection signal HALL (Y in step S31), the electrical angle estimation circuit 24 determines that there is no angle estimation error (step S32) and thereafter does not output the adjustment signal SS to the control clock generation circuit 23 until at least the next edge timing. Therefore, the basic update process continues to be executed (step S33), and the state returns to the state before step S30. If the target edge timing of the position detection signal HALL is the rising edge of the position detection signal HALL_u, the falling edge of the position detection signal HALL_v, the rising edge of the position detection signal HALL_w, the falling edge of the position detection signal HALL_u, the rising edge of the position detection signal HALL_v, or the falling edge of the position detection signal HALL_w, the next edge timing here is the fall edge of the position detection signal HALL_v, the rising edge of the position detection signal HALL_w, the falling edge of the position detection signal HALL_u, the rising edge of the position detection signal HALL_v, the falling edge of the position detection signal HALL_w, or the rising edge of the position detection signal HALL_u, respectively.

[0085] In case CS_3B where equation (3B) is satisfied at the target edge timing of the position detection signal HALL (Y in step S34), the electrical angle estimation circuit 24 determines that there is an angle estimation error and determines that the control electrical angle θc lags behind the detected electrical angle θd by a delay amount |θd_x - θc_x| at the target edge timing of the position detection signal HALL (step S35). |θd_x - θc_x| corresponds to the magnitude of the angle estimation error and represents the absolute value of the difference between the detected electrical angle θd_x and the control electrical angle θc_x. Note that when the target edge of the position detection signal HALL is the rising edge of the position detection signal HALL_u and equation (3B) is satisfied, the control electrical angle θc_x is, for example, 358°, and θd_x in "|θd_x - θc_x|" is considered to be 360°. In case CS_3B, the setting circuit 21 performs the acceleration update process for an acceleration control time Tacc_x corresponding to the delay amount |θd_x - θc_x| from the target edge timing of the position detection signal HALL, and then returns the update process of the control electrical angle θc to the basic update process (step S35). After the update process of the control electrical angle θc is returned to the basic update process, the state returns to the state before step S30. The acceleration control time Tacc_x is expressed by the following equation (3D). Tacc_x = Tp2 × |θd_x - θc_x| / (1-k A ) ...(3D)

[0086] In actuality, in case CS_3B, when the electrical angle estimation circuit 24 determines that there is an angle estimation error at the target edge timing of the position detection signal HALL, it initializes the counter value CVAL and generates a rising edge in the acceleration command signal SSacc, thereby switching the update processing of the control electrical angle θc from the basic update processing to the acceleration update processing, and thereafter adds 1 to the count value CVAL every time a rising edge occurs in the control clock signal CLKc. In case CS_3B, the electrical angle estimation circuit 24 defines the acceleration length control value Cacc_x and calculates the value "|θd_x-θc_x| / (1-k A)". If the right side of equation (3E) includes a decimal, the acceleration length control value Cacc_x may be calculated by rounding off or discarding the decimal part of the value on the right side of equation (3E). After the acceleration update process is started, when the count value CVAL reaches the acceleration length control value Cacc_x, the electrical angle estimation circuit 24 generates a fall edge in the acceleration command signal SSacc and stops outputting the adjustment signal SS, thereby returning the update process of the control electrical angle θc from the acceleration update process to the basic update process. In other words, when the duration of the state in which the clock signal CLK2 is set to the control clock signal CLKc reaches the product of the cycle length Tp2 of the clock signal CLK2 and the acceleration length control value Cacc_x (corresponding to the right side of equation (3D)), the control clock signal CLKc is returned to the clock signal CLK1. Cacc_x = |θd_x - θc_x| / (1-k A ) ... (3E)

[0087] In case CS_3C where equation (3C) is established at the target edge timing of the position detection signal HALL (Y in step S36), the electrical angle estimation circuit 24 determines that there is an angle estimation error and that the control electrical angle θc leads the detected electrical angle θd by the lead amount |θd_x - θc_x| at the target edge timing of the position detection signal HALL (step S37). In case CS_3C, the setting circuit 21 performs deceleration update processing for a deceleration control time Tdec_x corresponding to the lead amount |θd_x - θc_x| from the target edge timing of the position detection signal HALL, and then returns the update processing of the control electrical angle θc to the basic update processing (step S37). After the update processing of the control electrical angle θc is returned to the basic update processing, the state returns to the state before step S30. The deceleration control time Tdec_x is expressed by the following equation (3F): Tdec_x = Tp3 × |θd_x - θc_x| / (k B -1) ... (3F)

[0088] In actuality, in case CS_3C, when the electrical angle estimation circuit 24 determines that there is an angle estimation error at the target edge timing of the position detection signal HALL, it initializes the counter value CVAL and generates a rising edge in the deceleration command signal SSdec, thereby switching the update process of the control electrical angle θc from the basic update process to the deceleration update process. Thereafter, 1 is added to the count value CVAL every time a rising edge occurs in the control clock signal CLKc. In case CS_3C, the electrical angle estimation circuit 24 defines the deceleration length control value Cdec_x, and calculates the value "|θd_x - θc_x| / (k B -1)". If the right side of equation (3G) includes a decimal, the deceleration length control value Cdec_x may be calculated by rounding off or discarding the decimal part of the value on the right side of equation (3G). After the deceleration update process is started, when the count value CVAL reaches the deceleration length control value Cdec_x, the electrical angle estimation circuit 24 generates a fall edge in the deceleration command signal SSdec and stops outputting the adjustment signal SS, thereby returning the update process of the control electrical angle θc from the deceleration update process to the basic update process. In other words, when the duration of the state in which the clock signal CLK3 is set to the control clock signal CLKc reaches the product of the cycle length Tp3 of the clock signal CLK3 and the deceleration length control value Cdec_x (corresponding to the right side of equation (3F)), the control clock signal CLKc is returned to the clock signal CLK1. Cdec_x = |θd_x - θc_x| / (k B -1) ... (3G)

[0089] When the above-described error reduction methods α1 and α2 are used, the acceleration control time Tacc_x for case CS_3B is expressed by the following formula (3D_a), and the deceleration control time Tdec_x for case CS_3C is expressed by the following formula (3F_a). Tacc_x=Tp2×|θd_x−θc_x| (3D_a) Tdec_x=Tp3×|θd_x−θc_x| (3F_a)

[0090] <<Second Example>> A second example will be described. The above-described operations, including those shown in FIGS. 19 to 21, are operations in the first operating mode. The drive control circuit 20 operates in one of a plurality of operating modes, including the first operating mode and the second operating mode. After the motor 1 is started, the drive control circuit 20 operates in the first operating mode when the rotor 3 is rotating stably at a complete or approximately constant rotational speed (hereinafter referred to as the steady state). The basic update process, acceleration update process, and deceleration update process shown in this embodiment are processes suitable for use in the steady state, and are executed while the drive control circuit 20 operates in the first operating mode. However, if a sudden change occurs in the rotational speed of the rotor 3, the operating mode of the drive control circuit 20 is switched from the first operating mode to the second operating mode. In the process of rapid acceleration or deceleration of the rotational speed of the rotor 3, in the operation of FIG. 19, FIG. 20, or FIG. 21, if the error between the control electrical angle θc and the detected electrical angle θd becomes equal to or greater than an angle amount TH (e.g., 30°) corresponding to a threshold value, the process proceeds to step S18, S28, or S38.

[0091] FIG. 22 shows the relationship between the position detection signals HALL_u, HALL_v, and HALL_w and the clock signal CLK1 in the second operation mode. In any frame FR, the period from the rising edge timing of the position detection signal HALL_u to the falling edge timing of the position detection signal HALL_v is referred to as period P1, the period from the falling edge timing of the position detection signal HALL_v to the rising edge timing of the position detection signal HALL_w is referred to as period P2, the period from the rising edge timing of the position detection signal HALL_w to the falling edge timing of the position detection signal HALL_u is referred to as period P3, the period from the falling edge timing of the position detection signal HALL_u to the rising edge timing of the position detection signal HALL_v is referred to as period P4, the period from the rising edge timing of the position detection signal HALL_v to the falling edge timing of the position detection signal HALL_w is referred to as period P5, and the period from the falling edge timing of the position detection signal HALL_w to the rising edge timing of the position detection signal HALL_u is referred to as period P6.

[0092] The control clock generation circuit 23 in the second operation mode divides the time length of the most recent 60° detected electrical angle θd by a value (60° / ANG2) every time the detected electrical angle θd advances by 60°, thereby determining the period of the clock signal CLK1 (and therefore the period of the control clock signal CLKc). In the second operation mode, the control clock signal CLKc always coincides with the clock signal CLK1. Therefore, the length of one period of the control clock signal CLKc in the second operation mode is the period length Tp1 of the clock signal CLK1 (see FIG. 11).

[0093] Specifically, when a falling edge of the position detection signal HALL_v occurs in the frame FR[i], the control clock generation circuit 23 in the second operation mode divides the length of the period P1 in the frame FR[i] by a value (60° / ANG2) and sets the time obtained by this division as the cycle length Tp1 of the period P2 in the frame FR[i]. Similarly, when a rising edge of the position detection signal HALL_w occurs in the frame FR[i], the control clock generation circuit 23 in the second operation mode divides the length of the period P2 in the frame FR[i] by a value (60° / ANG2) and sets the time obtained by this division as the cycle length Tp1 of the period P3 in the frame FR[i]. Similarly, when a falling edge of the position detection signal HALL_u occurs in frame FR[i], the control clock generation circuit 23 in the second operation mode divides the length of the period P3 in frame FR[i] by a value (60° / ANG2) and sets the time obtained by this division as the period length Tp1 of the period P4 in frame FR[i]. The same applies to the occurrence of other edges in the position detection signals HALL_u, HALL_v, and HALL_w, and also to frames after frame FR[i] as long as the second operation mode continues.

[0094] In the second operation mode, the electrical angle estimation circuit 24 forcibly sets the control electrical angle θc to the detected electrical angle θd each time an edge occurs in the position detection signal HALL. That is, when a falling edge occurs in the position detection signal HALL_v, the electrical angle estimation circuit 24 in the second operation mode sets the control electrical angle θc to the detected electrical angle θd

[60] (i.e., 60°) at the timing of the falling edge of the position detection signal HALL_v, and thereafter updates the control electrical angle θc in accordance with the control clock signal CLKc until a rising edge occurs in the position detection signal HALL_w. Thereafter, when a rising edge occurs in the position detection signal HALL_w, the electrical angle estimation circuit 24 in the second operation mode sets the control electrical angle θc to the detected electrical angle θd

[120] (i.e., 120°) at the timing of the rising edge of the position detection signal HALL_w, and thereafter updates the control electrical angle θc in accordance with the control clock signal CLKc until a falling edge occurs in the position detection signal HALL_u. The same is true for the occurrence of other edges in the position detection signals HALL_u, HALL_v, and HALL_w, as long as the second operating mode continues.

[0095] By forcibly setting the detection electrical angle θd relative to the control electrical angle θc every time an edge occurs in the position detection signal HALL, discontinuities occur in the drive waveforms of the coils of each phase. However, during the process of rapid acceleration or deceleration of the rotational speed of the rotor 3, discontinuities are tolerated, and priority is given to making the control electrical angle θc follow the detection electrical angle θd.

[0096] In the second operating mode, the drive control circuit 20 (e.g., the electrical angle estimation circuit 24) monitors whether a predetermined stabilization condition is met. If the stabilization condition is not met, the drive control circuit 20 maintains the operating mode in the second operating mode. If the stabilization condition is met, the drive control circuit 20 switches from the second operating mode to the first operating mode. The stabilization condition is met when the above-described formula (3A), (3B), or (3C) is satisfied for the target edge of the position detection signal HALL, which is any of the rising and falling edges of the position detection signals HALL_u, HALL_v, and HALL_w. The stabilization condition is not met when none of formulas (3A), (3B), or (3C) is satisfied. That is, if the error between the control electrical angle θc and the detected electrical angle θd falls below the angle amount TH (e.g., 30°), the operation mode transitions from the second operating mode to the first operating mode.

[0097] <<Third Embodiment>> A third embodiment will be described. The method of acquiring the position detection signal HALL using three position detection units 4u, 4v, and 4w, each of which is formed by a Hall element or a Hall IC, has been described above, but the position detection signal HALL may also be acquired using only one or two of the position detection units 4u, 4v, and 4w. Furthermore, any method may be used to acquire the position detection signal HALL, and the position detection signal HALL may also be acquired in a so-called sensorless manner.

[0098] That is, for example, the position detection signal acquisition circuit 10 may detect the back electromotive forces generated in the coils 2u, 2v, and 2w during rotation of the rotor 3 based on the terminal voltages Vu, Vv, and Vw and the voltage at the neutral point NP, and generate the position detection signals HALL_u, HALL_v, and HALL_w by a known method from the detection results of the back electromotive forces. Alternatively, for example, the position detection signal acquisition circuit 10 may detect the current flowing through the coil 2u, the current flowing through the coil 2v, and the current flowing through the coil 2w, and generate the position detection signals HALL_u, HALL_v, and HALL_w by a known method from the detection results of each current.

[0099] <<Fourth Example>> A fourth example will now be described, with supplementary explanation of the angle amounts ANG1 and ANG2.

[0100] The position detection signal HALL is obtained by detecting the position of the rotor 3 in units of an angle amount ANG1 (e.g., 60°). As described above, the setting circuit 21 generates the control clock signal CLKc having a frequency corresponding to the rotational speed of the rotor 3 based on the position detection signal HALL, and estimates the electrical angle indicating the position of the rotor 3 in units of an angle amount ANG2 (e.g., 1°) as the control electrical angle θc based on the control clock signal CLKc and the position detection signal HALL. At this time, the setting circuit 21 updates the control electrical angle θc based on the control clock signal CLKc. In the position detection signal HALL, a singular signal (edge) is generated every time the electrical angle indicating the position of the rotor 3 changes by the angle amount ANG1 (e.g., 60°). The setting circuit 21 compares the detected electrical angle θd with the control electrical angle θc at the timing when the unique signal is generated, and if there is an error between the detected electrical angle θd and the control electrical angle θc, adjusts the update period of the control electrical angle θc in accordance with the error (switches the update period of the control electrical angle θc from the period length Tp1 to the period length Tp2 or Tp3).

[0101] The above-mentioned peculiar signals are edges in the position detection signal HALL. When the angle amount ANG1 is 60°, each of the six edges consisting of the rise edge and fall edge in the position detection signal HALL_u, the rise edge and fall edge in the position detection signal HALL_v, and the rise edge and fall edge in the position detection signal HALL_w corresponds to a peculiar signal.

[0102] However, the angle amount ANG1 is not limited to 60°. For example, in the position detection signal acquisition circuit 10 (see FIG. 4), only the position detection signal HALL_x may be acquired from the position detection signals HALL_u, HALL_v, and HALL_w. In this case, the position detection signal HALL_x is obtained by detecting the position of the rotor 3 using the angle amount ANG1 of 180° as the minimum unit, and of the six edges, only the rise edge and fall edge in the position detection signal HALL_x correspond to the peculiar signal. Here, the position detection signal HALL_x refers to any one of the position detection signals HALL_u, HALL_v, and HALL_w. Only one of the rise edge and fall edge in the position detection signal HALL_x may be the peculiar signal, in which case the angle amount ANG1 is 360°. As mentioned above, the angle amount ANG2 is also not limited to 1°.

[0103] <<Fifth Example>> A fifth example will be described.

[0104] The technology according to the present disclosure can also be applied to advance angle processing (advance angle control).

[0105] The motor drive system of Fig. 4 can be mounted on any electrical device. The electrical device may be an electrical component mounted on a vehicle such as an automobile, or may be a home appliance or industrial device. The motor 1 may be a motor for propelling a vehicle.

[0106] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0107] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples. The channel type of any FET can be changed between P-channel and N-channel types without departing from the spirit of the above.

[0108] The aforementioned transistors may be any type of transistor, provided that no disadvantages arise. For example, any transistor described above as a MOSFET may be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, provided that no disadvantages arise. Each transistor has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base. The aforementioned transistors may be made of any semiconductor material, such as silicon (Si), gallium nitride (GaN), gallium oxide (GaO), or silicon carbide (SiC), which are sometimes classified as power semiconductor materials.

[0109] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0110] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0111] A motor drive device according to one aspect of the present disclosure is a motor drive device (100) configured to drive a three-phase motor (1) having U-phase, V-phase, and W-phase coils (2u, 2v, 2w), and includes a control electrical angle setting circuit (21) configured to generate a control clock signal (CLKc) having a frequency corresponding to the rotational speed of the rotor based on position detection signals (HALL_u, HALL_v, HALL_w) obtained by detecting the position of a rotor of the three-phase motor in minimum units of a first angle amount (ANG1: for example, 60°), estimate an electrical angle indicating the position of the rotor in minimum units of a second angle amount (ANG2: for example, 1°) smaller than the first angle amount as a control electrical angle (θc) based on the control clock signal and the position detection signal, and update the control electrical angle based on the control clock signal. and a drive control signal generation circuit (22) configured to generate drive control signals (DRVu, DRVv, DRVw) for supplying a phase voltage corresponding to the control electrical angle to a coil of each phase based on the control electrical angle, wherein the three-phase motor is driven based on the drive control signals, and a singular signal (rising edge or falling edge in HALL_u, HALL_v, or HALL_w) is generated each time the electrical angle indicating the rotor position in the position detection signals changes by the first angle amount, and the control electrical angle setting circuit compares the control electrical angle with a detected electrical angle (θd) indicated by the position detection signals at the timing when the singular signal is generated, and when there is an error between the detected electrical angle and the control electrical angle, adjusts the update cycle of the control electrical angle in accordance with the error (first configuration).

[0112] This prevents discontinuous waveforms from being inserted into the drive waveforms of the coils of each phase, which is expected to reduce noise or vibrations associated with motor drive.

[0113] In the motor drive device according to the first configuration, the control electrical angle setting circuit may set the control clock signal to one of a base clock signal (CLK1) having a first cycle length (Tp1) based on the position detection signal, an acceleration clock signal (CLK2) having a second cycle length (Tp2) shorter than the first cycle length, or a deceleration clock signal (CLK3) having a third cycle length (Tp3) longer than the first cycle length, and when the singular signal occurs with the base clock signal set as the control clock signal, if there is an error between the detected electrical angle and the control electrical angle at the timing of the occurrence of the singular signal, the control electrical angle setting circuit may be configured to set the control clock signal to the acceleration clock signal or the deceleration clock signal for a time corresponding to the magnitude of the error so as to reduce the error, and then return the control clock signal to the base clock signal (second configuration).

[0114] In the motor drive device according to the second configuration, when the singular signal is generated with the base clock signal set to the control clock signal, if it is detected that the control electrical angle lags behind the detected electrical angle at the time the singular signal is generated, the control electrical angle setting circuit sets the acceleration clock signal to the control clock signal for an acceleration control time (Tacc_x) corresponding to an amount of delay (|θd_x - θc_x|) of the control electrical angle from the detected electrical angle, and then returns the control clock signal to the base clock signal; and when the singular signal is generated with the base clock signal set to the control clock signal, if it is detected that the control electrical angle leads behind the detected electrical angle at the time the singular signal is generated, the control electrical angle setting circuit sets the deceleration clock signal to the control clock signal for a deceleration control time (Tdec_x) corresponding to an amount of lead (|θd_x - θc_x|) of the control electrical angle from the detected electrical angle, and then returns the control clock signal to the base clock signal (third configuration).

[0115] In the motor drive device according to the second or third configuration, the control electrical angle setting circuit may be configured (fourth configuration) to maintain the state in which the base clock signal is set to the control clock signal when the singular signal occurs while the base clock signal is set to the control clock signal and the error is not detected.

[0116] The motor drive device according to any of the first to fourth configurations may have a configuration (fifth configuration) including an output stage circuit (30, 40) configured to supply a phase voltage to the coil of each phase in response to the drive control signal.

[0117] A motor drive system according to one aspect of the present disclosure has a configuration (sixth configuration) including a motor drive device according to the fifth configuration described above and a three-phase motor configured to be driven by the motor drive device.

[0118] REFERENCE SIGNS LIST 1 Motor 2u, 2v, 2w Coil 3 Rotor 4 Position detector 4u, 4v, 4w Position detection unit 100 Drive IC 10 Position detection signal acquisition circuit 20 Drive control circuit 21 Control electrical angle setting circuit 22 Drive control signal generation circuit 22a Waveform data table 23 Control clock generation circuit 231 to 233 Clock generation circuit 234 Selector 24 Electrical angle estimation circuit 30 Pre-driver 40 Inverter circuit 40u, 40v, 40w Half-bridge circuit MH High-side transistor ML Low-side transistor HALL_u, HALL_v, HALL_w Position detection signal CLKc Control clock signal CLK1 Clock signal (basic clock signal) CLK2 Clock signal (acceleration clock signal) CLK3 Clock signal (deceleration clock signal) θc Control electrical angle DRVu, DRVv, DRVw Drive control signals OUTu, OUTv, OUTw External terminals NP Neutral point Vu, Vv, Vw Voltage (phase voltage, terminal voltage)

Claims

1. A motor drive device configured to drive a three-phase motor having U-phase, V-phase, and W-phase coils, comprising: a control electrical angle setting circuit configured to generate a control clock signal having a frequency corresponding to the rotational speed of the rotor based on a position detection signal obtained by detecting the position of the rotor of the three-phase motor in minimum units of a first angle amount, estimate an electrical angle indicating the position of the rotor in minimum units of a second angle amount smaller than the first angle amount based on the control clock signal and the position detection signal, and update the control electrical angle based on the control clock signal; and a drive control signal generation circuit configured to generate a drive control signal based on the control electrical angle, for supplying a phase voltage corresponding to the control electrical angle to the coils of each phase, and drive the three-phase motor based on the drive control signal, and a singular signal is generated each time the electrical angle indicating the rotor position in the position detection signal changes by the first angle amount, the control electrical angle setting circuit compares the control electrical angle with the detected electrical angle indicated by the position detection signal at the timing when the singular signal occurs, and, if there is an error between the detected electrical angle and the control electrical angle, adjusts an update cycle of the control electrical angle in accordance with the error.

2. The motor drive device according to claim 1, wherein the control electrical angle setting circuit sets the control clock signal to a basic clock signal having a first cycle length based on the position detection signal, an acceleration clock signal having a second cycle length shorter than the first cycle length, or a deceleration clock signal having a third cycle length longer than the first cycle length, and when the singular signal occurs with the basic clock signal set to the control clock signal, and there is an error between the detected electrical angle and the control electrical angle at the timing of the occurrence of the singular signal, the control electrical angle setting circuit sets the acceleration clock signal or the deceleration clock signal to the control clock signal for a time period corresponding to the magnitude of the error so that the error is reduced, and then returns the control clock signal to the basic clock signal.

3. The motor drive device according to claim 2, wherein, when the singular signal occurs with the base clock signal set to the control clock signal, if it is detected that the control electrical angle lags behind the detected electrical angle at the time the singular signal occurs, the control electrical angle setting circuit sets the acceleration clock signal to the control clock signal for an acceleration control time corresponding to the amount of lag of the control electrical angle from the detected electrical angle, and then returns the control clock signal to the base clock signal; and when the singular signal occurs with the base clock signal set to the control clock signal, if it is detected that the control electrical angle leads behind the detected electrical angle at the time the singular signal occurs, the control electrical angle setting circuit sets the deceleration clock signal to the control clock signal for a deceleration control time corresponding to the amount of lead of the control electrical angle from the detected electrical angle, and then returns the control clock signal to the base clock signal.

4. The motor drive device according to claim 2 or 3, wherein the control electrical angle setting circuit maintains the state in which the base clock signal is set to the control clock signal if the singular signal occurs while the base clock signal is set to the control clock signal and the error is not detected.

5. A motor drive device according to any one of claims 1 to 4, comprising an output stage circuit configured to supply a phase voltage to a coil of each phase in response to the drive control signal.

6. A motor drive system comprising the motor drive device according to claim 5 and a three-phase motor configured to be driven by said motor drive device.

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