Silicon carbide device and manufacturing method therefor, and electronic device

Abstract

The present invention relates to the technical field of semiconductors, and in particular to a silicon carbide device and a manufacturing method therefor, and an electronic device. The silicon carbide device comprises a silicon carbide substrate layer and an epitaxial layer arranged on the silicon carbide substrate layer; a trench gate structure is provided on the side of the epitaxial layer away from the silicon carbide substrate layer; shielding structures are respectively provided on both sides of the trench gate structure; a first shielding region of each shielding structure extends towards one side of a first surface of the silicon carbide substrate layer, a second shielding region of the shielding structure is provided on the side of the first shielding region facing the first surface of the silicon carbide substrate layer, and in a first direction, a gap between two adjacent second shielding regions is smaller than a gap between two adjacent first shielding regions; the lengths of the first shielding regions are less than the lengths of the second shielding regions, and in the projection of the epitaxial layer, the second shielding regions completely cover the first shielding regions, and in a second direction, the depth of the trench gate structure is less than the depth of each shielding structure. The silicon carbide transistor in the present disclosure has high reliability and low on-resistance.

Description

Silicon carbide device, manufacturing method thereof and electronic device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411097431.4, filed on August 12, 2024, entitled "Silicon carbide device, manufacturing method thereof and electronic device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a silicon carbide device, a manufacturing method thereof and an electronic device. BACKGROUND

[0004] Silicon carbide, as a semiconductor material with wide band gap, high breakdown field strength, high thermal conductivity, and similar mobility to silicon, has broad prospects in power electronic applications and is widely used in new energy vehicles, charging piles, photovoltaic, etc.

[0005] Since the gate oxide layer at the bottom of the trench gate included in the silicon carbide device is close to the drift region, the gate oxide layer at the bottom of the trench gate needs to withstand greater electric field stress, which causes the gate oxide layer at the bottom of the trench gate to be easily broken down, thereby reducing the reliability of the silicon carbide device. Therefore, a wider shielding region is provided on both sides of the trench gate structure to protect the structure of the gate oxide layer, but this method increases the on-resistance of the silicon carbide device. Therefore, how to improve the reliability of the silicon carbide device while reducing the on-resistance of the silicon carbide device has become a technical problem to be solved in the field. SUMMARY

[0006] The embodiments of the present application provide a silicon carbide device, a manufacturing method thereof and an electronic device to improve the reliability of the silicon carbide transistor and reduce the on-resistance of the silicon carbide device.

[0007] In a first aspect, embodiments of the present application provide a silicon carbide device, the silicon carbide device comprising: a silicon carbide substrate layer; an epitaxial layer disposed on a first surface of the silicon carbide substrate layer; the epitaxial layer being provided with a trench gate structure on a side away from the first surface of the silicon carbide substrate layer, both sides of the trench gate structure being provided with a shielding structure, the shielding structure comprising a first shielding region and a second shielding region, the first shielding region extending to the side of the first surface of the silicon carbide substrate layer, the first shielding region being provided with the second shielding region on the side of the first surface of the silicon carbide substrate layer, along a first direction, there being a gap between two adjacent second shielding regions, the gap between the two adjacent second shielding regions being smaller than the gap between two adjacent first shielding regions, the length of the first shielding region being smaller than the length of the second shielding region, and in a projection of the epitaxial layer, the second shielding region entirely covers the first shielding region, along a second direction, the depth of the trench gate structure being smaller than the depth of the shielding structure.

[0008] In an embodiment, along the first direction, the difference between the length of the first shielding region and the length of the second shielding region is 10 nanometers to 5 micrometers.

[0009] In an embodiment, the first shielding region and the second shielding region are opposite in doping type to the epitaxial layer, and the doping concentration of the first shielding region and the second shielding region is between 10 times and 1,000,000 times the doping concentration of the epitaxial layer.

[0010] In an embodiment, along the second direction, the depth of the shielding structure is L, and along the first direction, the gap between two adjacent first shielding regions is d, L / d is between 0.5 and 20.

[0011] In an embodiment, along the first direction, a current conduction region is formed between two adjacent shielding structures, and a first doped region and a second doped region are provided between the trench gate structure and the first shielding region, the first doped region and the second doped region being sequentially stacked on a side of the current conduction region away from the silicon carbide substrate layer, wherein:

[0012] The doping type of the first doped region and the second doped region is opposite, and the doping type of the first doped region is the same as the doping type of the second shielding region.

[0013] In an embodiment, the trench gate structure comprises a polysilicon gate trench and a gate dielectric, the polysilicon gate trench comprising a bottom wall and a side wall, the thickness of the gate dielectric provided on the bottom wall of the polysilicon gate trench being Tb, the thickness of the gate dielectric provided on the side wall of the polysilicon gate trench being Ts, Tb≥Ts, and the value of Tb / Ts is between 1 and 3.

[0014] In one embodiment, along the second direction, the polysilicon gate trench has a depth greater than a depth of the first doped region.

[0015] In one embodiment, the silicon carbide device further comprises a covering dielectric layer disposed on a side of the epitaxial layer facing away from the silicon carbide substrate layer, the covering dielectric layer covering the polysilicon gate trench.

[0016] In a second aspect, embodiments of the present application provide a method for manufacturing a silicon carbide device as described in the first aspect above, comprising:

[0017] forming an epitaxial layer on the silicon carbide substrate layer;

[0018] forming two second shielding regions of the shielding structure in the epitaxial layer, the two second shielding regions being spaced apart along the first direction;

[0019] forming two first shielding regions of the shielding structure on a side of the second shielding regions facing away from the silicon carbide substrate layer, along the first direction, the length of the first shielding region is less than the length of the second shielding region, and the gap between the two first shielding regions is greater than the gap between the two second shielding regions, in the projection of the epitaxial layer, the second shielding region covers the first shielding region entirely;

[0020] forming a trench gate structure between the two first shielding regions, along the second direction, the depth of the trench gate structure is less than the depth of the first shielding region.

[0021] In a third aspect, embodiments of the present application provide an electronic device comprising a silicon carbide device as described in the first aspect above.

[0022] The silicon carbide device, the manufacturing method thereof, and the electronic device provided by embodiments of the present application have the following advantages. Along the first direction, the length of the first shielding region is less than the length of the second shielding region, and in the projection of the epitaxial layer, the second shielding region covers the first shielding region entirely. Along the second direction, the depth of the trench gate structure is less than the depth of the shielding structure. The gap between the first shielding regions determines the width of the conduction current channel and thus affects the conduction resistance. The length of the first shielding region relative to the length of the second shielding region is small, which can ensure that the conduction resistance of the silicon carbide device is small. The width of the second shielding region determines the shielding degree of the strong electric field stress and thus affects the protection effect of the trench gate structure. The distance between the two adjacent second shielding regions is small, which can improve the shielding capability of the second shielding region and reduce the risk that the gate oxide layer at the bottom of the trench gate structure is easily broken down. In addition, the simultaneous use of the two shielding structures, i.e., the first shielding region and the two second shielding regions, can ensure that a wider conduction current channel (i.e., the gap between the two adjacent first shielding regions) and a better strong electric field stress shielding effect appear in one silicon carbide device at the same time, so that the silicon carbide device is more compact. BRIEF DESCRIPTION OF DRAWINGS

[0023] Fig. 1 is a sectional view of a silicon carbide transistor according to an embodiment of the present application;

[0024] Fig. 2 is a flow chart of a method for manufacturing a silicon carbide transistor according to an embodiment of the present application;

[0025] Figs. 3a to 3i are process flow diagrams of a method for manufacturing a silicon carbide transistor according to an embodiment of the present application;

[0026] Fig. 4 is another flow chart of a method for manufacturing a silicon carbide transistor according to an embodiment of the present application;

[0027] Figs. 5a to 5i are process flow diagrams of a method for manufacturing a silicon carbide transistor according to an embodiment of the present application;

[0028] Fig. 6 is another flow chart of a method for manufacturing a silicon carbide transistor according to an embodiment of the present application;

[0029] Figs. 7a to 7i are process flow diagrams of a method for manufacturing a silicon carbide transistor according to an embodiment of the present application.

[0030] Reference numerals: 10 - silicon carbide substrate layer; 11 - first surface; 12 - second surface; 20 - epitaxial layer; 21 - current conduction region; 22 - first doped region; 23 - second doped region; 30 - polysilicon gate trench; 31 - bottom wall; 32 - side wall; 40 - gate dielectric; 50 - first shielding region; 60 - second shielding region; 70 - covering dielectric layer. DETAILED DESCRIPTION

[0031] Embodiments of a silicon carbide transistor, a method for manufacturing the same and an electronic device according to the present application will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below are merely a part of all embodiments of the present application and thus do not limit the present application in all aspects. Various embodiments that can be derived by those skilled in the art from the embodiments of the present application without creative work are within the scope of the present application.

[0032] Fig. 1 is a structural schematic diagram of a silicon carbide transistor according to an embodiment of the present application. In Fig. 1, the X direction is a first direction and the Y direction is a second direction. Referring to Fig. 1, the silicon carbide transistor includes a silicon carbide substrate layer 10 and an epitaxial layer 20 disposed on the silicon carbide substrate layer 10. The silicon carbide substrate layer 10 can be a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer. When the silicon carbide substrate layer 10 is a P-type substrate and the epitaxial layer 20 is an N-type epitaxial layer, the silicon carbide transistor according to the present application is a MOSFET power device. When the silicon carbide substrate layer 10 is an N-type substrate and the epitaxial layer 20 is an N-type epitaxial layer, the silicon carbide transistor according to the present application is an IGBT power device.

[0033] The silicon carbide substrate layer 10 includes a first surface 11 and a second surface 12 arranged oppositely along the thickness direction of the silicon carbide substrate layer 10, i.e., the second direction. The epitaxial layer 20 is arranged on the first surface 11 of the silicon carbide substrate layer 10, and the second surface 12 can be connected with a metal collector or a metal drain electrode D. The trench gate structure is arranged in the epitaxial layer 20, and the trench gate structure is arranged on the side of the epitaxial layer 20 away from the silicon carbide substrate layer 10. The two sides of the trench gate structure are provided with shielding structures, and the shielding structures include a first shielding area 50 and a second shielding area 60. The first shielding area 50 extends to the side of the first surface 11 of the silicon carbide substrate layer 10, and the side of the first shielding area 50 facing the first surface 11 of the silicon carbide substrate layer 10 is provided with the second shielding area 60. Along the first direction X, there is a gap d1 between two adjacent second shielding areas 60. The length h1 of the first shielding area 50 is less than the length h2 of the second shielding area 60. In the projection of the epitaxial layer 20, the second shielding area 60 covers the first shielding area 50 entirely. Along the second direction Y, the depth of the trench gate structure is less than the depth of the shielding structure. Specifically, the first direction X can also be the arrangement direction of the first shielding area 50, and the second direction Y can be the direction perpendicular to the first surface 11 and the second surface 12 of the silicon carbide substrate layer 10, and the first direction X and the second direction Y can be perpendicular to each other. The gap d between the first shielding areas 50 determines the width of the conduction current channel and thus affects the conduction resistance. The length of the first shielding area 50 relative to the length of the second shielding area 60 is small, which can ensure that the conduction resistance of the silicon carbide device is small. The width h2 of the second shielding area 60 determines the shielding degree of the strong electric field stress and thus affects the protection effect of the trench gate structure. The distance between the two adjacent second shielding areas 60 is small, which can improve the shielding ability of the second shielding area 60 and reduce the risk that the gate oxide layer at the bottom of the trench gate structure is easily broken down. In addition, the use of two first shielding areas 50 and two second shielding areas 60 at the same time can ensure that a wider conduction current channel (i.e., the gap d between the two adjacent first shielding areas 50) and a better strong electric field stress shielding effect appear in one silicon carbide device at the same time, so that the silicon carbide device is more compact.

[0034] More specifically, along the first direction, the difference between the length h1 of the first shielding area 50 and the length h2 of the second shielding area 60 is 10 nanometers to 5 micrometers, i.e., the difference between h2-h1 is between 10 nanometers and 5 micrometers. That is, it can ensure the low conduction resistance between the two first shielding areas 50, and also ensure the length of the second shielding area 60, and ensure the shielding effect of the first shielding area 50 and the second shielding area 60. If the difference between h2-h1 is not between 10 nanometers and 5 micrometers, it can only achieve the effect of low conduction resistance or protecting the gate oxide layer at the bottom of the trench gate structure, so that the low conduction resistance and the protection of the gate oxide layer of the silicon carbide device conflict with each other, and both cannot be achieved in the same silicon carbide device.

[0035] The first shielding region 50 and the second shielding region 60 are of the same doping type, and the doping type of the first shielding region 50 and the second shielding region 60 is opposite to the doping type of the epitaxial layer 20, that is, the doping type of the shielding structure is opposite to the doping type of the epitaxial layer 20, and the first shielding region 50 and the second shielding region 60 are P-type doped regions. The doping concentration of the first shielding region 50 and the second shielding region 60 is between 10 times and 1,000,000 times of the doping concentration of the epitaxial layer 20. Among them, the concentration of the first shielding region 50 and the second shielding region 60 determines the shielding effect of the strong electric field stress, the greater the concentration difference, the better the shielding effect, the smaller the gate oxide layer in the trench gate structure bears the electric field stress, and the better the reliability performance. If the doping concentration difference of the first shielding region 50 and the second shielding region 60 is not within the range of 10 times to 1,000,000 times, the effect of the first shielding region 50 and the second shielding region 60 cannot be effectively played, and thus the electric field stress borne by the gate oxide layer in the trench gate structure cannot be effectively reduced.

[0036] Continuing to refer to FIG. 1, along the second direction Y, the depth of the shielding structure is L, and along the first direction X, the gap between two adjacent first shielding regions is d, and L / d is between 0.5 and 20. Among them, the better the shielding effect of the strong electric field stress borne by the gate oxide layer in the trench gate structure is when L / d is between 0.5 and 20. If L / d is less than 0.5, the shielding effect cannot be achieved, and if L / d is greater than 20, the on-resistance of the silicon carbide device will be greatly increased.

[0037] Continuing to refer to FIG. 1, along the first direction X, a current conduction region 21 is formed between two adjacent first shielding regions 50 and two adjacent second shielding regions 60, that is, a current conduction region 21 is formed between two adjacent shielding structures, and the setting of the current conduction region 21 can reduce the resistance of the conduction between the shielding structures. A first doped region 22 and a second doped region 23 are arranged between the trench gate structure and the first shielding region 50, and the first doped region 22 and the second doped region 23 are sequentially stacked on the side of the current conduction region 21 away from the silicon carbide substrate layer 10, wherein: the doping types of the first doped region 22 and the second doped region 23 are opposite, and the doping type of the first doped region 22 is the same as that of the second shielding region 60, wherein the second shielding region 60 is a P-type doped region, and then the first doped region 22 is a P-type doped region, and the second doped region 23 is an N-type doped region, so as to ensure stable operation of the silicon carbide device.

[0038] In the above embodiment, the trench gate structure includes a polysilicon gate trench 30 and a gate dielectric 40, the polysilicon gate trench 30 includes a bottom wall 31 and a sidewall 32, the thickness of the gate dielectric disposed on the bottom wall 31 of the polysilicon gate trench 30 is Tb, the thickness of the gate dielectric disposed on the sidewall 32 of the polysilicon gate trench 30 is Ts, and Tb≥Ts. The thickness of the gate dielectric disposed on the bottom wall 31 is greater than the thickness of the gate dielectric disposed on the sidewall 32 of the polysilicon gate trench 30, which can increase the stress bearing capacity of the trench gate structure, and further improve the stress bearing capacity of the silicon carbide device. More specifically, Tb / Ts is equal to 1 to 3, that is, the thickness of the gate dielectric on the bottom wall 31 is 1 to 3 times the thickness of the gate dielectric on the sidewall 32. If Tb / Ts is less than 1, the stress bearing capacity of the trench gate structure is less increased, and the stress bearing capacity of the silicon carbide device is also less improved. If Tb / Ts is greater than 3, the thickness of the gate dielectric on the bottom wall is too thick, which affects the space inside the polysilicon gate trench 30. The sidewall of the polysilicon gate trench 30 is aligned with any crystal plane in the {1-100} crystal plane family or the {11-20} crystal plane family. In addition, the arrangement of the polysilicon gate on the sidewall of the polysilicon gate trench 30 is any one of strip arrangement, square arrangement, pin arrangement, hexagonal arrangement, or atomic lattice arrangement. The polysilicon gate trench 30 is connected to the gate electrode G through metal contact.

[0039] In an embodiment, along the second direction Y, the depth of the polysilicon gate trench 30 is h3, and the depth of the first doped region 22 is h4, h3 is greater than h4, to ensure normal operation of the device.

[0040] Referring back to FIG. 1, the silicon carbide device further includes a cover dielectric layer 70 disposed on the side of the epitaxial layer 20 away from the silicon carbide substrate layer 10, and the cover dielectric layer 70 covers the polysilicon gate trench structure. It can be understood that, along the first direction X, the length of the cover dielectric layer 70 is greater than the length of the polysilicon gate trench structure. More specifically, the projection of the cover dielectric layer 70 on the silicon carbide substrate layer 10 covers the entire polysilicon gate trench structure, and covers part of the two second doped regions 23, and the cover dielectric layer 70 separates the two second doped regions 23, so that the source S is separated by the cover dielectric layer 70 after being connected to the two second doped regions.

[0041] FIG. 2 is a flowchart of a method for manufacturing a silicon carbide device according to an embodiment of the present application;

[0042] FIGS. 3a to 3i are flowcharts of a method for manufacturing a silicon carbide device according to an embodiment of the present application. The method for manufacturing a silicon carbide device according to an embodiment of the present application includes the following steps, which are described with reference to FIGS. 2 and 3a to 3i.

[0043] S10: Forming an epitaxial layer 20 on the silicon carbide substrate layer 10. Wherein, the silicon carbide substrate layer 10 is a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer 20.

[0044] In step S10, the epitaxial layer 20 can be obtained by a CVD (chemical vapor deposition) process using methane or propane as a material growth gas and hydrogen as a carrier gas. Of course, the epitaxial layer 20 can also be obtained by other methods known to those skilled in the art, which are not limited herein.

[0045] S20: Forming two second shielding regions 60 of the shielding structure in the epitaxial layer 20, which are spaced apart along a first direction.

[0046] In step S20, a dielectric layer or polysilicon can be used as a hard mask, and an ion implantation process is used to implant a semiconductor impurity of a conductive type opposite to the silicon carbide substrate in the epitaxial layer 20 to form the second shielding region 60.

[0047] S30: Forming a first shielding region 50 of the shielding structure on the side of the second shielding region 60 away from the silicon carbide substrate layer 10, along the first direction, the length of the first shielding region 50 is less than the length of the second shielding region 60, and the gap between the two first shielding regions 50 is greater than the gap between the two second shielding regions 60. In the projection of the epitaxial layer 20, the second shielding region 60 covers the first shielding region 50 entirely.

[0048] In step S30, a self-aligned process is used to deposit a covering film on both sides of the ion implantation window, and then the bottom film is removed by etching to achieve the purpose of reducing the implantation window. The same doping as the first shielding region 50 is implanted through the hard mask, and two first shielding regions 50 are formed, which are symmetrically arranged.

[0049] Wherein, the hard mask is a dielectric layer or polysilicon.

[0050] S40: Forming a current conduction region 21 between the first shielding region 50 and the second shielding region 60.

[0051] In step S40, a photoetching and ion implantation process is used to form a current conduction region 21 between the two first shielding regions 50 and the two second shielding regions 60, i.e. to form a current conduction region 21 between the two shielding structures, and a first doped region 22 and a second doped region 23 on the side of the current conduction region 21 away from the silicon carbide substrate layer 10. The impurities in each region are activated by high-temperature annealing.

[0052] S50: Forming a trench gate structure between the two first shielding regions 50, along a second direction, the depth of the trench gate structure is less than the depth of the shielding structure.

[0053] In step S50, a polysilicon gate trench 30 is etched in the center between the two first shielding regions 50 by using a medium layer or polysilicon as a hard mask in combination with an etching process. The polysilicon gate trench 30 obtained by etching has a depth greater than that of the first doped region 22 and less than that of the shielding structure. The bottom wall 31 of the polysilicon gate trench 30 is deeper than the bottom of the first doped region 22, and the depth difference therebetween is between 10 nanometers and 5 micrometers, so as to ensure normal operation of the power device.

[0054] After step S50, a high-temperature annealing process is further performed in a non-oxidized and non-nitrided atmosphere to round the sharp corners on the bottom wall 31 of the polysilicon gate trench 30. After deep etching of the polysilicon gate trench 30, sharp corners will appear on the bottom and top thereof. If the corners are too sharp, the subsequent gate dielectric 40 will have a poor coverage effect, and an electric field will easily gather around the sharp corners, causing the silicon carbide device to break down prematurely and the reliability of the silicon carbide device to deteriorate. Therefore, the operation of rounding the sharp corners is needed.

[0055] The gate dielectric 40 material is produced on the bottom wall 31 of the polysilicon gate trench 30 by using a thermal oxidation or deposition and etching process, and the excess gate dielectric 40 material is etched away to obtain the gate dielectric 40. The thickness of the gate dielectric 40 arranged on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric 40 arranged on the sidewall 32 of the polysilicon gate trench 30 is Ts, Tb≥Ts and the range of Tb / Ts is between 1 and 3. If Tb / Ts is not within the range of 1 to 3, the reliability of the gate dielectric 40 will deteriorate, and the process difficulty will increase.

[0056] S60: A polysilicon gate is arranged in the polysilicon gate trench 30, and a covering dielectric layer 70 is formed on the surface of the epitaxial layer 20. The polysilicon layer covers the polysilicon gate trench 30, and the covering dielectric layer 70 covers the epitaxial layer 20 and the covering dielectric layer 70.

[0057] In step S60, a deposition and etching process is used to deposit a layer of polysilicon on the surface of the epitaxial layer 20, etch away the excess polysilicon material, deposit a layer of covering dielectric layer 70, and then selectively etch away part of the covering dielectric layer 70 above the second doped layer to form a polysilicon gate surrounded by a gate dielectric layer in the polysilicon gate trench 30. The relationship between the width Di of the covering dielectric layer 70 above the polysilicon gate trench 30 and the width Dg of the polysilicon gate trench 30 is Di>Dg.

[0058] S70: a metal layer is deposited on the surface of the epitaxial layer 20 by deposition and etching process, and after etching, the source electrode is formed on the surface of the first shielding region 50 and the second doped region 23; the gate electrode is formed on the polysilicon gate; after thinning the side of the silicon carbide substrate layer 10 away from the epitaxial layer 20, the drain electrode is formed by depositing a layer of metal, and finally the silicon carbide device is obtained.

[0059] FIG. 4 is another flow chart of a method for manufacturing a silicon carbide device according to an embodiment of the present application; and FIGS. 5a-5i are flow charts of a method for manufacturing a silicon carbide device according to an embodiment of the present application. Referring to FIGS. 4, 5a-5i, the method for manufacturing a silicon carbide device according to an embodiment of the present application includes: S100: forming an epitaxial layer 20 on a silicon carbide substrate layer 10. The silicon carbide substrate layer 10 is a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer 20.

[0060] In step S100, the epitaxial layer 20 can be obtained by a CVD (chemical vapor deposition) process using methane or propane as a material growth gas and hydrogen as a carrier gas. Of course, the epitaxial layer 20 can also be obtained by other methods known to those skilled in the art, which are not limited herein.

[0061] S200: forming a first doped region 22 in the epitaxial layer 20 by ion implantation. Compared with forming the first doped region 22 after forming the shielding structure, i.e., forming the first shielding region 50 and the second shielding region 60, this method can avoid the concentration deviation of the first doped region 22 caused by the ion implantation activation rate deviation, thereby avoiding the threshold voltage deviation of the device.

[0062] S300: forming two second shielding regions 60 of the shielding structure in the epitaxial layer 20, which are spaced apart along a first direction;

[0063] In step S300, a dielectric layer or polysilicon can be used as a hard mask, and a semiconductor impurity of a conductive type opposite to that of the silicon carbide substrate is implanted in the epitaxial layer 20 by ion implantation to form the second shielding region 60;

[0064] S400: forming a first shielding region 50 of the shielding structure on the side of the second shielding region 60 away from the silicon carbide substrate layer 10, the length of the first shielding region 50 is less than the length of the second shielding region 60 along the first direction, the gap between the two first shielding regions 50 is greater than the gap between the two second shielding regions 60, and the second shielding region 60 covers the first shielding region 50 in the projection of the epitaxial layer 20.

[0065] In step S400, a self-alignment process is adopted to deposit a covering film on both sides of the ion implantation window, and then the bottom film is removed by etching to achieve the purpose of reducing the implantation window. The same doping as the first shielding region 50 is implanted through the hard mask, and two first shielding regions 50 are formed, and the two first shielding regions 50 are symmetrically arranged.

[0066] The hard mask is a dielectric layer or polysilicon.

[0067] S500: Forming a current conduction region 21 between the first shielding region 50 and the second shielding region 60.

[0068] In step S500, a photolithography and ion implantation process is adopted to form a current conduction region 21 and a second doped region 23 in the region between the two first shielding regions 50 and the two second shielding regions 60, i.e. the region between the two shielding structures. The current conduction region 21 is located on the side of the first doped region 22 facing the silicon carbide substrate layer 10, and the second doped region 23 is located between the first doped region 22 away from the current conduction region 21. The impurities in each region are activated by high-temperature annealing.

[0069] S600: Forming a trench gate structure between the two shielding structures along the second direction, and the depth of the trench gate structure is less than the depth of the shielding structure.

[0070] In step S600, a dielectric layer or polysilicon is used as a hard mask, and a polysilicon gate trench 30 is etched in the center between the two first shielding regions 50 by combining with an etching process. The depth of the polysilicon gate trench 30 obtained by etching is greater than the depth of the first doped region 22, and the depth of the polysilicon gate trench 30 is less than the depth of the first shielding region 50. The bottom wall 31 of the polysilicon gate trench 30 is deeper than the bottom of the first doped region 22, and the depth difference between them is between 10 nanometers and 5 microns.

[0071] After step S600, step S601 is further included: adopting a high-temperature annealing process in a non-oxidizing and non-nitriding atmosphere to passivate and round the sharp corners on the bottom wall 31 of the polysilicon gate trench 30.

[0072] Step S602: Using a thermal oxidation or deposition and etching process to produce a gate dielectric 40 material on the bottom wall 31 of the polysilicon gate trench 30, and etching to remove excess gate dielectric 40 material to obtain the gate dielectric 40. The thickness of the gate dielectric 40 arranged on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric 40 arranged on the sidewall 32 of the polysilicon gate trench 30 is Ts, Tb≥Ts and Tb / Ts is equal to 1 to 3.

[0073] S700: Polysilicon gate is arranged in the polysilicon gate trench 30, and a covering dielectric layer 70 is formed on the surface of the epitaxial layer 20, the polysilicon layer covers the polysilicon gate trench 30, and the covering dielectric layer 70 covers the epitaxial layer 20 and the covering dielectric layer 70.

[0074] In step S700, a deposition and etching process is adopted to deposit a layer of polysilicon on the surface of the epitaxial layer 20, remove the excess polysilicon material by etching, then deposit a layer of covering dielectric layer 70, and then selectively etch the covering dielectric layer 70 on the second doped layer to form a polysilicon gate surrounded by a gate dielectric layer in the polysilicon gate trench 30; the relationship between the width Di of the covering dielectric layer 70 above the polysilicon gate trench 30 gate and the width Dg of the polysilicon gate trench 30 is Di>Dg.

[0075] S800: A deposition and etching process is adopted to deposit a layer of metal on the surface of the epitaxial layer 20, and after etching, a source electrode is formed on the surface of the first shielding area 50 and the second doped area 23; a gate electrode is formed on the polysilicon gate part; after thinning the side of the silicon carbide substrate layer 10 away from the epitaxial layer 20, a drain electrode is formed by depositing a layer of metal, and finally a silicon carbide device is obtained.

[0076] FIG. 6 is another flow chart of a method for manufacturing a silicon carbide device according to an embodiment of the present application; and FIGS. 7a-7i are flow charts of a method for manufacturing a silicon carbide device according to an embodiment of the present application. Referring to FIGS. 6, 7a-7i, a method for manufacturing a silicon carbide device according to an embodiment of the present application includes the following steps:

[0077] S1: An epitaxial layer 20 is formed on a silicon carbide substrate layer 10. The silicon carbide substrate layer 10 is a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer 20.

[0078] In step S1, the epitaxial layer 20 can be obtained by a CVD (chemical vapor deposition) process using methane or propane as a material growth gas and hydrogen as a carrier gas. Of course, the epitaxial layer 20 can also be obtained by other methods known to those skilled in the art, which are not limited herein.

[0079] S2: A current conduction area 21, a first doped area 22, and a second doped area 23 are sequentially formed in the epitaxial layer 20 by ion implantation. This method can avoid the concentration deviation of the first doped area 22 caused by the ion implantation activation rate deviation, thereby avoiding the threshold voltage deviation of the device. At the same time, the second doped area 23 can be removed together by etching the first shielding area 50, thereby saving a photolithography process and further simplifying the process flow. In addition, the impurities in each area are activated by high-temperature annealing in this step.

[0080] S3: Forming two second shielding regions 60 of shielding structures in the epitaxial layer 20, which are spaced apart along the first direction;

[0081] In step S3, a medium layer or polysilicon can be used as a hard mask, and an ion implantation process is used to implant semiconductor impurities of the opposite conductivity type to the silicon carbide substrate in the epitaxial layer 20 to form the second shielding regions 60.

[0082] S4: Forming first shielding regions 50 of shielding structures on the side of the second shielding regions 60 away from the silicon carbide substrate layer 10, the length of the first shielding regions 50 is less than the length of the second shielding regions 60 along the first direction, and the gap between the two first shielding regions 50 is greater than the gap between the two second shielding regions 60, and in the projection of the epitaxial layer 20, the second shielding regions 60 completely cover the first shielding regions 50.

[0083] In step S4, a self-aligned process is used to deposit a covering film on both sides of the ion implantation window, and then the bottom film is removed by etching to achieve the purpose of narrowing the implantation window. The same doping as the first shielding regions 50 is implanted through the hard mask, and two first shielding regions 50 are formed, and the two first shielding regions 50 are symmetrically arranged.

[0084] The hard mask is a medium layer or polysilicon. The difference between the length of the first shielding region 50 and the length of the second shielding region 60 is 10 nanometers to 5 microns.

[0085] S5: Forming a trench gate structure between the two shielding structures, the depth of the trench gate structure is less than the depth of the shielding structure along the second direction.

[0086] In step S5, a medium layer or polysilicon is used as a hard mask, and a polysilicon gate trench 30 is etched in the center between the two first shielding regions 50 by combining an etching process. The depth of the polysilicon gate trench 30 obtained by etching is greater than the depth of the first doped region 22, and the depth of the polysilicon gate trench 30 is less than the depth of the first shielding region 50. The bottom wall 31 of the polysilicon gate trench 30 is deeper than the bottom of the first doped region 22, and the depth difference between them is between 10 nanometers and 5 microns.

[0087] After step S5, it further includes: using a high-temperature annealing process in a non-oxidizing and non-nitriding atmosphere to passivate the sharp corners on the bottom wall 31 of the polysilicon gate trench 30 to round them.

[0088] The gate dielectric 40 is produced by using thermal oxidation or deposition and etching process to produce gate dielectric 40 material on the bottom wall 31 of the polysilicon gate trench 30, and etching to remove the excess gate dielectric 40 material. The thickness of the gate dielectric 40 on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric 40 on the sidewall 32 of the polysilicon gate trench 30 is Ts, Tb≥Ts and Tb / Ts equals to 1 to 3.

[0089] S6: The polysilicon gate is arranged inside the polysilicon gate trench 30, and the covering dielectric layer 70 is formed on the surface of the epitaxial layer 20, the polysilicon layer covers the polysilicon gate trench 30, and the covering dielectric layer 70 covers the epitaxial layer 20 and the covering dielectric layer 70.

[0090] In step S6, a layer of polysilicon is deposited on the surface of the epitaxial layer 20 by using deposition and etching process, and the excess polysilicon material is etched and removed, and then a layer of covering dielectric layer 70 is deposited, and then the covering dielectric layer 70 on part of the second doped layer is selectively etched and removed, to form a polysilicon gate surrounded by a gate dielectric layer in the polysilicon gate trench 30; the relationship between the width Di of the covering dielectric layer 70 above the polysilicon gate trench 30 gate and the width Dg of the polysilicon gate trench 30 is Di>Dg.

[0091] S7: A layer of metal is deposited on the surface of the epitaxial layer 20 by using deposition and etching process, and the source electrode is formed on the surface of the first shielding area 50 and the second doped area 23 after etching; the gate electrode is formed on the polysilicon gate part; after thinning the side of the silicon carbide substrate layer 10 away from the epitaxial layer 20, the drain electrode is formed by depositing a layer of metal, and finally the silicon carbide device is obtained.

[0092] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A silicon carbide device, characterized by, Comprising: a silicon carbide substrate layer; an epitaxial layer disposed on a first surface of the silicon carbide substrate layer; a trench gate structure disposed on a side of the epitaxial layer away from the first surface of the silicon carbide substrate layer, both sides of the trench gate structure are provided with shielding structures, the shielding structure includes a first shielding area and a second shielding area, the first shielding area extends to the side of the first surface of the silicon carbide substrate layer, the first shielding area is provided with the second shielding area on the side of the first surface of the silicon carbide substrate layer, along the first direction, there is a gap between adjacent two second shielding areas, the gap between adjacent two second shielding areas is smaller than the gap between adjacent two first shielding areas; along the first direction, the length of the first shielding area is smaller than the length of the second shielding area, and in the projection of the epitaxial layer, the second shielding area covers the first shielding area entirely, along the second direction, the depth of the trench gate structure is smaller than the depth of the shielding structure.

2. The silicon carbide device of Claim 1 wherein, Along the first direction, the difference between the length of the first shielding area and the length of the second shielding area is 10 nanometers to 5 microns.

3. The silicon carbide device of Claim 1 wherein, The doping type of the first shielding area and the second shielding area is opposite to that of the epitaxial layer, and the doping concentration of the first shielding area and the second shielding area is between 10 times and 1,000,000 times of the doping concentration of the epitaxial layer.

4. The silicon carbide device of Claim 1 wherein, Along the second direction, the depth of the shielding structure is L, along the first direction, the gap between adjacent two first shielding areas is d, and L / d is between 0.5 and 20.

5. The silicon carbide device of any one of claims 1 to 4, wherein, Along the first direction, a current conduction area is formed between adjacent two shielding structures, and a first doped area and a second doped area are disposed between the trench gate structure and the first shielding area, the first doped area and the second doped area are stacked on the side of the current conduction area away from the silicon carbide substrate layer in sequence, wherein: the doping type of the first doped area and the second doped area is opposite, and the doping type of the first doped area is the same as that of the shielding structure.

6. The silicon carbide device of Claim 5 wherein, The trench gate structure includes a polysilicon gate trench and a gate dielectric, the polysilicon gate trench includes a bottom wall and a side wall, the thickness of the gate dielectric disposed on the bottom wall of the polysilicon gate trench is Tb, the thickness of the gate dielectric disposed on the side wall of the polysilicon gate trench is Ts, Tb≥Ts, and the ratio of Tb / Ts is between 1 and 3.

7. The silicon carbide device of Claim 6 wherein, Along the second direction, the depth of the polysilicon gate trench is greater than the depth of the first doped area.

8. The silicon carbide device of Claim 6 wherein, The silicon carbide device further includes a covering dielectric layer disposed on the side of the epitaxial layer away from the silicon carbide substrate layer, and the covering dielectric layer covers the polysilicon gate trench.

9. A method for fabricating a silicon carbide device, comprising: Comprising: forming an epitaxial layer on a silicon carbide substrate layer; forming two second shielding areas of shielding structures spaced apart along a first direction in the epitaxial layer; The first shielding region of the shielding structure is formed on the side of the second shielding region away from the silicon carbide substrate layer, and the length of the first shielding region is less than the length of the second shielding region in the first direction, and the gap between the two first shielding regions is greater than the gap between the two second shielding regions, and the second shielding region covers the first shielding region completely in the projection of the epitaxial layer. The trench gate structure is formed between the two first shielding regions, and the depth of the trench gate structure is less than the depth of the shielding structure in the second direction.

10. An electronic device, characterized by The silicon carbide device comprises the silicon carbide device as claimed in any one of claims 1 to 8.

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