Hardware parameter adjustment method and apparatus, and computing device and storage medium

Abstract

The present application belongs to the technical field of computers. Provided are a hardware parameter adjustment method and apparatus, and a computing device and a storage medium. In the hardware parameter adjustment method provided in the present application, an instruction distribution feature corresponding to an instruction sequence is acquired, wherein the instruction distribution feature is related to a consumed time duration for executing instructions, and the consumed time duration is also related to parameters of hardware. Thus, on the basis of the instruction distribution feature corresponding to the instruction sequence, and a plurality of hardware parameter sets, the consumed time duration for executing the instruction sequence under each hardware parameter set can be acquired, and on the basis of the consumed time duration, a target hardware parameter set is determined from among the plurality of hardware parameter sets. In the present method, a target hardware parameter set is determined on the basis of an instruction distribution feature of an instruction sequence, and the instruction distribution feature is applicable to different architectures. In addition, in the present method, a consumed time duration is calculated on the basis of an instruction distribution feature, without the need to simulate the operation of an instruction sequence, thereby achieving short time consumption and high efficiency of hardware parameter adjustment.

Description

Hardware parameter adjustment methods, devices, computing equipment, and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411182798.6, filed on August 26, 2024, entitled "Hardware Parameter Adjustment Method, Apparatus, Computing Device and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to a hardware parameter adjustment method, apparatus, computing device, and storage medium. Background Technology

[0003] With the development of computer technology, more and more computing-related business scenarios have emerged, such as big data scenarios, database scenarios, distributed storage scenarios, and virtualization scenarios. Different business scenarios have different computational loads, memory access frequency, and data volumes. The computing performance of hardware in these business scenarios can be optimized by adjusting hardware parameters (such as CPU frequency, number of CPU cores, cache size, and memory size).

[0004] Current methods for adjusting computer hardware parameters involve running a test instruction sequence for a specific business scenario using a simulator developed for that architecture under different sets of hardware parameters. The time taken for the simulator to run the test instruction sequence under each set of hardware parameters is recorded. Based on the set of hardware parameters with the shortest execution time, the hardware is adjusted accordingly.

[0005] In the above method, an architecture is first preset, and then a simulator is developed specifically for the characteristics of this preset architecture. Therefore, the simulator and the preset architecture are strongly coupled. It is difficult for a single simulator to be applied to multiple different architectures, and the simulator takes a long time to run the above instruction sequence, resulting in low efficiency in adjusting hardware parameters. Summary of the Invention

[0006] This application provides a hardware parameter adjustment method, apparatus, computing device, and storage medium, which can improve the efficiency of hardware parameter adjustment. The technical solution is as follows.

[0007] Firstly, a hardware parameter adjustment method is provided, comprising: for an instruction sequence corresponding to a computing service, obtaining instruction distribution characteristics corresponding to the instruction sequence, wherein the instruction distribution characteristics indicate the distribution of instruction types; based on the instruction distribution characteristics and multiple hardware parameter sets, obtaining the execution time of the instruction sequence under each hardware parameter set, wherein each hardware parameter set includes the parameter value of at least one parameter of the hardware; and determining a target hardware parameter set based on the execution time of the instruction sequence under each hardware parameter set.

[0008] The instruction sequence includes instructions belonging to different instruction types, such as ALU instructions, MSI instructions, DMI instructions, MDPI instructions, LD instructions, ST instructions, FPDPI instructions, FPMI instructions, and B instructions. Instruction types include computational and non-computational types. Computational types include addition, subtraction, multiplication, and division for integers; addition, subtraction, multiplication, and division for floating-point numbers; and logical operation types.

[0009] Non-computational types refer to instructions that do not involve computational functions. For example, non-computational types include cached types and branched types. Cached type instructions are used to store data obtained during the execution of an instruction sequence into a cache or external memory. Alternatively, cached type instructions are used to retrieve corresponding data from a cache or load corresponding data from external memory into a cache and then retrieve the data from the cache.

[0010] Branch-type instructions are used to control the execution of a portion of an instruction sequence. If the decision of a branch-type instruction is to execute it, the computing device executes the portion of the instructions corresponding to that branch-type instruction; if the decision is not to execute it, the computing device skips the portion of the instructions corresponding to that branch-type instruction.

[0011] Multiple hardware parameter sets are pre-set sets of hardware parameters. Each set of hardware parameters includes the parameter values ​​of preset parameters of the hardware. These preset parameters are parameters in the hardware parameters that are related to the execution time of the instruction sequence. The target set of hardware parameters can be the set of hardware parameters with the shortest execution time among the multiple sets of hardware parameters.

[0012] The computing device pre-builds a service operation enabling platform and a backend configuration environment corresponding to the computing service, enabling the computing device to execute the computing service. The service operation enabling platform provides computing service, while the backend configuration environment stores, processes, and maintains the data corresponding to the computing service.

[0013] The hardware parameter adjustment method provided in this application obtains the instruction distribution characteristics corresponding to the instruction sequence. These characteristics are related to the execution time of the instructions, which in turn is related to the hardware parameters. Therefore, based on the instruction distribution characteristics and multiple hardware parameter sets, the execution time of the instruction sequence under each hardware parameter set can be obtained. Then, based on this execution time, the target hardware parameter set is determined from the multiple hardware parameter sets. Since this method determines the target hardware parameter set based on the instruction distribution characteristics of the instruction sequence, and these characteristics are applicable to different architectures, and furthermore, this method calculates the execution time based on the instruction distribution characteristics without simulating the execution of the instruction sequence, resulting in shorter execution time and higher efficiency in hardware parameter adjustment.

[0014] Optionally, after determining the target hardware parameter set, the hardware parameters are adjusted according to the target hardware parameter set.

[0015] Optionally, the above-mentioned acquisition of instruction distribution features corresponding to the instruction sequence includes: acquiring instruction type distribution features corresponding to the instruction sequence based on the instruction types to which each instruction in the instruction sequence belongs. The instruction type distribution features indicate the distribution of instructions of different instruction types within the instruction sequence. In the instruction sequence, the execution time for instructions of different instruction types varies; therefore, the instruction type distribution features acquired in this process can reflect the execution time of the instruction sequence.

[0016] Optionally, the above-mentioned method of obtaining the execution time of the instruction sequence under each hardware parameter set based on instruction distribution characteristics and multiple hardware parameter sets includes: calculating the instruction type distribution characteristics and multiple hardware parameter sets to obtain the execution time of the instruction sequence under each hardware parameter set.

[0017] Optionally, the above-mentioned acquisition of instruction distribution features corresponding to the instruction sequence includes: acquiring cached instruction features corresponding to the instruction sequence based on the cached instructions included in the instruction sequence, wherein the cached instruction features indicate the quantity distribution and position distribution of cached instructions in the instruction sequence. The quantity distribution indicates the number of cached instructions in the instruction sequence, and the position distribution indicates the position of the cached instructions in the instruction sequence.

[0018] This cache instruction characteristic indicates the distribution of the number of cached instructions between two adjacent cached instructions accessing the same memory address. "Multiple memory addresses being the same memory address" means that these multiple memory addresses have the same starting address and offset length. The more cached instructions between two adjacent cached instructions accessing the same memory address, the more concentrated the cache instructions are, and the greater the probability of a cache layer being full. This also reduces the likelihood that data will be stored in the same cache layer when executing two adjacent cached instructions accessing the same memory address. Conversely, the fewer cached instructions between two adjacent cached instructions accessing the same memory address, the more dispersed the cache instructions are, and the less likely a cache layer will be full. Therefore, the cache instruction characteristic reflects the probability that a computing device will store data for the same memory address in the same cache layer.

[0019] If the computing device can store the data at the same memory access address obtained during the execution of the instruction sequence into the same cache layer, then during the execution of the later cache instruction among two cache instructions, the computing device does not need to spend additional time storing the data into the next level cache layer; if the computing device fails to store the data at the same memory access address obtained during the execution of the instruction sequence into the same cache layer, then during the execution of the later cache instruction among two cache instructions, the computing device will have to spend additional time storing the data into the next level cache layer.

[0020] When cached instructions are used to retrieve corresponding data from the cache or load corresponding data from external memory into the cache and then retrieve that data, for reasons similar to those described above, the more cached instructions there are between two adjacent cached instructions accessing the same memory address, the lower the probability that these two adjacent cached instructions will find their corresponding data in the same cache layer. Conversely, the fewer cached instructions there are between two adjacent cached instructions accessing the same memory address, the higher the probability that these two adjacent cached instructions will find their corresponding data in the same cache layer. Therefore, this cached instruction characteristic can also reflect the probability that the computing device finds the corresponding data for two adjacent cached instructions accessing the same memory address in the same cache layer.

[0021] If the computing device finds the corresponding data for two adjacent cache instructions targeting the same memory address within the same cache layer, then during the execution of the latter cache instruction, the computing device does not need to spend additional time retrieving the corresponding data from the next level cache layer. If the computing device fails to find the corresponding data for two adjacent cache instructions targeting the same memory address within the same cache layer, then during the execution of the latter cache instruction, the computing device will need to spend additional time retrieving the corresponding data from the next level cache layer.

[0022] In summary, this cache instruction characteristic can reflect the time consumption caused by the cache instruction.

[0023] Optionally, the above-mentioned acquisition of instruction distribution features corresponding to the instruction sequence includes: acquiring branch instruction features corresponding to the instruction sequence based on the branch instructions included in the instruction sequence, wherein the branch instruction features indicate the distribution of the number of branch instructions in the instruction sequence. During the execution of the instruction sequence, the computing device performs branch prediction on the branch instructions, and executes the instructions on the branch path indicated by the branch prediction result in advance according to the branch prediction result, so as to improve the execution efficiency of the instruction sequence. Since the branch prediction result of a branch instruction is incorrect, the computing device will discard the result obtained by executing the instruction on that branch path and instead execute the instruction on another branch path. Furthermore, the above-mentioned branch instruction features are calculated based on the probability that the branch prediction result of each branch instruction in the instruction sequence is to be executed. Therefore, the branch instruction features can reflect the probability that the branch prediction result of a branch instruction is to be executed. Thus, through the above-mentioned branch instruction features, the time consumption caused by the branch prediction error of a branch instruction can be obtained.

[0024] Optionally, the aforementioned branch instruction characteristics also indicate the positional distribution of branch instructions in the instruction sequence. The more dispersed the positional distribution of branch instructions in the instruction sequence, the more instructions might be executed prematurely if the branch prediction result is "execute." Conversely, the more concentrated the positional distribution of branch instructions in the instruction sequence, the fewer instructions might be executed prematurely if the branch prediction result is "execute." Therefore, this positional distribution can reflect the number of instructions executed prematurely if the branch prediction result is "execute," and can reflect the time consumption caused by branch prediction errors.

[0025] Optionally, the above-mentioned method of obtaining the execution time of the instruction sequence under each hardware parameter set based on instruction distribution characteristics and multiple hardware parameter sets includes: processing the instruction distribution characteristics based on a neural network to obtain the corresponding loss rate; obtaining the execution time of the instruction sequence under each hardware parameter set based on the loss rate and multiple hardware parameter sets; the loss rate indicates the probability of time consumption based on instruction distribution characteristics; wherein, the neural network is trained based on historical instruction sequences and corresponding historical running information, and can output the loss rate corresponding to the input instruction distribution characteristics according to the input instruction distribution characteristics.

[0026] Optionally, the aforementioned sets of multiple hardware parameters may include the hardware parameters of computing nodes in a distributed system, or the sets of multiple hardware parameters may include the hardware parameters of hardware in an electronic device, or the sets of multiple hardware parameters may include the hardware parameters of servers in a cloud service system.

[0027] Secondly, a hardware parameter adjustment device is provided for executing the aforementioned hardware parameter adjustment method. Specifically, the hardware parameter adjustment device includes a functional module for executing the hardware parameter adjustment method provided in the first aspect or any optional embodiment of the first aspect.

[0028] Thirdly, a computing device or cluster of computing devices is provided, the computing device including a processor for executing program code, causing the computing device or cluster of computing devices to perform operations as described in the hardware parameter adjustment method above.

[0029] Fourthly, a computer program product containing instructions is provided, which, when executed by a computing device, causes the computing device to perform the hardware parameter adjustment method provided in the first aspect or any alternative method of the first aspect.

[0030] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0031] Figure 1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of the structure of a computing device cluster provided in an embodiment of the present invention;

[0033] Figure 3 is a flowchart of a hardware parameter adjustment method provided in an embodiment of the present invention;

[0034] Figure 4 is a schematic diagram of a reuse distance provided by an embodiment of the present invention;

[0035] Figure 5 is a histogram of reuse distance distribution provided by an embodiment of the present invention;

[0036] Figure 6 is a schematic diagram of a stack distance provided by an embodiment of the present invention;

[0037] Figure 7 is a schematic diagram of another stack distance provided by an embodiment of the present invention;

[0038] Figure 8 is a stack distance distribution histogram provided by an embodiment of the present invention;

[0039] Figure 9 is a schematic diagram of a hardware parameter adjustment device provided in an embodiment of the present invention. Detailed Implementation

[0040] The embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.

[0041] Figure 1 is a schematic diagram of a computing device provided in an embodiment of the present invention. It should be understood that the computing device described below can implement any function of any of the methods described below. Typically, the computing device 100 includes a processor 101 and a memory 102.

[0042] Processor 101 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 101 may be implemented using at least one hardware form selected from digital signal processing (DSP), field-programmable gate array (FPG A), and programmable logic array (PLA). Processor 101 may also include a main processor and a coprocessor. The main processor, also known as the central processing unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 101 may integrate a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 101 may also include an artificial intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0043] The memory 102 may include one or more computer-readable storage media, which may be non-transitory. For example, the memory 102 may be a high-speed random access memory or a non-volatile memory, or it may be one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 102 are used to store at least one program segment, which is executed by the processor 101 to implement the hardware parameter adjustment method provided in the method embodiments of this application.

[0044] In some embodiments, the computing device 100 may also optionally include a peripheral device interface 103 and at least one peripheral device. The processor 101, memory 102, and peripheral device interface 103 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 103 via a bus, signal line, or circuit board.

[0045] In this embodiment of the invention, the computing device 100 can be configured as a terminal or a server, and the terminal or server acts as the execution subject to implement the technical solutions provided in this embodiment of the invention.

[0046] In some embodiments, the computing device 100 may be a portable mobile terminal such as a smartphone, tablet, or laptop, or a desktop terminal such as a desktop computer. The computing device 100 may also be referred to by other names such as a laptop terminal, and the embodiments of the present invention do not limit this.

[0047] In some embodiments, computing devices 100 can be independent physical servers, and multiple computing devices 100 can be implemented as a computing device cluster as shown in Figure 2, that is, a server cluster composed of multiple physical servers. This computing device cluster can apply a distributed file system to store and manage data. Computing devices 100 can also be cloud servers providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Taking a computing device as a cloud server as an example, a computing device can also be called a cloud platform (short for cloud computing platform), which refers to services based on hardware and software resources that provide computing, network, and storage capabilities. Through the network "cloud," massive amounts of data are processed and analyzed remotely and then returned to the user, featuring large-scale, distributed, virtualized, highly available, scalable, on-demand service, and security characteristics. Cloud platforms can achieve rapid deployment and release of configurable computing resources with relatively low management costs or low interaction complexity between users and service providers.

[0048] The computing device 100 shown in Figure 1 above is used to execute the hardware parameter adjustment method provided in this embodiment of the invention. This method is applied to the execution process of a computing task to adjust the parameters of the hardware used to execute the task. After the computing device 100 obtains the instruction sequence (trace stream) corresponding to the computing task, it analyzes the instruction sequence to obtain the instruction distribution characteristics. Since the instruction distribution characteristics and hardware parameters are related to the execution time of the instruction sequence, the computing device 100 can obtain the execution time of the instruction sequence under each hardware parameter set based on the instruction distribution characteristics and multiple hardware parameter sets. It then adjusts the hardware parameters of the computing device 100 to the parameters corresponding to the set with the shortest execution time. Using the adjusted computing device 100 to execute the instruction sequence minimizes the execution time and improves the execution efficiency of the instruction sequence.

[0049] The above process is illustrated by taking the example of the computing device 100 adjusting the parameters of its own hardware. For example, the computing device 100 adjusts parameters such as the number of CPU processing cores, CPU frequency, and CPU cache size used to execute the above computing task.

[0050] In some embodiments, the computing device 100, according to the hardware parameter adjustment method provided in this embodiment of the invention, adjusts the hardware of other computing devices. Specifically, the computing device 100 receives a sequence of instructions to be executed from other computing devices, calculates the set of hardware parameters with the shortest execution time, and sends this set of hardware parameters to the other computing devices. The other computing devices adjust the parameters of their own hardware according to this set of hardware parameters, and then execute the instruction sequence. Alternatively, the computing device 100 remotely adjusts the hardware parameters of other computing devices according to the set of hardware parameters with the shortest execution time. Upon completion of the hardware parameter adjustment, the other computing devices begin executing the instruction sequence.

[0051] In other embodiments, the instruction sequence to be executed is executed by a computing cluster such as a distributed system or a cloud service system. The computing device 100 calculates the set of hardware parameters that minimizes the execution time of the instruction sequence based on the instruction sequence to be executed, and then calls one or more computing devices in the computing cluster that match the set of hardware parameters to execute the instruction sequence.

[0052] Figure 3 is a flowchart of a hardware parameter adjustment method provided by an embodiment of the present invention, which is executed by the computing device shown in Figure 1. It should be noted that this embodiment of the present invention uses instruction distribution characteristics, including instruction type distribution characteristics, cached instruction characteristics, and branch instruction characteristics, as an example for illustration. After obtaining these three characteristics, the computing device obtains the duration corresponding to each of the three characteristics and the hardware parameter set, and then obtains the execution time of the instruction sequence under the hardware parameter set based on the durations corresponding to these three characteristics. In other embodiments, the instruction distribution characteristics may include any one or two of the instruction type distribution characteristics, cached instruction characteristics, and branch instruction characteristics. Accordingly, the computing device only needs to execute the process of obtaining one or two of these characteristics and the process of obtaining the execution time corresponding to the instruction sequence based on these characteristics. This embodiment of the present invention does not limit this.

[0053] As shown in Figure 3, the method includes the following steps:

[0054] 301. The computing device obtains the instruction sequence corresponding to the code segment corresponding to the computing task to be executed.

[0055] In this context, the computational task to be executed corresponds to a code segment, which in turn corresponds to a sequence of instructions. An instruction sequence includes multiple instructions used to execute and implement the aforementioned computational task. The computational task can be any task within a business scenario. For example, it could be performing calculations on large amounts of data using a specific algorithm in a big data scenario; it could be performing operations such as adding, deleting, modifying, and querying data in a database scenario; it could be processing data in any one or more storage nodes in a distributed storage scenario; or it could be calling virtual computing resources to process data in virtual storage devices in a virtualization scenario.

[0056] In some embodiments, the computing device provides a compilation window to the user, through which it obtains the code segment corresponding to the computational task to be executed, input by the user, or obtains the code segment corresponding to the computational task to be executed from a file specified by the user. The computing device executes the code segment. During the execution of the code segment, the computing device compiles the code segment to obtain the compilation result, which is used as the instruction sequence corresponding to the code segment. It should be noted that the execution process of the computational task can be divided into two parts. In the first part, the computing device executes the code segment corresponding to the computational task to obtain the instruction sequence corresponding to the code segment. In the second part, the computing device executes the instruction sequence corresponding to the code segment to implement the computational task. In the above embodiments, the computing device only needs to execute the code segment corresponding to the computational task to obtain the instruction sequence corresponding to the code segment, without needing to execute the instruction sequence corresponding to the code segment itself, and therefore does not involve processes such as running or simulating the execution of the instruction sequence.

[0057] In some embodiments, the computing device executes the code segment, obtains a log file corresponding to the execution process of the code segment, analyzes the log file, extracts the instructions corresponding to the code segment from the log file, and arranges the extracted instructions into an instruction sequence according to the execution order of the instructions. The process of extracting instructions from the log file includes: the computing device matching a pre-prepared first string or first regular expression with multiple records in the log file one by one, and extracting the records in the log file that successfully match the first string or first regular expression as the instructions corresponding to the code segment. The pre-prepared first string is obtained by summarizing the records corresponding to instructions in the historical log files and is a string within the records corresponding to the instructions. The pre-prepared first regular expression is also obtained by summarizing the records corresponding to instructions in the historical log files and indicates the record format of the records corresponding to the instructions.

[0058] It should be noted that the code segments obtained in the embodiments of the present invention are all publicly available, authorized by users, or fully authorized by all parties.

[0059] 302. The computing device obtains the instruction type distribution characteristics corresponding to the instruction sequence based on the instruction type to which each instruction belongs in the instruction sequence. The instruction type distribution characteristics indicate the distribution of instructions of different instruction types in the instruction sequence.

[0060] In this embodiment of the invention, the computing device analyzes each instruction in the instruction sequence to obtain the instruction type to which each instruction belongs. For each instruction type, the computing device counts the number of instructions under different instruction types, thereby obtaining the instruction type distribution characteristics corresponding to the instruction sequence. Since the execution time of instructions of different instruction types is different, the instruction type distribution characteristics obtained in this process can reflect the execution time of the instruction sequence.

[0061] The analysis of each instruction in the instruction sequence to determine its instruction type can be performed in several ways. One method involves splitting each instruction into multiple strings based on spaces within the instruction sequence. The computing device then matches the second string corresponding to the instruction type against each of these strings. If the second string is present in all the strings, the computing device determines the instruction type corresponding to that second string as the instruction type to which the instruction belongs. Here, the second string corresponding to the instruction type is a string belonging to an instruction of that instruction type.

[0062] One approach is to perform regular expression matching on each instruction in the instruction sequence, based on the regular expression corresponding to the instruction type. If a match is found, the computing device determines the instruction type corresponding to that regular expression as the instruction type to which the instruction belongs. The regular expression corresponding to the instruction type indicates the description format of instructions belonging to that instruction type.

[0063] One approach is to obtain the prefix string of each instruction and match it with the third string corresponding to the instruction type. If a match is found, the instruction type corresponding to the third string is determined as the instruction type to which the instruction belongs. Here, the third string corresponding to the instruction type is the prefix string of the instructions belonging to that instruction type.

[0064] 303. The computing device analyzes the cached instructions included in the instruction sequence based on the instruction sequence to obtain the reuse distance distribution corresponding to the instruction sequence.

[0065] Among them, cache instructions refer to instructions that belong to the cache type.

[0066] The reuse distance refers to the number of cached instructions between two adjacent cached instructions for the same memory access address. When a cached instruction is used to store data obtained during the execution of an instruction sequence into the cache or external memory, the reuse distance reflects the probability that the computing device stores the data obtained during the execution of the instruction sequence corresponding to the first cached instruction and the data obtained during the execution of the instruction sequence corresponding to the second cached instruction into the same cache layer. Alternatively, when a cached instruction is used to retrieve corresponding data from the cache or load corresponding data from external memory into the cache and then retrieve the data from the cache, the reuse distance reflects the probability that the computing device finds the corresponding data of the first cached instruction and the second cached instruction in the same cache layer.

[0067] The principle of reuse distance is explained below. The instruction that comes first in the two adjacent cached instructions is called the first cached instruction, and the instruction that comes later in the two adjacent cached instructions is called the second cached instruction.

[0068] For adjacent cached instructions targeting the same memory access address—that is, the first cached instruction and the second cached instruction—when the first cached instruction is executed, the data corresponding to the first cached instruction is stored in that cache layer. When the second cached instruction is executed, if that cache layer is full, the data corresponding to the second cached instruction will be stored in another cache layer. Therefore, it is possible for the data corresponding to the first cached instruction and the data corresponding to the second cached instruction to be stored in different cache layers. Furthermore, if the reuse distance of the first cached instruction is greater, it means there are more cached instructions between the two cached instructions, and the amount of data stored in that cache layer may be larger. This increases the likelihood of the cache layer becoming full, making it more likely that the data of the first and second cached instructions will not be stored in the same cache layer. In addition, a greater reuse distance increases the likelihood that the data corresponding to the first cached instruction will be removed from that cache layer as data in that cache layer changes. Therefore, the greater the reuse distance, the more likely the data corresponding to the first cache instruction and the second cache instruction will be stored in different cache layers. When a cache-type instruction is used to store data obtained during the execution of an instruction sequence into a cache or external memory, the probability that the computing device stores the data corresponding to the first cache instruction and the data corresponding to the second cache instruction in the same cache layer is smaller. Or, when a cache-type instruction is used to retrieve corresponding data from a cache or load corresponding data from external memory into a cache and then retrieve the data from the cache, the probability that the computing device finds the data corresponding to the first cache instruction and the second cache instruction in the same cache layer is smaller.

[0069] Similarly, the smaller the reuse distance, the greater the probability that the computing device stores the data corresponding to the first cache instruction and the data corresponding to the second cache instruction in the same cache layer when the cache-type instruction is used to store the data obtained during the execution of the instruction sequence into the cache or external memory. Or, the greater the probability that the computing device finds the data corresponding to the first cache instruction and the second cache instruction in the same cache layer when the cache-type instruction is used to retrieve the corresponding data from the cache or load the corresponding data from external memory into the cache and then retrieve the data from the cache.

[0070] The reuse distance will be explained below with reference to Figure 4.

[0071] As shown in Figure 4, instructions x1 to x8 are eight consecutive instructions in the instruction sequence. Instructions x1 and x8 access data at memory address a1, instructions x2, x5, and x7 access data at memory address a2, and instructions x3, x4, and x6 access data at memory address a3. Therefore, the reuse distance corresponding to instruction x1 is 6, the reuse distance corresponding to instruction x2 is 2, the reuse distance corresponding to instruction x3 is 0, the reuse distance corresponding to instruction x4 is 1, and the reuse distance corresponding to instruction x5 is 1.

[0072] Furthermore, the reuse distance distribution indicates the number of reuse distances of different sizes among the multiple reuse distances corresponding to the instruction sequence. This reuse distance distribution can be represented by a reuse distance distribution histogram. Figure 5 is a reuse distance distribution histogram provided by an embodiment of the present invention. As shown in Figure 5, the horizontal axis represents the reuse distance, and the vertical axis represents the number of reuse distances. In this histogram, the reuse distance distribution is as follows: "There are 2 reuse distances with a value of 1, 4 reuse distances with a value of 2, 6 reuse distances with a value of 3, 8 reuse distances with a value of 4, and 4 reuse distances with a value of 5."

[0073] In this embodiment of the invention, for each cached instruction in the instruction sequence, the computing device analyzes the cached instruction to obtain the reuse distance corresponding to the cached instruction. For each size of reuse distance, the computing device obtains the number of cached instructions corresponding to the reuse distance and uses the number of cached instructions as the number of reuse distances to obtain the reuse distance distribution corresponding to the instruction sequence.

[0074] In some embodiments, the computing device analyzes the cached instruction to obtain the reuse distance corresponding to the cached instruction, including: taking the first cached instruction in the instruction sequence as an example, the computing device takes the first cached instruction as the first cached instruction. Based on the memory access address corresponding to the first cached instruction, the computing device searches for a cached instruction whose memory access address is the same as the memory access address corresponding to the first cached instruction from among multiple cached instructions following the first cached instruction in the instruction sequence. If the cached instruction is found, the computing device determines the instruction closest to the first cached instruction among the found cached instructions as the second cached instruction, obtains the number of cached instructions between the first and second cached instructions in the instruction sequence, and obtains this number as the reuse distance corresponding to the first cached instruction. If the cached instruction is not found, the computing device determines that the reuse distance corresponding to the first cached instruction is infinite and does not include this reuse distance in the reuse distance distribution.

[0075] In some embodiments, the computing device analyzes the cached instruction to obtain the reuse distance corresponding to the cached instruction, including: the computing device compares the memory access address corresponding to the first cached instruction with a plurality of cached instructions following the first cached instruction one by one, determines the first cached instruction whose memory access address is the same as the memory access address corresponding to the first cached instruction as the second cached instruction, obtains the number of cached instructions between the first cached instruction and the second cached instruction in the instruction sequence, and obtains the number of cached instructions as the reuse distance corresponding to the first cached instruction. If there is no instruction among the plurality of cached instructions whose memory access address is the same as the memory access address corresponding to the first cached instruction, then the reuse distance corresponding to the first cached instruction is determined to be infinite, and the reuse distance is not included in the reuse distance distribution.

[0076] The process of obtaining the reuse distance corresponding to the cached instruction described above is illustrated using the example of obtaining the reuse distance in a forward-to-back direction, which can also be referred to as the forward reuse distance. In some embodiments, the computing device obtains the reuse distance corresponding to the cached instruction in a backward-to-forward direction, which can also be referred to as the backward reuse distance.

[0077] There are several ways to obtain the backward reuse distance. One method involves the following steps: Taking the last cached instruction in the instruction sequence as an example, this last cached instruction is designated as the second cached instruction. The computing device, based on the memory access address corresponding to the second cached instruction, searches for a cached instruction with the same memory access address as the second cached instruction from among the cached instructions preceding it in the instruction sequence. If this cached instruction is found, the computing device identifies the instruction closest to the second cached instruction among the found cached instructions as the first cached instruction, and calculates the number of cached instructions between the first and second cached instructions in the instruction sequence. This number is then used as the reuse distance corresponding to the second cached instruction. If the cached instruction is not found, the computing device determines that the reuse distance corresponding to the second cached instruction is infinite and does not include this reuse distance in the reuse distance distribution.

[0078] Another backward reuse distance acquisition method includes the following steps: The computing device compares the memory access address corresponding to the second cache instruction with multiple cache instructions preceding the second cache instruction one by one. The first cache instruction whose memory access address matches the memory access address of the second cache instruction is identified as the first cache instruction. The number of cache instructions between the first and second cache instructions in the instruction sequence is then calculated, and this number is taken as the reuse distance corresponding to the second cache instruction. If no instruction among the multiple cache instructions has a memory access address matching the memory access address of the second cache instruction, the reuse distance corresponding to the second cache instruction is determined to be infinite, and this reuse distance is not included in the reuse distance distribution.

[0079] The reuse distance obtained through the above process reflects the probability that the computing device stores the data at the same memory access address obtained during the execution of the instruction sequence into the same cache layer. If the computing device can store the data at the same memory access address obtained during the execution of the instruction sequence into the same cache layer, then during the execution of the second cache instruction, the computing device does not need to spend additional time storing the data corresponding to the second cache instruction into the next level cache layer; if the computing device fails to store the data at the same memory access address obtained during the execution of the instruction sequence into the same cache layer, then during the execution of the second cache instruction, the computing device will need to spend additional time storing the data corresponding to the second cache instruction into the next level cache layer.

[0080] Taking a computing device that includes a first-level cache layer, a second-level cache layer, and memory as an example, where the data corresponding to the first cache instruction is stored in the first-level cache layer, during the execution of the second cache instruction, if the capacity of the first-level cache layer is full, the computing device will store the data corresponding to the second cache instruction in the second-level cache layer; if the capacity of the second-level cache layer is full, the computing device will store the data corresponding to the second cache instruction in memory.

[0081] The aforementioned reuse distance also reflects the probability that the computing device finds the corresponding data for the first cache instruction and the second cache instruction in the same cache layer. If the computing device finds the corresponding data for the first cache instruction and the second cache instruction in the same cache layer, then during the execution of the second cache instruction, the computing device does not need to spend additional time to retrieve the corresponding data for the second cache instruction in the next level cache layer; if the computing device fails to find the corresponding data for the first cache instruction and the second cache instruction in the same cache layer, then during the execution of the second cache instruction, the computing device will need to spend additional time to retrieve the corresponding data for the second cache instruction in the next level cache layer.

[0082] Taking a computing device that includes a first-level cache layer, a second-level cache layer, and memory as an example, if the first cache instruction retrieves the corresponding data in the first-level cache layer, since the data in the memory access address is likely to be accessed by the computing device again in the short term after being accessed by the computing device, the computing device will store the data in the first-level cache layer.

[0083] If the L1 cache is full, the computing device may move the data at the memory access address from the L1 cache to the L2 cache. If the L2 cache is full, the computing device will move the data at the memory access address from the L2 cache to main memory. When the computing device requests access to the data at the memory access address, it will then load the data at that memory address into the L1 cache level by level. During the execution of instructions in the L2 cache, the computing device first searches for the data corresponding to the instruction in the L1 cache. If the computing device finds the data in the L1 cache, it retrieves the data. If the computing device does not find the data in the L1 cache, it searches for the data in the L2 cache. If the computing device finds the data in the L2 cache, it will spend additional time loading the data from the L2 cache into the L1 cache, and then retrieve the data from the L1 cache. If the computing device does not find the data in the L2 cache, it will search for the data in main memory, spend additional time loading the data from main memory into the L2 cache, and then load the data from the L2 cache into the L1 cache, and then retrieve the data from the L1 cache. Therefore, the reuse distance distribution obtained by the above process can reflect the time taken to execute cached instructions in the instruction sequence.

[0084] In the above implementation, cached instruction characteristics are illustrated using reuse distance distribution as an example. Since reuse distance refers to the number of cached instructions between two adjacent cached instructions accessing the same memory address, and this number reflects not only the quantity of cached instructions in the instruction sequence but also their positions, the reuse distance distribution indicates not only the quantity distribution of cached instructions in the instruction sequence but also their positional distribution. In other words, the above steps represent a possible implementation of a computing device obtaining the cached instruction characteristics corresponding to an instruction sequence based on the cached instructions included in the instruction sequence. In this method, the reuse distance distribution is used to indicate the quantity and positional distribution of cached instructions in the instruction sequence, thereby achieving the goal of obtaining the distribution of instruction types.

[0085] The above embodiments illustrate the use of a computing device to obtain the reuse distance distribution corresponding to an instruction sequence as an example. In some embodiments, the computing device analyzes the cached instructions included in the instruction sequence based on the instruction sequence to obtain the stack distance distribution corresponding to the instruction sequence. Here, stack distance refers to the number of different cache layers hit by the cached instructions between the first and second cached instructions. A cached instruction hitting a cache layer means that, when a cached instruction is used to store data obtained during the execution of an instruction sequence into a cache or external memory, the computing device stores the data obtained during the execution of the instruction sequence corresponding to the cached instruction into that cache layer; or, when a cached instruction is used to store data obtained during the execution of an instruction sequence into a cache or external memory, the computing device obtains the data corresponding to the cached instruction from that cache layer. Stack distance can also reflect the probability that a computing device stores data from the same memory access address obtained during the execution of an instruction sequence into the same cache layer when cached instructions are used to store data in the cache or external memory. Alternatively, when cached instructions are used to retrieve corresponding data from the cache or load corresponding data from external memory into the cache and then retrieve the data from the cache, it reflects the probability that the computing device finds the corresponding data for the first and second cached instructions in the same cache layer. A larger stack distance indicates more different cache layers hit by the two cached instructions, suggesting a greater likelihood that each hit cache layer is full, thus increasing the probability that the data corresponding to the first and second cached instructions are stored in different cache layers. Therefore, the larger the stack distance, the more likely the data corresponding to the first cache instruction and the second cache instruction will be stored in different cache layers. When a cache-type instruction is used to store data obtained during the execution of an instruction sequence into the cache or external memory, the probability that the computing device will store the data corresponding to the first cache instruction and the data corresponding to the second cache instruction in the same cache layer is lower. Alternatively, when a cache-type instruction is used to retrieve corresponding data from the cache or load corresponding data from external memory into the cache, and then retrieve the data from the cache, the probability that the computing device will find the data corresponding to the first cache instruction and the data corresponding to the second cache instruction in the same cache layer is lower. Conversely, the smaller the stack distance, the greater the probability that the computing device will store the data corresponding to the first cache instruction and the data corresponding to the second cache instruction in the same cache layer when a cache-type instruction is used to store data obtained during the execution of an instruction sequence into the cache or external memory. Alternatively, when a cache-type instruction is used to retrieve corresponding data from the cache or load corresponding data from external memory into the cache, and then retrieve the data from the cache, the probability that the computing device will find the data corresponding to the first cache instruction and the data corresponding to the second cache instruction in the same cache layer is higher.

[0086] The following explanation of the stack distance is based on Figure 6.

[0087] As shown in Figure 6, instructions x1 to x8 are eight consecutive instructions in the instruction sequence. Instructions x1 and x8 are two adjacent identical cached instructions and both hit cache layer L1. Instructions x2, x3, and x5 hit cache layer L2, instruction x4 hits cache layer L3, and instructions x6 and x7 hit cache layer L4. Therefore, the number of different cache layers hit between instructions x1 and x8 is 3, and the stack distance corresponding to instruction x1 is 3. For another example, as shown in Figure 7, instructions x(i) and x(i-4) are two adjacent identical cached instructions, instructions x(j) and x(j-4) are two adjacent identical cached instructions, and instructions x(k) and x(k-4) are two adjacent identical cached instructions. Between instructions x(i) and x(i-4), instructions x(i-3) to x(i-1) hit the same cache layer, so the stack distance corresponding to instruction x(i-4) is 1. Between instructions x(j) and x(j-4), instruction x(j-3) hits a cache layer, instructions x(j-2) and x(j-1) hit the same cache layer, and the cache layer hit by instruction x(j-3) is different from the cache layer hit by instruction x(j-2). Therefore, the stack distance for instruction x(j-4) is 2. Between instructions x(k) and x(k-4), instructions x(k-3), x(k-2), and x(k-1) hit different cache layers. Therefore, the stack distance for instruction x(k-4) is 3.

[0088] Furthermore, the stack distance distribution indicates the number of stack distances of different sizes among the multiple stack distances corresponding to the instruction sequence. This stack distance distribution can be represented by a stack distance distribution histogram. Figure 8 is a stack distance distribution histogram provided by an embodiment of the present invention. As shown in Figure 8, the horizontal axis is the stack distance and the vertical axis is the number of stack distances. In this histogram, the stack distance distribution is as follows: "There are 2 stack distances with a value of 1, 4 stack distances with a value of 2, 6 stack distances with a value of 3, 8 stack distances with a value of 4, and 4 stack distances with a value of 5."

[0089] The process of obtaining the stack distance distribution corresponding to the instruction sequence includes: for each cached instruction in the instruction sequence, the computing device analyzes the cached instruction to obtain the stack distance corresponding to the cached instruction; for each size of stack distance, the computing device obtains the number of cached instructions corresponding to the stack distance, and uses the number of cached instructions as the number of stack distances to obtain the stack distance distribution corresponding to the instruction sequence.

[0090] In some embodiments, the process by which the computing device analyzes the cached instruction to obtain the stack distance corresponding to the cached instruction includes: taking the first cached instruction in the instruction sequence as an example, the computing device takes the first cached instruction as the first cached instruction. Based on the memory access address corresponding to the first cached instruction, the computing device searches for a cached instruction with the same memory access address as the first cached instruction from among multiple cached instructions following the first cached instruction in the instruction sequence. If the cached instruction is found, the computing device determines the instruction closest to the first cached instruction among the found cached instructions as the second cached instruction, obtains the number of different cache layers hit between the first and second cached instructions in the instruction sequence, and obtains this number as the stack distance corresponding to the first cached instruction. If the cached instruction is not found, the computing device determines that the stack distance corresponding to the first cached instruction is infinite and does not include this stack distance in the stack distance distribution.

[0091] In some embodiments, the process by which the computing device analyzes the cached instruction to obtain the stack distance corresponding to the cached instruction includes: the computing device comparing the memory access address corresponding to the first cached instruction with a plurality of cached instructions following the first cached instruction one by one; identifying the first cached instruction whose memory access address is the same as the memory access address corresponding to the first cached instruction as the second cached instruction; obtaining the number of different cache layers hit by the cached instructions between the first cached instruction and the second cached instruction in the instruction sequence; and obtaining this number of layers as the stack distance corresponding to the first cached instruction. If there is no instruction among the plurality of cached instructions whose memory access address is the same as the memory access address corresponding to the first cached instruction, then the stack distance corresponding to the first cached instruction is determined to be infinite, and this stack distance is not included in the stack distance distribution.

[0092] In the above implementation, the cached instruction characteristics are illustrated using stack distance distribution as an example. Stack distance refers to the number of different cache layers hit by two adjacent cached instructions for the same memory access address. A larger stack distance indicates a potentially larger number of cached instructions between two adjacent cached instructions for the same memory access address, while a smaller stack distance indicates a potentially smaller number of cached instructions between two adjacent cached instructions for the same memory access address. The number of cached instructions between these two adjacent instructions not only reflects the quantity of cached instructions in the instruction sequence but also their positions. Therefore, stack distance distribution indicates not only the quantity distribution of cached instructions in the instruction sequence but also their positional distribution. In other words, the above steps are a possible implementation method for a computing device to obtain the cached instruction characteristics corresponding to an instruction sequence based on the cached instructions included in the instruction sequence. In this method, stack distance distribution is used to indicate the quantity and positional distribution of cached instructions in the instruction sequence, thereby achieving the purpose of obtaining the distribution of instruction types.

[0093] The above process is illustrated by taking the example of a computing device analyzing cached instructions to obtain the stack distance corresponding to a cached instruction. In some embodiments, the computing device combines the forward reuse distance and backward reuse distance corresponding to each cached instruction in the instruction sequence to calculate the stack distance corresponding to the cached instruction, so as to obtain the stack distance corresponding to the cached instruction. Accordingly, taking the t-th cached instruction in the instruction sequence as an example, the computing device uses the following formula (1) to obtain the stack distance corresponding to the t-th cached instruction, where t is an integer greater than 0:

[0094] Where, x t Indicates the t-th cached instruction in the instruction sequence, S(x) t ) indicates the stack distance corresponding to the t-th cached instruction, r indicates the backward reuse distance corresponding to the t-th cached instruction, x i Indicates the i-th cached instruction in the instruction sequence, where i is an integer greater than 0. The forward reuse distance corresponding to the i-th cached instruction in the instruction sequence.

[0095] The above embodiments are illustrated using the example of a computing device obtaining the stack distance distribution corresponding to an instruction sequence. In some embodiments, after obtaining the stack distance corresponding to each cached instruction in the instruction sequence, the computing device calculates the expected stack distance (average stack distance) corresponding to cached instructions with different reuse distances in the instruction sequence based on the stack distance and reuse distance corresponding to each cached instruction. This expected stack distance is the average stack distance calculated based on the stack distances corresponding to cached instructions with the same reuse distance. It can reflect the probability that the computing device stores the data of the same memory access address obtained during the execution of the instruction sequence into the same cache layer when the number of cached instructions between two adjacent cached instructions for the same memory access address is fixed, or the probability that the computing device finds the data corresponding to the first cached instruction and the second cached instruction in the same cache layer. Accordingly, the computing device uses the following formula (2) to obtain the expected stack distance corresponding to cached instructions with different reuse distances in the instruction sequence:

[0096] Where r indicates a reuse distance of r, ES(r) indicates the expected stack distance corresponding to the cached instruction with a reuse distance of r in the instruction sequence, and n r T(r) indicates the number of cached instructions with a reuse distance of r in the instruction sequence, and T(r) indicates all cached instructions with a reuse distance of r in the instruction sequence. i Indicates the i-th cache instruction among cache instructions with a reuse distance of r, S(x i Instruction x i The corresponding stack distance.

[0097] In the above implementation, the cached instruction characteristics are illustrated using the expected stack distance as an example. The expected stack distance is the average stack distance calculated based on the stack distances of cached instructions with the same reuse distance. A larger expected stack distance likely indicates a higher number of cached instructions between two adjacent cached instructions accessing the same memory address, while a smaller expected stack distance likely indicates a lower number of cached instructions between two adjacent cached instructions accessing the same memory address. The number of cached instructions between these two adjacent instructions reflects not only the quantity of cached instructions in the instruction sequence but also their positions. Therefore, the expected stack distance reflects not only the quantity distribution of cached instructions in the instruction sequence but also their positional distribution. In other words, the above steps represent a possible implementation of a computing device obtaining the cached instruction characteristics corresponding to an instruction sequence based on the cached instructions included in the instruction sequence. In this method, the expected stack distance indicates the quantity and positional distribution of cached instructions in the instruction sequence, thereby achieving the goal of obtaining the distribution of instruction types.

[0098] The embodiments of the present invention do not limit the type of cache instruction features.

[0099] 304. The computing device processes the reuse distance distribution corresponding to the instruction sequence through the first loss rate model and outputs the cache loss rate corresponding to the instruction sequence. The cache miss rate corresponds to the cache layer. The cache loss rate corresponding to the cache layer indicates the proportion of instructions in the instruction sequence that cannot store the corresponding data in the cache layer or cannot find the corresponding data in the cache layer.

[0100] The first loss rate model is a pre-trained neural network that outputs the cache loss rate corresponding to the instruction sequence based on the reuse distance distribution corresponding to the input instruction sequence. When the computing device is configured with a single-level cache layer, the first loss rate model is trained at that single-level cache layer and outputs the cache loss rate corresponding to that single-level cache layer. When the computing device is equipped with multiple-level cache layers, the first loss rate model is trained at each of the multiple cache layers and outputs the cache loss rate corresponding to each of those multiple cache layers.

[0101] The computing device used to train the first loss rate model can be the computing device used in the embodiments of the present invention, or it can be other computing devices, and the embodiments of the present invention do not limit it. The training process of the first loss rate model includes multiple rounds of training. The following describes the training process of the first loss rate model using the computing device used in the embodiments of the present invention, taking a computing device equipped with two levels of caching layers (level 1 caching layer and level 2 caching layer) as an example.

[0102] Before model training, the computing device obtains the stack distance distribution corresponding to historical instruction sequences. It compares the stack distances in this distribution with the capacity of the L1 cache layer used to execute the historical instruction sequence, and obtains the number of stack distances greater than the L1 cache layer capacity. This number is then divided by the total number of stack distances in the stack distance distribution to obtain the actual cache loss rate corresponding to that L1 cache layer. The computing device then compares the stack distances in the stack distance distribution with the capacity of the L2 cache layer used to execute the historical instruction sequence, and obtains the number of stack distances greater than the L2 cache layer capacity. This number is then divided by the total number of stack distances in the stack distance distribution to obtain the actual cache loss rate corresponding to that L2 cache layer.

[0103] During model training, the computing device inputs the reuse distance distribution corresponding to the historical instruction sequence into the first loss rate model. The first loss rate model performs forward propagation calculations based on the reuse distance distribution and outputs the calculation results as the predicted cache loss rate corresponding to the historical instruction sequence. This predicted cache loss rate includes the predicted cache loss rate corresponding to the first-level cache layer and the predicted cache loss rate corresponding to the second-level cache layer. Since the first loss rate model is trained based on the reuse distance distribution corresponding to the historical instruction sequence and the actual cache loss rate, it learns the correspondence between the reuse distance distribution corresponding to the instruction sequence and the actual cache loss rate, thus enabling it to output the predicted cache loss rate corresponding to the instruction sequence based on the reuse distance distribution.

[0104] The computing device calculates the loss value for this training round based on the cache loss rates of the first-level cache layer, the second-level cache layer, and the predicted cache loss rate obtained before model training. In some embodiments, the calculation of the loss value includes: the computing device calculating the absolute value of the difference between the actual cache loss rate and the predicted cache loss rate for the first-level cache layer to obtain the loss value for the first-level cache layer; calculating the absolute value of the difference between the cache loss rate and the predicted cache loss rate for the second-level cache layer to obtain the loss value for the second-level cache layer. The computing device adds the loss values ​​for the first-level cache layer and the second-level cache layer, or calculates the average of the loss values ​​for the first-level cache layer and the second-level cache layer to obtain the loss value for this training round.

[0105] If the loss value is greater than or equal to the first loss value threshold, or if the number of training epochs of the model has not reached the first preset number of epochs, the computing device adjusts the first loss rate model through backpropagation based on the loss value, and then proceeds to the next round of training. If the loss value is less than the first loss value threshold, or if the number of training epochs of the model has reached the first preset number of epochs, the computing device stops training the first loss rate model and outputs the first loss rate model that has been trained.

[0106] In this embodiment of the invention, the reuse distance distribution corresponding to the instruction sequence is processed by a pre-trained first loss rate model, and the cache loss rate corresponding to the instruction sequence is output. Based on the relationship between the reuse distance distribution and the cache loss rate in the historical instruction sequence, a more accurate cache loss rate corresponding to the instruction sequence can be obtained. Based on the more accurate cache loss rate, the execution time of the instruction sequence can be obtained, which makes the obtained execution time more accurate.

[0107] In some embodiments, the computing device trains the first loss rate model using reuse distance distribution and cache loss rate under various cache replacement behaviors, so that the first loss rate model can be applied to various cache replacement behaviors. Here, cache replacement behavior refers to: when the cache capacity is full or close to its limit, and new data needs to be stored in the cache, how to determine the old data to be deleted from the cache. For example, the least recently used (LRU) cache replacement behavior means: when new data needs to be stored in the cache, the old data that has been used the least within a preset time period is deleted from the cache. In some embodiments, the computing device trains the first loss rate model using reuse distance distribution and cache loss rate under the least recently used (LRU) cache replacement behavior.

[0108] The above process is illustrated using the cache loss rate corresponding to the instruction sequence output by the first loss rate model as an example. In some embodiments, the cache loss number corresponding to the instruction sequence output by the first loss rate model is also corresponding to the cache layer. The cache loss number corresponding to the cache layer indicates the number of instructions in the instruction sequence that cannot store the corresponding data in the cache layer or cannot find the corresponding data in the cache layer. This can more intuitively reflect the impact of cached instructions on the execution time of the instruction sequence.

[0109] The above process is illustrated using the reuse distance distribution through a first loss rate model as an example. In some embodiments, where the above process obtains the stack distance distribution corresponding to the instruction sequence, the above process processes the stack distance distribution through the first loss rate model and outputs the cache loss rate corresponding to the instruction sequence. This embodiment of the invention does not limit this. The training process of the first loss rate model is the same as the training process described above, and will not be repeated here.

[0110] In some embodiments, when the process described above obtains the expected stack distance corresponding to the instruction sequence, the process processes the expected stack distance using a first loss rate model and outputs the cache loss rate corresponding to the instruction sequence. This embodiment of the invention does not limit the scope of the invention. The training process of this first loss rate model is similar to the training process described above, and will not be repeated here. Since the computing device can obtain the cache loss rate by calculating the stack distance distribution, the cache loss rate obtained through the stack distance distribution or the expected stack distance is more accurate.

[0111] Step 304 described above is a possible implementation whereby a computing device processes instruction distribution features based on a neural network to obtain a corresponding loss rate. This loss rate indicates the likelihood of time consumption based on the instruction distribution features. The neural network is trained based on historical instruction sequences and corresponding historical execution information. In this possible implementation, the instruction distribution features include cached instruction features, and the neural network is a first loss rate model that processes the cached instruction features and outputs a corresponding loss rate, i.e., the cache loss rate. In some embodiments, if the computing device obtains the cached instruction features corresponding to the instruction sequence by executing step 303, the computing device can execute step 304 to obtain the cache loss rate corresponding to the instruction sequence based on the cached instruction features. However, if the computing device does not execute step 303, it does not need to execute step 304.

[0112] 305. The computing device analyzes the branch instructions included in the instruction sequence based on the instruction sequence to obtain the branch entropy corresponding to the instruction sequence. The branch entropy indicates the probability that the branch prediction result of the branch instruction in the instruction sequence is to be executed.

[0113] Here, a branch instruction refers to an instruction belonging to the branch type. Branch prediction for a branch instruction involves: based on the historical execution records of the corresponding branch instruction in the historical instruction sequence, obtaining the probability that the branch instruction was executed in the historical execution process of the historical instruction sequence, and using this probability as the branch prediction result for the branch instruction in the current instruction sequence. When this probability is greater than or equal to a probability threshold, the branch instruction is executed as the branch prediction result for the branch instruction in the current instruction sequence. The historical execution records may include the number of times the branch instruction was executed in the historical execution process of the historical instruction sequence and the number of times the branch instruction was not executed.

[0114] In this embodiment of the invention, the computing device analyzes the branch instructions included in the instruction sequence based on the historical execution records of the instruction sequence and historical instruction sequences. It obtains the probability that the branch prediction result of each branch instruction in the instruction sequence will be executed under the historical instruction sequence; this probability is called the probability corresponding to the branch instruction. For each branch instruction, the computing device calculates the probability corresponding to that branch instruction to obtain the linear Shankly entropy corresponding to that branch instruction. Then, based on the probability and linear Shankly entropy of each branch instruction, it calculates the branch entropy corresponding to the instruction sequence. The linear Shankly entropy corresponding to a branch instruction indicates the accuracy of determining the branch prediction result based on the probability corresponding to that branch instruction. A larger linear Shankly entropy corresponds to a branch instruction, the lower the accuracy of determining the branch prediction result based on the probability corresponding to that branch instruction; conversely, a smaller linear Shankly entropy corresponds to a branch instruction, the higher the accuracy of determining the branch prediction result based on the probability corresponding to that branch instruction.

[0115] In the above implementation, branch instruction characteristics are illustrated using branch entropy as an example. The quantity distribution indicates the number of instructions in the instruction sequence whose branch prediction result is execution. Since branch entropy indicates the probability that a branch prediction result in the instruction sequence is execution, multiplying this probability by the total number of instructions in the instruction sequence yields the number of instructions whose branch prediction result is execution. Therefore, branch entropy can indicate the quantity distribution of branch instructions in the instruction sequence. In other words, the above steps are a possible implementation method for a computing device to obtain the branch instruction characteristics corresponding to an instruction sequence based on the branch instructions included in the instruction sequence. In this method, branch entropy is used to indicate the quantity distribution of branch instructions in the instruction sequence, thereby achieving the purpose of obtaining the distribution of instruction types.

[0116] Accordingly, the process of obtaining the branch entropy corresponding to the instruction sequence includes the following steps A1 to A3.

[0117] A1. The computing device analyzes the branch instructions included in the instruction sequence based on the instruction sequence, and obtains the branch prediction result of each branch instruction in the instruction sequence under each historical instruction sequence as the probability of execution.

[0118] The probability that a branch instruction will be executed in the historical instruction sequence refers to the probability that the branch instruction will be executed in the current instruction sequence, based on the historical execution record of the branch instruction in the historical execution process of the historical instruction sequence.

[0119] In this embodiment of the invention, for each branch instruction in the instruction sequence, the computing device calculates the probability that the branch instruction will be executed in the historical execution process of each historical instruction sequence based on the historical execution record corresponding to that branch instruction in the historical execution process of each historical instruction sequence. This probability is then used as the probability that the branch prediction result of the branch instruction in each historical instruction sequence is the execution probability. The following explanation uses the example of obtaining the probability that the branch prediction result of the k-th branch instruction in the instruction sequence is the execution probability in the historical instruction sequence H, where k is an integer greater than 0.

[0120] Before obtaining the probability of execution of the branch prediction result of the branch instruction, the historical instruction sequence H is executed at least once. During the execution, the number of times each branch instruction in the historical instruction sequence H is executed and the number of times it is not executed are recorded to obtain the historical execution record corresponding to the historical instruction sequence H.

[0121] The computing device executing the historical instruction sequence H can be the computing device used in this embodiment of the invention, or it can be another computing device; this embodiment of the invention does not limit this. If the computing device executing the historical instruction sequence H is the computing device used in this embodiment of the invention, the computing device retrieves the historical execution record corresponding to the k-th branch instruction in the current instruction sequence from the locally stored historical execution records. If the computing device executing the historical instruction sequence H is another computing device, the computing device receives the historical instruction sequence H and the historical execution record corresponding to the historical instruction sequence H sent by the other computing device, and retrieves the historical execution record corresponding to the k-th branch instruction in the current instruction sequence from the historical execution record corresponding to the historical instruction sequence H.

[0122] In the process of obtaining the probability that the branch prediction result of the branch instruction is to be executed, the computing device calculates the probability that the branch prediction result of the k-th branch instruction is to be executed under the historical instruction sequence H based on the historical execution record corresponding to the k-th branch instruction in the historical execution record of the historical instruction sequence H. Accordingly, the computing device uses the following formula (3) to calculate the probability:

[0123] Where H indicates the historical instruction sequence, p(k,H) indicates the probability that the branch prediction result of the k-th branch instruction in the instruction sequence is executed under the historical instruction sequence H, n1(k,H) indicates the number of times the k-th branch instruction is executed during the execution of the historical instruction sequence H, and n0(k,H) indicates the number of times the k-th branch instruction is not executed during the execution of the historical instruction sequence H.

[0124] A2. The computing device calculates the linear Shannon entropy corresponding to each branch instruction in the instruction sequence based on the branch prediction result of each branch instruction in the historical instruction sequence as the probability of execution.

[0125] In this embodiment of the invention, for each branch instruction in the instruction sequence, the computing device calculates the linear Shannon entropy corresponding to the branch instruction based on the probability that the branch instruction is executed according to the branch prediction result in the historical instruction sequence. Accordingly, the computing device uses the following formula (4) to calculate the linear Shannon entropy corresponding to each branch instruction in the instruction sequence. E L (p)=2×min (p,1-p) (4)

[0126] Where p indicates the probability that the branch prediction result of the branch instruction in the historical instruction sequence is to be executed, and E L (p) indicates the linear Shannon entropy corresponding to probability p, and min(p,1-p) indicates the minimum value between probability p and 1-p.

[0127] A3. The computing device calculates the branch entropy corresponding to the instruction sequence based on the branch prediction result of each branch instruction in each historical instruction sequence as the probability of execution and the linear Shannon entropy corresponding to each branch instruction.

[0128] In this embodiment of the invention, the computing device calculates the branch entropy corresponding to the instruction sequence using the following formula (5) based on the probability of execution of each branch instruction in each historical instruction sequence and the linear Shannon entropy corresponding to each branch instruction.

[0129] Where E indicates the branch entropy corresponding to the instruction sequence, N indicates the total number of branch instructions in the instruction sequence, n(k,H) indicates the sum of the number of times the k-th branch instruction in the instruction sequence was executed during the execution of the historical instruction sequence H and the number of times the k-th branch instruction was not executed during the execution of the historical instruction sequence H, p(k,H) indicates the probability that the branch prediction result of the k-th branch instruction in the instruction sequence under the historical instruction sequence H is executed, E L (p(k,H)) indicates the linear Shannon entropy corresponding to the k-th branch instruction, ∑ H n(k,H)×E L (p(k,H)) indicates the summation operation for each historical instruction sequence, ∑ k ∑ H n(k,H)×E L (p(k,H)) indicates that the summation operation is performed on each branch instruction in the instruction sequence.

[0130] The above process is illustrated using branch entropy as an example of branch instruction characteristics. In some embodiments, the computing device counts the number of branch instructions in every preset number of consecutive instructions in the instruction sequence to obtain the branch instruction characteristics corresponding to the instruction sequence. For example, if the instruction sequence includes 20 million instructions, the computing device counts the number of branch instructions in every million instructions to obtain the branch instruction characteristics corresponding to the instruction sequence.

[0131] In the above implementation, the branch instruction feature is illustrated using the number of branch instructions in every preset number of consecutive instructions as an example. This branch instruction feature indicates the number of branch instructions in every preset number of consecutive instructions in the instruction sequence. The number of branch instructions in every preset number of consecutive instructions not only reflects the quantity of branch instructions in the instruction sequence but also their position. A smaller number of branch instructions in every preset number of consecutive instructions suggests a higher number of instructions between adjacent branch instructions, resulting in a more dispersed distribution of branch instructions. Conversely, a larger number of branch instructions in every preset number of consecutive instructions suggests a lower number of instructions between adjacent branch instructions, resulting in a more concentrated distribution of branch instructions. Therefore, this branch instruction feature indicates not only the quantity distribution of branch instructions in the instruction sequence but also their positional distribution. In other words, the above steps represent a possible implementation of a computing device obtaining the branch instruction feature corresponding to an instruction sequence based on the branch instructions included in the instruction sequence. In this method, the number of branch instructions in every preset number of consecutive instructions indicates the quantity and positional distribution of branch instructions in the instruction sequence, thereby achieving the purpose of obtaining the distribution of instruction types.

[0132] The above-mentioned branch instruction distribution reflects the number of instructions executed prematurely when the branch prediction result is "execute," and also reflects the time consumed due to branch prediction errors. The more dispersed the branch instruction distribution, the more instructions are executed prematurely when the branch prediction result is "execute," and the longer the time consumed due to branch prediction errors. Conversely, the more concentrated the branch instruction distribution, the fewer instructions are executed prematurely when the branch prediction result is "execute," and the shorter the time consumed due to branch prediction errors.

[0133] 306. The computing device processes the branch entropy corresponding to the instruction sequence through the second loss rate model and outputs the branch loss rate corresponding to the instruction sequence.

[0134] In some embodiments, the second loss rate model is a linear model, denoted by Linear(). The computing device processes the branch entropy corresponding to the instruction sequence using this linear model and outputs the branch loss rate corresponding to the instruction sequence, i.e., m. bpred =Linear(E), where m bpredE represents the branch loss rate corresponding to the instruction sequence, and E represents the branch entropy corresponding to the instruction sequence. This linear model reflects the relationship between branch entropy and branch loss rate. Obtaining the branch loss rate through this linear model is relatively accurate and requires less computation.

[0135] In some embodiments, the second loss rate model is a pre-trained neural network capable of outputting the branch loss rate corresponding to the input instruction sequence based on the branch entropy of the input instruction sequence. The computing device used to train the second loss rate model can be the computing device used in the embodiments of the present invention, or other computing devices; the embodiments of the present invention do not limit this. The training process of the second loss rate model includes multiple rounds of training. The following describes one round of training of the second loss rate model using the computing device used in the embodiments of the present invention as an example.

[0136] Before model training, the computing device acquires the branch entropy and branch loss rate corresponding to the historical instruction sequence. The process of acquiring the branch loss rate for this historical instruction sequence includes: the computing device obtaining the branch prediction results and historical execution records of each branch instruction in the historical instruction sequence from the historical execution information corresponding to that historical instruction sequence. Based on the branch prediction results and historical execution records of each branch instruction in the historical instruction sequence, the computing device calculates the proportion of branch instructions with incorrect branch predictions among all branch instructions, thus obtaining the branch loss rate corresponding to that historical instruction sequence.

[0137] During model training, the computing device inputs the branch entropy corresponding to the historical instruction sequence into the second loss rate model. The second loss rate model performs forward propagation calculations based on this branch entropy and outputs the result as the predicted branch loss rate corresponding to the historical instruction sequence. Since this second loss rate model is trained based on the branch entropy and actual branch loss rate of the historical instruction sequence, it learns the correspondence between the branch entropy and the actual branch loss rate, thus enabling it to output the predicted branch loss rate of the instruction sequence based on the branch entropy.

[0138] The computing device calculates the loss value corresponding to the current training round based on the branch loss rate obtained before model training and the predicted branch loss rate. If the loss value is greater than or equal to a second loss value threshold, or if the number of training rounds has not reached a second preset number of rounds, the computing device adjusts the second loss rate model through backpropagation based on the loss value, and then proceeds to the next training round. The process of obtaining the loss value is the same as that of obtaining the loss value during the training of the first loss rate model, and will not be repeated here. If the loss value is less than the second loss value threshold, or if the number of training rounds has reached a second preset number of rounds, the computing device stops training the second loss rate model and outputs the trained second loss rate model. The more historical instruction sequences used in the model training process, the more accurate the branch loss rate output by the trained second loss rate model.

[0139] This process obtains the branch loss rate corresponding to the instruction sequence through a pre-trained second loss rate model. Based on the relationship between branch entropy and branch loss rate in historical instruction sequences, it can obtain a more accurate branch loss rate corresponding to the instruction sequence. Based on this more accurate branch loss rate, the execution time of the instruction sequence can be obtained, making the obtained execution time more accurate.

[0140] Steps 302, 303, and 305 above describe a possible implementation method whereby a computing device obtains instruction distribution characteristics corresponding to the instruction sequence for a computing service. These instruction distribution characteristics indicate the distribution of instruction types and can also be referred to as architecture-independent computing characteristics. In this possible implementation, the instruction distribution characteristics include three features: instruction type distribution characteristics, cached instruction characteristics, and distributed instruction characteristics. The cached instruction characteristics are based on reuse distance distribution, and the branch instruction characteristics are based on branch entropy.

[0141] It should be noted that the embodiments of the present invention are illustrated by taking the execution of steps 302, 303, and 305 above to obtain three features: instruction type distribution features, cached instruction features, and distributed instruction features. In some embodiments, the computing device can execute any one or any two of steps 302, 303, and 305 above to obtain the features corresponding to the executed steps, and independently implement the determination process of the target hardware parameter set based on the obtained features. In some embodiments, the computing device can process the instruction sequence using pre-developed analysis tools to output the above features.

[0142] Step 306 described above is a possible implementation whereby a computing device processes instruction distribution features based on a neural network to obtain a corresponding loss rate. This loss rate indicates the likelihood of time consumption based on the instruction distribution features. The neural network is trained based on historical instruction sequences and corresponding historical execution information. In this possible implementation, the instruction distribution features include branch instruction features, and the neural network is a second loss rate model that processes the branch instruction features and outputs the corresponding loss rate, i.e., the branch loss rate. In some embodiments, if the computing device obtains the branch instruction features corresponding to the instruction sequence by executing step 305, the computing device can execute step 306 to obtain the branch loss rate corresponding to the instruction sequence based on the branch instruction features. If the computing device does not execute step 305, step 306 is unnecessary.

[0143] 307. The computing device acquires multiple sets of hardware parameters, each set of hardware parameters including the parameter value of at least one parameter of the hardware.

[0144] The multiple hardware parameter sets include hardware parameters of computing nodes in a distributed system, or hardware parameters of hardware in electronic devices, or hardware parameters of servers in a cloud service system. These multiple hardware parameter sets are pre-set sets of hardware parameters, each set including the parameter values ​​of preset hardware parameters, which are parameters related to the execution time of the instruction sequence.

[0145] The following explanation uses a CPU as an example to illustrate the hardware parameter set and its acquisition process. CPU parameters include configurable parameters and microarchitecture parameters. Configurable parameters are those that can be adjusted during the execution of a computing task, while microarchitecture parameters are those that can be adjusted when the computing device is offline. Configurable parameters include the number of CPU cores, CPU frequency, the size of each level of CPU cache, and the size of the main memory. Microarchitecture parameters include the size of the execution unit, the number of ports, the branch prediction width, the maximum capacity of the re-order buffer (ROB), the maximum capacity of each cache layer (cache size), and the corresponding cache latency of each cache layer (cache latency). Both the configurable and microarchitecture parameters mentioned above are related to the duration of the instruction sequence; therefore, the hardware parameter set includes the parameter values ​​of both configurable and microarchitecture parameters. In some embodiments, CPU parameters also include: big.LITTLE, hyper-threading, pipeline specifications, memory bandwidth, memory latency, network bandwidth, and network latency, etc. This embodiment of the invention does not limit these parameters and will not list them all here.

[0146] In this embodiment of the invention, the computing device receives multiple sets of hardware parameters sent by other computing devices, or the computing device arranges and combines possible values ​​of various preset parameters to generate multiple sets of hardware parameters. The possible values ​​of the preset parameters refer to values ​​within the parameter value range of the preset parameters or commonly used values ​​of the preset parameters; this embodiment of the invention does not limit this.

[0147] In different hardware parameter adjustment scenarios, computing devices generate hardware parameter sets in different ways. For example, when using a CPU in a pre-defined electronic device to perform a computing task, the computing device obtains the parameter values ​​of the microarchitecture class parameters corresponding to the CPU based on the CPU model. The computing device then arranges and combines the possible values ​​of the configurable class parameters to obtain multiple hardware parameter sets, and adds the parameter values ​​of the microarchitecture class parameters corresponding to the CPU to these multiple hardware parameter sets. When using computing nodes in a distributed system or servers in a cloud service system that can call different CPUs to perform computing tasks, the computing device arranges and combines the possible values ​​of the configurable class parameters and the microarchitecture class parameters to obtain multiple hardware parameter sets. Finally, during the process of adjusting or designing the CPU's microarchitecture, the computing device arranges and combines the possible values ​​of the configurable class parameters and the microarchitecture class parameters to obtain multiple hardware parameter sets. This allows the target hardware parameter sets obtained in subsequent processes to provide effective reference information for microarchitecture adjustment or design, thereby enabling scalable research on microarchitecture characteristics and analysis and verification of microarchitecture performance.

[0148] This embodiment of the invention uses the example of a hardware parameter set including the parameter values ​​of all configurable parameters and microarchitecture parameters mentioned above. In some embodiments, the parameters related to the duration of the instruction sequence may differ depending on the features used to obtain the duration. During the generation of the hardware parameter set, the computing device can generate a corresponding hardware parameter set based on the parameters related to the duration of the instruction sequence. This embodiment of the invention does not limit this. For example, when the duration of the instruction sequence is obtained only based on the branch instruction features, the parameters related to the duration of the instruction sequence include branch resolution time and branch prediction width. The computing device arranges and combines the possible values ​​of branch resolution time and branch prediction width to generate multiple hardware parameter sets. Here, branch resolution time refers to the time spent when the branch prediction result of a branch instruction is incorrect, and branch prediction width refers to the number of branch instructions that can be predicted simultaneously.

[0149] It should be noted that step 307 can be executed before the preceding steps, and the execution order of step 307 is not limited in this embodiment of the invention.

[0150] 308. The computing device combines multiple sets of hardware parameters to calculate the instruction type distribution characteristics, the cache loss rate corresponding to the instruction sequence, and the branch loss rate corresponding to the instruction sequence, and obtains the first duration, second duration, and third duration of the execution of the instruction sequence under each set of hardware parameters.

[0151] This invention takes a CPU as an example and describes the process of calculating the first execution time of the instruction sequence under each hardware parameter set based on multiple hardware parameter sets and instruction type distribution characteristics; the process of calculating the second execution time of the instruction sequence under each hardware parameter set based on the cache loss rate corresponding to multiple hardware parameter sets and instruction sequences; and the process of calculating the third execution time of the instruction sequence under each hardware parameter set based on the branch loss rate corresponding to multiple hardware parameter sets and instruction sequences.

[0152] In some embodiments, the process of calculating the first duration of the instruction sequence under each hardware parameter set based on multiple hardware parameter sets and instruction type distribution characteristics includes: for each hardware parameter set, the computing device obtains the parameter value corresponding to the parameter from the hardware parameter set according to a preset parameter related to the first duration; calculates the effective dispatch rate corresponding to the hardware parameter set based on the instruction type distribution characteristics and the parameter value; the effective dispatch rate indicates the number of instructions that can be executed per unit time under the hardware parameter set. The computing device calculates the first duration of the instruction sequence under the hardware parameter set based on the effective dispatch rate and the total number of instructions in the instruction sequence.

[0153] In the calculation of the effective dispatch rate corresponding to the aforementioned hardware parameter set, different hardware parameters in the set have different effects on the effective dispatch rate. For example, the larger the parameter value of some hardware parameters, the larger the effective dispatch rate; conversely, the smaller the parameter value of others, the larger the effective dispatch rate. Therefore, the computing device calculates the dispatch rate corresponding to different hardware parameters based on the distribution characteristics of different hardware parameters and instruction types in the hardware parameter set. From these different dispatch rates and the base dispatch rate, a minimum dispatch rate is selected as the effective dispatch rate of the hardware parameter set to ensure its accuracy.

[0154] In calculating the dispatch rate corresponding to different hardware parameters, the computing device can calculate the dispatch rate corresponding to at least two hardware parameters from the hardware parameter set. For example, the computing device can divide the maximum capacity of the reorder cache by the bottleneck instruction latency and the average critical path length corresponding to the maximum capacity of the reorder cache to obtain the dispatch rate corresponding to the maximum capacity of the reorder cache, the bottleneck instruction latency, and the average critical path length corresponding to the maximum capacity of the reorder cache. The computing device can also calculate the dispatch rate corresponding to at least one hardware parameter from the hardware parameter set and the instruction type distribution characteristics. For example, the computing device can divide the total number of instructions in the instruction sequence by the number of instructions executed under a certain port to obtain the dispatch rate corresponding to that port. This embodiment of the invention does not limit the calculation process of the dispatch rate.

[0155] In the above process, since the execution time of instructions of different instruction types is different and the distribution characteristics of instruction types have a significant impact on the execution time of instruction sequences, the first execution time of the instruction sequence under the hardware parameter set is calculated based on the instruction type distribution characteristics of the instruction sequence. This first execution time is relatively consistent with the actual execution time of the instruction sequence under the hardware parameter set. The target hardware parameters are determined based on this relatively consistent first execution time. The determined target hardware parameter set can make the execution time of the instruction sequence shorter.

[0156] In some embodiments, the process of calculating the second execution time of the instruction sequence under each hardware parameter set based on the cache miss rate corresponding to multiple hardware parameter sets and instruction sequences includes: the computing device multiplying the cache miss rate corresponding to each cache level by the total number of instructions in the instruction sequence to obtain the cache miss number corresponding to each cache level. For each hardware parameter set, the computing device obtains the cache latency time corresponding to each cache layer from the hardware parameter set. Since the cache latency time corresponding to a cache layer indicates the time consumed by the computing device to store the data corresponding to the cached instruction in the cache layer, or, the cache latency time corresponding to a cache layer indicates the time consumed by the computing device to retrieve the corresponding data from the cache layer in the process of retrieving data from the cache according to the cached instruction, the computing device can calculate the second execution time of the instruction sequence under each hardware parameter set based on the cache latency time corresponding to each cache layer and the cache miss number. It should be noted that, taking the cache instruction used to store data obtained during the execution of the instruction sequence as an example, the cache latency of the other cache layers, except for the last cache layer, is the parameter in the hardware parameter set. The cache latency of the last cache layer is calculated by the number of cache instructions that can store data into memory in parallel, the memory entry time, and the bus transmission and waiting time involved in storing the corresponding data from the cache into memory.

[0157] During the execution of an instruction sequence, the time consumed by storing the data corresponding to the cached instructions in different cache layers varies. Therefore, by using the cache loss rate mentioned above, a second time consumed by storing the corresponding data according to the cached instructions can be obtained. Combining this second time with the execution time of the instruction sequence can make the obtained execution time more accurate.

[0158] In some embodiments, the process of calculating the third duration of executing the instruction sequence under each hardware parameter set based on the branch loss rate corresponding to multiple hardware parameter sets and instruction sequences includes: for each hardware parameter set, the computing device obtains the branch parsing time and branch prediction width from the hardware parameter set, and calculates the third duration of executing the instruction sequence under that hardware parameter set based on the branch prediction time, branch prediction width, and branch loss rate corresponding to the instruction sequence. Since the branch prediction rate indicates the proportion of branch instructions with incorrect branch prediction results among all branch instructions, the branch prediction width indicates the number of branch instructions that can be predicted simultaneously, and the branch parsing time indicates the time consumed in predicting branch instructions, the computing device can obtain the third duration of executing the instruction sequence under the hardware parameter set based on the branch prediction time, branch prediction width, and branch loss rate corresponding to the instruction sequence.

[0159] During the execution of an instruction sequence, errors in branch prediction can cause the computing device to re-execute parts of the instruction sequence. Therefore, by using the aforementioned branch loss rate, we can obtain the third duration consumed by the branch prediction error. Combining this third duration with the execution time of the instruction sequence can make the obtained time more accurate.

[0160] The processes described above for obtaining the second and third durations are possible implementations of how a computing device, based on a loss rate and multiple hardware parameter sets, obtains the execution time of an instruction sequence under each hardware parameter set. In obtaining the second duration, the loss rate is the cache loss rate; in obtaining the third duration, the loss rate is the branch loss rate.

[0161] It should be noted that the embodiments of the present invention are illustrated by taking the example of a computing device obtaining a first duration, a second duration, and a third duration based on instruction type distribution characteristics, cached instruction characteristics, and branch instruction characteristics, respectively. In some embodiments, the step of obtaining the first duration is an optional step corresponding to the step of obtaining instruction type distribution characteristics; the step of obtaining the second duration is an optional step corresponding to the step of obtaining cached instruction characteristics; and the step of obtaining the third duration is an optional step corresponding to the step of obtaining branch instruction characteristics. When the computing device only obtains instruction type distribution characteristics, the computing device performs the step of obtaining the first duration based on the instruction type distribution characteristics; when the above process only obtains cache loss rate, the computing device performs the step of obtaining the second duration based on cache loss rate; and when the above process only obtains branch loss rate, the computing device performs the step of obtaining the third duration based on branch loss rate. When the computing device obtains two of the above-mentioned instruction type distribution characteristics, cached instruction characteristics, and branch instruction characteristics, the computing device performs the step of obtaining the duration corresponding to each of the two characteristics.

[0162] 309. The computing device obtains the execution time of the instruction sequence under each hardware parameter set based on the first, second, and third execution times of the instruction sequence under each hardware parameter set.

[0163] The execution time can be represented by the number of instructions per clock (IPC), which indicates the average execution time of one instruction in the instruction sequence. The computing device described above obtains the execution time of the instruction sequence under each hardware parameter set based on the first, second, and third execution times. There are several ways to do this, which are described below.

[0164] In some embodiments, the computing device sums the first, second, and third execution durations of the instruction sequence under each set of hardware parameters to obtain the execution time of the instruction sequence under each set of hardware parameters. Obtaining the execution time of the instruction sequence in this way requires less computation.

[0165] In some embodiments, for each set of hardware parameters, the computing device processes the first, second, and third execution times of the instruction sequence executed under that set of hardware parameters using a time-consuming model, and outputs the execution time of the instruction sequence executed under that set of hardware parameters. This time-consuming model is a pre-trained model that can output the execution time corresponding to the set of hardware parameters based on the first, second, and third execution times corresponding to the input set of hardware parameters. The computing device training this time-consuming model can be the computing device used in the embodiments of the present invention, or other computing devices; the embodiments of the present invention do not limit this. The training process of the time-consuming model includes multiple rounds of training. The following describes one round of training of the time-consuming model using the computing device used in the embodiments of the present invention as an example.

[0166] Before model training, the computing device acquires the first duration, second duration, and third duration corresponding to the historical instruction sequence, as well as the actual execution time of the historical instruction sequence. This historical instruction sequence can be the same as or different from the historical instruction sequence mentioned above; this embodiment of the invention does not limit this. The process of acquiring the first duration, second duration, and third duration corresponding to the historical instruction sequence is similar to the process of acquiring the first duration, second duration, and third duration corresponding to the instruction sequence described above, and will not be repeated here. The first duration, second duration, third duration, and actual execution time corresponding to the historical instruction sequence can be acquired by the computing device used in this embodiment of the invention based on the historical instruction sequence, or they can be sent by other computing devices to the computing device used in this embodiment of the invention; this embodiment of the invention does not limit this.

[0167] During model training, the computing device inputs the first, second, and third durations corresponding to the historical instruction sequence into the time-consuming model. The time-consuming model performs forward propagation calculations based on these durations and outputs the predicted time-consuming duration for the historical instruction sequence. Since the time-consuming model is trained based on the first, second, and third durations of the historical instruction sequence and the actual time-consuming duration, it learns the correspondence between the first, second, and third durations of the instruction sequence and the actual time-consuming duration. Therefore, it can output the actual time-consuming duration of the instruction sequence based on the first, second, and third durations of the instruction sequence.

[0168] The computing device calculates the loss value corresponding to the current training round based on the actual training time obtained before model training. The process of obtaining this loss value is the same as that of obtaining the loss value during the training of the first loss rate model described above, and will not be repeated here. If the loss value is greater than or equal to the third loss value threshold, or if the number of training rounds of the model has not reached the third preset number of rounds, the computing device adjusts the training time model through backpropagation based on the loss value, and then proceeds to the next training round. If the loss value is less than the third loss value threshold, or if the number of training rounds of the model has reached the third preset number of rounds, the computing device stops training the training time model and outputs the completed training time model.

[0169] Steps 307 to 309 described above represent a possible implementation of a computing device obtaining the execution time of an instruction sequence under each set of hardware parameters based on instruction distribution characteristics and multiple sets of hardware parameters. This possible implementation is illustrated using instruction distribution characteristics including instruction type distribution characteristics, cached instruction characteristics, and branch instruction characteristics as examples, comprehensively considering different factors affecting the execution time and obtaining a more accurate execution time. In some embodiments, if the computing device obtains any one of the instruction type distribution characteristics, cached instruction characteristics, and branch instruction characteristics corresponding to the instruction sequence, the computing device independently obtains the execution time corresponding to the instruction sequence based on that single characteristic.

[0170] For example, when the computing device only obtains the instruction type distribution characteristics corresponding to the instruction sequence, the computing device obtains the first duration corresponding to each hardware parameter set based on the instruction type distribution characteristics and multiple hardware parameter sets, and uses the first duration corresponding to each hardware parameter set as the time consumption duration corresponding to each hardware parameter set. This process is also a possible implementation method for the computing device to obtain the time consumption duration of executing the instruction sequence under each hardware parameter set based on the instruction distribution characteristics and multiple hardware parameter sets.

[0171] For example, if a computing device obtains the cached instruction characteristics corresponding to an instruction sequence based solely on cached instructions within that sequence, it can then obtain the cache loss rate corresponding to that instruction sequence based on these cached instruction characteristics. Based on this cache loss rate and multiple hardware parameter sets, it can obtain a second duration for each hardware parameter set and use this second duration as the execution time for each hardware parameter set. This process is one possible implementation where the computing device obtains the execution time of the instruction sequence under each hardware parameter set based on the loss rate and multiple hardware parameter sets. The loss rate indicates the likelihood of execution time arising from instruction distribution characteristics. In this possible implementation, the instruction distribution characteristics are cached instruction characteristics, the loss rate is the cache loss rate, and the execution time is the second duration.

[0172] For example, when a computing device obtains the branch instruction characteristics corresponding to an instruction sequence based solely on the branch instructions within that sequence, it then obtains the branch loss rate based on these characteristics. Based on this loss rate and multiple hardware parameter sets, it obtains the third duration for each set of hardware parameters and uses this third duration as the execution time for each set. This process is one possible implementation where the computing device, based on the loss rate and multiple hardware parameter sets, obtains the execution time for each instruction sequence under each hardware parameter set. The loss rate indicates the likelihood of execution time arising from instruction distribution characteristics. In this possible implementation, the instruction distribution characteristics are branch instruction characteristics, the loss rate is the branch loss rate, and the execution time is the third duration.

[0173] The above process is illustrated by taking the example of a computing device independently obtaining the time duration corresponding to an instruction sequence based on any feature corresponding to the instruction sequence. In some embodiments, when the computing device obtains any two of the following features: instruction type distribution feature, cached instruction feature, and branch instruction feature corresponding to the instruction sequence, the computing device obtains the time duration corresponding to the instruction sequence based on these two features.

[0174] For example, when a computing device obtains the instruction type distribution characteristics and cached instruction characteristics corresponding to an instruction sequence, the computing device obtains a first duration corresponding to each hardware parameter set based on the instruction type distribution characteristics and multiple hardware parameter sets, and obtains a second duration corresponding to each hardware parameter set based on the cached instruction characteristics and multiple hardware parameter sets. The computing device then obtains the execution time corresponding to each hardware parameter set based on the first and second durations. This process is also a possible implementation of the computing device obtaining the execution time of the instruction sequence under each hardware parameter set based on the instruction distribution characteristics and multiple hardware parameter sets. The process of obtaining the execution time based on the first and second durations is similar to the process of obtaining the execution time based on the first, second, and third durations, and will not be described again in this embodiment.

[0175] For example, when the computing device obtains the instruction type distribution characteristics and branch instruction characteristics corresponding to the instruction sequence, it obtains the execution time corresponding to each hardware parameter set in a manner similar to that used in the above process when only the instruction type distribution characteristics and cached instruction characteristics corresponding to the instruction sequence are obtained. This process is also a possible implementation method for the computing device to obtain the execution time of the instruction sequence under each hardware parameter set based on the instruction distribution characteristics and multiple hardware parameter sets.

[0176] For example, when the computing device obtains the cached instruction characteristics and branch instruction characteristics corresponding to the instruction sequence, it obtains the execution time corresponding to each hardware parameter set in a manner similar to that used in the above process where only the instruction type distribution characteristics and cached instruction characteristics corresponding to the instruction sequence are obtained. This process is a possible implementation where the computing device obtains the execution time of the instruction sequence under each hardware parameter set based on the loss rate and multiple hardware parameter sets. The loss rate is used to indicate the probability of time consumption based on the instruction distribution characteristics. In this implementation, the instruction distribution characteristics include cached instruction characteristics and branch instruction characteristics, the loss rate includes cache loss rate and branch loss rate, and the execution time is the time obtained based on the second and third execution times.

[0177] 310. The computing device determines the set of hardware parameters with the shortest processing time as the target set of hardware parameters.

[0178] In this embodiment of the invention, the computing device sorts multiple hardware parameter sets in ascending order and determines the hardware parameter set that is first in the sorted order as the target hardware parameter set. Alternatively, the computing device sorts multiple hardware parameter sets in descending order and determines the hardware parameter set that is last in the sorted order as the target hardware parameter set. This embodiment of the invention does not limit the specific method used.

[0179] This step is one possible implementation of a computing device determining a target hardware parameter set based on the execution time of an instruction sequence under each hardware parameter set. This embodiment of the invention uses the example of a computing device determining a target hardware parameter set based on the execution time of an instruction sequence under each hardware parameter set. In some embodiments, the computing device obtains a hardware parameter set corresponding to the instruction distribution characteristics corresponding to the instruction sequence from a pre-prepared expert library, and determines this hardware parameter set as the target hardware parameter set. The expert library includes multiple hardware parameter sets and the instruction distribution characteristics corresponding to each hardware parameter set.

[0180] The hardware parameter adjustment method provided in this invention obtains the instruction distribution characteristics corresponding to the instruction sequence. These characteristics are related to the execution time of the instruction, which in turn is related to the hardware parameters. Therefore, based on the instruction distribution characteristics and multiple hardware parameter sets, the execution time of the instruction sequence under each hardware parameter set can be obtained. Then, based on this execution time, a target hardware parameter set is determined from the multiple hardware parameter sets. Since this method determines the target hardware parameter set based on the instruction distribution characteristics of the instruction sequence, and these characteristics are applicable to different architectures (such as different CPU microarchitectures), this method can be applied to different architectures and has strong generalization capabilities. Furthermore, this method calculates the execution time based on the instruction distribution characteristics, without simulating the execution of the instruction sequence, resulting in shorter execution time and higher efficiency in hardware parameter adjustment.

[0181] The foregoing details the process of determining the target hardware parameter set. After determining the target hardware parameter set, the computing device schedules the execution of the aforementioned computing tasks based on this set to improve their efficiency. Specifically, if the target hardware parameter set includes hardware parameters of computing nodes in a distributed system, or hardware parameters of servers in a cloud service system, the computing device will call upon computing nodes or cloud servers matching the target hardware parameter set to execute the computing tasks. This ensures that the task is executed using the device with the shortest execution time, thereby improving the overall efficiency of the computing task.

[0182] If the aforementioned set of multiple hardware parameters includes the hardware parameters of the hardware in the electronic device, the computing device adjusts the hardware parameters of the hardware in the electronic device according to the target set of hardware parameters, and uses the adjusted electronic device to execute the aforementioned computing task. When the electronic device is a cloud resource, the computing device adjusts the hardware parameters of the hardware in the electronic device online according to the target set of hardware parameters, and uses the adjusted cloud resources to execute the aforementioned computing task. This enables the hardware parameters to be adjusted in real time according to different computing tasks, thereby improving the hardware's execution efficiency for different computing tasks.

[0183] The method of the present invention has been described above, and the apparatus of the present invention will be described below. It should be understood that the apparatus described below has any of the functions of the computing device in the above method. The hardware parameter adjustment method provided by the embodiments of the present invention has been described in detail above with reference to Figures 1 to 8. Based on the same inventive concept, the hardware parameter adjustment apparatus provided by the embodiments of the present invention will be described below with reference to Figure 9. It should be understood that the technical features described in the method embodiments are also applicable to the following apparatus embodiments.

[0184] Referring to Figure 9, an embodiment of the present invention provides a hardware parameter adjustment device, which includes:

[0185] The feature acquisition module 901 is used to acquire the instruction distribution features corresponding to the instruction sequence for the computing service, and the instruction distribution features indicate the distribution of instruction types.

[0186] The duration acquisition module 902 is used to acquire the execution time of the instruction sequence under each hardware parameter set based on the instruction distribution characteristics and multiple hardware parameter sets, wherein each hardware parameter set includes the parameter value of at least one parameter of the hardware.

[0187] The determination module 903 is used to determine the target hardware parameter set from multiple hardware parameter sets based on the execution time of the instruction sequence under each hardware parameter set.

[0188] In some embodiments, the feature acquisition module 901 includes:

[0189] The type feature acquisition unit is used to acquire the instruction type distribution features corresponding to the instruction sequence based on the instruction type to which each instruction in the instruction sequence belongs. The instruction type distribution features indicate the distribution of instructions of different instruction types in the instruction sequence.

[0190] In some embodiments, the feature acquisition module 901 includes:

[0191] The cache feature acquisition unit is used to acquire cache instruction features corresponding to the instruction sequence based on the cache instructions included in the instruction sequence. The cache instruction features indicate the quantity distribution and position distribution of cache instructions in the instruction sequence.

[0192] In some embodiments, the feature acquisition module 901 includes:

[0193] The branch feature acquisition unit is used to acquire the branch instruction features corresponding to the instruction sequence based on the branch instructions included in the instruction sequence. The branch instruction features indicate the distribution of the number of branch instructions in the instruction sequence.

[0194] In some embodiments, the branch instruction features described above also indicate the positional distribution of branch instructions in the instruction sequence.

[0195] In some embodiments, the duration acquisition module 902 is used for:

[0196] The distribution characteristics of non-computational instructions are processed by neural networks to obtain the corresponding loss rate. Based on the loss rate and multiple hardware parameter sets, the execution time of the instruction sequence under each hardware parameter set is obtained. The loss rate indicates the probability of time consumption based on instruction distribution characteristics.

[0197] The neural network is trained based on historical instruction sequences and corresponding historical operation information.

[0198] In some embodiments, the aforementioned multiple hardware parameter sets include hardware parameters of computing nodes in a distributed system, or, the multiple hardware parameter sets include hardware parameters of hardware in an electronic device, or, the multiple hardware parameter sets include hardware parameters of servers in a cloud service system.

[0199] It should be understood that the hardware parameter adjustment device corresponds to the computing device in the above method embodiments. The modules in the device and the other operations and / or functions described above are for implementing various steps and methods implemented by the computing device in the method embodiments. For specific details, please refer to the above method embodiments. For the sake of brevity, they will not be repeated here.

[0200] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code that can be executed by a processor in a computing device to perform the hardware parameter adjustment method in the above embodiments. For example, the computer-readable storage medium is a non-transitory computer-readable storage medium, such as read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0201] This invention also provides a computer program product or computer program, which includes program code and computer instructions stored in a computer-readable storage medium. A processor in a computing device reads the program code from the computer-readable storage medium and executes the program code, causing the computing device to perform the above-described hardware parameter adjustment method.

[0202] In addition, this embodiment of the invention also provides an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute the hardware parameter adjustment methods in the above-described method embodiments.

[0203] In this embodiment, the apparatus, device, computer-readable storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding methods provided above, and will not be repeated here.

[0204] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the hardware parameter adjustment method embodiment provided in the above embodiments belongs to the same concept, and its specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0205] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0206] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0207] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0208] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0209] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0210] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0211] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the sensitive words involved in this application were obtained with full authorization.

[0212] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0213] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for adjusting hardware parameters, characterized in that, The method includes: For a given instruction sequence corresponding to a computing service, obtain the instruction distribution characteristics corresponding to the instruction sequence, wherein the instruction distribution characteristics indicate the distribution of instruction types; Based on the instruction distribution characteristics and multiple hardware parameter sets, the execution time of the instruction sequence under each hardware parameter set is obtained respectively, wherein each hardware parameter set includes the parameter value of at least one hardware parameter; Based on the execution time of the instruction sequence under each set of hardware parameters, a target hardware parameter set is determined from the plurality of hardware parameter sets.

2. The method according to claim 1, characterized in that, The step of obtaining the instruction distribution features corresponding to the instruction sequence includes: Based on the instruction type to which each instruction in the instruction sequence belongs, the instruction type distribution feature corresponding to the instruction sequence is obtained. The instruction type distribution feature indicates the distribution of instructions of different instruction types in the instruction sequence.

3. The method according to claim 2, characterized in that, The step of obtaining the execution time of the instruction sequence under each set of hardware parameters based on the instruction distribution characteristics and multiple sets of hardware parameters includes: The time taken to execute the instruction sequence under each set of hardware parameters is calculated based on the instruction type distribution characteristics and the multiple sets of hardware parameters.

4. The method according to any one of claims 1 to 3, characterized in that, The step of obtaining the instruction distribution features corresponding to the instruction sequence includes: Based on the cached instructions included in the instruction sequence, the cached instruction features corresponding to the instruction sequence are obtained, and the cached instruction features indicate the quantity distribution and position distribution of the cached instructions in the instruction sequence.

5. The method according to any one of claims 1 to 4, characterized in that, The step of obtaining the instruction distribution features corresponding to the instruction sequence includes: Based on the branch instructions included in the instruction sequence, the branch instruction features corresponding to the instruction sequence are obtained, and the branch instruction features indicate the quantity distribution of branch instructions in the instruction sequence.

6. The method according to claim 5, characterized in that, The branch instruction feature also indicates the positional distribution of branch instructions in the instruction sequence.

7. The method according to any one of claims 1 to 6, characterized in that, The step of obtaining the execution time of the instruction sequence under each set of hardware parameters based on the instruction distribution characteristics and multiple sets of hardware parameters includes: The distribution characteristics of non-computational instructions are processed based on a neural network to obtain a corresponding loss rate. Based on the loss rate and the multiple hardware parameter sets, the execution time of the instruction sequence under each hardware parameter set is obtained. The loss rate is used to indicate the probability of time consumption based on the instruction distribution characteristics. The neural network is trained based on historical instruction sequences and corresponding historical operation information.

8. The method according to any one of claims 1 to 7, characterized in that, The multiple sets of hardware parameters include the hardware parameters of computing nodes in a distributed system, or the multiple sets of hardware parameters include the hardware parameters of hardware in an electronic device, or the multiple sets of hardware parameters include the hardware parameters of servers in a cloud service system.

9. A hardware parameter adjustment device, characterized in that, The device includes: The feature acquisition module is used to acquire the instruction distribution features corresponding to the instruction sequence for the computing service, wherein the instruction distribution features indicate the distribution of instruction types; The duration acquisition module is used to acquire the execution time of the instruction sequence under each set of hardware parameters based on the instruction distribution characteristics and multiple sets of hardware parameters, wherein each set of hardware parameters includes the parameter value of at least one parameter of the hardware. The determination module is used to determine the target hardware parameter set from the plurality of hardware parameter sets based on the execution time of the instruction sequence under each set of hardware parameters.

10. The apparatus according to claim 9, characterized in that, The feature acquisition module is used for: Based on the instruction type to which each instruction in the instruction sequence belongs, the instruction type distribution feature corresponding to the instruction sequence is obtained. The instruction type distribution feature indicates the distribution of instructions of different instruction types in the instruction sequence.

11. The apparatus according to claim 10, characterized in that, The duration acquisition module is used for: The time taken to execute the instruction sequence under each set of hardware parameters is calculated based on the instruction type distribution characteristics and the multiple sets of hardware parameters.

12. The apparatus according to any one of claims 8 to 11, characterized in that, The feature acquisition module is used for: Based on the cached instructions included in the instruction sequence, the cached instruction features corresponding to the instruction sequence are obtained, and the cached instruction features indicate the quantity distribution and position distribution of the cached instructions in the instruction sequence.

13. The apparatus according to any one of claims 8 to 12, characterized in that, The feature acquisition module is used for: Based on the branch instructions included in the instruction sequence, the branch instruction features corresponding to the instruction sequence are obtained, and the branch instruction features indicate the quantity distribution of branch instructions in the instruction sequence.

14. The apparatus according to claim 13, characterized in that, The branch instruction feature also indicates the positional distribution of branch instructions in the instruction sequence.

15. The apparatus according to any one of claims 9 to 14, characterized in that, The duration acquisition module is used for: The distribution characteristics of non-computational instructions are processed based on a neural network to obtain a corresponding loss rate. Based on the loss rate and the multiple hardware parameter sets, the execution time of the instruction sequence under each hardware parameter set is obtained. The loss rate is used to indicate the probability of time consumption based on the instruction distribution characteristics. The neural network is trained based on historical instruction sequences and corresponding historical operation information.

16. The apparatus according to any one of claims 9 to 15, characterized in that, The multiple sets of hardware parameters include the hardware parameters of computing nodes in a distributed system, or the multiple sets of hardware parameters include the hardware parameters of hardware in an electronic device, or the multiple sets of hardware parameters include the hardware parameters of servers in a cloud service system.

17. A computing device, characterized in that, The computing device includes a processor and a memory, the processor being configured to execute at least one piece of program code stored in the memory to enable the computing device to perform the method as described in any one of claims 1 to 8.

18. A computing device cluster, characterized in that, It includes at least one computing device, each computing device including a processor and memory; The processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device to cause the computing device cluster to perform the hardware parameter adjustment method as described in any one of claims 1 to 8.

19. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device, the computing device performs the hardware parameter adjustment method as described in any one of claims 1 to 8.

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