Control method and apparatus, and chip, electronic device and server

Abstract

The present application is applied to the technical field of storage. Provided are a control method and apparatus, and a chip, an electronic device and a server. The method comprises: acquiring a data access instruction stream of a processor under a target service, and identifying instruction features of the instruction stream, wherein the instruction features may comprise the proportions of different types of instructions, such as loading, storage, replacement and locking, the instruction features can reflect features of the current computing service of the processor (e.g., whether there are more read operations or more write operations); and then adjusting parameters of a register on the basis of the instruction features, such that the adjusted parameters of the register are adapted to the service currently executed by the processor.

Description

Control methods, devices, chips, electronic equipment, and servers

[0001] This application claims priority to Chinese Patent Application No. 202411188888.6, filed on August 27, 2024, entitled "Control Method, Apparatus, Chip, Electronic Device and Server", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of storage technology, and in particular to a control method, device, chip, electronic device, and server. Background Technology

[0003] Registers are internal storage units within the processor. When the processor needs to execute an instruction or access data, it first checks whether the corresponding instruction or data is stored in the register. If the corresponding data is stored in the register (i.e., a register hit), the processor will directly retrieve the data from the register. Only when the corresponding data is not in the register will the processor read the data from the cache or main memory.

[0004] The operating mode of a register affects its hit rate. For example, registers with prefetch functionality can improve the hit rate by predicting subsequent data accesses and retrieving data from the cache or memory in advance. Furthermore, registers have various prefetch modes, such as prefetching according to storage order or access frequency. Different prefetch modes and parameters, such as the prefetch window size, result in different prefetched data.

[0005] Currently, processors are used in a wide range of business scenarios, and these scenarios have different data access requirements. However, the parameters of current registers are usually fixed, making them unable to adapt to different business scenarios and resulting in a low register data hit rate. Summary of the Invention

[0006] In view of this, this application provides a control method, apparatus, chip, electronic device, and server. By acquiring the processor's instruction stream, the method identifies the instruction characteristics of the instruction stream, which reflect the characteristics of the processor's current computational tasks. Then, based on the instruction characteristics, the method adjusts the register parameters to adapt them to the tasks currently being executed by the processor.

[0007] In a first aspect, a control method is provided, applied to a processor, the method comprising: acquiring an instruction stream for running a target service, wherein the processor's registers are in a first operating mode; determining a second operating mode of the register corresponding to the target service based on the instruction characteristics of the instruction stream; and adjusting the registers from the first operating mode to the second operating mode.

[0008] In the above scheme, the instruction characteristics of the processor's instruction stream can reflect the characteristics of the target business being executed by the processor, such as whether the current business involves more read operations or more write operations. Specifically, the instruction stream can be sent by the processor core to storage devices such as registers, caches, or main memory, or it can be sent by the processor to external devices, such as remote servers or storage devices including databases. Furthermore, by adjusting the register's operating mode according to the instruction characteristics, making the adjusted register operating mode suitable for the business being executed by the current processor, the register data hit rate can be improved, thus increasing data access efficiency.

[0009] In conjunction with the first aspect, in some implementations, the method further includes: determining a first performance prediction result for running the target service in the first operating mode based on instruction characteristics and a first operating mode; selecting at least one candidate operating mode from the operating modes of the registers, and determining a second performance prediction result for running the target service in the at least one candidate operating mode; determining the candidate operating mode with the highest second performance prediction result from the at least one candidate operating mode as the second operating mode, and the second performance prediction result of the second operating mode is higher than the first performance prediction result.

[0010] In the above scheme, the processor determines the second operating mode of the registers that need adjustment by predicting the performance of different register parameters under the target service and selecting the register parameters with higher predicted performance under the target service as the register parameters corresponding to the second operating mode. Furthermore, by adjusting the register operating mode according to instruction characteristics, the adjusted register operating mode is adapted to the service being executed by the current processor, which can improve register data hit rate and data access efficiency.

[0011] In conjunction with the first aspect, in some implementations, the method further includes: obtaining the first register parameter when the register is in the first working mode; inputting the instruction characteristics and the first register parameter into the performance prediction model to obtain the first performance prediction result.

[0012] In the above scheme, the processor obtains the performance of different register parameters under the target service through a performance prediction model. Instruction characteristics and register parameters are input into the performance prediction model to obtain the corresponding performance prediction results. For example, the performance prediction model can be any prediction model based on multinomial regression, multilayer perceptron, convolutional neural network, etc. Furthermore, based on the performance prediction results, register parameters with better performance can be predicted in advance. Then, the register parameters are adjusted to these better-performing parameters, making the adjusted register operating mode suitable for the service executed by the current processor. This improves register data hit rate and data access efficiency.

[0013] In conjunction with the first aspect, in some implementations, the method further includes: collecting the actual performance results of the target service; and updating the performance prediction model based on the actual performance results and the second register parameters corresponding to the second working mode.

[0014] In the above scheme, after the processor updates the register parameter configuration according to the optimal register parameters, it can also monitor the processor's business operation to obtain the actual performance parameters. Based on the actual performance parameters and the register parameters actually applied to the current registers, the aforementioned performance prediction model is updated to obtain the performance prediction model with updated model parameters. Therefore, in subsequent performance prediction processes, the performance prediction model with updated model parameters can obtain more accurate performance prediction results.

[0015] In conjunction with the first aspect, in some implementations, instruction characteristics include the distribution of different types of instructions in the instruction stream. The types of instructions include one or more of the following: load instructions, store instructions, replace instructions, lock instructions, data move instructions, arithmetic instructions, logical instructions, comparison instructions, branch instructions, control flow instructions, and stack operation instructions.

[0016] In the above scheme, instruction characteristics can be the distribution of different types of instructions in the instruction stream, such as their proportion in the instruction stream. Furthermore, instruction characteristics can reflect the data access characteristics of the business being executed by the processor. Subsequently, appropriate register parameters can be obtained by adjusting the instruction characteristics, making the adjusted register operating mode suitable for the business being executed by the current processor, thereby improving register data hit rate and data access efficiency.

[0017] In conjunction with the first aspect, in some implementations, the first performance prediction result and the second performance prediction result include one or more of the following: register data hit rate, processor pipeline efficiency, and database transaction response time.

[0018] In the above scheme, the performance prediction result can be any one or a combination of processor performance, storage performance, and database-related performance. The performance prediction result can be used to select the register parameters that are more suitable for the processor to run the current business. Then, the register parameters are adjusted to parameters with better performance, so that the adjusted register working mode is suitable for the business executed by the current processor, which can improve the register data hit rate and improve data access efficiency.

[0019] Secondly, this application provides a control device, including an acquisition unit, a determination unit, and an adjustment unit. The acquisition unit is used to acquire the instruction stream under the execution of a target service, wherein the processor's registers are in a first working mode. The determination unit is used to determine the second working mode of the register corresponding to the target service based on the instruction characteristics of the instruction stream. The adjustment unit is used to adjust the register from the first working mode to the second working mode.

[0020] In conjunction with the second aspect, in some implementations, the determining unit is further configured to determine a first performance prediction result of the target service running in the first operating mode based on instruction characteristics and the first operating mode; the determining unit is further configured to select at least one candidate operating mode from the operating modes of the register, and determine a second performance prediction result of the target service running in the at least one candidate operating mode; the determining unit is further configured to determine the candidate operating mode with the highest second performance prediction result from the at least one candidate operating mode as the second operating mode, and the second performance prediction result of the second operating mode is higher than the first performance prediction result.

[0021] In conjunction with the second aspect, in some implementations, the acquisition unit is also used to acquire the first register parameter when the register is in the first working mode; the determination unit is also used to input the instruction characteristics and the first register parameter into the performance prediction model to obtain the first performance prediction result.

[0022] In conjunction with the second aspect, in some implementations, the acquisition unit is also used to collect the actual performance results of the target service; the adjustment unit is also used to update the performance prediction model based on the actual performance results and the second register parameters corresponding to the second working mode.

[0023] In conjunction with the second aspect, in some implementations, instruction characteristics include the distribution of different types of instructions in the instruction stream. The types of instructions include one or more of the following: load instructions, store instructions, replace instructions, lock instructions, data move instructions, arithmetic instructions, logical instructions, comparison instructions, branch instructions, control flow instructions, and stack operation instructions.

[0024] In conjunction with the second aspect, in some implementations, the first performance prediction result and the second performance prediction result include one or more of the following: register data hit rate, processor pipeline efficiency, and database transaction response time.

[0025] Thirdly, this application provides a chip including a processor and a data interface, wherein the processor reads instructions stored in a memory through the data interface to execute the method described in the first aspect.

[0026] Fourthly, this application provides an electronic device including a processor and a memory, wherein the memory is used to store instructions and the processor is used to execute the instructions, and when the processor executes the instructions, it performs the method described in the first aspect.

[0027] Fifthly, this application provides a server including a processor and a memory, the memory for storing instructions, and the processor for executing the instructions, wherein when the processor executes the instructions, it performs the method described in the first aspect.

[0028] In a sixth aspect, this application provides a computer-readable storage medium storing instructions that, when executed on an electronic device, perform the method described in the first aspect.

[0029] In a seventh aspect, this application provides a computer program product including computer instructions, which, when executed by an electronic device, cause the electronic device to perform the method described in the first aspect. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0031] Figure 1 is a schematic diagram of the structure of an electronic device storage system provided in an embodiment of this application;

[0032] Figure 2 is a schematic diagram of a control device provided in an embodiment of this application;

[0033] Figure 3 is an interactive schematic diagram of a control method provided in an embodiment of this application;

[0034] Figure 4 is a flowchart illustrating a control method provided in an embodiment of this application;

[0035] Figure 5 is a flowchart illustrating another control method provided in an embodiment of this application;

[0036] Figure 6 is a schematic diagram of another control device provided in an embodiment of this application;

[0037] Figure 7 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0038] The illustrative embodiments of this application include, but are not limited to, control methods, devices, chips, electronic devices, and servers.

[0039] First, the storage architecture of the electronic device involved in the embodiments of this application will be introduced. As shown in Figure 1, the processor integrates at least one register (also called a register set). The processor accesses data from the register set relatively quickly, but the storage space of the register set and the number of registers it contains are limited. It is usually only used to store temporary data and instructions during instruction execution. When there is no data that the processor needs to access in the register set, the processor will send an instruction stream to the cache to read the data from the cache. Further, when there is no data that the processor needs to access in the cache, the processor will retrieve the data that needs to be accessed from memory. Here, the cache is a high-speed memory between the registers and memory, used to temporarily store data and instructions that will be used by the processor. Memory is the main memory of the computer. The processor accesses data from memory relatively slowly, but memory has a larger capacity and can store more data and instructions.

[0040] Users can modify the operating mode of the register bank by adjusting its parameter settings. For example, adjusting the `in_order_ctlr_el1` parameter can change the execution order of received data access instructions, or adjusting the relevant parameters of `adpp_l1v_mop_el1` can change the register's prefetch mode.

[0041] However, different business scenarios for processor applications place different requirements on register operating modes. For example, the business being processed by the processor may involve a large number of read operations, a large number of write operations, or a large number of computational operations. In read-heavy scenarios, registers need to prefetch a large amount of data from the cache or memory. Conversely, in computation-heavy scenarios, registers need to be able to process data access instructions in parallel.

[0042] However, current processors cannot dynamically adjust the register's operating mode according to the business scenario. This results in register operating modes being unsuitable for the current business scenario, and the execution order of instructions issued by the processor to the registers being suboptimal, thus reducing the processor's execution efficiency. Alternatively, it may cause the registers to fail to prefetch the data required by the processor, forcing the processor to read data from the cache or memory, increasing data access time and reducing processor execution efficiency.

[0043] To improve the efficiency of processor data access, this application provides a control method that acquires the processor's instruction stream and identifies its instruction characteristics. These instruction characteristics include the proportion of different instruction types, such as load, store, replace, lock, data move, arithmetic, logic, comparison, branch, control flow, stack operations, and input / output (I / O) instructions. The instruction characteristics reflect the characteristics of the processor's current computational tasks (e.g., whether there are more read or write operations). Then, register parameters are adjusted based on these instruction characteristics to adapt to the current processor's execution needs.

[0044] For example, the instruction stream issued by the processor can specifically be a stream of instructions sent by the processor core to storage devices such as registers, caches, or memory, or it can be a stream of instructions sent by the processor to external devices, such as remote servers or storage devices including databases. Furthermore, a higher proportion of loaded instructions in the processor's instruction stream indicates that there are many read operations in the currently executing task. This allows adjustments to the register prefetching parameters, such as increasing the prefetch window size or decreasing the threshold for triggering prefetching, to enable registers to prefetch data from caches or memory more quickly and to prefetch more data into registers, thereby improving register hit rate and increasing the processor's data access efficiency.

[0045] If a processor's instruction stream contains a high proportion of storage instructions (also known as write instructions), the order in which registers process the instruction stream can be adjusted. For example, multiple write operations can be merged, thereby reducing the number of data writes to memory. Since memory write operations have high latency, reducing write operations can decrease waiting time, thus improving overall response speed. Alternatively, if a processor's instruction stream contains a high proportion of write instructions, the register write-back policy parameters can be adjusted to reduce the number of memory write operations, thereby improving performance.

[0046] In some embodiments, the processor can determine the register parameters to be adjusted in the following manner: The processor can obtain the parameters of the current register configuration (hereinafter referred to as the initial register parameters, and as an instance of the first register parameters). Based on the initial register parameters and the instruction characteristics of the instruction flow, the processor uses a performance prediction model to predict the performance of the service running under the current workload and the initial register parameters. For example, the performance prediction result can be one or more performance parameters such as register data hit rate and processor pipeline efficiency. Then, based on the performance prediction result and the initial register parameters, the processor adjusts the initial register parameters through Bayesian optimization to obtain a set of better register parameters (i.e., the optimal register parameters, and as an instance of the second register parameters), wherein the performance prediction result obtained by the prediction model for the optimal register parameters is better than the performance prediction result for the initial register parameters. The processor then adjusts the register parameters to the optimal register parameters.

[0047] Optionally, the processor can perform multiple register parameter optimizations and set a cutoff condition for the optimization. When the cutoff condition is met, the currently optimized register parameters are taken as the optimal register parameters. For example, the cutoff condition could be that the number of optimizations reaches a preset number. Alternatively, the cutoff condition could be that the performance prediction result corresponding to the register parameters obtained in this optimization (hereinafter referred to as the optimization performance prediction result) differs from the previous optimization performance prediction result by a preset difference. This means that the current optimization does not significantly improve register performance, and a relatively good register parameter has been obtained. Therefore, the register parameters obtained in this round of optimization can be taken as the optimal register parameters.

[0048] In other embodiments, after updating the register parameter configuration based on the optimal register parameters, the processor can also monitor the processor's operational status to obtain actual performance parameters, such as the register data hit rate and processor pipeline efficiency during actual operation. Then, based on the actual performance parameters and the register parameters currently being used (i.e., the optimal register parameters), the aforementioned performance prediction model is updated to obtain a performance prediction model with updated parameters. Consequently, in subsequent performance prediction processes, the performance prediction model with updated parameters can obtain more accurate performance prediction results.

[0049] The electronic devices to which the aforementioned processors are used can be mobile phones, tablets, wearable devices, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), or dedicated cameras (such as SLR cameras and point-and-shoot cameras). Electronic devices can also be physical servers or cloud devices, such as x86 servers, ARM servers, etc., or virtual machines (VMs) implemented based on general-purpose physical servers combined with network functions virtualization (NFV) technology. A virtual machine refers to a complete computer system simulated by software, possessing full hardware system functionality and running in a completely isolated environment. This application does not impose any restrictions on the specific type of the electronic device.

[0050] The structure of a control system provided in this application is described below. For example, the control system 200 may include a self-optimization module 210, which is used to determine the current service type being run by the processor based on the processor's instruction flow. The self-optimization module 210 also obtains the initial register parameters of the current registers, optimizes the register parameters according to the current service type to obtain the optimal register parameters suitable for the currently running service, and then adjusts the register's operating mode based on the optimal register parameters.

[0051] In some embodiments, the control system 200 may further include a self-learning module 220, which is used to collect actual performance parameters of the processor when it is actually running business, and then update the self-optimization module 210 based on the actual performance parameters so that the self-optimization module 210 can obtain more accurate optimal register parameters.

[0052] In some embodiments, the structure of the control system 200 may also refer to FIG2. As shown in FIG2, the self-optimization module 210 of the control system 200 may include a data acquisition and monitoring submodule 211, a performance prediction submodule 212, a self-optimization submodule 213, and a configuration activation submodule 214. The self-learning module 220 may include a performance monitoring submodule 221 and an incremental feedback submodule 222.

[0053] The acquisition and monitoring submodule 211 acquires the instruction stream of the processor under the currently running service (as an instance of the target service) and the initial parameters in the current register working mode.

[0054] Specifically, the instruction stream can be a stream of instructions sent by the processor core to registers, cache, or memory, or it can be a stream of instructions sent by the processor's electronic device to other external devices. This application does not impose specific limitations on the type of instruction stream. For example, Figure 2 illustrates the example of the processor sending an instruction stream to the cache.

[0055] The data acquisition and monitoring submodule 211 will also analyze the instruction characteristics of the acquired instruction stream and send the instruction characteristics and initial register parameters to the performance prediction submodule 212. The instruction characteristics include the proportion of different instruction types such as load, store, replace, lock, data move, arithmetic, logic, comparison, branch, control flow, stack operations, and I / O.

[0056] Furthermore, the data acquisition and monitoring submodule 211 will also output instruction features to the incremental feedback submodule 222, so that the incremental feedback submodule 222 updates the performance prediction model in the performance prediction submodule 212.

[0057] The performance prediction submodule 212, based on a pre-trained performance prediction model, predicts the performance of the current instruction stream and initial register parameters using the input instruction features and initial register parameters. For example, the performance prediction result can be one or more parameters such as register data hit rate, processor pipeline efficiency, and transaction response time of the database associated with the processor's business operations. The performance prediction model can be any prediction model based on multinomial regression, multilayer perceptron (MLP), convolutional neural network (CNN), or similar models.

[0058] The self-optimization submodule 213, based on the performance prediction results corresponding to the initial register parameters and the initial register parameters, generates a set of register parameters with better performance prediction results (i.e., optimal register parameters) through Bayesian optimization, and sends the optimal register parameters to the configuration activation submodule 214.

[0059] Bayesian optimization refers to using a surrogate function to replace the objective function relating register parameters and performance prediction results. Then, by sampling the surrogate function, the optimal register parameters corresponding to the optimal performance prediction result within the surrogate function are gradually found. The surrogate function can be a function generated based on algorithms such as Gaussian processes, random forests, or reinforcement learning (e.g., deep Q-network, DQN).

[0060] In other words, the self-optimization submodule 213 first determines the modified register parameters within the range of available working parameters for the register, and then returns the modified register parameters to the performance prediction submodule 212, which predicts the performance of the register parameters for this round. The self-optimization submodule 213 then compares the performance prediction result of the current round with the performance prediction result of the previous round to determine the register parameters to be optimized in the next round. For example, if the performance prediction result of the current round is poor, the next round will not select a value close to the current round's value, but will select a parameter value from another range as the optimized register parameters. This process is repeated multiple times until the final generated register parameters are the optimal register parameters.

[0061] Among these, the performance prediction result of the optimal register parameters is the register parameter with the highest performance prediction result among all groups of register parameters during the optimization process, and the performance prediction result of the optimal register parameters is also higher than that of the initial register parameters. The highest performance prediction result can be one or more of the following: highest register data hit rate, highest processor pipeline efficiency, and shortest database transaction response time.

[0062] Optionally, the self-optimization submodule 213 can also set an optimization cutoff condition. The register parameters obtained when the optimization cutoff condition is met are the optimal register parameters. The cutoff condition can be one or more of the following: the number of optimization attempts reaches a preset number, or the difference between the performance prediction result obtained from the register parameters in this round of optimization and the performance prediction result in the previous round of optimization is less than a preset difference.

[0063] The configuration activation submodule 214 applies the optimal register parameters obtained by the self-optimization submodule 213 to the current register, so that the register operating mode is suitable for the business being run by the current processor. Furthermore, the configuration activation submodule 214 can also send the optimal register parameters to the incremental feedback submodule 222.

[0064] The performance monitoring submodule 221 is used to acquire the actual operating status of the current business load and obtain actual performance parameters, such as the hit rate of register data and processor pipeline efficiency during actual operation. Then, the actual performance parameters are sent to the incremental feedback submodule 222.

[0065] The incremental feedback submodule 222 performs incremental learning and optimization of the performance prediction model of the performance prediction module by acquiring instruction characteristics, the optimal register parameters currently used in the registers, and the collected actual performance parameters. Specifically, the incremental feedback submodule 222 compares the prediction results of the performance prediction model with the actual performance parameters, analyzes the differences between the two, identifies the sources of prediction errors in the performance prediction model, and determines whether there are systematic biases or random fluctuations. Then, the incremental feedback submodule 222 incrementally updates the performance prediction model based on the collected data and error analysis results. For example, the incremental feedback submodule 222 can adjust the model parameters of the performance prediction model and update the model weights.

[0066] Furthermore, the control system 200 provided in this application can identify the current service type of the processor through the instruction stream under the target service, determine the data access requirements, and then adjust the register parameters to adapt to the service being run by the processor, thereby improving the register data hit rate and data access efficiency. Moreover, the control system 200 will also adjust the prediction model for the performance parameters of the predicted register parameters based on the actual performance parameters of the processor during operation, making the subsequent prediction process more accurate.

[0067] Based on the control system 200 shown in Figure 2, the interaction process between the various modules in the control system 200 can also be seen in Figure 3.

[0068] As shown in Figure 3, the cache can send the acquired instruction stream to the performance prediction model, and the register can send the current initial register parameters to the performance prediction model. For example, Figure 3 shows a partial instruction stream in one scenario, where the unsigned bit field move (UBFM) instruction is used to extract and move bit fields in the register, x19 is the destination register, x20 is the source register, #61 indicates extracting from the 62nd bit of x20, and #61 indicates extracting a 61-bit field. Add instructions, such as "Add x20,x20,#0x1", add the current value of register x20 to the immediate value 0x1 (i.e., decimal 1).

[0069] The performance prediction model, based on a pre-trained model, predicts the performance of the current instruction stream and initial register parameters using the instruction characteristics of the input instruction stream and the initial register parameters. See the description of the aforementioned performance prediction submodule 212 for details. Then, based on the performance prediction results and the initial register parameters, the register parameters are optimized. The iterative optimizer for this optimization can be any of Random Forest, Strongest Learning, or Gaussian Process. See the relevant description of the aforementioned self-optimization submodule 213 for details.

[0070] The optimal register parameters obtained through optimization can be used for register parameter configuration, i.e., hot-activated optimal register parameters. Furthermore, after obtaining the optimal register parameters, the performance prediction model of the performance prediction module can be incrementally optimized using the acquired instruction characteristics, the optimal register parameters, and the collected actual performance parameters. For details, please refer to the relevant description of the aforementioned self-optimization submodule 213.

[0071] For example, register parameters may include: parameters that adjust the operating mode of the bus interface unit (BIU) control register (e.g., biu_ctlr_el1), such as changing the BIU control register cache coherency, error handling, and other operating modes; parameters that control the Level 1 data prefetching (ADP) behavior of the Load / Store Unit (LSU) (e.g., lsu_l1adpctlr_el1); parameters that control the timeout behavior of the L2 cache (e.g., l2_to_ctlr_el1); parameters that enable or disable the L2 cache's temporary storage function (e.g., l2stashen_el1); parameters that control the behavior of the CPU performance counters (e.g., cpuprefctlr_el1); and parameters that control the Level 1 virtual memory operation prefetcher (ADP) (e.g., adpp_l1v_mop_el1), etc.

[0072] To address the aforementioned problem of slow data access efficiency in processors, this application provides a control method that can be applied to processors in electronic devices. The control method provided in this application is described in detail below. As shown in Figure 4, the control method may include the following steps:

[0073] S410: Obtain the instruction stream of the processor while running the target service.

[0074] When a processor executes a task, it needs to access data from storage devices, which may include registers, cache, or main memory, or one or more of these. The processor's registers operate in its first operating mode. The instruction stream of the processor during the execution of a target task is used to read, move, or write data to storage devices. Specifically, the instruction stream sent by the processor core to any of the processor's internal registers, cache, or main memory reflects the processor's current data access needs. Alternatively, the instruction stream can also be a stream of instructions sent by the processor to other external devices. For example, the electronic device to which the processor belongs can send instruction streams to other computing devices or storage devices; these instruction streams can also reflect the characteristics of the task currently being executed by the processor.

[0075] S420: Based on the instruction characteristics of the instruction stream, determine the second operating mode of the register corresponding to the processor's workload.

[0076] The processor also extracts instruction characteristics from the instruction stream, such as the proportion of different types of instructions like load, store, replace, and lock. By analyzing the proportion of each instruction, the processor can determine the data access needs of its current workload, such as whether there are more write or read operations. Furthermore, corresponding register operating modes are available for different data access needs. When registers operate in the second operating mode determined by the current instruction characteristics, the register's operating mode can adapt to the processor's current workload, potentially improving the processor's performance.

[0077] For example, the operating mode of a register can be determined by register parameters, such as the execution order of data access instructions and the register prefetching mode (e.g., prefetch window size, prefetch range). If the processor's current workload involves many read operations, the register can be adjusted to a read-heavy operating mode, for example, by increasing the register prefetch window size or decreasing the threshold for triggering prefetching. Conversely, if the processor's current workload involves many write operations, the register can be adjusted to a write-heavy operating mode, for example, by adjusting the order in which the register processes the instruction stream, such as merging multiple write operations, thereby reducing the number of data writes to the memory device.

[0078] In some embodiments, the processor determines the second operating mode corresponding to the processor's business through a self-optimization method. Specifically, the processor can obtain the parameters of the current register configuration, that is, the register parameters corresponding to the current first operating mode (denoted as the initial register parameters). Based on the initial register parameters and the instruction characteristics of the instruction stream, the processor predicts the performance under the current business load through a performance prediction model (as an instance of the first performance prediction result). Then, based on the performance prediction result and the initial register parameters, the processor adjusts the initial register parameters to obtain a set of better register parameters (denoted as the optimal register parameters).

[0079] For example, the process of generating optimal register parameters for the processor can involve selecting at least one candidate register parameter from the available working parameters of the register, determining the performance prediction results corresponding to each candidate register parameter, and selecting the candidate register parameter with the highest performance prediction result as the optimal register parameter. The highest performance prediction result includes one or more parameters such as the highest register data hit rate, the highest processor pipeline efficiency, and the shortest database transaction response time. Furthermore, the performance prediction result of the optimal register parameter (as an example of the second performance prediction result) is better than the performance prediction results of the other candidate register parameters and the initial register parameter. For further details, please refer to the relevant descriptions of the aforementioned performance prediction submodule 212 and self-optimization submodule 213.

[0080] S430: Change the register from the first working mode to the second working mode.

[0081] The processor can adjust the register from the current first operating mode to the second operating mode so that the register operating mode is suitable for the current processor workload.

[0082] In some embodiments, the processor may also repeatedly execute the above method to continue to collect the instruction stream currently sent by the processor to the storage device in real time and adjust the working mode of the registers in real time so that the working mode of the registers can adapt to the business load of the processor.

[0083] Furthermore, the control method provided in this application can identify the current service type of the processor through the instruction stream generated by the processor, determine the data access requirements, and then adjust the register parameters to adapt the register parameters to the service being run by the processor, thereby improving the register data hit rate and data access efficiency.

[0084] This application also provides a control method that can be applied to a processor in an electronic device, specifically taking the processor identifying instruction characteristics based on the instruction stream sent from the processor core to the cache as an example. As shown in Figure 5, the control method may include the following steps:

[0085] S510: Obtains instruction stream samples from the input buffer and performs statistical analysis of instruction characteristics, as well as obtains initial register parameters.

[0086] The processor can acquire the instruction stream sent by the processor to the cache, and the initial register parameters of the currently applied registers. The instruction stream is used to access data in the cache. Here, we take acquiring the instruction stream sent by the processor to the cache as an example; in some embodiments, it can also acquire the instruction stream sent by the processor to registers or memory. For further details, please refer to the aforementioned description of the acquisition and monitoring submodule 211.

[0087] S520: Based on the performance prediction model, it obtains performance prediction results through instruction characteristics and initial register parameters.

[0088] The processor can predict the performance of the current instruction stream and initial register parameters based on a pre-trained performance prediction model, using input instruction characteristics and initial register parameters. For example, the performance prediction result can be one or more parameters such as register data hit rate and processor pipeline efficiency. See the description of the aforementioned performance prediction submodule 212 for further details.

[0089] S530: Based on the performance prediction results and the initial register parameters, the optimal register parameters are obtained through optimization.

[0090] Based on the predicted performance and the current initial register parameters, the processor generates optimal register parameters through Bayesian optimization. The processor can perform multiple rounds of register parameter optimization, and the register parameters generated in each round can be sent to the performance prediction model to generate corresponding performance prediction results. The optimal register parameters are generated when a cutoff condition is met. The cutoff condition can be one or more of the following: the number of optimization attempts reaches a preset number, or the difference between the performance prediction result obtained from the current round of optimization and the performance prediction result from the previous round is less than a preset difference. For further details, please refer to the description of the aforementioned self-optimization submodule 213.

[0091] S540: Update the current register parameter configuration based on the optimal register parameters.

[0092] The processor will apply the optimized register parameters obtained through optimization to the current register so that the register's operating mode is suitable for the current processor's workload.

[0093] S550: Collects actual performance parameters and updates the performance prediction model based on the actual performance parameters.

[0094] The processor also collects the actual operation of the current business under the optimal register parameters in real time to obtain the actual performance parameters. Then, based on the obtained instruction characteristics, the optimal register parameters currently applied by the register, and the collected actual performance parameters, it incrementally updates the performance prediction model used in the aforementioned step S520, so that the subsequent prediction process can be more accurate.

[0095] Furthermore, through the control method provided in this application, the processor can identify the current service type of the processor by caching the instruction stream received, determine the data access requirements, and then adjust the register parameters to adapt to the service being run by the processor, thereby improving the register data hit rate and data access efficiency. Moreover, the processor will also adjust the prediction model for the performance parameters of the predicted register parameters based on the actual performance parameters during processor operation, making the subsequent prediction process more accurate.

[0096] This application also provides another control device, as shown in FIG6, which includes an acquisition unit 610, a determination unit 620, and an adjustment unit 630.

[0097] The acquisition unit 610 is used to acquire the instruction stream of the target service, wherein the processor's registers are in a first working mode; the determination unit 620 is used to determine the second working mode of the register corresponding to the target service based on the instruction characteristics of the instruction stream; and the adjustment unit 630 is used to adjust the register from the first working mode to the second working mode.

[0098] The determining unit 620 is further configured to determine a first performance prediction result of the target service running in the first working mode based on instruction characteristics and the first working mode; the determining unit 620 is further configured to select at least one candidate working mode from the working modes of the register and determine a second performance prediction result of the target service running in the at least one candidate working mode; the determining unit 620 is further configured to determine the candidate working mode with the highest second performance prediction result from the at least one candidate working mode as the second working mode, and the second performance prediction result of the second working mode is higher than the first performance prediction result.

[0099] The acquisition unit 610 is also used to acquire the first register parameter when the register is in the first working mode; the determination unit 620 is also used to input the instruction characteristics and the first register parameter into the performance prediction model to obtain the first performance prediction result.

[0100] The acquisition unit 610 is also used to collect the actual performance results of the target service; the adjustment unit 630 is also used to update the performance prediction model based on the actual performance results and the second register parameters corresponding to the second working mode.

[0101] Instruction characteristics include the distribution of different types of instructions in the instruction stream. The types of instructions include one or more of the following: load instructions, store instructions, replace instructions, lock instructions, data move instructions, arithmetic instructions, logical instructions, comparison instructions, branch instructions, control flow instructions, and stack operation instructions.

[0102] The first and second performance prediction results include one or more of the following: register data hit rate, processor pipeline efficiency, and database transaction response time.

[0103] Furthermore, through the control device provided in this application, the processor can identify the current service type of the processor through the instruction stream, determine the data access requirements, and then adjust the register parameters to adapt the register parameters to the service being run by the processor, thereby improving the register data hit rate and data access efficiency. Moreover, the processor will also adjust the prediction model for the performance parameters of the predicted register parameters based on the actual performance parameters during processor operation, making the subsequent prediction process more accurate.

[0104] The methods of the embodiments of this application have been described in detail above. In order to facilitate better implementation of the above-described solutions of the embodiments of this application, relevant equipment for cooperating in implementing the above solutions is also provided below.

[0105] Figure 7 is a schematic diagram of the structure of an electronic device 700 provided in this application. As shown in Figure 7, the electronic device 700 includes a processor 710, a communication interface 720, and a memory 730. The processor 710, communication interface 720, and memory 730 can be interconnected via an internal bus 740, or they can communicate via wireless transmission or other means. This embodiment of the application takes the connection via bus 740 as an example. Bus 740 can be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. Bus 740 can be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, bus 740 can also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus 740 in the figure.

[0106] Processor 710 may consist of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and hardware chips. The aforementioned hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. Processor 710 executes various types of digital storage instructions, such as digital storage instructions in software or firmware stored in memory 730, enabling electronic device 700 to provide a variety of services.

[0107] The memory 730 stores program code, which is executed by the processor 710 to perform the processing steps of the control method in the above embodiments. The program code may include one or more software modules, such as the software modules provided in the embodiment of FIG2, like the self-optimization module 210 and the self-learning module 220. The self-optimization module 210 determines the current service type being run by the processor based on the instruction stream sent to the cache by the processor. The self-optimization module 210 also obtains the initial register parameters of the current registers, optimizes the register parameters according to the current service type, obtains the optimal register parameters suitable for the current service type, and then updates the register parameters to the optimal register parameters. The self-learning module 220 collects the actual performance parameters of the processor during actual service execution and then updates the self-optimization module 210 based on the actual performance parameters so that the self-optimization module 210 can obtain more accurate optimal register parameters.

[0108] The memory 730 may include volatile memory, such as random access memory (RAM); the memory 730 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 730 may also include combinations of the above types. The memory 730 may store program code, specifically executing steps S410-S430 and their optional steps in the embodiment of FIG4, or executing steps S510-S550 and their optional steps in the embodiment of FIG5, which will not be described in detail here.

[0109] The communication interface 720 can be an internal interface (such as a high-speed serial computer expansion bus), a wired interface (such as an Ethernet interface), or a wireless interface (such as a cellular network interface or a wireless LAN interface) for communicating with other devices or modules.

[0110] It should be noted that Figure 7 is merely one possible implementation of the embodiment of this application. In practical applications, the electronic device 700 may include more or fewer components, which is not limited here. For content not shown or described in the embodiments of this application, please refer to the relevant descriptions in the embodiments of Figure 4 or Figure 5 above, which will not be repeated here.

[0111] It should be understood that this embodiment can be implemented using a general-purpose physical server, such as an ARM server or an x86 server, or it can be implemented using a virtual machine based on a general-purpose physical server combined with NFV technology. A virtual machine refers to a complete computer system with complete hardware system functions simulated by software and running in a completely isolated environment. This application does not make any specific limitations.

[0112] The electronic device 700 shown in Figure 7 can also be a server. The server includes a processor and a memory. The memory is used to store instructions, and the processor is used to execute the instructions. When the processor executes the instructions, the method flow shown in Figure 4 or Figure 5 is implemented. The electronic device 700 shown in Figure 7 can also be a computer cluster consisting of at least one server. This application does not make specific limitations.

[0113] This application also provides a computer-readable storage medium storing instructions that, when executed on a processor, implement the method flow shown in FIG4 or FIG5.

[0114] This application also provides a computer program product, in which the method flow shown in FIG4 or FIG5 is implemented when the computer program product is run on a processor.

[0115] This application also provides a chip, which includes a processor and a data interface. When the processor reads instructions stored in the memory through the data interface, the method flow shown in FIG4 or FIG5 is implemented. The above embodiments can be implemented entirely or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tape), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media. Semiconductor media can be SSDs.

[0116] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A control method, characterized in that, Applied to a processor, wherein the processor's registers are in a first operating mode, the method includes: Obtain the instruction stream for running the target service; Based on the instruction characteristics of the instruction stream, determine the second operating mode of the register corresponding to the target service; Adjust the register from the first operating mode to the second operating mode.

2. The method according to claim 1, characterized in that, The step of determining the second operating mode of the register corresponding to the target service based on the instruction characteristics of the instruction stream includes: Based on the instruction characteristics and the first working mode, a first performance prediction result is determined for running the target service in the first working mode. Select at least one candidate operating mode from the operating modes of the register, and determine a second performance prediction result for running the target service under the at least one candidate operating mode; The candidate working mode with the highest second performance prediction result is determined from the at least one candidate working mode as the second working mode, and the second performance prediction result of the second working mode is higher than the first performance prediction result.

3. The method according to claim 2, characterized in that, The step of determining the first performance prediction result of running the target service in the first working mode based on the instruction characteristics and the first working mode includes: Obtain the first register parameter when the register is in the first working mode; The instruction characteristics and the first register parameters are input into the performance prediction model to obtain the first performance prediction result.

4. The method according to claim 3, characterized in that, The method further includes: Collect the actual performance results of the target service; The performance prediction model is updated based on the actual performance results and the second register parameters corresponding to the second working mode.

5. The method according to claim 1, characterized in that, The instruction characteristics include the distribution of different types of instructions in the instruction stream, wherein the instruction types include one or more of the following: load instructions, store instructions, replace instructions, lock instructions, data move instructions, arithmetic instructions, logical instructions, comparison instructions, branch instructions, control flow instructions, and stack operation instructions.

6. The method according to claim 2, characterized in that, The first performance prediction result and the second performance prediction result include one or more of the following: register data hit rate, processor pipeline efficiency, and database transaction response time.

7. A control device, characterized in that, Applied to a processor, wherein the processor's registers are in a first operating mode, the control device includes an acquisition unit, a determination unit, and an adjustment unit: The acquisition unit is used to acquire the instruction stream for running the target service; The determining unit is used to determine the second working mode of the register corresponding to the target service based on the instruction characteristics of the instruction stream; The adjustment unit is used to adjust the register from the first working mode to the second working mode.

8. The apparatus according to claim 7, characterized in that, The determining unit is further configured to determine a first performance prediction result for running the target service in the first working mode based on the instruction characteristics and the first working mode. The determining unit is further configured to select at least one candidate working mode from the working modes of the register, and determine a second performance prediction result for running the target service under the at least one candidate working mode; The determining unit is further configured to determine the candidate working mode with the highest second performance prediction result from the at least one candidate working mode as the second working mode, and the second performance prediction result of the second working mode is higher than the first performance prediction result.

9. The apparatus according to claim 8, characterized in that, The acquisition unit is also used to acquire the first register parameter when the register is in the first working mode; The determining unit is further configured to input the instruction features and the first register parameters into the performance prediction model to obtain the first performance prediction result.

10. The apparatus according to claim 9, characterized in that, The acquisition unit is also used to collect the actual performance results of the target service; The adjustment unit is also used to update the performance prediction model based on the actual performance results and the second register parameters corresponding to the second working mode.

11. The apparatus according to claim 7, characterized in that, The instruction characteristics include the distribution of different types of instructions in the instruction stream, wherein the instruction types include one or more of the following: load instructions, store instructions, replace instructions, lock instructions, data move instructions, arithmetic instructions, logical instructions, comparison instructions, branch instructions, control flow instructions, and stack operation instructions.

12. The apparatus according to claim 8, characterized in that, The first performance prediction result and the second performance prediction result include one or more of the following: register data hit rate, processor pipeline efficiency, and database transaction response time.

13. A chip, characterized in that, The chip includes a processor and a data interface. The processor reads instructions stored in the memory through the data interface to execute the method as described in any one of claims 1 to 6.

14. An electronic device, characterized in that, It includes a processor and a memory, the memory being used to store instructions, the processor being used to execute the instructions, and when the processor executes the instructions, it performs the method as described in any one of claims 1 to 6.

15. A server, characterized in that, It includes a processor and a memory, the memory being used to store instructions, the processor being used to execute the instructions, and when the processor executes the instructions, it performs the method as described in any one of claims 1 to 6.

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