Oscillation circuit and control method of oscillation frequency

Abstract

The present invention constitutes a frequency synchronization loop of an oscillation circuit without using an amplifier for comparing voltages.　This oscillation circuit comprises: an oscillator; and a phase comparison unit that constitutes a feedback loop for the oscillator on the basis of the result of comparing phases obtained by converting the oscillation frequency of the oscillator. The phase comparison unit may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase. The phase comparison unit may include: a phase frequency detector (PFD) connected to subsequent stages of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a subsequent stage of the PFD; and a loop filter connected to a subsequent stage of the charge pump circuit.

Description

Oscillator circuit and method for controlling oscillation frequency

[0001] The present technology relates to an oscillator circuit and a method for controlling an oscillation frequency, and more particularly, to an oscillator circuit and a method for controlling an oscillation frequency that can stabilize an oscillation frequency based on a frequency locked loop (FLL).

[0002] A feedback loop oscillator has been proposed as a high-precision oscillator that can be integrated on a semiconductor chip. For example, an oscillator circuit having a feedback circuit that adjusts a control signal so that a detection voltage corresponding to a reference current approaches a reference voltage has been disclosed (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-191486

[0004] However, in the above-mentioned conventional technology, an amplifier is used to compare the detected voltage corresponding to the reference current with the reference voltage, which causes constant power consumption in the amplifier, which may lead to an increase in the power consumption of the oscillator circuit.

[0005] This technology was developed in light of these circumstances, and aims to configure a frequency-locked loop for an oscillator circuit without using an amplifier for comparing voltages.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an oscillation circuit including an oscillator and a phase comparator that configures a feedback loop for the oscillator based on a comparison result of a phase into which an oscillation frequency of the oscillator is converted, thereby providing an effect of configuring a frequency-locked loop for the oscillation circuit without using an amplifier that compares voltages.

[0007] In the first aspect, the phase comparator may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase, thereby providing an effect that a frequency-locked loop of the oscillation circuit is configured based on a comparison result of the phase obtained by converting a voltage according to the oscillation frequency of the oscillator.

[0008] In the first aspect, the input source and output destination of the first sub-oscillator and the second sub-oscillator may be alternately switched, thereby eliminating a mismatch between the first sub-oscillator and the second sub-oscillator based on the switching operation.

[0009] In the first aspect, the phase comparator may include a PFD (Phase Frequency Detector) connected to a stage subsequent to the first sub-oscillator and the second sub-oscillator, a charge pump circuit connected to a stage subsequent to the PFD, and a loop filter connected to a stage subsequent to the charge pump circuit, thereby providing an effect that the oscillation frequency of the oscillator is controlled based on a comparison result of the phase into which the oscillation frequency of the oscillator is converted.

[0010] In the first aspect, the first sub-oscillator and the second sub-oscillator may each be an LC oscillator or a ring oscillator, thereby providing an effect that the first sub-oscillator and the second sub-oscillator are configured in an analog manner.

[0011] In the first aspect, the first sub-oscillator and the second sub-oscillator may each be a digitally controlled oscillator (DCO), thereby providing an effect that the first sub-oscillator and the second sub-oscillator are configured digitally.

[0012] In the first aspect, a switched capacitor may be provided for converting an oscillation frequency of the oscillator into the control voltage, thereby producing an effect that a control voltage according to the oscillation frequency of the oscillator is generated.

[0013] In the first aspect, the clock signal may be used as a reference clock source for an integrated circuit, thereby stabilizing the operation of the integrated circuit that operates based on a clock without an external reference clock source.

[0014] In addition, in the first aspect, the clock signal may be integrated into a semiconductor chip on which the integrated circuit is formed, thereby providing an advantage that an integrated circuit that operates based on a clock is configured without requiring an external oscillator that supplies a clock.

[0015] In the first aspect, a PLL (Phase Locked Loop) may be provided connected downstream of the oscillator, thereby stabilizing the oscillation frequency of the PLL without requiring an external reference clock source as a reference clock for the PLL.

[0016] A second aspect of the present invention is a method for controlling an oscillation frequency, comprising the steps of: converting an oscillation frequency of an oscillator into a control voltage based on switched capacitor operation; converting the control voltage into a first phase based on a first oscillation operation based on the control voltage; converting the reference voltage into a second phase based on a second oscillation operation based on a reference voltage; detecting a difference between the first phase and the second phase; converting the difference between the first phase and the second phase into a current based on charge pump operation; and controlling the oscillation frequency of the oscillator based on loop filter operation based on the current. This provides an effect of configuring a frequency-locked loop of an oscillation circuit without using an amplifier for comparing voltages.

[0017] FIG. 1 is a circuit diagram showing a configuration example of an oscillator circuit according to a first embodiment. FIG. 2 is a circuit diagram showing a configuration example of an oscillator applied to the oscillator circuit according to the first embodiment. FIG. 3 is a circuit diagram showing another configuration example of an oscillator applied to the oscillator circuit according to the first embodiment. FIG. 4 is a circuit diagram showing a configuration example of a PFD (Phase Frequency Detector) and a charge pump circuit applied to the oscillator circuit according to the first embodiment. FIG. 5 is a diagram showing waveforms during operation of the PFD and the charge pump circuit according to the first embodiment. FIG. 6 is a circuit diagram showing a configuration example of a loop filter applied to the oscillator circuit according to the first embodiment. FIG. 7 is a block diagram showing a configuration example of an oscillator circuit according to the first embodiment. FIG. 8 is a diagram showing waveforms during operation of the oscillator circuit according to the first embodiment. FIG. 9 is a circuit diagram showing a configuration example of an oscillator circuit according to a second embodiment. FIG. 10 is a circuit diagram showing a configuration example of an oscillator circuit according to a third embodiment. FIG. 11 is a circuit diagram showing a first example of a chopper circuit according to the third embodiment. FIG. 12 is a circuit diagram showing a second example of a chopper circuit according to the third embodiment. FIG. 13 is a timing chart showing chopper operation of the oscillator circuit according to the third embodiment. FIG. 14 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to a fourth embodiment is applied. FIG. 15 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to a fifth embodiment is applied. FIG. 10 is a circuit diagram showing a configuration example of an ADPLL (All Digital PLL) circuit applicable to an oscillator circuit according to a fifth embodiment. FIG. 11 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to a sixth embodiment is applied. FIG. 12 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to a seventh embodiment is applied. FIG. 13 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to an eighth embodiment is applied. FIG. 14 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to a ninth embodiment is applied. FIG. 15 is a block diagram showing a configuration example of a solid-state imaging device to which an oscillator circuit according to a tenth embodiment is applied. FIG. 16 is a perspective view showing an example of a stack of a solid-state imaging device according to an eleventh embodiment. FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 18 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0018] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a feedback loop for an oscillator is configured based on a comparison result of the phase into which the oscillation frequency of the oscillator is converted) 2. Second embodiment (an example in which a sub-oscillator in the preceding stage of a PFD is configured with a DCO (Digitally Controlled Oscillator)) 3. Third embodiment (an example in which the input source and output destination of the sub-oscillator are alternately switched) 4. Fourth embodiment (an example in which an FLL is applied to a solid-state imaging device) 5. Fifth embodiment (an example in which a PLL used in an AD converter and a logic circuit, and a PLL used in a communication interface are provided subsequent to the FLL) 6. Sixth embodiment (an example in which a PLL used in an AD converter and a logic circuit is provided subsequent to the FLL) 7. Seventh embodiment (an example in which a PLL used in a communication interface is provided subsequent to the FLL) 8. 8. Eighth embodiment (an example in which a PLL used in an AD converter, a logic circuit, and a communication interface is provided after an FLL) 9. Ninth embodiment (an example in which an FLL used in an AD converter and a logic circuit, and an FLL used in a communication interface are provided) 10. Tenth embodiment (an example in which the frequency of an FLL used in a solid-state imaging device is externally controllable) 11. Eleventh embodiment (an example in which semiconductor chips on which solid-state imaging devices are formed are stacked) 12. Application to a moving body

[0019] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an oscillator circuit according to a first embodiment.

[0020] In the figure, the oscillation circuit includes an oscillator 101 and a phase comparator 102. In this case, the oscillation circuit can operate as an FLL. This oscillation circuit may be used as a reference clock source for an integrated circuit.

[0021] The oscillator 101 generates an oscillation signal Fo based on an oscillation operation. The oscillator 101 can change an oscillation frequency fs based on voltage control. The oscillator 101 may be a ring oscillator, an LC oscillator, or a DCO (Digitally Controlled Oscillator).

[0022] The phase comparator 102 forms a feedback loop for the oscillator 101 based on the comparison result between a phase φ2 obtained by converting the oscillation frequency fs of the oscillator 101 and a reference phase φ1. The phase comparator 102 includes a switched capacitor 106, sub-oscillators SB1 and SB2, a PFD 103, a charge pump circuit 104, a loop filter 105, and resistors R1 to R3.

[0023] The switched capacitor 106 and the resistor R3 convert the oscillation frequency fs of the oscillator 101 into a control voltage V2. The switched capacitor 106 and the resistor R3 are connected in series. The control voltage V2 is output from the connection point of the switched capacitor 106 and the resistor R3 and input to the sub-oscillator SB2. The switched capacitor 106 includes a capacitance C1 and switches W1 and W2.

[0024] The switches W1 and W2 are connected in series to each other. A capacitor C1 is connected to the connection point of the switches W1 and W2. The switches W1 and W2 are alternately turned on and off based on the oscillation signal Fo of the oscillator 101. At this time, the switching of the switches W1 and W2 is set to be in opposite phase to each other. The switches W1 and W2 may be field-effect transistors. The oscillation frequency fs of the oscillator 101 may be divided.

[0025] The resistors R1 and R2 generate a reference voltage V1. The resistors R1 and R2 are connected in series with each other. The reference voltage V1 is output from the connection point of the resistors R1 and R2 and input to the sub-oscillator SB1.

[0026] The sub-oscillator SB1 converts the reference voltage V1 generated via resistors R1 and R2 into a phase φ1 and outputs it to the PFD 103.

[0027] The sub-oscillator SB2 converts the control voltage V2 generated via the switched capacitor 106 and the resistor R3 into a phase φ2 and outputs it to the PFD 103.

[0028] The PFD 103 controls the charge pump circuit 104 based on the difference between the phases φ1 and φ2 of the outputs of the sub-oscillators SB1 and SB2. The PFD 103 is connected to the subsequent stages of the sub-oscillators SB1 and SB2.

[0029] The charge pump circuit 104 generates a current I according to the difference between the phases φ1 and φ2 detected by the PFD 103, and outputs the current I to the loop filter 105. The charge pump circuit 104 is connected to the subsequent stage of the PFD 103.

[0030] The loop filter 105 applies a control voltage corresponding to the current I output from the charge pump circuit 104 to the oscillator 101. The loop filter 105 is connected to the subsequent stage of the charge pump circuit 104.

[0031] When the oscillation signal Fo generated by the oscillator 101 is input to the switched capacitor 106, a current corresponding to the oscillation frequency fs of the oscillation signal Fo is generated and flows through the resistor R3. Then, a control voltage V2 is generated according to the voltage drop across the resistor R3 at that time and is input to the sub-oscillator SB2.

[0032] At this time, when switch W1 is turned on and switch W2 is turned off, current is supplied to capacitor C1 via switch W1, and charge is accumulated in capacitor C1. When switch W1 is turned off and switch W2 is turned on, the charge accumulated in capacitor C1 is discharged via switch W2 and flows into resistor R3. Here, as the oscillation frequency fs of oscillator 101 increases, the number of times the charge accumulated in capacitor C1 is discharged increases, and the current generated by switched capacitor 106 increases. At this time, switched capacitor 106 can be regarded as the impedance of resistor R, and the resistance R of switched capacitor 106 can be given by the formula 1 / (fs C1). Therefore, as the oscillation frequency fs of oscillator 101 increases, the resistance R of switched capacitor 106 decreases and the control voltage V2 increases.

[0033] The reference voltage V1 generated via resistors R1 and R2 is converted to a phase φ1 by the sub-oscillator SB1, and the control voltage V2 generated via the switched capacitor 106 and resistor R3 is converted to a phase φ2 by the sub-oscillator SB2 and output to the PFD 103. At this time, an integral effect occurs when the sub-oscillators SB1 and SB2 convert the voltages to phases φ1 and φ2. This makes it possible to increase the loop gain and suppress noise that occurs after conversion to each phase φ1 and φ2 within the band range.

[0034] The phases φ1 and φ2 converted by the sub-oscillators SB1 and SB2 are input to the PFD 103, which detects the difference between the phases φ1 and φ2. The current I generated by the charge pump circuit 104 is then controlled based on the difference between the phases φ1 and φ2.

[0035] Then, in the loop filter 105, the control voltage of the oscillator 101 is changed according to the current I generated by the charge pump circuit 104, and the oscillation frequency fs of the oscillator 101 changes. When the phases φ1 and φ2 converted by the sub-oscillators SB1 and SB2 become equal, the current I generated by the charge pump circuit 104 becomes zero, and the oscillator 101 enters a steady state. At this time, when the switched capacitor 106 is regarded as an impedance, the resistance R becomes equal to the resistance value of the resistor R1, and the oscillation frequency fs of the oscillator 101 can be given by fs=1 / (R1·C1).

[0036] 2 is a circuit diagram showing an example of the configuration of an oscillator applied to the oscillation circuit according to the first embodiment, in which the oscillator is a ring oscillator.

[0037] In the figure, the ring oscillator has multiple (odd number) inverters 131 connected in multiple stages, with the output of the last inverter being fed back to the input of the first inverter. The power supply system of each inverter 131 is grounded via a field-effect transistor 132. A bias voltage VB is applied to the gate of the field-effect transistor 132. By controlling the bias voltage VB, the driving force of each inverter 131 can be controlled, thereby controlling the oscillation frequency of the ring oscillator. This ring oscillator can be used for the oscillator 101 and the sub-oscillators SB1 and SB2.

[0038] 3 is a circuit diagram showing another example of the configuration of an oscillator applied to the oscillation circuit according to the first embodiment, in which the oscillator is an LC oscillator.

[0039] In the figure, an LC oscillator generates an oscillation signal based on resonance between an inductor 141 and a capacitor 142. The oscillation signal is a differential output signal. The LC oscillator includes an inductor 141, a capacitor 142, transistors 143 and 144, and a current source 145. The transistors 143 and 144 are N-channel field effect transistors.

[0040] The inductor 141 and the capacitor 142 are connected in parallel. The drains of the transistors 143 and 144 are connected to both ends of the capacitor 142. The drain of the transistor 143 is connected to the gate of the transistor 144, and the drain of the transistor 144 is connected to the gate of the transistor 143. The sources of the transistors 143 and 144 are connected to the ground potential via the current source 145. The capacitor 142 can have a variable capacitance. The oscillation frequency of the LC oscillator can be controlled by controlling the capacitance of the capacitor 142 based on the control voltage VC. This LC oscillator can be used for the oscillator 101 and the sub-oscillators SB1 and SB2.

[0041] FIG. 4 is a circuit diagram showing an example of the configuration of a PFD and a charge pump circuit applied to the oscillation circuit according to the first embodiment.

[0042] In the figure, the PFD 103 includes flip-flops 151 and 152, a buffer 153, and an AND circuit 154. A fixed potential is applied to the D terminals of the flip-flops 151 and 152. Oscillator signals CK1 and CK2 from the sub-oscillators SB1 and SB2 are input to the clock terminals of the flip-flops 151 and 152. The oscillation signals CK1 and CK2 include phases φ1 and φ2 of the outputs of the sub-oscillators SB1 and SB2. Control signals UP and DN corresponding to the phases φ1 and φ2 are output from the Q terminals of the flip-flops 151 and 152, respectively. At this time, the control signal UP increases the control voltage VC of the oscillator 101, and the control signal DN decreases the control voltage VC of the oscillator 101. A first input of AND circuit 154 is connected to the Q terminal of flip-flop 151, and a second input of AND circuit 154 is connected to the Q terminal of flip-flop 152. An output of AND circuit 154 is connected to the R terminal of flip-flop 152 via buffer 153. At this time, when control signals UP and DN both rise, flip-flops 151 and 152 are reset via AND circuit 154. Therefore, the state in which control signals UP and DN both rise is eliminated.

[0043] The charge pump circuit 104 includes current sources 161 and 162 and switches W3 and W4. The switches W3 and W4 are connected in series. A current I is output from the connection point of the switches W3 and W4. The switch W3 is turned on and off based on a control signal UP, and the switch W4 is turned on and off based on a control signal DN. The switches W3 and W4 may be field-effect transistors. The switch W3 is connected in series with the current source 161, and the switch W4 is connected in series with the current source 161.

[0044] Here, as the difference in the oscillation frequencies of the oscillation signals CK1 and CK2 of the sub-oscillators SB1 and SB2 increases, the difference in the phases φ1 and φ2 detected by the PFD 103 also increases. As the difference in the phases φ1 and φ2 detected by the PFD 103 increases, the time from when one of the oscillation signals CK1 and CK2 of the sub-oscillators SB1 and SB2 rises to when the other of the oscillation signals CK1 and CK2 of the sub-oscillators SB1 and SB2 rises also increases. This increases the duration of the output of one of the control signals UP and DN. As the duration of the output of one of the control signals UP and DN increases, the on-time of the switches W3 and W4 controlled by the control signals UP and DN also increases, and the duration of the output of the current I from the charge pump circuit 104 also increases.

[0045] The current I output from the charge pump circuit 104 is input to the loop filter 105. Here, the current I output from the charge pump circuit 104 is integrated by the loop filter 105, thereby generating a control voltage according to the duration of the current I output from the charge pump circuit 104, and applying this to the oscillator 101. Therefore, it is no longer necessary to use an amplifier to control the oscillation frequency fs of the oscillator 101, and the oscillation circuit can be configured with an amplifier.

[0046] For example, if an amplifier stacks transistors to increase its gain, it requires a power supply voltage sufficient to drive those transistors. For example, a folded cascode amplifier requires a voltage of Vth + 3Vod, and even if Vth = 0.5V and Vod = 0.1V, a power supply voltage of 0.8V is required. Here, Vth is the threshold voltage of the transistor, and Vod is the voltage applied to the current source connected in series to the transistor.

[0047] 1, the reference voltage V1 and control voltage V2 are converted to phases φ1 and φ2 via the sub-oscillators SB1 and SB2, respectively, and compared by the PFD 103 and charge pump circuit 104. This allows the oscillator circuit to be configured with an amplifier, eliminating the need for a transistor stack like in a folded cascode amplifier, and enabling a lower voltage. In this case, the charge pump circuit 104 only needs a drive voltage Vod = 0.2 V.

[0048] FIG. 5 is a diagram showing waveforms during operation of the PFD and charge pump circuit according to the first embodiment.

[0049] In the figure, when both control signals UP and DN are falling, the phase of oscillation signal CK1 leads the phase of oscillation signal CK2. At this time, control signal UP rises in response to the rising edge of oscillation signal CK1, and control voltage VC increases. Then, when both control signals UP and DN rise, reset signal RS is output via AND circuit 154, resetting flip-flops 151 and 152. At this time, control voltage VC is maintained at a constant value.

[0050] On the other hand, when both control signals UP and DN are falling, the phase of oscillation signal CK1 lags behind the phase of oscillation signal CK2. At this time, control signal DN rises in response to the rising edge of oscillation signal CK2, and control voltage VC is reduced. Then, when both control signals UP and DN rise, reset signal RS is output via AND circuit 154, and flip-flops 151 and 152 are reset. At this time, control voltage VC is maintained at a constant value.

[0051] 6 is a circuit diagram showing an example of the configuration of a loop filter applied to the oscillator circuit according to the first embodiment, where a in the figure is a circuit diagram showing a first example of the configuration of the loop filter 105, and b in the figure is a circuit diagram showing a second example of the configuration of the loop filter 105.

[0052] In the figure, a first configuration example of the loop filter 105 includes a capacitor C2. The capacitor C2 is connected to the charge pump circuit 104. At this time, a current I generated by the charge pump circuit 104 flows through the capacitor C2, and a voltage corresponding to the current I is generated.

[0053] In the second configuration example of the loop filter 105 shown in FIG. 1B, a resistor R4 and a capacitor C3 are added to the first configuration example of the loop filter 105. The resistor R4 and the capacitor C3 are connected in series. The series circuit of the resistor R4 and the capacitor C3 is connected in parallel to the capacitor C3. In this case, the series circuit of the resistor R4 and the capacitor C3 ensures the stability of the FLL.

[0054] FIG. 7 is a block diagram showing an example of the configuration of the oscillator circuit according to the first embodiment.

[0055] In the figure, the sub-oscillator SB1 is represented by a transfer function K1 / s, and the sub-oscillator SB2 is represented by a transfer function K2 / s. K1 and K2 are the gains of the sub-oscillators SB1 and SB2, respectively. The PFD 103 is represented by a subtractor 171 and a transfer function H1. The charge pump circuit 104 is represented by a transfer function H2. The loop filter 105 is represented by a transfer function H3. The oscillator 101 is represented by a gain K3. The switched capacitor 106 and resistor R3 are represented by a feedback constant β. At this time, an integral effect occurs when the sub-oscillators SB1 and SB2 convert to phases φ1 and φ2, respectively, and 1 / s is introduced into the transfer function.

[0056] 8 is a diagram showing waveforms during operation of the oscillator circuit according to the first embodiment, where a in the diagram shows the relationship between time and the oscillation frequency fs of the oscillation signal Fo of the oscillator 101, b in the diagram shows the relationship between time and the reference voltage V1 and the control voltage V2, and c in the diagram shows the relationship between time and each of the phases φ1 and φ2.

[0057] In the diagram, the control voltage V2 changes in accordance with the change in the oscillation frequency fs of the oscillation signal Fo. At this time, the reference voltage V1 is maintained constant, and when the control voltage V2 coincides with the reference voltage V1, the oscillation frequency fs of the oscillation signal Fo transitions to a steady state.

[0058] Here, as shown in Fig. 1c, the phase φ1 is given by the integral value of the reference voltage V1, and the phase φ2 is given by the integral value of the control voltage V2. When the oscillation frequency fs of the oscillation signal Fo transitions to a steady state, the slopes of the phases φ1 and φ2 become equal.

[0059] In this way, in the first embodiment described above, a feedback loop for the oscillator 101 is configured based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted. This makes it possible to configure a frequency-locked loop for the oscillation circuit without using an amplifier that compares voltages, thereby reducing the power consumption of the oscillation circuit.

[0060] 2. Second Embodiment In the first embodiment described above, the sub-oscillators SB1 and SB2 in the preceding stage of the PFD 103 are configured in an analog manner. In this second embodiment, the sub-oscillators in the preceding stage of the PFD 103 are configured in a digital manner.

[0061] FIG. 9 is a circuit diagram showing an example of the configuration of an oscillator circuit according to the second embodiment.

[0062] In the figure, this oscillation circuit includes an oscillator 101 and a phase comparison unit 202. The phase comparison unit 202 includes sub-oscillators SD1 and SD2 instead of the sub-oscillators SB1 and SB2 of the first embodiment described above. Furthermore, this phase comparison unit 202 includes ADCs (Analog to Digital Converters) 201 and 202 in addition to the phase comparison unit 102 of the first embodiment described above. Other configurations of the phase comparison unit 202 of the second embodiment are similar to the configuration of the phase comparison unit 102 of the first embodiment described above.

[0063] The ADC 201 digitizes the reference voltage V1 and outputs it to the sub-oscillator SD1. The ADC 202 digitizes the control voltage V2 and outputs it to the sub-oscillator SD2.

[0064] The sub-oscillator SD1 converts the digital value of the reference voltage V1 into a phase φ1 and outputs it to the PFD 103. The sub-oscillator SD1 is connected to the subsequent stage of the ADC 201.

[0065] The sub-oscillator SD2 converts the digital value of the control voltage V2 into a phase φ2 and outputs it to the PFD 103. The sub-oscillator SD2 is connected to the subsequent stage of the ADC 202.

[0066] As described above, in the second embodiment, the sub-oscillators SD1 and SD2 in the front stage of the PFD 103 are configured digitally, and a feedback loop for the oscillator 101 is configured based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted. This makes it possible to configure a frequency-locked loop for the oscillation circuit without using an amplifier for comparing voltages, and reduces the power consumption of the oscillation circuit.

[0067] 3. Third Embodiment In the first embodiment described above, a feedback loop for the oscillator 101 is configured based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted. In this third embodiment, a feedback loop for the oscillator 101 is configured based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted, and the input source and output destination of the sub-oscillators SB1 and SB2 are alternately switched.

[0068] FIG. 10 is a circuit diagram showing an example of the configuration of an oscillator circuit according to the third embodiment.

[0069] In the figure, this oscillation circuit includes an oscillator 101 and a phase comparison unit 302. The phase comparison unit 302 is obtained by adding chopper circuits 311 and 312 to the phase comparison unit 102 of the first embodiment described above. Other configurations of the phase comparison unit 302 of the third embodiment are similar to the configuration of the phase comparison unit 102 of the first embodiment described above.

[0070] The chopper circuit 311 alternately switches the connection destinations of the resistor R1 and the switched capacitor 106. The chopper circuit 312 alternately switches the input source and output destination of each of the sub-oscillators SB1 and SB2.

[0071] At this time, the input terminal AP of the chopper circuit 311 is connected to the resistor R1, and the input terminal AN of the chopper circuit 311 is connected to the switched capacitor 106. The output terminal BP of the chopper circuit 311 is connected to the resistor R2, and the output terminal BN of the chopper circuit 311 is connected to the resistor R3.

[0072] An input terminal AP of the chopper circuit 312 is connected to the sub-oscillator SB1, and an input terminal AN of the chopper circuit 312 is connected to the sub-oscillator SB2. An output terminal BP of the chopper circuit 312 is connected to a first input of the PFD 103, and an output terminal BN of the chopper circuit 312 is connected to a second input of the PFD 103. A first input of the PFD 103 is the clock terminal of the flip-flop 151, and a second input of the PFD 103 is the clock terminal of the flip-flop 152.

[0073] FIG. 11 is a circuit diagram illustrating a first example of a chopper circuit according to the third embodiment.

[0074] In the figure, the chopper circuit includes transistors 421 to 424. Each of the transistors 421 to 424 can be an N-channel field effect transistor. The transistor 421 is connected between the input terminal AP and the output terminal BP of the chopper circuit. The transistor 422 is connected between the input terminal AP and the output terminal BN of the chopper circuit. The transistor 423 is connected between the input terminal AN and the output terminal BP of the chopper circuit. The transistor 424 is connected between the input terminal AN and the output terminal BN of the chopper circuit.

[0075] A chopper signal CP is applied to the gates of the transistors 421 and 424, and an inverted chopper signal CPB is applied to the gates of the transistors 422 and 423. The inverted chopper signal CPB is an inverted version of the chopper signal CP. The chopper signal CP may be generated by frequency-dividing the FLL output.

[0076] FIG. 12 is a circuit diagram illustrating a second example of a chopper circuit according to the third embodiment.

[0077] In the figure, the chopper circuit includes transmission gates 431 to 434. Each of the transmission gates 431 to 434 can use a pair of an N-channel field effect transistor and a P-channel field effect transistor. The transmission gate 431 is connected between the input terminal AP and the output terminal BP of the chopper circuit. The transmission gate 432 is connected between the input terminal AP and the output terminal BN of the chopper circuit. The transmission gate 433 is connected between the input terminal AN and the output terminal BP of the chopper circuit. The transmission gate 434 is connected between the input terminal AN and the output terminal BN of the chopper circuit.

[0078] A chopper signal CP is applied to the non-inverting gate of each of the transmission gate transistors 431 and 434, and an inverted chopper signal CPB is applied to the inverting gate of each of the transmission gate transistors 431 and 434. A chopper signal CP is applied to the inverting gate of each of the transmission gate transistors 432 and 433, and an inverted chopper signal CPB is applied to the non-inverting gate of each of the transmission gate transistors 432 and 433.

[0079] FIG. 13 is a timing chart showing the chopper operation of the oscillation circuit according to the third embodiment.

[0080] In the figure, the chopper signal CP can be generated, for example, by dividing the oscillation signal Fo of the oscillator 101 by 16. A non-overlapping period can be provided between the chopper signal CP and the inverted chopper signal CPB.

[0081] When the chopper signal CP is turned on, the input terminal AP and output terminal BP of each chopper circuit 311, 312 are connected, and the input terminal AN and output terminal BN of each chopper circuit 311, 312 are connected. When the inverted chopper signal CPB is turned on, the input terminal AP and output terminal BN of each chopper circuit 311, 312 are connected, and the input terminal AN and output terminal BP of each chopper circuit 311, 312 are connected.

[0082] As a result, the resistor R1 and the switched capacitor 106 are alternately connected to the resistors R2, R3 and the sub-oscillators SB1, SB2, thereby reducing the mismatch therebetween.

[0083] As described above, in the third embodiment, a feedback loop for oscillator 101 is configured based on the comparison result of the phase into which the oscillation frequency of oscillator 101 is converted, and the resistors R2, R3 and the sub-oscillators SB1, SB2 to be used are alternately switched. This makes it possible to reduce mismatches between resistors R2, R3 and the sub-oscillators SB1, SB2, and to improve the accuracy of the FLL frequency.

[0084] 4. Fourth Embodiment In the first embodiment described above, the oscillation frequency of the FLL is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted. In this fourth embodiment, an FLL whose oscillation frequency is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted is applied to a solid-state imaging device.

[0085] 14 is a block diagram showing an example of the configuration of a solid-state imaging device to which an oscillator circuit according to the fourth embodiment is applied. In this figure, blocks that operate based on a clock signal are selected from among the blocks used in the solid-state imaging device 501.

[0086] In the figure, a solid-state imaging device 501 includes an FLL 502, frequency divider circuits 503 and 505, an AD converter 504, a logic circuit 506, and a communication interface 507. The FLL 502 can be used as a clock source for the AD converter 504, the logic circuit 506, and the communication interface 507. The communication interface 507 may be a low-amplitude differential interface such as LVDS (Low Voltage Differential Signaling) or SLVS-EC (Scalable Low Voltage Signaling Embedded Clock).

[0087] In this case, the clock frequency of the FLL 502 can be set according to the operating frequency of the communication interface 507. Furthermore, frequency divider circuits 503 and 505 may be provided in front of the AD converter 504 and the logic circuit 506, respectively, according to the operating frequencies of the AD converter 504 and the logic circuit 506.

[0088] The FLL 502 can set the clock frequency without a reference clock, which allows the AD converter 504, logic circuit 506, and communication interface 507 to operate without an external reference clock such as a crystal oscillator, thereby enabling integration of the solid-state imaging device 501.

[0089] As described above, in the fourth embodiment, the FLL 502, whose oscillation frequency is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted, is applied to the solid-state imaging device 501. This makes it possible to increase the frequency of the clock signal used in the solid-state imaging device 501 while suppressing an increase in power consumption of the oscillator circuit, thereby enabling higher resolution and a higher frame rate to be achieved while suppressing an increase in power consumption of the solid-state imaging device 501. Note that, in order to support image readout at a bi-frame rate, the FLL 502 may be made compatible with high-frequency operation in accordance with an increase in the speed of the AD converter 504.

[0090] 5. Fifth Embodiment In the above-described fourth embodiment, the FLL 502, in which the oscillation frequency is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted, is applied to the solid-state imaging device 501. In this fifth embodiment, a PLL used in the AD converter 504 and logic circuit 506 and a PLL used in the communication interface 507 are provided in a stage subsequent to the FLL 502.

[0091] FIG. 15 is a block diagram showing an example of the configuration of a solid-state imaging device to which an oscillator circuit according to the fifth embodiment is applied.

[0092] In the figure, a solid-state imaging device 511 is obtained by adding PLLs 512 and 513 to the solid-state imaging device 501 of the fourth embodiment described above. Other configurations of the solid-state imaging device 511 of the fifth embodiment are similar to the configurations of the solid-state imaging device 501 of the fourth embodiment described above.

[0093] The PLL 512 is connected in front of the frequency divider circuits 503 and 505. The PLL 513 is connected in front of the communication interface 507. At this time, the output of the PLL 502 is input to the frequency divider circuits 503 and 505 via the PLL 512, and is input to the AD converter 504 and the logic circuit 506 after being frequency-divided by the frequency divider circuits 503 and 505. The output of the FLL 502 is also input to the communication interface 507 via the PLL 513.

[0094] At this time, each of the PLLs 512 and 513 can use the FLL 502 as a reference clock, which eliminates the need for an external reference clock such as a crystal oscillator to operate each of the PLLs 512 and 513, thereby enabling integration of the solid-state imaging device 511.

[0095] 16 is a circuit diagram showing an example of the configuration of an ADPLL (All Digital PLL) circuit applicable to the oscillation circuit according to the fifth embodiment. This ADPLL can be applied to each of the PLLs 512 and 513.

[0096] In the figure, the ADPLL forms a feedback loop based on phase synchronization and outputs a clock signal CLK. The clock signal CLK can be determined based on a reference clock REF and a frequency command word (FCW) parameter. The ADPLL includes an accumulator 211, an adder 212, a loop filter 213, an oscillator 214, a frequency divider 215, a counter 216, and a time-to-digital converter (TDC) 217. The frequency divider 215 is optional.

[0097] The accumulator 211 sets a count-up value for each cycle of the reference clock RCK based on the FCW parameter and outputs the count-up value to the adder 212. The FCW parameter can specify the ratio of the frequency of the clock signal CLK to the frequency of the reference clock REF. The FCW parameter can be provided from outside the ADPLL.

[0098] The adder 212 subtracts the output of the counter 216 and the output of the TDC 217 from the output of the accumulator 211, and outputs the result to the loop filter 213. The output of the adder 212 can indicate the phase error between the reference clock REF and the clock signal CLK.

[0099] The loop filter 213 band-limits the input to the oscillator 214 to reduce the effect of quantization error. The gain of the loop filter 213 can be adjusted based on the calibration of the ADPLL.

[0100] The oscillator 214 generates a clock signal CLK based on an oscillation operation, and can change the oscillation frequency based on an oscillator tuning word.

[0101] The frequency divider 215 divides the frequency of the clock signal CLK generated by the oscillator 214 and feeds the divided signal back to the counter 216 and the TDC 217 .

[0102] The counter 216 counts up for each clock of the clock signal CLK and outputs the count to the adder 212. At this time, the counter 216 can detect the phase in units of one cycle of the clock signal CLK.

[0103] The TDC 217 detects the time difference between the reference clock RCK and the clock signal CLK, digitizes it, and outputs it to the adder 212. At this time, the ADPLL can operate the phase locked loop so that the phase error approaches 0. The TDC 217 may be a delay line TDC.

[0104] As described above, in the fifth embodiment, the PLLs 512 and 513 are connected in a stage subsequent to the FLL 502, whose oscillation frequency is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted. This makes it possible to increase the frequency of the clock signal used in the solid-state imaging device 501, while stabilizing and improving the accuracy of the clock signal frequency.

[0105] 6. Sixth Embodiment In the above-described fifth embodiment, the PLL 512 used in the AD converter 504 and the logic circuit 506 and the PLL 513 used in the communication interface 507 are provided in a stage subsequent to the FLL 502. In this sixth embodiment, the PLL 512 used in the AD converter 504 and the logic circuit 506 is provided in a stage subsequent to the FLL 502.

[0106] FIG. 17 is a block diagram showing an example of the configuration of a solid-state imaging device to which an oscillator circuit according to the sixth embodiment is applied.

[0107] In the figure, a solid-state imaging device 521 is obtained by adding a PLL 512 to the solid-state imaging device 501 of the fourth embodiment described above. The other configuration of the solid-state imaging device 521 of the sixth embodiment is the same as the configuration of the solid-state imaging device 501 of the fourth embodiment described above.

[0108] The PLL 512 is connected in the preceding stage of the frequency divider circuits 503 and 505. At this time, the output of the PLL 502 is input to the frequency divider circuits 503 and 505 via the PLL 512, and is input to the AD converter 504 and the logic circuit 506 after being frequency-divided by the frequency divider circuits 503 and 505.

[0109] As described above, in the sixth embodiment, the PLL 512 used in the AD converter 504 and the logic circuit 506 is provided in the subsequent stage of the FLL 502. This makes it possible to increase the frequency of the clock signal used in the AD converter 504 and the logic circuit 506, while stabilizing and improving the accuracy of the frequency of the clock signal.

[0110] 7. Seventh Embodiment In the sixth embodiment described above, the PLL 512 used in the AD converter 504 and the logic circuit 506 is provided in the subsequent stage of the FLL 502. In this seventh embodiment, the PLL 513 used in the communication interface 507 is provided in the subsequent stage of the FLL 502.

[0111] FIG. 18 is a block diagram showing an example of the configuration of a solid-state imaging device to which an oscillator circuit according to the seventh embodiment is applied.

[0112] In the figure, a solid-state imaging device 531 is obtained by adding a PLL 513 to the solid-state imaging device 501 of the above-described fourth embodiment. Other configurations of the solid-state imaging device 531 of the seventh embodiment are similar to the configurations of the solid-state imaging device 501 of the above-described fourth embodiment.

[0113] The PLL 513 is connected to the front stage of the communication interface 507. At this time, the output of the PLL 502 is input to the communication interface 507 via the PLL 513.

[0114] As described above, in the seventh embodiment, the PLL 513 used in the communication interface 507 is provided in the subsequent stage of the FLL 502. This makes it possible to increase the frequency of the clock signal used in the communication interface 507, while stabilizing and improving the accuracy of the frequency of the clock signal.

[0115] 8. Eighth Embodiment In the fifth embodiment described above, the PLL 512 used in the AD converter 504 and the logic circuit 506 and the PLL 513 used in the communication interface 507 are provided in the subsequent stage of the FLL 502. In this eighth embodiment, the PLL 514 used in the AD converter 504, the logic circuit 506, and the communication interface 507 is provided in the subsequent stage of the FLL 502.

[0116] FIG. 19 is a block diagram showing an example of the configuration of a solid-state imaging device to which an oscillator circuit according to the eighth embodiment is applied.

[0117] In the figure, a solid-state imaging device 541 is obtained by adding a PLL 514 to the solid-state imaging device 501 of the above-described fourth embodiment. Other configurations of the solid-state imaging device 541 of the eighth embodiment are similar to the configurations of the solid-state imaging device 501 of the above-described fourth embodiment.

[0118] The PLL 514 is connected to the subsequent stage of the FLL 502. At this time, the output of the FLL 502 is input to the frequency divider circuits 503 and 505 via the PLL 514, and is input to the AD converter 504 and the logic circuit 506 after being frequency-divided by the frequency divider circuits 503 and 505. The output of the FLL 502 is also input to the communication interface 507 via the PLL 514.

[0119] At this time, the PLL 514 can use the FLL 502 as a reference clock, which eliminates the need for an external reference clock such as a crystal oscillator to operate the PLLs 512 and 513, thereby enabling integration of the solid-state imaging device 541.

[0120] As described above, in the eighth embodiment, the PLL 514 used in the AD converter 504, logic circuit 506, and communication interface 507 is provided in the subsequent stage of the FLL 502. This makes it possible to increase the frequency of the clock signal used in the AD converter 504, logic circuit 506, and communication interface 507, while stabilizing and improving the accuracy of the frequency of the clock signal.

[0121] 9. Ninth Embodiment In the above-described fourth embodiment, the FLL 502, in which the oscillation frequency is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted, is applied to the solid-state imaging device 501. In this ninth embodiment, an FLL is provided for use in the AD converter 504 and the logic circuit 506, and an FLL is provided for use in the communication interface 507.

[0122] FIG. 20 is a block diagram showing an example of the configuration of a solid-state imaging device to which an oscillator circuit according to the ninth embodiment is applied.

[0123] In the figure, a solid-state imaging device 551 includes FLLs 552 and 553 instead of the FLL 502 of the fourth embodiment. Other configurations of the solid-state imaging device 551 of the ninth embodiment are similar to the configuration of the solid-state imaging device 501 of the first embodiment.

[0124] The FLL 552 can be used as a clock source for the AD converter 504 and the logic circuit 506. The FLL 553 can be used as a clock source for the communication interface 507.

[0125] In this case, the clock frequency of the FLL 553 can be set according to the operating frequency of the communication interface 507. Furthermore, frequency divider circuits 503 and 505 may be provided in front of the AD converter 504 and the logic circuit 506, respectively, according to the operating frequencies of the AD converter 504 and the logic circuit 506.

[0126] As described above, the ninth embodiment provides the FLL 552 used in the AD converter 504 and the logic circuit 506, and the FLL 553 used in the communication interface 507. This makes it possible to increase the frequency of the clock signal used in the solid-state imaging device 501 while suppressing an increase in power consumption of the oscillator circuit, thereby enabling higher resolution and a higher frame rate to be achieved while suppressing an increase in power consumption of the solid-state imaging device 501.

[0127] 10. Tenth Embodiment In the above-described fourth embodiment, the FLL 502, whose oscillation frequency is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted, is applied to the solid-state imaging device 501. In this tenth embodiment, the frequency of the FLL 502 used in the solid-state imaging device can be externally controlled.

[0128] FIG. 21 is a block diagram showing an example of the configuration of a solid-state imaging device to which the oscillator circuit according to the tenth embodiment is applied.

[0129] In the figure, a solid-state imaging device 561 is obtained by adding a logic circuit 562 to the solid-state imaging device 501 of the fourth embodiment described above. Other configurations of the solid-state imaging device 561 of the tenth embodiment are similar to the configurations of the solid-state imaging device 501 of the fourth embodiment described above.

[0130] The solid-state imaging device 561 is connected to a processor 563. The processor 563 can receive frequency information FIM of the FLL 502. The processor 563 can then transmit frequency adjustment information FID to the solid-state imaging device 561, which adjusts the frequency of the FLL 502 in accordance with a deviation in the frequency of the FLL 502. The processor 563 may be a central processing unit (CPU) or a graphics processing unit (GPU). The processor 563 may be a single-core processor or a multi-core processor.

[0131] The logic circuit 562 can adjust the frequency of the FLL 502 based on the frequency adjustment information FID transmitted from the processor 563. A variable capacitance element may be provided in the FLL 502 to adjust the frequency of the FLL 502. In this case, the logic circuit 562 can adjust the frequency of the FLL 502 by changing the capacitance of the variable capacitance element of the FLL 502 based on the frequency adjustment information FID.

[0132] As described above, in the tenth embodiment, the frequency of the FLL 502 used in the solid-state imaging device 561 can be adjusted by the processor 563. This makes it possible to improve the accuracy of the frequency of the clock signal used in the solid-state imaging device 561.

[0133] 11. Eleventh Embodiment In the first embodiment described above, the oscillation frequency of the FLL is controlled based on the comparison result of the phase into which the oscillation frequency of the oscillator 101 is converted. In this eleventh embodiment, substrates on which a solid-state imaging device is formed, the solid-state imaging device having a pixel array section in which pixels are arranged in a matrix, are stacked.

[0134] FIG. 22 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to the eleventh embodiment.

[0135] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921. The semiconductor material of the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0136] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor substrate 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0137] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The oscillator circuit 928 may have any of the configurations of the first to tenth embodiments described above. In this case, it is possible to reduce the power consumption of the oscillator circuit 928 and to integrate the oscillator circuit 928 on the semiconductor chip 921.

[0138] As described above, in the eleventh embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0139] Although the above-described embodiments show examples in which the oscillator circuit is applied to a solid-state imaging device, the oscillator circuit can be applied to any circuit, such as an integrated circuit, as long as it operates based on a clock signal. In this case, the oscillator circuits of the first to third embodiments described above may be used as a reference clock source for the integrated circuit. For example, the oscillator circuit may be used as a reference clock source for a processor, a communication device, an AD converter, a logic circuit, an image processing circuit, a display device, etc.

[0140] 12. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0141] FIG. 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0142] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0143] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0144] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0145] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0146] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0147] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0148] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0149] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0150] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0151] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 23, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0152] FIG. 24 is a diagram showing an example of the installation position of the imaging unit 12031.

[0153] In FIG. 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0154] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0155] 24 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0156] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0157] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0158] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0159] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0160] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, each of the oscillator circuits according to the above-described embodiments can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to reduce the size of the imaging unit 12031 while reducing power consumption.

[0161] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0162] The present technology may also be configured as follows: (1) An oscillation circuit comprising: an oscillator; and a phase comparator that configures a feedback loop for the oscillator based on a comparison result of the phase into which the oscillation frequency of the oscillator is converted. (2) The oscillation circuit according to (1), wherein the phase comparator comprises: a first sub-oscillator that converts a reference voltage into a phase; and a second sub-oscillator that converts a control voltage into which the oscillation frequency of the oscillator is converted into a phase. (3) The oscillation circuit according to (2), wherein the phase comparator comprises: a chopper circuit that alternately switches the input source and output destination of the first sub-oscillator and the second sub-oscillator. (4) The oscillation circuit according to (2) or (3), wherein the phase comparator comprises: a phase frequency detector (PFD) connected downstream of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected downstream of the PFD; and a loop filter connected downstream of the charge pump circuit. (5) The oscillation circuit according to any one of (2) to (4), wherein the first sub-oscillator and the second sub-oscillator are each an LC oscillator or a ring oscillator. (6) The oscillation circuit according to any one of (2) to (4), wherein the first sub-oscillator and the second sub-oscillator are each a DCO (Digitally Controlled Oscillator). (7) The oscillation circuit according to any one of (2) to (6), comprising a switched capacitor that converts the oscillation frequency of the oscillator into the control voltage. (8) The oscillation circuit according to any one of (1) to (7), wherein the oscillation circuit is used as a reference clock source for an integrated circuit. (9) The oscillation circuit according to (8), wherein the oscillation circuit is integrated on a semiconductor chip on which the integrated circuit is formed. (10) The oscillation circuit according to any one of (1) to (9), comprising a PLL (Phase Locked Loop) connected in a stage subsequent to the oscillator.(11) A method for controlling an oscillation frequency, comprising: a step of converting an oscillation frequency of an oscillator into a control voltage based on switched capacitor operation; a step of converting the control voltage into a first phase based on a first oscillation operation based on the control voltage; a step of converting the reference voltage into a second phase based on a second oscillation operation based on a reference voltage; a step of detecting a difference between the first phase and the second phase; a step of converting the difference between the first phase and the second phase into a current based on charge pump operation; and a step of controlling the oscillation frequency of the oscillator based on loop filter operation based on the current.

[0163] 101 Oscillator 102 Phase comparator 103 PFD 104 Charge pump circuit 105 Loop filter 106 Switched capacitor SB1, SB2 Sub-oscillator R1 to R3 Resistors C1 Capacitor W1, W2 Switch

Claims

1. An oscillation circuit comprising: an oscillator; and a phase comparator that forms a feedback loop for the oscillator based on a comparison result of the phase into which the oscillation frequency of the oscillator is converted.

2. The oscillation circuit according to claim 1, wherein the phase comparison unit comprises a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase.

3. The oscillation circuit according to claim 2, further comprising a chopper circuit that alternately switches the input source and output destination of the first sub-oscillator and the second sub-oscillator.

4. The oscillation circuit according to claim 2, wherein the phase comparison unit comprises: a PFD (Phase Frequency Detector) connected to a stage subsequent to the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a stage subsequent to the PFD; and a loop filter connected to a stage subsequent to the charge pump circuit.

5. The oscillator circuit according to claim 2, wherein the first sub-oscillator and the second sub-oscillator are each an LC oscillator or a ring oscillator.

6. The oscillation circuit according to claim 2, wherein the first sub-oscillator and the second sub-oscillator are each a DCO (Digitally Controlled Oscillator).

7. The oscillation circuit according to claim 2, further comprising a switched capacitor for converting the oscillation frequency of said oscillator into said control voltage.

8. The oscillator circuit according to claim 1, which is used as a reference clock source for an integrated circuit.

9. The oscillator circuit according to claim 8, which is integrated on a semiconductor chip on which said integrated circuit is formed.

10. The oscillation circuit according to claim 1, further comprising a PLL (Phase Locked Loop) connected in a subsequent stage to the oscillator.

11. A method for controlling an oscillation frequency, comprising: a step of converting an oscillation frequency of an oscillator into a control voltage based on switched capacitor operation; a step of converting the control voltage into a first phase based on a first oscillation operation based on the control voltage; a step of converting the reference voltage into a second phase based on a second oscillation operation based on a reference voltage; a step of detecting a difference between the first phase and the second phase; a step of converting the difference between the first phase and the second phase into a current based on charge pump operation; and a step of controlling the oscillation frequency of the oscillator based on loop filter operation based on the current.

Images