Method for manufacturing group iii nitride semiconductor device

Abstract

A method for manufacturing a Group III nitride semiconductor device according to the present disclosure comprises: a first step for disposing a second impurity by ion implantation in a predetermined region near the surface of a first Group III nitride semiconductor layer containing a first impurity; a second step for forming a second Group III nitride semiconductor protective layer containing a third impurity on the surface of the first Group III nitride semiconductor layer at a temperature of 1200°C or higher; and a third step for removing at least a portion of the protective layer to expose a region on the surface of the first Group III nitride semiconductor layer.

Description

Method for manufacturing a group III nitride semiconductor device

[0001] The present disclosure relates to a method for manufacturing a Group III nitride semiconductor device, and more particularly to a method for manufacturing a Group III nitride semiconductor device that facilitates p-type conversion by ion implantation.

[0002] In order to realize vertical group-III nitride power devices, localized p-type conductivity control technology using ion implantation is important. In the process of fabricating a p-type region by ion implantation, activation annealing is performed after the ion implantation to restore the crystallinity. However, nitride semiconductors suffer from thermal decomposition at high heat treatment temperatures, which causes nitrogen desorption from the substrate surface, resulting in degradation of crystallinity. For example, in the case of GaN, thermal decomposition occurs at temperatures above 850°C. When an annealing process at temperatures above 1200°C is performed to activate the ion-implanted region, decomposition of GaN (nitrogen desorption) occurs during the annealing process. Therefore, it is extremely difficult to convert group-III nitride semiconductors to p-type conductivity by ion implantation.

[0003] A technique for suppressing nitrogen desorption from a nitride semiconductor and realizing p-type conductivity by ion implantation is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2020-155468

[0005] Patent Document 1 proposes a method of suppressing nitrogen desorption by high-pressure annealing in a high-pressure environment equal to or higher than the saturated vapor pressure of GaN, thereby realizing p-type conversion by ion implantation.

[0006] However, in the high-pressure annealing of Patent Document 1, for example, when annealing at 1400°C, the saturated vapor pressure of GaN is 600 MPa at 1400°C. Therefore, it is necessary to create a high pressure of 600 MPa or more inside the crucible in which the GaN substrate is placed. It is technically difficult to create a pressure vessel that can withstand the harsh conditions of a high pressure of 600 MPa or more and a high temperature of 1400°C, particularly a large pressure vessel that can accommodate large-area nitride semiconductor substrates. Therefore, in the manufacture of Group III nitride semiconductor devices, there is still room for improvement in the conventional method of realizing p-type conversion by ion implantation.

[0007] Therefore, the present disclosure is intended to solve the above-mentioned conventional problems, and has an object to provide a method for manufacturing a group III nitride semiconductor device that facilitates p-type conversion by ion implantation.

[0008] In order to achieve the above object, a method for manufacturing a Group III nitride semiconductor device according to the present disclosure includes: a first step of disposing a second impurity by ion implantation in a predetermined region near the surface of a first Group III nitride semiconductor layer containing a first impurity; a second step of forming a protective layer of a second Group III nitride semiconductor containing a third impurity on the surface of the first Group III nitride semiconductor layer at a temperature of 1200°C or higher; and a third step of removing at least a portion of the protective layer to expose a region on the surface of the first Group III nitride semiconductor layer.

[0009] According to one aspect of the present disclosure, it is possible to provide a method for manufacturing a Group III nitride semiconductor device that facilitates p-type conversion by ion implantation.

[0010] 1 is a schematic diagram showing the configuration of an apparatus for forming a protective layer of a Group III nitride semiconductor; 2 is a flowchart showing a process for forming a protective layer of a Group III nitride semiconductor; 3 is a schematic diagram showing the configuration of an apparatus for forming a protective layer of a Group III nitride semiconductor; 4 is a flowchart showing a process for forming a protective layer of a Group III nitride semiconductor; 5 is a schematic diagram showing the configuration of an apparatus for forming a protective layer of a Group III nitride semiconductor; 6 is a schematic diagram showing the configuration of an apparatus for forming a protective layer of a Group III nitride semiconductor;

[0011] According to a first aspect of the present disclosure, there is provided a method for manufacturing a Group III nitride semiconductor device, comprising: a first step of disposing a second impurity by ion implantation in a predetermined region near the surface of a first Group III nitride semiconductor layer containing a first impurity; a second step of forming a protective layer of a second Group III nitride semiconductor containing a third impurity on the surface of the first Group III nitride semiconductor layer at a temperature of 1200°C or higher; and a third step of removing at least a portion of the protective layer to expose a region on the surface of the first Group III nitride semiconductor layer.

[0012] According to this aspect, it is possible to provide a method for manufacturing a group III nitride semiconductor device that facilitates p-type conversion by ion implantation.

[0013] According to a second aspect of the present disclosure, there is provided a method for manufacturing a Group III nitride semiconductor device as defined in the first aspect, wherein the second step includes supplying a nitrogen-containing gas and a Group III element oxide gas into a chamber at near atmospheric pressure, and growing a second Group III nitride crystal constituting a protective layer on a surface of the first Group III nitride semiconductor layer disposed in the chamber.

[0014] According to a third aspect of the present disclosure, the third step is an electrochemical etching step, and the carrier concentration of the protective layer of the second Group III nitride semiconductor is 5E+19 / cm ３ and the carrier concentration of the first Group III nitride semiconductor layer is 5E+19 / cm ３ The present invention provides a method for manufacturing a Group III nitride semiconductor device according to the first or second aspect, wherein the number of times of the first or second semiconductor device is less than 1000 μm.

[0015] According to a fourth aspect of the present disclosure, the carrier concentration of the region is 5E+19 / cm ３ The present invention provides a method for manufacturing a Group III nitride semiconductor device according to a third aspect, wherein the thickness of the semiconductor device is less than 100 nm.

[0016] According to a fifth aspect of the present disclosure, there is provided a method for manufacturing a Group III nitride semiconductor device according to any one of the first to fourth aspects, wherein the second Group III nitride semiconductor is gallium nitride, and the third impurity is oxygen.

[0017] According to a sixth aspect of the present disclosure, there is provided the method for manufacturing a Group III nitride semiconductor device according to any one of the first to fifth aspects, wherein the second impurity is a p-type impurity and is at least one selected from the group consisting of magnesium, calcium, beryllium, and zinc.

[0018] According to a seventh aspect of the present disclosure, there is provided the method for manufacturing a Group III nitride semiconductor device according to any one of the first to sixth aspects, wherein the first impurity is at least one selected from the group consisting of oxygen, silicon, tin, germanium, carbon, iron, and manganese.

[0019] Any of the above-described various embodiments may be combined appropriately to achieve the effects of each of them.

[0020] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, more detailed explanation than necessary may be omitted. For example, detailed explanation of well-known matters or redundant explanation of substantially the same configuration may be omitted. This is to avoid unnecessary redundancy in the following explanation and to facilitate understanding by those skilled in the art.

[0021] A method for manufacturing a Group III nitride semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 8. The accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter recited in the claims. In addition, in each drawing, the dimensions of each element are exaggerated for ease of explanation. Note that substantially identical elements in the drawings are designated by the same reference numerals.

[0022] First Embodiment (Process for Providing a p-type Conductor in Manufacturing a Group III Nitride Semiconductor Device) A process for providing a p-type Conductor in manufacturing a Group III nitride semiconductor device according to a first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a flowchart of the process for providing a p-type Conductor in manufacturing a Group III nitride semiconductor device according to an embodiment of the present disclosure.

[0023] Group III nitride semiconductor devices include light-emitting devices using Group III nitride semiconductors, such as light-emitting diodes, and electronic devices using Group III nitride semiconductors, such as field-effect transistors. In the manufacture of Group III nitride semiconductor devices, a localized p-type region can be formed by the process shown in the flowchart of FIG.

[0024] 1 can include the steps of forming a group III nitride semiconductor layer (S01), disposing p-type impurities in the group III nitride semiconductor layer (S02), forming a protective layer of the group III nitride semiconductor at a temperature of 1200° C. or higher and activating the impurity-implanted region (S03), and removing the protective layer of the group III nitride semiconductor to expose the p-type region (S04). Each step will be described below.

[0025] (Step S01 of Forming a Group III Nitride Semiconductor Layer) In step S01, a Group III nitride semiconductor layer is formed on a support substrate. In this embodiment, the support substrate may be, for example, a substrate that can be used as a substrate for epitaxial growth, such as a GaN freestanding substrate, an AlN freestanding substrate, a sapphire substrate, or a silicon substrate. The Group III nitride semiconductor layer may be composed of, for example, gallium nitride containing n-type impurities (hereinafter referred to as an "n-type GaN layer"). The n-type impurities contained in the n-type GaN layer may be at least one selected from the group consisting of oxygen, silicon, tin, germanium, carbon, iron, and manganese. The n-type GaN layer can be formed by epitaxial growth, for example, generally by the HVPE method. The n-type GaN layer formed by the HVPE method contains n-type impurities and has a dopant concentration of 5E+19 / cm. ３ In this specification, E represents a power of 10. For example, 1E+19 is a power of 10. １９ means.

[0026] The n-type GaN layer can be formed by the HVPE method using a conventionally known method, and therefore a detailed description thereof will be omitted.

[0027] (Step S02 of disposing p-type impurities) Next, step S02 of disposing p-type impurities in the group III nitride semiconductor layer will be described with reference to Fig. 2. Fig. 2 is a conceptual diagram showing the step of disposing p-type impurities M in the group III nitride semiconductor layer 10 by ion implantation in the process of Fig. 1. Note that Fig. 2 does not show a support substrate that supports the group III nitride semiconductor layer 10.

[0028] 2 is an n-type GaN layer, and in step S02 of disposing a p-type impurity in the n-type GaN layer, p-type impurity M is ion-implanted from surface 10a of the n-type GaN layer. At this time, for example, a resist mask can be used to locally implant the ions into predetermined positions on surface 10a of the n-type GaN layer. After the ion implantation, the resist mask is removed.

[0029] The ion species of the p-type impurity M implanted into the n-type GaN layer may be at least one selected from the group consisting of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc). In this embodiment, Mg is used as the p-type impurity, and Mg ions can be implanted into the impurity-implanted region 20 near the surface 10a of the n-type GaN layer.

[0030] The acceleration voltage for ion implantation can be set according to the implantation depth. The higher the acceleration voltage, the deeper the depth to which Mg is implanted. In this embodiment, the impurity implanted region 20 having a depth D can be formed by implanting Mg ions multiple times at different acceleration voltages to different implantation depths. In this embodiment, the concentration of the p-type impurity Mg in the impurity implanted region 20 is set to 5E+20 / cm across the depth D. ３ At this time, due to the self-compensation effect in the n-type GaN layer, the carrier concentration of the impurity-implanted region 20 is less than 5E+19 / cm ３ is less than.

[0031] Nitrogen may also be implanted together with the Mg ion implantation. By implanting p-type impurities and nitrogen together, nitrogen vacancies that may occur during ion implantation can be reduced.

[0032] (Step S03 of Forming a Protective Layer of a Group III Nitride Semiconductor and Activating an Impurity-Implanted Region) Next, step S03 of forming a protective layer of a Group III nitride semiconductor at a temperature of 1200° C. or higher and activating the impurity-implanted region will be described with reference to FIGS. 3 to 5. FIG. 3 is a schematic diagram showing the configuration of an apparatus 150 for forming a protective layer of a Group III nitride semiconductor, and FIG. 4 is a flowchart showing a process 300 for forming a protective layer of a Group III nitride semiconductor. FIG. 5 is a conceptual diagram showing the steps of forming a protective layer 30 of a Group III nitride semiconductor and activating the impurity-implanted region 20 in the process of FIG. 1.

[0033] <Outline of Apparatus for Forming a Protective Layer of a Group III Nitride Semiconductor> An outline of an apparatus 150 for forming a protective layer of a Group III nitride semiconductor according to an embodiment of the present disclosure will be described with reference to Fig. 3. Note that in Fig. 3, the size, ratio, etc. of each component may differ from the actual size, ratio, etc.

[0034] In an apparatus 150 for forming a protective layer of a Group III nitride semiconductor according to an embodiment of the present disclosure, a source reaction chamber 101 is disposed within a source chamber 100, and a source boat 104 carrying a starting Group III element source 105 is disposed within the source reaction chamber 101. A reactive gas supply pipe 103 is connected to the source reaction chamber 101, supplying a reactive gas that reacts with the starting Group III element source 105, and the source reaction chamber 101 also has a Group III oxide gas outlet 107. Here, a reducing gas is used as the reactive gas when the starting Group III source is an oxide, and an oxidizing gas is used when the starting Group III source is a metal. The source chamber 100 is further provided with a first carrier gas supply port 102.

[0035] The Group III oxide gas generated in the raw material reaction chamber 101 is discharged into the raw material chamber 100 through the Group III oxide gas outlet 107, and flows together with the carrier gas from the carrier gas outlet 108 through the connecting pipe 109 to the growth chamber 111.

[0036] The growth chamber 111 includes a Group III oxide gas and carrier gas supply port 118, an oxidizable gas supply port 113, a nitrogen-containing gas supply port 112, a second carrier gas supply port 114, and an exhaust port 119. A substrate susceptor 117 is provided within the growth chamber 111, and a support substrate 116 on which an n-type GaN layer 10 having an impurity region 20 is formed is placed on the substrate susceptor 117. In the process of forming a protective layer for a Group III nitride semiconductor, a protective layer for a Group III nitride semiconductor is formed on a surface 10a of the n-type GaN layer 10.

[0037] <Process for Forming a Protective Layer of a Group III Nitride Semiconductor> A process 300 for forming a protective layer of a Group III nitride semiconductor according to this embodiment will be described in detail with reference to FIGS. 3 and 4 . In process 300, a Group III nitride crystal is grown by oxide vapor phase epitaxy (OVPE) using a Group III element oxide gas as a raw material to form a protective layer of the Group III nitride semiconductor. In this embodiment, the protective layer of the Group III nitride semiconductor is a gallium nitride crystal layer and is composed of gallium nitride crystal. In the following description, the protective layer of the Group III nitride semiconductor will be referred to as a "GaN protective layer." The process for forming a GaN protective layer will be described using, as an example, metallic Ga as the starting Group III element source 105.

[0038] 4 may include a reactive gas supply step (S301), a Group III element oxide gas generation step (S302), a Group III element oxide gas supply step (S303), a nitrogen-containing gas supply step (S304), a Group III nitride crystal generation step (S305), and a residual gas exhaust step (S306). Each step is described below. All steps in the Group III nitride semiconductor protective layer formation step (S300) may be performed at or near atmospheric pressure. In this specification, "near atmospheric pressure" refers to a pressure range including a ±10% pressure fluctuation around atmospheric pressure, i.e., a range of 0.9 atm to 1.1 atm.

[0039] (1) In the reactive gas supply step S 301 , a reactive gas is supplied to the source reaction chamber 101 through the reactive gas supply pipe 103 .

[0040] Methods for generating a group III oxide gas are roughly classified into a method for reducing the starting Ga source 105 and a method for oxidizing the starting Ga source 105. For example, in the reduction method, an oxide (e.g., Ga ２ O ３ ), a reducing gas (e.g., H ２ Gas, CO gas, CH ４ Gas, C ２ H ６ Gas, H ２ S gas, SO ２ On the other hand, in the oxidation method, a non-oxide (e.g., liquid Ga) is used as the starting Ga source 105, and an oxidizing gas (e.g., H ２ O gas, O ２ In step S301, a reactive gas corresponding to the starting Ga source 105 used can be supplied to the raw material reaction chamber 101, and in this embodiment, for example, when metallic Ga is used as the starting Group III element source 105, an oxidizing gas is supplied as the reactive gas from the reactive gas supply pipe 103 to the raw material reaction chamber 101.

[0041] (2) In the Group III element oxide gas generating step S302, the reactive gas supplied to the raw material reaction chamber 101 in the reactive gas supplying step reacts with metal Ga, which is the starting Group III element source 105, to produce Group III oxide gas Ga ２ O gas is generated. Ga ２ The O gas is discharged from the source reaction chamber 101 to the source chamber 100 via the group III oxide gas discharge port 107. ２ The O gas is mixed with a first carrier gas supplied to the source chamber from a first carrier gas supply port 102, and is supplied to a Group III oxide gas and carrier gas outlet port 108. Here, an inert gas or H gas can be used as the first carrier gas.

[0042] In this embodiment, the reactive gas is H 2 , which is an oxidizing gas. ２ When O gas is supplied to the source reaction chamber 101, a group III oxide gas is generated, for example, according to the following formula (1).

[0043]

[0044] Here, the temperature of the first heater 106 is set to Ga ２ The temperature is set to 800° C. or higher in consideration of the boiling point of O gas, and to be lower than 1800° C. so as to be lower than the temperature of the second heater 115. The starting Ga source is placed in the source boat 104. The source boat 104 preferably has a shape that can increase the contact area between the reactive gas and the starting Ga source.

[0045] (3) In the Group III element oxide gas supply step S303, Ga generated in the Group III element oxide gas generation step S302 is supplied. ２ The group III element oxide gas GaO gas is supplied to the growth chamber 111 via the group III oxide gas and carrier gas outlet 108, the connecting pipe 109, and the group III oxide gas and carrier gas supply port 118. In this embodiment, the group III element oxide gas GaO gas is supplied to the growth chamber 111. ２ The amount of O gas can be adjusted.

[0046] Furthermore, when the temperature of the connecting pipe 109 connecting the source chamber 100 and the growth chamber 111 drops below the temperature of the source chamber 100, a reverse reaction of the reaction for producing the Group III oxide gas occurs, and the starting Ga source 105 precipitates inside the connecting pipe 109. Therefore, the connecting pipe 109 is heated by the third heater 110 to a temperature higher than that of the first heater 106 so that the temperature does not drop below that of the source chamber 100.

[0047] (4) In the nitrogen-containing gas supply step S304, a nitrogen-containing gas is supplied to the growth chamber 111 from the nitrogen-containing gas supply port 112. The nitrogen-containing gas is NH ３ Gas, NO Gas, NO ２ Gas, N ２ O gas, N ２ H ２ Gas, N ２ H ４ Gas, etc. can be used.

[0048] (5) In the Group III nitride crystal growth step S305, the source gases supplied into the growth chamber via the various supply steps are synthesized to grow a Group III nitride crystal. The growth chamber 111 is heated by the second heater 115 to a temperature at which the Group III oxide gas and the nitrogen-containing gas react. During this process, the growth chamber 111 is heated so that its temperature does not drop below the temperature of the source chamber 100, in order to prevent a reverse reaction of the reaction that produces the Group III oxide gas.

[0049] In this embodiment, the temperature of the second heater 115 can be set so that the temperature of the support substrate 116 placed in the growth chamber 111 is 1200° C. or higher. ２ The temperature of the third heater 110 can be set according to the set temperature of the second heater 115 so as to suppress temperature fluctuations in the growth chamber 111 caused by the O gas and the first carrier gas. This allows the support substrate 116 placed in the growth chamber 111 to be maintained at a temperature of 1200°C or higher, enabling GaN crystal to grow on the support substrate 116. At the same time, a temperature of 1200°C or higher meets the temperature condition for activating the impurity-implanted region 20 in the n-type GaN layer 10 on the support substrate 116, and therefore the impurity-implanted region 20 can be activated.

[0050] In this embodiment, in step S305, the Group III oxide gas, Ga, which is supplied to the growth chamber 111 through the Group III element oxide gas supply step S303, is ２ O gas and NH 4 , a nitrogen-containing gas, which is supplied to the growth chamber 111 through the nitrogen-containing gas supply step S304. ３ By mixing the gas with the gas upstream of the support substrate 116, GaN crystals are grown on the support substrate 116 according to the following formula (2), and a GaN protective layer made of GaN crystals can be formed on the surface 10 a of the n-type GaN layer 10.

[0051]

[0052] In step S205, for example, a nitrogen-containing gas NH ３ With respect to the amount of Group III oxide gas Ga２ By adjusting the supply amount of O gas, the carrier concentration of the group III nitride GaN crystal to be produced can be adjusted.

[0053] 5 , in the group III nitride crystal growth step S305, GaN crystals are grown at a temperature of 1200° C. or higher to form a GaN protective layer 30 on the surface 10 a of the n-type GaN layer 10, and the impurity-implanted region 20 is activated to form a p-type region 20A. The growth of GaN crystals on the surface 10 a of the n-type GaN layer 10 means that the equilibrium between adsorption and desorption on the surface is tilted toward adsorption. Therefore, the impurity-implanted region 20 can be activated to form the p-type region 20A while suppressing nitrogen desorption from the n-type GaN layer 10 using the growth driving force of the GaN protective layer.

[0054] In addition, in order to prevent the nitrogen-containing gas shown in FIG. 3 from being decomposed by heat from the growth chamber 111, it is preferable to cover the nitrogen-containing gas supply port 112 and the outer wall of the growth chamber 111 with a heat insulating material.

[0055] Parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117 can be a problem. Therefore, by controlling the concentrations of the group III oxide gas and the nitrogen-containing gas using the second carrier gas supplied to the growth chamber 111 from the second carrier gas supply port 114, it is possible to suppress the parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117. Here, the second carrier gas can be an inert gas or H ２ A gas can be used.

[0056] (6) In the residual gas exhaust step S306, the carrier gas that does not contribute to the growth of GaN crystals and unreacted gas are exhausted from the exhaust port 119.

[0057] The carrier concentration of a group III nitride semiconductor depends on the concentration of impurity elements contained in the group III nitride semiconductor. The GaN protective layer formed by the OVPE method can contain high concentrations of impurity elements, and therefore has a very high carrier concentration, and can have a carrier concentration higher than that of an n-type GaN layer formed by, for example, the HVPE method. Specifically, in this embodiment, the impurity contained in the GaN protective layer 30 may be oxygen, and the GaN protective layer 30 has a carrier concentration of 5E+19 / cm ３ On the other hand, an n-type GaN layer formed by the HVPE method or the like can have a high carrier concentration of 5E+19 / cm ３ has a carrier concentration of less than

[0058] Thus, in step S03 of forming a protective layer for a Group III nitride semiconductor and activating the impurity-implanted region, the GaN protective layer is formed by OVPE at a temperature of 1200°C or higher, thereby enabling activation of the impurity-implanted region while suppressing nitrogen desorption. OVPE, which can be performed at near atmospheric pressure, enables activation of the impurity-implanted region without requiring the harsh conditions of high-pressure annealing. Furthermore, OVPE, which is a vapor phase growth method, can easily accommodate large-area nitride semiconductor substrates, for example, up to 12 inches.

[0059] The time required to activate the impurity implantation region 20 varies depending on the concentration of the impurity contained in the impurity implantation region 20 and the depth D of the impurity implantation region 20. In the OVPE method, the time required to form the GaN protective layer can be set as needed, and annealing can also be performed for a long period of time as needed.

[0060] Furthermore, the thickness T of the GaN protective layer formed in step S03 can be varied depending on the time for activating the impurity-implanted region 20 and the temperature of the OVPE group III nitride crystal growth step S305. In principle, it is possible to form a GaN protective layer with a uniform thickness T using the OVPE method. The present disclosure is not limited to the thickness T of the GaN protective layer.

[0061] (Step S04 of removing the protective layer of the Group III nitride semiconductor and exposing the p-type region) Returning to Fig. 1 , next, step S04 of removing the protective layer of the Group III nitride semiconductor and exposing the p-type region will be described with reference to Fig. 6 and Fig. 7 . Fig. 6 is a conceptual diagram showing the step of removing the protective layer of the Group III nitride semiconductor and exposing the p-type region in the process of Fig. 1 . Fig. 7 is a graph showing the carrier concentration dependence of the etching rate in electrochemical etching of a Group III nitride semiconductor.

[0062] In this embodiment, step S04 is performed by electrochemical etching. It is generally known that the etching rate of electrochemical etching varies depending on the electrical conductivity of the etching target. The inventors of the present application have investigated the relationship between the etching rate and the carrier concentration of the etching target in electrochemical etching of a Group III nitride semiconductor. Figure 7 shows the relationship between the etching rate and the carrier concentration of the etching target when the carrier concentration is 1E+15 / cm ３ GaN substrate A less than about 2E+18 / cm ３ GaN substrate B of about 1E+19 / cm ３ GaN substrate C of about 5E+19 / cm ３ GaN substrate D of about 1E+20 / cm ３ 1 shows the results of measuring the etching rates when electrochemical etching was performed using GaN substrate E of 1 and GaN substrate E of 2.

[0063] As shown in FIG. 7, when the carrier concentration is 1E+15 / cm ３ The etching rate of GaN substrate A is almost zero and is 2E+18 / cm ３ In the case of GaN substrate B, the etching rate is 200 μm / h, but this is due to etching into a porous structure, and electrochemical etching does not progress substantially. On the other hand, the carrier concentration is about 1E+19 / cm ３ The etching rate of GaN substrate C increased to about 600 μm / h. Furthermore, the carrier concentration increased to 5E+19 / cm ３ When the etching rate exceeds 5E+19 / cm ３It has been found that the etching rates of the above GaN substrates D and E reach 3000 μm / h or more. Based on this finding, in this embodiment, the GaN protective layer 30 with a high carrier concentration can be selectively removed by electrochemical etching.

[0064] As shown in FIG. 6, in step S04, electrochemical etching was performed to obtain a thickness of 5E+19 / cm ３ At least a portion of the GaN protective layer 30 having a high carrier concentration of 5E+19 / cm or more can be removed by etching, thereby exposing the p-type region 20A on the surface 10a of the n-type GaN layer 10. ３ The n-type GaN layer 10 having a carrier concentration of less than 5E+19 / cm has a low etching rate and can essentially function as an etch stop layer. ３ The etching rate is low and the exposed portion can be exposed without being substantially etched.

[0065] Electrochemical etching can be performed by a conventionally known method using a solution of an alkali such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or an acid such as hydrochloric acid (HCl) dissolved in water, glycol, etc. A detailed description thereof will be omitted here.

[0066] As described above, by the process including steps S01 to S04, nitrogen desorption can be suppressed without requiring high-pressure annealing in the manufacture of a group III nitride semiconductor device, and p-type conversion by ion implantation can be achieved.

[0067] (Fabrication of p-type region by example) Using the method for manufacturing a group III nitride semiconductor device according to an embodiment of the present disclosure, a localized p-type region was formed by ion implantation. Examples according to the embodiment of the present disclosure will be described below.

[0068] In this example, an impurity region was formed on the surface of an n-type GaN layer containing n-type impurity silicon (Si) by ion implantation at an acceleration voltage of 30 keV with a dose of 5.8E+13 / cm. ２Mg and nitrogen were co-implanted from the surface of the n-type GaN layer in the order of N→Mg by implantation of N and Mg.

[0069] Next, a GaN protective layer was formed on the surface of the n-type GaN layer by OVPE, and the impurity-implanted region was activated by OVPE at 1200° C. for 1 hour.

[0070] Subsequently, a portion of the GaN protective layer was removed by electrochemical etching. The n-type GaN substrate with the GaN protective layer formed thereon was immersed in a 1 M KOH aqueous solution, and electrochemical etching was performed with the substrate side as the anode and a platinum (Pt) electrode as the cathode at an applied voltage of 13 V. The surface flatness of the substrate after the GaN protective layer was removed was confirmed by AFM, and a low-temperature photoluminescence (PL) spectrum was obtained.

[0071] (Evaluation of p-type region by example)

[0072] In this example, an n-type GaN layer that is not intentionally doped with impurities is doped with a peak concentration of 1E+19 / cm ３ The carrier concentration of the GaN protective layer formed by the OVPE method was measured using a Hall measurement method, and was found to be 5E+19 / cm ３ That was all.

[0073] Scanning electron microscope (SEM) observation revealed that the GaN protective layer formed by OVPE was polycrystalline and had a film thickness of approximately 40 μm. Although some GaN protective layer remained, electrochemical etching succeeded in selectively removing most of the GaN protective layer. After removing the GaN protective layer, the surface flatness of the substrate was evaluated with an AFM, revealing an RMS value of 0.4 nm, with no surface roughness observed.

[0074] The results of low-temperature photoluminescence measurement of the substrate surface exposed after removing the GaN protective layer are shown in Figure 8. Figure 8 shows the low-temperature photoluminescence (PL) spectrum of the surface of the n-type GaN layer from which the GaN protective layer was removed according to the example. As shown in Figure 8, a peak P1 due to Mg was clearly observed at a photon energy of approximately 3.28 eV, confirming that Mg was activated.

[0075] According to the p-type conversion process of this embodiment, it is possible to manufacture a group III nitride semiconductor device in which a local p-type region can be formed by ion implantation.

[0076] In the above description, the Group III nitride semiconductor layer formed on the support substrate is described as a gallium nitride crystal layer (n-type GaN layer), but the present disclosure is not limited to this. For example, the Group III nitride semiconductor layer may be composed of AlGaN (aluminum gallium nitride), AlN (aluminum nitride), InN (indium nitride), InGaN (indium gallium nitride), or a mixed crystal thereof.

[0077] Furthermore, although the protective layer of a Group III nitride semiconductor formed by OVPE has been described as a gallium nitride crystal layer (GaN protective layer), the present disclosure is not limited thereto. For example, in the apparatus 150 for forming a protective layer of a Group III nitride semiconductor shown in FIG. 3 , an In source and an Al source can be used as the starting Group III element source 105 in addition to a Ga source. The Group III nitride crystal layer formed may be composed of, for example, InN (indium nitride), AlN (aluminum nitride), or the like.

[0078] In the above description, step S04 of removing the protective layer of the Group III nitride semiconductor and exposing the p-type region shown in FIG. 1 is described as being performed by electrochemical etching, but the present disclosure is not limited to this. For example, the protective layer of the Group III nitride semiconductor can also be removed by photoelectrochemical etching or mechanical processing.

[0079] As described above, the accompanying drawings and detailed description have been provided to explain exemplary embodiments of the technology disclosed herein. Therefore, the components described in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to illustrate the technology. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential.

[0080] Although the present disclosure has been fully described in connection with the preferred embodiments with reference to the accompanying drawings, various modifications are possible within the scope of the claims, and such modifications and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the present disclosure.

[0081] The present disclosure is applicable to the manufacture of Group III nitride semiconductor devices. According to the method for manufacturing a Group III nitride semiconductor device according to the present disclosure, nitrogen desorption can be suppressed without requiring high-pressure annealing, and p-type conversion can be achieved by ion implantation.

[0082] 10 Group III nitride semiconductor layer (n-type GaN layer) 20 Impurity-implanted region 20A p-type region 30 Group III nitride semiconductor protective layer (GaN protective layer) 100 Source chamber 101 Source reaction chamber 102 First carrier gas supply port 103 Reactive gas supply pipe 104 Source boat 105 Starting Group III element source (starting Ga source) 106 First heater 107 Group III oxide gas outlet 108 Group III oxide gas and carrier gas outlet 109 Connecting pipe 110 Third heater 111 Growth chamber 112 Nitrogen-containing gas supply port 113 Oxidizable gas supply port 114 Second carrier gas supply port 115 Second heater 116 Support substrate 117 Substrate susceptor 118 Group III oxide gas and carrier gas supply port 119 Exhaust port 150: Apparatus for forming a protective layer of a group III nitride semiconductor 300: Process for forming a protective layer of a group III nitride semiconductor

Claims

1. A method for manufacturing a Group III nitride semiconductor device, comprising: a first step of disposing a second impurity by ion implantation in a predetermined region near the surface of a first Group III nitride semiconductor layer containing a first impurity; a second step of forming a protective layer of a second Group III nitride semiconductor containing a third impurity on the surface of the first Group III nitride semiconductor layer at a temperature of 1200°C or higher; and a third step of removing at least a portion of the protective layer to expose the region on the surface of the first Group III nitride semiconductor layer.

2. The method for producing a Group III nitride semiconductor device according to claim 1, wherein the second step comprises supplying a nitrogen-containing gas and a Group III element oxide gas into a chamber at near atmospheric pressure, and growing a second Group III nitride crystal constituting the protective layer on the surface of the first Group III nitride semiconductor layer placed in the chamber.

3. The third step is an electrochemical etching step, and the carrier concentration of the second Group III nitride semiconductor protective layer is 5E+19 / cm ３ and wherein the carrier concentration of the first Group III nitride semiconductor layer is 5E+19 / cm ３ The method for producing a Group III nitride semiconductor device according to claim 1 or 2, wherein the thickness of the semiconductor device is less than 100 nm.

4. The carrier concentration of the region is 5E+19 / cm ３ The method of claim 3 , wherein the thickness of the III-nitride semiconductor device is less than 100 nm.

5. The method for producing a Group III nitride semiconductor device according to claim 1 or 2, wherein the second Group III nitride semiconductor is gallium nitride, and the third impurity is oxygen.

6. The method for producing a Group III nitride semiconductor device according to claim 1 or 2, wherein the second impurity is a p-type impurity and is at least one selected from the group consisting of magnesium, calcium, beryllium, and zinc.

7. The method for producing a Group III nitride semiconductor device according to claim 1 or 2, wherein the first impurity is at least one selected from the group consisting of oxygen, silicon, tin, germanium, carbon, iron, and manganese.

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