Array substrate, display panel, display apparatus and driving method

Abstract

An array substrate, a display panel, a display apparatus and a driving method. The array substrate comprises: a plurality of gate lines (G); a plurality of data lines (D); a plurality of pixel electrode rows (P00), wherein the plurality of pixel electrode rows (P00) extend in a first direction (X) and are arranged in a second direction (Y), at least one of the plurality of pixel electrode rows (P00) comprises a plurality of pixel electrodes (P) emitting light of different colors, and the pixel electrodes (P) are located in regions formed by the intersection of the gate lines (G) and the data lines (D); and a plurality of transistors (T), wherein the pixel electrodes (P) are electrically connected to the gate lines (G) and the data lines (D) by means of the transistors (T), a plurality of pixel electrodes (P) electrically connected to the same data line (D) by means of the transistors (T) are alternately located on different sides of the data line (D), and two pixel electrodes (P) located in at least some adjacent pixel electrode rows (P00) and electrically connected to the same data line (D) by means of the transistors (T) emit light of the same color.

Description

Array substrate, display panel, display device and driving method

[0001] Cross-reference to related applications

[0002] This application claims priority to the Chinese patent application No. 202411328682.9, filed on September 23, 2024, and entitled "Array substrate, display panel, display device and driving method", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor, and in particular to an array substrate, a display panel, a display device and a driving method. BACKGROUND

[0004] Liquid crystal display panel is a high-tech that has developed rapidly in recent years. It has been widely used in flat panel display devices due to its advantages of thinness, lightness, low radiation, high contrast, fast response speed and low energy consumption. SUMMARY

[0005] The present application provides an array substrate, a display panel, a display device and a driving method. The array substrate comprises:

[0006] a substrate;

[0007] a plurality of gate lines extending along a first direction;

[0008] a plurality of data lines extending along a second direction;

[0009] a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; at least one of the plurality of pixel electrode rows comprises a plurality of pixel electrodes with different light-emitting colors; the pixel electrodes are located in regions formed by the intersection of the gate lines and the data lines;

[0010] a plurality of transistors, the pixel electrodes are electrically connected to the gate lines and the data lines through the transistors, and a plurality of pixel electrodes on the same data line are electrically connected through the transistors, and are alternately located on different sides of the data line;

[0011] wherein the light-emitting colors of two pixel electrodes located in at least partially adjacent pixel electrode rows and electrically connected to the same data line through the transistors are the same.

[0012] In a possible implementation, in adjacent pixel electrode rows, the pixel electrodes with the same light-emitting color are distributed in a staggered manner.

[0013] In a possible implementation, in adjacent pixel electrode rows, the minimum misregistration width of the pixel electrodes with the same light emission color is the same as the interval between two adjacent pixel electrodes in the same pixel electrode row.

[0014] In a possible implementation, the light emission colors of any two pixel electrodes electrically connected to the same data line are the same.

[0015] In a possible implementation, the array substrate comprises a plurality of first pixel electrode repeating units; the first pixel repeating unit comprises a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, and a sixth pixel electrode.

[0016] The first pixel electrode is electrically connected to the Nth gate line and the Mth data line through the transistor; the second pixel electrode is electrically connected to the Nth gate line and the M+1th data line through the transistor; the third pixel electrode is electrically connected to the Nth gate line and the M+2th data line through the transistor; the fourth pixel electrode is electrically connected to the N+1th gate line and the M+1th data line through the transistor; the fifth pixel electrode is electrically connected to the N+1th gate line and the M+2th data line through the transistor; and the sixth pixel electrode is electrically connected to the N+1th gate line and the M+3th data line through the transistor; wherein N and M represent positive integers.

[0017] The light emission colors of the first pixel electrode and the sixth pixel electrode are the same; the light emission colors of the second pixel electrode and the fourth pixel electrode are the same; and the light emission colors of the third pixel electrode and the fifth pixel electrode are the same.

[0018] In a possible implementation, the array substrate comprises a plurality of pixel electrode row groups extending in the first direction and arranged in the second direction; at least one pixel electrode row group in the plurality of pixel electrode row groups comprises two pixel electrode rows.

[0019] The light emission colors of two pixel electrodes electrically connected to the same data line and located in the same pixel electrode row group are the same.

[0020] In a possible implementation, the light emission colors of two pixel electrodes electrically connected to the same data line and located in adjacent pixel electrode row groups are different.

[0021] In a possible implementation, the array substrate comprises: a plurality of second pixel electrode repeating units; the second pixel repeating unit comprises: a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, a twelfth pixel electrode, a thirteenth pixel electrode, a fourteenth pixel electrode, a fifteenth pixel electrode, a sixteenth pixel electrode, a seventeenth pixel electrode, an eighteenth pixel electrode, a nineteenth pixel electrode, a twentieth pixel electrode, a twenty-first pixel electrode, a twenty-second pixel electrode, a twenty-third pixel electrode, a twenty-fourth pixel electrode, and a twenty-fifth pixel electrode;

[0022] The seventh pixel electrode is electrically connected to the Jth gate line and the Kth data line through the transistor; the eighth pixel electrode is electrically connected to the Jth gate line and the K+1th data line through the transistor; the ninth pixel electrode is electrically connected to the Jth gate line and the K+2th data line through the transistor; the tenth pixel electrode is electrically connected to the (J+1)th gate line and the K+1th data line through the transistor; the eleventh pixel electrode is electrically connected to the (J+1)th gate line and the K+2th data line through the transistor; the twelfth pixel electrode is electrically connected to the (J+1)th gate line and the K+3th data line through the transistor; the thirteenth pixel electrode is electrically connected to the (J+2)th gate line and the Kth data line through the transistor; the fourteenth pixel electrode is electrically connected to the (J+2)th gate line and the K+1th data line through the transistor; the fifteenth pixel electrode is electrically connected to the (J+2)th gate line and the K+2th data line through the transistor; the sixteenth pixel electrode is electrically connected to the (J+3)th gate line and the K+1th data line through the transistor; the seventeenth pixel electrode is electrically connected to the (J+3)th gate line and the K+2th data line through the transistor; the eighteenth pixel electrode is electrically connected to the (J+3)th gate line and the K+3th data line through the transistor; the nineteenth pixel electrode is electrically connected to the (J+4)th gate line and the Kth data line through the transistor; the twentieth pixel electrode is electrically connected to the (J+4)th gate line and the K+1th data line through the transistor; the twenty-first pixel electrode is electrically connected to the (J+4)th gate line and the K+2th data line through the transistor; the twenty-second pixel electrode is electrically connected to the (J+5)th gate line and the K+1th data line through the transistor; the twenty-third pixel electrode is electrically connected to the (J+5)th gate line and the K+2th data line through the transistor; the twenty-fourth pixel electrode is electrically connected to the (J+5)th gate line and the K+3th data line through the transistor; wherein J and K represent positive integers;

[0023] The light emitting colors of the seventh pixel electrode, the twelfth pixel electrode, the fourteenth pixel electrode, the sixteenth pixel electrode, the twenty-first pixel electrode, and the twenty-third pixel electrode are the same; the light emitting colors of the eighth pixel electrode, the tenth pixel electrode, the fifteenth pixel electrode, the seventeenth pixel electrode, the nineteenth pixel electrode, and the twenty-fourth pixel electrode are the same; and the light emitting colors of the ninth pixel electrode, the eleventh pixel electrode, the thirteenth pixel electrode, the eighteenth pixel electrode, the twentieth pixel electrode, and the twenty-second pixel electrode are the same.

[0024] In a possible implementation, the length of the pixel electrode in the first direction is greater than the length of the pixel electrode in the second direction.

[0025] In a possible implementation, the length of the pixel electrode in the first direction is less than the length of the pixel electrode in the second direction.

[0026] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure also includes the array substrate provided by the embodiments of the present disclosure, and further includes a counter substrate arranged opposite to the counter substrate.

[0027] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes the display panel provided by the embodiments of the present disclosure.

[0028] Based on the same inventive concept, the driving method for driving the array substrate provided by the embodiments of the present disclosure also includes the following steps.

[0029] controlling the data lines to sequentially load data signals;

[0030] controlling at least two adjacent gate lines to be turned on in a period in which the data lines load the same data signal, so that two pixel electrodes which are electrically connected to the same data line through the transistors and which are located in adjacent rows of pixel electrodes load the same data signal.

[0031] In a possible implementation, the step of controlling at least two adjacent gate lines to be turned on in a period in which the data lines load the same data signal includes the following steps.

[0032] controlling the nth gate line to be turned on and controlling the (n+1)th gate line to be turned on, wherein the (n+1)th gate line has a first period in which the (n+1)th gate line is turned on at the same time as the nth gate line, and a second period in which the (n+1)th gate line is turned off later than the nth gate line;

[0033] In the first time period and the second time period, a first data signal is loaded to the mth data line, so that the two pixel electrodes electrically connected to the nth and (n+1)th gate lines and the mth data line are all loaded with the first data signal, wherein n and m represent positive integers.

[0034] In a possible implementation, the control of the opening of at least two adjacent gate lines in the time period during which the data line is loaded with the same data signal comprises:

[0035] The jth and (j+1)th gate lines are controlled to be opened simultaneously, wherein the (j+1)th gate line has a third time period during which the (j+1)th gate line is opened simultaneously with the jth gate line.

[0036] In the third time period, a second data signal is loaded to the kth data line, so that the two pixel electrodes electrically connected to the jth and (j+1)th gate lines and the kth data line are all loaded with the second data signal, wherein j represents an odd or even number and k represents a positive integer. BRIEF DESCRIPTION OF DRAWINGS

[0037] FIG. 1A is a schematic diagram of a pixel architecture according to an embodiment of the present application;

[0038] FIG. 1B is a schematic diagram of a pixel architecture according to another embodiment of the present application;

[0039] FIG. 2A is a schematic diagram of an array substrate layout corresponding to the pixel architecture shown in FIG. 1A;

[0040] FIG. 2B is a film layer diagram of a layer in which a common electrode is located in FIG. 2A;

[0041] FIG. 2C is a film layer diagram of a layer in which a gate line is located in FIG. 2A;

[0042] FIG. 2D is a film layer diagram of a layer in which an active layer is located in FIG. 2A;

[0043] FIG. 2E is a film layer diagram of a data line in FIG. 2A;

[0044] FIG. 2F is a film layer diagram of a pixel electrode in FIG. 2A;

[0045] FIG. 3 is a schematic diagram of a pixel architecture according to another embodiment of the present application;

[0046] FIG. 4 is a schematic diagram of a pixel architecture according to another embodiment of the present application;

[0047] FIG. 5A is a schematic diagram of a sub-pixel arrangement corresponding to a three-gate pixel architecture according to an embodiment of the present application;

[0048] FIG. 5B is an enlarged schematic diagram of a pixel in FIG. 5A;

[0049] FIG. 6A is a schematic view of a sub-pixel arrangement corresponding to a single gate pixel architecture according to an embodiment of the present application;

[0050] FIG. 6B is a schematic view of an enlarged pixel according to FIG. 6A;

[0051] FIG. 7 is a timing diagram of an HSR mode according to an embodiment of the present application;

[0052] FIG. 8 is a timing diagram of a DLG mode according to an embodiment of the present application;

[0053] FIG. 9 is a flowchart of a driving method of an array substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0055] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0056] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to which the discussion pertains and which is related to the error in measurement of the particular quantity (i.e., limitations of the measurement system). For example, "approximately" can mean that the difference with respect to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0057] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0058] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0059] Referring to Figures 1A, 1B, 2A-2F, 3, and 4, where Figure 1A is an equivalent pixel architecture diagram of Figure 2A; Figure 2B is a film diagram of the layer containing the common electrode in Figure 2A; Figure 2C is a film diagram of the layer containing the gate line in Figure 2A; Figure 2D is a film diagram of the layer containing the active layer in Figure 2A; Figure 2E is a film diagram of the data line in Figure 2A; and Figure 2F is a film diagram of the pixel electrode in Figure 2A; this embodiment of the invention provides an array substrate, comprising:

[0060] Substrate;

[0061] Multiple grid lines G extend along a first direction X;

[0062] Multiple data lines D extend along the second direction Y;

[0063] Multiple pixel electrode rows P00 extend along a first direction X and are arranged along a second direction Y; at least one pixel electrode row P00 includes: multiple pixel electrodes P with different emitted light colors; the pixel electrode P is located in the area formed by the intersection of the gate line G and the data line D.

[0064] The plurality of transistors T, the pixel electrode P is electrically connected to the gate line G and the data line D through the transistor T, and the plurality of pixel electrodes P electrically connected to the same data line D through the transistor T are alternately located on different sides of the data line D; for example, referring to FIG. 1A, for the second data line D(M+1) in the left-to-right direction, the plurality of pixel electrodes P electrically connected to the second data line D(M+1) are respectively and alternately electrically connected to the right side and the left side of the second data line D(M+1), specifically, in the top-to-bottom direction in FIG. 1A, the first pixel electrode P (i.e., the green pixel electrode G emitting green light) is electrically connected to the right side of the second data line D(M+1), the second pixel electrode P (i.e., the green pixel electrode G emitting green light) is electrically connected to the left side of the second data line D(M+1), the third pixel electrode P (i.e., the green pixel electrode G emitting green light) is electrically connected to the right side of the second data line D(M+1), the fourth pixel electrode P (i.e., the green pixel electrode G emitting green light) is electrically connected to the left side of the second data line D(M+1), the fifth pixel electrode P (i.e., the green pixel electrode G emitting green light) is electrically connected to the right side of the second data line D(M+1), and the sixth pixel electrode P (i.e., the green pixel electrode G emitting green light) is electrically connected to the left side of the second data line D(M+1);

[0065] The light-emitting color of the two pixel electrodes P located in at least part of the adjacent pixel electrode rows P00 and electrically connected to the same data line D through the transistor T is the same. The light-emitting color of the pixel electrode P can be understood as the light-emitting color of the area where the pixel electrode P is located when the display panel is powered on and displays. Specifically, for example, when the display panel is a liquid crystal display panel, the light-emitting color of the pixel electrode P can be the color emitted by the color resistance in the area where the pixel electrode P is located.

[0066] In the embodiments of the present disclosure, the plurality of pixel electrodes P electrically connected to the same data line D through the transistor T are alternately located on different sides of the data line D, and the light-emitting color of the two pixel electrodes P located in at least part of the adjacent pixel electrode rows P00 and electrically connected to the same data line D through the transistor T is the same. Therefore, when performing display driving, the two pixel electrodes P of the adjacent pixel electrode rows P00 can be loaded with the data signal of the same data line D, that is, the two adjacent gate lines G can share the data signal of the data line D, frequency doubling driving can be applied, the scanning frequency of the display panel is improved, the picture is smoother during the display process of the display panel, there is no delay, the specification of the display device is improved (for example, 60Hz→120Hz), and the product competitiveness is improved.

[0067] In the display panel provided by the embodiment of the present disclosure, the plurality of pixel electrodes P electrically connected to the same data line D through the transistor T are alternately located on different sides of the data line D, that is, the display panel provided by the embodiment of the present disclosure has a Z-shaped architecture, and the pixel architecture data line can realize pixel-level dot inversion by frame inversion, so that the brightness uniformity of the panel is better. Moreover, the frame inversion is within a frame, and the same data line is a positive polarity signal or a negative polarity signal, and the frame inversion mode has the advantages of low power consumption and less heat generation of an integrated circuit chip (IC) compared with the dot inversion mode. The embodiment of the present disclosure can realize the effect of dot inversion by frame inversion, and in the case of better brightness uniformity of the display panel, the display panel also has the advantages of low power consumption and less heat generation of an integrated circuit chip (IC).

[0068] The display panel provided by the embodiment of the present disclosure can adopt a super frequency multiplication technology (Hardware Super Resolution, HSR) and / or a dual line gate G simultaneous opening frequency multiplication technology (Dual Line Gate, DLG) mode. Without changing the original hardware and chip computing power, the refresh rate of the display panel can be improved by the signal frequency multiplication mode of the gate driving circuit. For example, the 60Hz FHD product specification is 1920*1080*60Hz, which can be improved to 1920*540*120Hz specification; the 120Hz 4K product specification is 3840*2160*120Hz, which can be improved to 3840*1080*240Hz specification.

[0069] The HSR driving mode can be a mode in which the outputs of multiple rows of scanning signals share the data output. In order to enable adjacent two rows of scanning lines (gate lines G) to share the data of the data line D, the pixel architecture needs to connect one data line of adjacent two rows to the sub-pixels of the same color, so that the functions of correctly displaying R, G and B single-color pictures and correctly displaying pictures can be realized. The DLG mode is a mode in which two rows of gate lines G scanning line timing are the same and are simultaneously opened, and share the data line signal, so one data line of every two rows needs to be connected to the sub-pixels of the same color.

[0070] As shown in FIG. 7, the data signal of "1" is loaded to the nth gate line and the nth+1 gate line. Taking the pixel architecture shown in FIG. IB as an example, the HSR driving can be realized by the timing shown in FIG. 7. For example, when N = n and M = m, the nth gate line is controlled to be opened, and the effective period of the nth gate line includes a start period t0 and a first period t1 in sequence. The start period t0 can be a pre-charge time length. For example, taking G(n+4) as an example, the start period t0 can pre-charge "1", "2", "2", and the liquid crystal will also deflect in the start period t0, but this stage is not the required data, so it can be regarded as a pre-charge period, so that the liquid crystal can be deflected in advance. When the first period t1 arrives, the pixel electrode will be charged to the required data "3", that is, the data pre-charged in the start period t0 can be overwritten by the data in the first period t1. In the first period t1, the pixel electrode P can be loaded with a data signal with content "1" through the data line D. Since the scanning frequency of the gate line is doubled, when the data line still loads the data signal with content "1", the nth+1 gate line has also been opened, so the data signal with content "1" can also be loaded to the pixel electrode controlled by the nth+1 gate line.

[0071] The difference between the DLG mode and the HSR mode is that two adjacent gate lines are opened at the same time, so the same data signal can be loaded to the pixel electrodes controlled by the two gate lines at the same time.

[0072] In a possible implementation, as shown in FIGS. IB, 2A, 3 and 5A, the length b1 of the pixel electrode P in the first direction X is greater than the length b2 in the second direction Y, that is, in the embodiment of the present disclosure, the display panel can be a display panel with a triple gate (Triple Gate) pixel architecture, which can reduce the number of chip on film (COF) used and reduce the cost of the display panel. Moreover, in a conventional Triple Gate pixel architecture, the pixel electrodes located in adjacent two rows of pixel electrodes and electrically connected to the same data line have different light-emitting colors, and cannot realize frequency doubling driving. However, in the embodiment of the present disclosure, for the display panel with the Triple Gate pixel architecture, for each data line D, the pixel electrodes connected by each adjacent two rows of pixel electrodes are all the same color sub-pixels, and the frequency doubling driving mode (HSR mode and / or DLG mode) can be realized, so that the display panel with the Triple Gate pixel architecture has the advantages of low cost and smooth display process without delay, and the display product competitiveness is further improved.

[0073] In a possible implementation, referring to FIG. 4 and FIG. 6A, the length b1 of the pixel electrode P in the first direction X is less than the length b2 in the second direction Y, that is, in the embodiment of the present disclosure, the display panel can also be a display panel of a single gate pixel architecture. In a conventional single gate pixel architecture, the pixel electrodes located in two adjacent rows of pixel electrodes and electrically connected to the same data line have different light-emitting colors, and cannot achieve frequency doubling driving. However, in the embodiment of the present disclosure, for the display panel of the single gate pixel architecture, for each data line D, the pixel electrodes connected by each two adjacent rows of pixel electrodes are all sub-pixels of the same color, and the frequency doubling driving mode (HSR mode and / or DLG mode) can be realized, so that the display process is smoother and there is no delay, and the competitiveness of the display product is further improved.

[0074] It should be noted that FIG. 3 and FIG. 4, or FIG. 5A and FIG. 6A mainly show the difference between the Triple Gate and Single Gate architectures. Although the pixel architectures shown in FIG. 3 and FIG. 4 are the same in terms of pixel connection sequence, different display panel architectures will result in different pixel designs, that is, the total area and resolution of the display area AA are the same, but the number of gate lines and data lines and the amount of COF are different. In the Triple Gate architecture shown in FIG. 3 or FIG. 5A, the B-G-R in the second direction Y (that is, the vertical direction) is a pixel (Pixel), the number of gate lines G (and the sub-pixels in the second direction Y) is 1080*3, and the number of data lines D (and the sub-pixels in the first direction X) is 1920, so the amount of COF single machine is 1920 / 960=2; the total width of the display area AA along the first direction X is b1*1920, and the total width of the display area AA along the second direction Y is b2*1080*3; in the Single Gate architecture shown in FIG. 4 or FIG. 6A: the B-G-R in the first direction X (that is, the horizontal direction) is a Pixel, the number of data lines D (and the sub-pixels in the first direction X) is 1920*3, and the number of gate lines G (and the sub-pixels in the second direction Y) is 1080; so the amount of COF single machine is 1920*3 / 960=6, the total width of the display area AA along the first direction X is b1*1920*3, and the total width of the display area AA along the second direction Y is b2*1080.

[0075] In a possible implementation, referring to FIG. 5B, which is an enlarged schematic view of a pixel in FIG. 5A, b1=3b2, and the three sub-pixels can form a square pixel; in a possible implementation, referring to FIG. 6B, which is an enlarged schematic view of a pixel in FIG. 6A, b2=3b1, and the three sub-pixels can form a square pixel.

[0076] In a possible implementation, referring to FIG. 1A, FIG. 3 and FIG. 4, in the adjacent pixel electrode row P00, the pixel electrodes P of the same light-emitting color are staggered. For example, as shown in FIG. 1A, the first pixel electrode row P100 and the second pixel electrode row P00 are staggered in the upward direction, and the green pixel electrodes G of the same light-emitting color are staggered and not located in the same column. That is, the green pixel electrode G of the first pixel electrode row P100 and the red pixel electrode R of the second pixel electrode row P00, which is adjacent to the green pixel electrode G and emits red light, are located in the same column.

[0077] In a possible implementation, referring to FIG. 1B, in the adjacent pixel electrode row P00, the minimum stagger width a1 of the pixel electrodes P of the same light-emitting color is the same as the interval a2 between the adjacent two pixel electrodes P in the same pixel electrode row P00. Compared with the conventional technology, in the embodiment of the present disclosure, in the horizontal direction of each pixel electrode row, the sub-pixels of the same color are displaced by one sub-pixel relative to the previous sub-pixel row, to form a new pixel arrangement mode, and the sub-pixels of the three primary colors R, G and B are still retained in each pixel, so that the sub-pixel ratio in the pixel is 1:1:1, the resolution is the same as that of the conventional structure, but the HSR frequency multiplication mode can be implemented, so that the refresh rate of the display panel is improved.

[0078] In a possible implementation, referring to FIG. 1B, the array substrate comprises a plurality of first pixel electrode repeating units PA; the first pixel repeating unit PA comprises a first pixel electrode P1, a second pixel electrode P2, a third pixel electrode P3, a fourth pixel electrode P4, a fifth pixel electrode P5 and a sixth pixel electrode P6.

[0079] The first pixel electrode P1 is electrically connected to the Nth gate line G and the Mth data line D through a transistor T; the second pixel electrode P2 is electrically connected to the Nth gate line G and the M+1th data line D through a transistor T; the third pixel electrode P3 is electrically connected to the Nth gate line G and the M+2th data line D through a transistor T; the fourth pixel electrode P4 is electrically connected to the N+1th gate line G and the M+1th data line D through a transistor T; the fifth pixel electrode P5 is electrically connected to the N+1th gate line G and the M+2th data line D through a transistor T; and the sixth pixel electrode P6 is electrically connected to the N+1th gate line G and the M+3th data line D through a transistor T; wherein N and M represent positive integers.

[0080] The first pixel electrode P1 and the sixth pixel electrode P6 are of the same light-emitting color; the second pixel electrode P2 and the fourth pixel electrode P4 are of the same light-emitting color; and the third pixel electrode P3 and the fifth pixel electrode P5 are of the same light-emitting color.

[0081] In the embodiments of the present disclosure, by adjusting the positions of different sub-pixels, a pixel arrangement mode with 2 rows * 3 columns of sub-pixels as the minimum cycle unit is formed, so that the display panel with the Triple Gate pixel architecture can apply the HSR frequency doubling mode, thereby further improving the specification of the display device (for example, 60Hz→120Hz) and enhancing the product competitiveness; moreover, compared with the prior art, the pixel arrangement mode with 2 rows * 3 columns of sub-pixels as the minimum cycle unit is formed in the embodiments of the present disclosure, and the sub-pixels of the three primary colors RGB are still reserved in each pixel, so that the sub-pixel ratio in the pixel can be 1:1:1, the same resolution is maintained, and at the same time, the HSR frequency doubling mode can be applied, thereby providing the refresh rate of the display panel.

[0082] In a possible implementation, as shown in FIG. 1B, the first pixel electrode P1 and the sixth pixel electrode P6 both emit blue light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit green light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit red light.

[0083] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 can also both emit blue light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit red light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit green light.

[0084] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit green light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit blue light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit red light.

[0085] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit green light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit red light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit blue light.

[0086] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit red light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit green light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit blue light.

[0087] In another possible implementation, the first pixel electrode P1 and the sixth pixel electrode P6 both emit red light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit blue light; and the third pixel electrode P3 and the fifth pixel electrode P5 both emit green light.

[0088] For the light emitting colors of the two pixel electrodes P located in at least partially adjacent pixel electrode rows P00 and electrically connected to the same data line D through the transistor T being the same, in a possible implementation, the light emitting colors of any two pixel electrodes P electrically connected to the same data line D can be the same. For example, as shown in FIG. 1A, for any data line D, the light emitting colors of the pixel electrodes P electrically connected to the data line D are the same. For example, for the second data line D from left to right, the pixel electrodes P electrically connected to the second data line D are all green pixel electrodes G emitting green light. For example, for the third data line D from left to right, the pixel electrodes P electrically connected to the third data line D are all red pixel electrodes R emitting red light. For example, for the fourth data line D from left to right, the pixel electrodes P electrically connected to the fourth data line D are all blue pixel electrodes B emitting blue light.

[0089] In the embodiments of the present disclosure, the light emitting colors of any two pixel electrodes P electrically connected to the same data line D are the same, and the HSR mode and the DLG mode can be supported at the same time.

[0090] For the light emitting colors of the two pixel electrodes P located in at least partially adjacent pixel electrode rows P00 and electrically connected to the same data line D through the transistor T being the same, in a possible implementation, every two adjacent pixel electrode rows can be a group, the light emitting colors of the two pixel electrodes P located in the two pixel electrode rows in the group and electrically connected to the same data line D are the same. Specifically, in combination with FIG. 3 or FIG. 4, the array substrate comprises: a plurality of pixel electrode row groups PZ extending along a first direction X and arranged along a second direction Y; at least one of the plurality of pixel electrode row groups PZ comprises: two pixel electrode rows P00; the light emitting colors of the two pixel electrodes P electrically connected to the same data line D and located in the same pixel electrode row group PZ are the same.

[0091] In the embodiments of the present disclosure, the light emitting colors of any two pixel electrodes P electrically connected to the same data line D are the same, and the DLG mode can be implemented.

[0092] In a possible implementation, in combination with FIG. 3 or FIG. 4, the light emitting colors of the two pixel electrodes P electrically connected to the same data line D and located in adjacent pixel electrode row groups PZ are different. For example, as shown in FIG. 3, for the second data line D from left to right, the pixel electrodes P electrically connected to the second data line D are, from top to bottom, two green pixel electrodes G emitting green light, two blue pixel electrodes B emitting blue light, and two red pixel electrodes R emitting red light.

[0093] In a possible implementation, referring to FIG. 3 or FIG. 4, the array substrate comprises: a plurality of second pixel electrode repeating units PB; the second pixel repeating unit PB comprises: a seventh pixel electrode P7, an eighth pixel electrode P8, a ninth pixel electrode P9, a tenth pixel electrode P10, an eleventh pixel electrode P11, a twelfth pixel electrode P12, a thirteenth pixel electrode P13, a fourteenth pixel electrode P14, a fifteenth pixel electrode P15, a sixteenth pixel electrode P16, a seventeenth pixel electrode P17, an eighteenth pixel electrode P18, a nineteenth pixel electrode P19, a twentieth pixel electrode P20, a twenty-first pixel electrode P21, a twenty-second pixel electrode P22, a twenty-third pixel electrode P23, a twenty-fourth pixel electrode P24, and a twenty-fifth pixel electrode P25;

[0094] The seventh pixel electrode P7 is electrically connected to the Jth gate line G and the Kth data line D through the transistor T; the eighth pixel electrode P8 is electrically connected to the Jth gate line G and the K+1th data line D through the transistor T; the ninth pixel electrode P9 is electrically connected to the Jth gate line G and the K+2th data line D through the transistor T; the tenth pixel electrode P10 is electrically connected to the (J+1)th gate line G and the K+1th data line D through the transistor T; the eleventh pixel electrode P11 is electrically connected to the (J+1)th gate line G and the K+2th data line D through the transistor T; the twelfth pixel electrode P12 is electrically connected to the (J+1)th gate line G and the K+3th data line D through the transistor T; the thirteenth pixel electrode P13 is electrically connected to the (J+2)th gate line G and the Kth data line D through the transistor T; the fourteenth pixel electrode P14 is electrically connected to the (J+2)th gate line G and the K+1th data line D through the transistor T; the fifteenth pixel electrode P15 is electrically connected to the (J+2)th gate line G and the K+2th data line D through the transistor T; the sixteenth pixel electrode P16 is electrically connected to the (J+3)th gate line G and the K+1th data line D through the transistor T; the seventeenth pixel electrode P17 is electrically connected to the (J+3)th gate line G and the K+2th data line D through the transistor T; the eighteenth pixel electrode P18 is electrically connected to the (J+3)th gate line G and the K+3th data line D through the transistor T; the nineteenth pixel electrode P19 is electrically connected to the (J+4)th gate line G and the Kth data line D through the transistor T; the twentieth pixel electrode P20 is electrically connected to the (J+4)th gate line G and the K+1th data line D through the transistor T; the twenty-first pixel electrode P21 is electrically connected to the (J+4)th gate line G and the K+2th data line D through the transistor T; the twenty-second pixel electrode P22 is electrically connected to the (J+5)th gate line G and the K+1th data line D through the transistor T; the twenty-third pixel electrode P23 is electrically connected to the (J+5)th gate line G and the K+2th data line D through the transistor T; the twenty-fourth pixel electrode P24 is electrically connected to the (J+5)th gate line G and the K+3th data line D through the transistor T; wherein J and K represent positive integers.

[0095] The light-emitting colors of the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 are the same; the light-emitting colors of the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 are the same; and the light-emitting colors of the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 are the same.

[0096] In the embodiments of the present disclosure, by adjusting the positions of different sub-pixels, a pixel arrangement mode with 6 rows * 3 columns of sub-pixels as a minimum cycle unit is formed, so that the display panel with the Triple Gate pixel architecture or the single gate pixel architecture can apply the HSR frequency doubling mode, thereby further improving the specification of the display device (for example, 60 Hz → 120 Hz) and enhancing the product competitiveness.

[0097] In a possible implementation, referring to FIG. 3 or FIG. 4, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit blue light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit green light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit red light.

[0098] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit blue light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit red light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit green light.

[0099] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit green light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit red light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit blue light.

[0100] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit green light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit red light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit blue light.

[0101] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit red light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit green light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit blue light.

[0102] In another possible implementation manner, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 can all emit red light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 can all emit blue light; and the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 can all emit green light.

[0103] In a possible implementation manner, FIGS. 2B-2F can be single-layer schematic diagrams of respective film layers arranged on the substrate in sequence, that is, the array substrate can be sequentially arranged with a common electrode layer, a gate line layer, an active layer, a data line layer, and a pixel electrode layer on the substrate; the common electrode layer can include a plurality of common electrode blocks Z arranged in an array, and there can be no insulating layer between the common electrode layer and the layer where the gate line G is located; the common electrode block Z and the gate line G are spaced apart from each other and insulated from each other; the layer where the gate line G is located can further include a plurality of first common connection lines G0 extending along a first direction X, and a plurality of common electrode blocks Z in the first direction X can be directly overlapped with the first common connection line G0, so as to connect the plurality of common electrode blocks Z in the first direction X to each other; the layer where the pixel electrode P is located can further include a plurality of overlapping portions P0, and in combination with FIG. 2A, a plurality of common electrode blocks Z in a second direction Y can be electrically connected to each other through the overlapping portion P0, so as to connect the plurality of common electrode blocks Z in the second direction Y to each other, and thus the common electrode layer forms a horizontal and vertical electrical connection structure; optionally, the common electrode block Z and the overlapping portion P0 can be electrically connected through a via K2; optionally, the active layer can include a plurality of active patterns F; the pixel electrode P can be electrically connected to the drain of the transistor T through a first via K1; optionally, the common electrode block Z can be a block electrode, and the pixel electrode P can have a plurality of slits.

[0104] Based on the same inventive concept, the embodiments of the present disclosure further provide a display panel, which comprises the array substrate provided by the embodiments of the present disclosure.

[0105] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device comprising the display panel provided by the embodiments of the present disclosure. The implementation of the display device can refer to the implementation of the above-mentioned display panel, and the repeated parts will not be described herein.

[0106] In a specific implementation, the display device in the embodiments of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are understood by those skilled in the art and are not described here again, and should not be considered as a limitation on the present disclosure.

[0107] Based on the same inventive concept, the embodiments of the present disclosure also provide a driving method for driving the array substrate as described in the embodiments of the present disclosure. Referring to FIG. 9, the driving method comprises the following steps:

[0108] In step S100, the data line is sequentially loaded with a data signal.

[0109] In step S200, at least two adjacent gate lines are controlled to be turned on during a period in which the data line is loaded with the same data signal, so that two pixel electrodes located in adjacent pixel electrode rows and electrically connected to the same data line through transistors are loaded with the same data signal.

[0110] In a possible implementation, in combination with FIG. 7, for step S200, at least two adjacent gate lines are controlled to be turned on during a period in which the data line is loaded with the same data signal, which comprises:

[0111] The nth gate line is controlled to be turned on, and the n+1th gate line is controlled to be turned on, wherein the n+1th gate line has a first period t1 of being turned on at the same time as the nth gate line, and a second period t2 of being turned off later than the nth gate line.

[0112] In the first period t1 and the second period t2, the first data signal is loaded to the mth data line, so that two pixel electrodes electrically connected to the nth gate line, the n+1th gate line, and the mth data line are all loaded with the first data signal, wherein n and m represent positive integers.

[0113] In a possible implementation, in combination with FIG. 8, for step S200, at least two adjacent gate lines are controlled to be turned on during a period in which the data line is loaded with the same data signal, which comprises:

[0114] The jth gate line and the j+1th gate line are controlled to be turned on at the same time, wherein the j+1th gate line has a third period t3 of being turned on at the same time as the jth gate line.

[0115] In the third period t4, the second data signal is loaded to the kth data line, so that two pixel electrodes electrically connected to the jth gate line, the j+1th gate line, and the kth data line are all loaded with the second data signal, wherein j represents an odd number or an even number, and k represents a positive integer.

[0116] In one possible implementation, in a current frame, the polarity of the active signal loaded on adjacent data lines can be opposite, for example, one data line loads a positive polarity data signal and the adjacent data line loads a negative polarity data signal; in a next frame, the active signal loaded on each data line can be opposite to the polarity of the active data signal loaded on that data line in the previous frame, for example, in a current frame, one data line loads a positive polarity data signal, in a next frame, the data line loads a negative polarity data signal.

[0117] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be made to the preferred embodiments by those of skill in the art once they have the benefit of the present disclosure. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments. The preferred embodiments of the disclosure are described above, and the following claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments.

[0118] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. An array substrate, wherein, The array substrate comprises: a plurality of first pixel electrode repeating units; the first pixel repeating unit comprises: a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode and a sixth pixel electrode; The first pixel electrode is electrically connected to the Nth gate line and the Mth data line through the transistor; the second pixel electrode is electrically connected to the Nth gate line and the M+1th data line through the transistor; the third pixel electrode is electrically connected to the Nth gate line and the M+2th data line through the transistor; the fourth pixel electrode is electrically connected to the N+1th gate line and the M+1th data line through the transistor; the fifth pixel electrode is electrically connected to the N+1th gate line and the M+2th data line through the transistor; the sixth pixel electrode is electrically connected to the N+1th gate line and the M+3th data line through the transistor; wherein N and M represent positive integers; The light-emitting colors of the first pixel electrode and the sixth pixel electrode are the same; the light-emitting colors of the second pixel electrode and the fourth pixel electrode are the same; the light-emitting colors of the third pixel electrode and the fifth pixel electrode are the same. The array substrate comprises: a plurality of pixel electrode row groups extending along the first direction and arranged along the second direction; at least one pixel electrode row group in the plurality of pixel electrode row groups comprises: two pixel electrode rows; The light-emitting colors of the two pixel electrodes electrically connected to the same data line and located in the same pixel electrode row group through the transistor are the same. The light-emitting colors of the two pixel electrodes electrically connected to the same data line and located in adjacent pixel electrode row groups through the transistor are different. ​ ​ 2. The array substrate of claim 1, wherein, ​ 3. The array substrate of claim 2, wherein, ​ 4. The array substrate of any one of claims 1-3, wherein, ​ 5. The array substrate of claim 4, wherein, ​ ​ ​ 6. The array substrate of any one of claims 1-3, wherein, ​ ​ 7. The array substrate of claim 6, wherein, ​ 8. The array substrate of claim 6 or 7, wherein, The array substrate comprises: a plurality of second pixel electrode repeating units; the second pixel repeating unit comprises: a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, a twelfth pixel electrode, a thirteenth pixel electrode, a fourteenth pixel electrode, a fifteenth pixel electrode, a sixteenth pixel electrode, a seventeenth pixel electrode, an eighteenth pixel electrode, a nineteenth pixel electrode, a twentieth pixel electrode, a twenty-first pixel electrode, a twenty-second pixel electrode, a twenty-third pixel electrode, a twenty-fourth pixel electrode and a twenty-fifth pixel electrode; The seventh pixel electrode is electrically connected to the Jth gate line and the Kth data line through the transistor; the eighth pixel electrode is electrically connected to the Jth gate line and the K+1th data line through the transistor; the ninth pixel electrode is electrically connected to the Jth gate line and the K+2th data line through the transistor; the tenth pixel electrode is electrically connected to the J+1th gate line and the K+1th data line through the transistor; the eleventh pixel electrode is electrically connected to the J+1th gate line and the K+2th data line through the transistor; the twelfth pixel electrode is electrically connected to the J+1th gate line and the K+3th data line through the transistor; the thirteenth pixel electrode is electrically connected to the J+2th gate line and the Kth data line through the transistor; the fourteenth pixel electrode is electrically connected to the J+2th gate line and the K+1th data line through the transistor; the fifteenth pixel electrode is electrically connected to the J+2th gate line and the K+2th data line through the transistor; the sixteenth pixel electrode is electrically connected to the J+3th gate line and the K+1th data line through the transistor; the seventeenth pixel electrode is electrically connected to the J+3th gate line and the K+2th data line through the transistor; the eighteenth pixel electrode is electrically connected to the J+3th gate line and the K+3th data line through the transistor; the nineteenth pixel electrode is electrically connected to the J+4th gate line and the Kth data line through the transistor; the twentieth pixel electrode is electrically connected to the J+4th gate line and the K+1th data line through the transistor; the twenty-first pixel electrode is electrically connected to the J+4th gate line and the K+2th data line through the transistor; the twenty-second pixel electrode is electrically connected to the J+5th gate line and the K+1th data line through the transistor; the twenty-third pixel electrode is electrically connected to the J+5th gate line and the K+2th data line through the transistor; the twenty-fourth pixel electrode is electrically connected to the J+5th gate line and the K+3th data line through the transistor; wherein J and K represent positive integers. The seventh pixel electrode, the twelfth pixel electrode, the fourteenth pixel electrode, the sixteenth pixel electrode, the twenty-first pixel electrode, and the twenty-third pixel electrode have the same light emission color; the eighth pixel electrode, the tenth pixel electrode, the fifteenth pixel electrode, the seventeenth pixel electrode, the nineteenth pixel electrode, and the twenty-fourth pixel electrode have the same light emission color; and the ninth pixel electrode, the eleventh pixel electrode, the thirteenth pixel electrode, the eighteenth pixel electrode, the twentieth pixel electrode, and the twenty-second pixel electrode have the same light emission color.

9. The array substrate of any one of claims 1-8, wherein, The length of the pixel electrode in the first direction is greater than the length of the pixel electrode in the second direction.

10. The array substrate of any of claims 1-3, 6-8, wherein, The length of the pixel electrode in the first direction is less than the length of the pixel electrode in the second direction.

11. A display panel, wherein, The array substrate comprises a counter substrate disposed opposite to the counter substrate.

12. A display device, wherein, The display panel comprises the array substrate.

13. A driving method of the array substrate according to any one of claims 1 to 10, wherein, The driving method comprises: controlling the data lines to sequentially load data signals; controlling at least two adjacent gate lines to be turned on during a period in which the data lines load the same data signal, so that two pixel electrodes, which are electrically connected to the same data line and located in adjacent rows of pixel electrodes, load the same data signal.

14. The driving method of claim 13, wherein, The controlling at least two adjacent gate lines to be turned on during a period in which the data lines load the same data signal comprises: controlling an nth gate line to be turned on and controlling an (n+1)th gate line to be turned on, wherein the (n+1)th gate line has a first period in which the (n+1)th gate line is turned on at the same time as the nth gate line, and a second period in which the (n+1)th gate line is turned off later than the nth gate line; loading a first data signal to an mth data line during the first period and the second period, so that two pixel electrodes, which are electrically connected to the nth gate line, the (n+1)th gate line, and the mth data line, load the first data signal, wherein n and m represent positive integers.

15. The driving method of claim 13, wherein, The controlling at least two adjacent gate lines to be turned on during a period in which the data lines load the same data signal comprises: controlling a jth gate line and a (j+1)th gate line to be turned on at the same time, wherein the (j+1)th gate line has a third period in which the (j+1)th gate line is turned on at the same time as the jth gate line; loading a second data signal to a kth data line during the third period, so that two pixel electrodes, which are electrically connected to the jth gate line, the (j+1)th gate line, and the kth data line, load the second data signal, wherein j represents an odd number or an even number, and k represents a positive integer.

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