Display panel and manufacturing method therefor, and display apparatus

Abstract

The present application belongs to the technical field of display. Disclosed are a display panel and a manufacturing method therefor, and a display apparatus,. The display panel comprises: a substrate, a first electrode layer, a light-emitting layer, a second electrode layer, a peripheral wire, a retaining wall and an inorganic partition layer. The inorganic isolation layer comprises an isolation portion located in a display area and a first protection portion located in a non-display area, and therefore crosstalk between pixels can be ameliorated by means of the isolation portion in the display area, such that the display effect of the display panel can be improved; in addition, the first protection portion in the non-display area protects the side of an exposed portion in the peripheral wire that is away from the substrate, such that a structural design of multi-layer wiring can be used for the exposed portion in the peripheral wire, thereby reducing the resistance of the exposed portion in the peripheral wire, and ameliorating the occurrence of the adverse phenomenon that the exposed portion is likely burned due to overheating.

Description

Display panel, manufacturing method thereof and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a manufacturing method thereof and a display device. BACKGROUND

[0002] The pixel driving circuit of the display panel needs to be connected to a peripheral wire to provide a power supply signal to each pixel driving circuit through the peripheral wire, thereby ensuring that the pixel driving circuit can control the corresponding light emitting device to emit light.

[0003] However, in the process of transmitting the power supply signal, the peripheral wire in the current display panel is prone to heat generation, which leads to the phenomenon of being easily burned by the peripheral wire, thereby reducing the reliability of the display panel.

[0004] SUMMARY

[0005] The present application provides a display panel, a manufacturing method thereof and a display device. The technical solution can solve the problem of low reliability of the display panel in the prior art, and is as follows:

[0006] In one aspect, a display panel is provided, the display panel has a display area and a non-display area located at the periphery of the display area, and the non-display area has a bending area; the display panel comprises a substrate, a first electrode layer, a light emitting layer, a second electrode layer, a peripheral wire, a barrier wall and an inorganic partition layer located on one side of the substrate.

[0007] The first electrode layer, the light emitting layer and the second electrode layer are stacked on one side of the substrate, and the first electrode layer, the light emitting layer and the second electrode layer are all distributed in the display area;

[0008] The barrier wall is located in the non-display area and surrounds the display area;

[0009] The peripheral wire is distributed in the non-display area, and the peripheral wire has an exposed part, and the orthographic projection of the exposed part on the substrate is located between the orthographic projection of the barrier wall on the substrate and the orthographic projection of the bending area on the substrate.

[0010] The inorganic partition layer comprises a partition part located in the display area and a first protection part located in the non-display area; the partition part is used to partition at least part of the organic light emitting film in the light emitting layer, the first protection part is located on the side of the exposed part away from the substrate, and the orthographic projection of the first protection part on the substrate overlaps with the orthographic projection of the exposed part on the substrate.

[0011] Optionally, a projection of the exposure portion on the substrate is located within a projection of the first protection portion on the substrate.

[0012] Optionally, the exposure portion comprises a first exposure trace and a second exposure trace connected to each other, and the first exposure trace and the second exposure trace are arranged in a stacked manner away from the substrate.

[0013] The first protection portion is located on a side of the second exposure trace away from the substrate.

[0014] Optionally, the display panel further comprises an inorganic insulating layer.

[0015] The inorganic insulating layer has a portion located between the first exposure trace and the second exposure trace, and the portion of the inorganic insulating layer between the first exposure trace and the second exposure trace has a first via, and the second exposure trace is partially overlapped with the first exposure trace through the first via.

[0016] Alternatively, the inorganic insulating layer has a hollow groove, a projection of the exposure portion on the substrate is located within a projection of the hollow groove on the substrate, and a side of the first exposure trace away from the substrate and a side of the second exposure trace toward the substrate are fully overlapped.

[0017] Optionally, the exposure portion further comprises a third exposure trace connected to the second exposure trace, the third exposure trace is arranged in a stacked manner with the second exposure trace, and the third exposure trace is located on a side of the second exposure trace away from the substrate.

[0018] The first protection portion is located on a side of the third exposure trace away from the substrate.

[0019] Optionally, a side of the second exposure trace away from the substrate and a side of the third exposure trace toward the substrate are fully overlapped.

[0020] Optionally, the non-display area further comprises a binding area, and the binding area is located on a side of the bending area away from the display area.

[0021] The display panel further comprises a plurality of connection pins in the binding area, the connection pins at least comprise a first pin portion arranged in the same layer as the exposure portion, and the inorganic partition layer further comprises a second protection portion in the binding area, the second protection portion is located on a side of the first pin portion away from the substrate, and a projection of the second protection portion on the substrate overlaps with a projection of the first pin portion on the substrate.

[0022] Optionally, the connecting pin further comprises a second pin portion, the second pin portion is located on a side of the second protection portion away from the substrate, the second protection portion has a second via, and the second pin portion is partially overlapped with the first pin portion through the second via;

[0023] Optionally, the connecting pin further comprises a third pin portion, the third pin portion is located on a side of the first pin portion close to the substrate, and a side of the third pin portion away from the substrate is fully overlapped with a side of the first pin portion facing the substrate.

[0024] Optionally, when the exposed portion comprises a first exposed trace and a second exposed trace, the first pin portion comprises a first sub-pin and a second sub-pin which are stacked; the first sub-pin is arranged in the same layer as the first exposed trace and is made of the same material, and the second sub-pin is arranged in the same layer as the second exposed trace and is made of the same material.

[0025] Optionally, when the exposed portion comprises a first exposed trace, a second exposed trace and a third exposed trace, the first pin portion comprises the first sub-pin, the second sub-pin and a third sub-pin which are stacked; the first sub-pin is arranged in the same layer as the first exposed trace and is made of the same material, the second sub-pin is arranged in the same layer as the second exposed trace and is made of the same material, and the third sub-pin is arranged in the same layer as the third exposed trace and is made of the same material.

[0026] Optionally, the display panel further comprises a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer which are stacked on a side of the second electrode layer away from the substrate;

[0027] The organic encapsulation layer is located in the area surrounded by the barrier wall, and part of the boundary of the projection of the first inorganic encapsulation layer and the second inorganic encapsulation layer on the substrate is located between the projection of the barrier wall on the substrate and the projection of the bending area on the substrate.

[0028] Part of the first inorganic encapsulation layer distributed between the barrier wall and the bending area is in contact with the side of the first protection portion away from the substrate.

[0029] Optionally, the peripheral trace comprises a first power signal line and a second power signal line, and the potential of the power signal loaded on the first power signal line is higher than the potential of the power signal loaded on the second power signal line.

[0030] The first power signal line has the exposed portion, and / or the second power signal line has the exposed portion.

[0031] Optionally, the display panel further has an aperture region and a transition region, the display region is located at the periphery of the aperture region, and the transition region is located between the aperture region and the display region.

[0032] The display panel further includes a plurality of conductive isolation columns located on one side of the substrate, the plurality of conductive isolation columns are distributed in the transition region, the conductive isolation columns are annular and surround the aperture region, and the conductive isolation columns are used to isolate the part of the light-emitting layer distributed in the transition region.

[0033] The orthogonal projection of the inorganic isolation layer on the substrate does not overlap with the orthogonal projection of the transition region on the substrate.

[0034] In another aspect, a manufacturing method of a display panel is provided, the display panel has a display region and a non-display region located at the periphery of the display region, and the non-display region has a bending region; the manufacturing method of the display panel includes:

[0035] forming a first electrode layer, a light-emitting layer, a second electrode layer, a peripheral trace, a barrier wall, and an inorganic isolation layer on one side of a substrate;

[0036] The first electrode layer, the light-emitting layer, and the second electrode layer are stacked on one side of the substrate, and the first electrode layer, the light-emitting layer, and the second electrode layer are all distributed in the display region at least;

[0037] The barrier wall is located in the non-display region and surrounds the display region;

[0038] The peripheral trace is distributed in the non-display region, and the peripheral trace has an exposed part, and the orthogonal projection of the exposed part on the substrate is located between the orthogonal projection of the barrier wall on the substrate and the orthogonal projection of the bending region on the substrate;

[0039] The inorganic isolation layer includes an isolation part located in the display region and a first protection part located in the non-display region; the isolation part is used to isolate at least part of the organic light-emitting film in the light-emitting layer, the first protection part is located on the side of the exposed part away from the substrate, and the orthogonal projection of the first protection part on the substrate overlaps with the orthogonal projection of the exposed part on the substrate.

[0040] Optionally, the display panel further has an aperture region and a transition region, the display region is located at the periphery of the aperture region, and the transition region is located between the aperture region and the display region; the inorganic isolation layer is formed on one side of the substrate, including:

[0041] forming an inorganic thin film layer on the substrate with the first conductive layer and the third planar layer, the first conductive layer comprising a plurality of isolation columns in the transition region, and the third planar layer being on a side of the first conductive layer away from the substrate;

[0042] performing a patterning process on the inorganic thin film layer to form an inorganic transition layer, the inorganic transition layer comprising the isolation portion and the first protection portion, and a transition protection portion in the transition region, the transition protection portion covering the plurality of isolation columns;

[0043] after sequentially forming the first electrode layer and the pixel definition layer on a side of the inorganic transition layer away from the substrate, removing the transition protection portion in the inorganic transition layer to obtain the inorganic isolation layer.

[0044] In another aspect, a display device is provided, comprising any of the display panels described above. The technical solutions provided in the embodiments of the present application have at least the following beneficial effects:

[0045] Since the inorganic isolation layer comprises the isolation portion in the display region and the first protection portion in the non-display region, the isolation portion in the display region can improve the crosstalk between pixels, and the first protection portion in the non-display region can protect the side of the exposed portion in the peripheral wire away from the substrate, so that the exposed portion in the peripheral wire can adopt a multi-layer wire structure design, reduce the resistance of the exposed portion in the peripheral wire, and improve the phenomenon that the exposed portion is easily burned due to overheating. In addition, the inorganic isolation layer further comprises a second protection portion in the non-display region, which can protect the side of the first pin portion away from the substrate, avoid the reaction between the first pin portion and the etching solution used when forming the first electrode layer, and thus avoid the short circuit between two adjacent connecting pins caused by the precipitation of silver impurities. In this way, the reliability of the display panel can be effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] FIG. 1 is a top view of a display panel according to an embodiment of the present application;

[0048] FIG. 2 is a schematic diagram of the film layer structure of the display panel shown in FIG. 1 at A-A’;

[0049] FIG. 3 is a partial enlarged view of the display panel shown in FIG. 1 at B;

[0050] FIG. 4 is a schematic diagram of a film layer structure of the display panel shown in FIG. 1 at C-C';

[0051] FIG. 5 is a schematic diagram of a cross section of the display panel shown in FIG. 3 at D-D';

[0052] FIG. 6 is another schematic diagram of a cross section of the display panel shown in FIG. 3 at D-D';

[0053] FIG. 7 is a schematic diagram of a cross section of the display panel shown in FIG. 3 at E-E';

[0054] FIG. 8 is a partial enlarged view of a binding area according to an embodiment of the present application;

[0055] FIG. 9 is a schematic diagram of a cross section of a single connecting pin according to an embodiment of the present application;

[0056] FIG. 10 is a schematic diagram of a cross section of another single connecting pin according to an embodiment of the present application;

[0057] FIG. 11 is a schematic diagram of a film layer structure of the display panel shown in FIG. 1 at F-F';

[0058] FIG. 12 is a schematic diagram of a film layer structure of a display panel in a display area according to an embodiment of the present application;

[0059] FIG. 13 is an effect diagram of forming an inorganic thin film layer on a substrate with a first conductive layer and a first planar layer according to an embodiment of the present application;

[0060] FIG. 14 is an effect diagram of an inorganic transition layer obtained after a patterning process of the inorganic thin film layer according to an embodiment of the present application;

[0061] FIG. 15 is an effect diagram of sequentially forming a first electrode layer and a pixel definition layer on a side of the inorganic transition layer facing away from the substrate according to an embodiment of the present application;

[0062] FIG. 16 is a schematic diagram of removing a transition protection portion according to an embodiment of the present application;

[0063] FIG. 17 is an effect diagram of performing an over-etching process on a conductive isolation column according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0065] Please refer to FIG. 1, which is a top view of a display panel according to an embodiment of the present application. The display panel 000 can have a display area 001 and a non-display area 002, the non-display area 002 being located at the periphery of the display area 001, and the non-display area 002 having a bending area 002a and a binding area 002b.

[0066] Please refer to FIG. 1, FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram of the film layer structure of the display panel shown in FIG. 1 at A-A', and FIG. 3 is a partial enlarged view of the display panel shown in FIG. 1 at B. The display panel 000 can include a substrate 100, and light emitting devices 200, an encapsulation layer 300, a barrier 400 and peripheral wires 500 located at one side of the substrate 100.

[0067] The number of the light emitting devices 200 can be multiple, and the multiple light emitting devices 200 can be distributed in the display area 001. For example, the display panel 000 can include a first electrode layer 201, a light emitting layer 202 and a second electrode layer 203 which are stacked, and the first electrode layer 201, the light emitting layer 202 and the second electrode layer 203 are all distributed at least in the display area 001. Here, the first electrode layer 201, the light emitting layer 202 and the second electrode layer 203 can be used to form the multiple light emitting devices 200.

[0068] For example, the display panel 000 can further include a pixel definition layer 600. The pixel definition layer 600 can be distributed in the display area 001, and the pixel definition layer 600 can have multiple pixel openings K. The first electrode layer 201 can be located at the side of the pixel definition layer 600 facing the substrate 100, and the light emitting layer 202 and the second electrode layer 203 can be located at the side of the pixel definition layer 600 away from the substrate 100. And the first electrode layer 201 can include multiple first electrodes corresponding to the multiple pixel openings K, and the orthogonal projection of each first electrode on the substrate 100 can be located in the orthogonal projection of the corresponding pixel opening K on the substrate 100. Therefore, the part of the light emitting layer 202 distributed in each pixel opening K can be in contact with the corresponding first electrode. In this case, for any one pixel opening K, the first electrode (also commonly referred to as anode) corresponding to this pixel opening K, and the part of the light emitting layer 202 and the second electrode layer 203 distributed in this pixel opening K (also commonly referred to as cathode), can form a light emitting device 200.

[0069] The encapsulation layer 300 is located at the side of the multiple light emitting devices 200 away from the substrate 100, and the encapsulation layer 300 can be used to encapsulate each light emitting device 200, so that the water and oxygen in the external environment are not easy to erode into the interior of the light emitting device 200, and the light emitting device 200 is not damaged.

[0070] The barrier wall 400 can be located in the non-display area 002, and can be distributed around the display area 001. Here, the number of the barrier wall 400 is usually at least one, and in the case that the number of the barrier wall 400 is multiple, the multiple barrier walls 400 can be sequentially nested in the non-display area 002. For example, as shown in FIG. 3, the number of the barrier wall 400 in the display panel 000 is two, and the two barrier walls 400 are respectively a first barrier wall 401 and a second barrier wall 402. The first barrier wall 401 can be distributed around the display area 001, and the second barrier wall 402 can be distributed around the first barrier wall 401, and the second barrier wall 402 is at a certain distance from the first barrier wall 401.

[0071] The peripheral wire 500 can be distributed in the non-display area 002. Here, the peripheral wire 500 can be a power signal line, so that the peripheral wire 500 can provide a power signal to each light emitting device 200 in the display area 001. The peripheral wire 500 can have an exposed portion 501, and the orthogonal projection of the exposed portion 501 on the substrate 100 can be located between the orthogonal projection of the barrier wall 400 on the substrate 100 and the orthogonal projection of the bending area 002a on the substrate 100. For example, as shown in FIG. 4, the orthogonal projection of the exposed portion 501 on the substrate 100 can be located between the orthogonal projection of the second barrier wall 402 on the substrate 100 and the orthogonal projection of the bending area 002a on the substrate 100.

[0072] In the present application, the display panel 000 can further include a plurality of pixel region circuits (not shown in FIG. 2, which will be described in subsequent embodiments). The plurality of pixel driving circuits can be electrically connected one-to-one with the plurality of light emitting devices 200, and each pixel driving circuit can be used to drive the corresponding light emitting device 200 to emit light. Here, the peripheral wire 500 can be electrically connected with each pixel driving circuit, so that the peripheral wire 500 can provide a power signal to each pixel driving circuit. For example, as shown in FIGS. 1 and 3, the peripheral wire 500 can include a first power signal line 510 and a second power signal line 520, and the potential of the power signal loaded on the first power signal line 510 is higher than the potential of the power signal loaded on the second power signal line 520. That is, the first power signal line 510 can be a high-level power signal line, and the second power signal line 520 can be a low-level power signal line. The first power signal line 510 can be used to apply a high-level power signal to each pixel driving circuit, and the second power signal line 520 can be used to apply a low-level power signal to each pixel driving circuit.

[0073] Here, the first power signal line 510 has an exposed portion 501, and / or the second power signal line 520 has an exposed portion 501. It should be noted that the embodiments of the present application are illustratively described by taking the first power signal line 510 and the second power signal line 520 as examples, both of which have exposed portions 501.

[0074] In the embodiment of the present application, the encapsulation layer 300 can include: a first inorganic encapsulation layer 301, an organic encapsulation layer 302 and a second inorganic encapsulation layer 303 which are stacked on the side of the second electrode layer 203 away from the substrate 100. Here, the first inorganic encapsulation layer 301 can be in contact with the side of the second electrode layer 203 away from the substrate 100, that is, the first inorganic encapsulation layer 301 can cover the plurality of light emitting devices 200. The organic encapsulation layer 302 can ensure that the part of the display panel 000 located in the display area 001 is better in flatness, so as to ensure that the subsequent other functional layers (for example, the touch electrode layer or the color resistance layer) formed on the part of the encapsulation layer 300 located in the display area 001 are better in effect. However, because the organic encapsulation layer 302 is poor in water and oxygen isolation ability, it is necessary to set the barrier wall 400 to block the organic encapsulation layer 302, and to use the second inorganic encapsulation layer 303 to cover the side of the organic encapsulation layer 302 away from the substrate 100, and to make the edge part of the first inorganic encapsulation layer 301 in contact with the edge part of the second inorganic encapsulation layer 303, so as to ensure that the first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 can wrap the organic encapsulation layer 302.

[0075] To this end, the organic encapsulation layer 302 can be located in the area surrounded by the barrier wall 400, and the orthographic projection of the first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 on the substrate 100 covers the orthographic projection of the barrier wall 400 on the substrate 100. That is, the orthographic projection of the first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 on the substrate 100 exists a part of the boundary, which can be located between the orthographic projection of the barrier wall 400 on the substrate 100 and the orthographic projection of the bending area 002a on the substrate 100.

[0076] It should be noted that there are a plurality of conductive layers which are stacked in the display panel 000, and an insulating layer needs to be set between each two adjacent conductive layers for insulation. Here, the current of the power signal loaded on the peripheral wiring 500 is usually large, and therefore, the peripheral wiring 500 usually needs to adopt a multi-layer wiring mode to reduce the resistance of the peripheral wiring 500, so as to reduce the probability of the heating problem of the peripheral wiring 500. Here, each layer of wiring in the peripheral wiring 500 belongs to a part of a conductive layer.

[0077] It should be further noted that, among the conductive layers which can be used as the peripheral wiring 500, only the conductive layer closest to the substrate 100 needs to be covered by the inorganic insulating layer and the organic insulating layer at the same time, and the other conductive layers can only be covered by the organic insulating layer.

[0078] In this case, since a part of the first inorganic encapsulation layer 301 and the second inorganic encapsulation layer 303 in the encapsulation layer 300 needs to be distributed between the barrier wall 400 and the bending area 002a, and the first inorganic encapsulation layer 301 is made of inorganic material, it is necessary to remove all the organic insulating layers in the area between the barrier wall 400 and the bending area 002a in the display panel 000 so that the first inorganic encapsulation layer 301 can be firmly connected with the inorganic insulating layer arranged in this area. After the organic insulating layer in this area is removed, the conductive layer which can only be covered by the organic insulating layer cannot be arranged in this area. Therefore, only the conductive layer which can be covered by both the inorganic insulating layer and the organic insulating layer is usually arranged in this area.

[0079] That is, the part of the conductive layer which can be covered by both the inorganic insulating layer and the organic insulating layer between the barrier wall 400 and the bending area 002a can be used as the exposed part 501 in the peripheral wire 500. In this way, the exposed part 501 has only one layer of wire, and the resistance of the exposed part 501 in the peripheral wire 500 is large, so that the exposed part 501 is prone to be burnt due to overheating.

[0080] To solve the above problems, please refer to FIG. 4 and FIG. 5, FIG. 4 is a schematic diagram of the partial film layer structure of the display panel shown in FIG. 1 at C-C', and FIG. 5 is a schematic diagram of the film layer structure of the display panel shown in FIG. 3 at D-D'. The display panel 000 can further include an inorganic partition layer 700. The inorganic partition layer 700 can include a partition part 701 arranged in the display area, and a first protection part 702 arranged in the non-display area.

[0081] The partition part 701 is used to partition at least part of the organic light-emitting film in the light-emitting layer 202, the first protection part 702 is arranged on the side of the exposed part 501 away from the substrate 100, and the orthographic projection of the first protection part 702 on the substrate 100 intersects with the orthographic projection of the exposed part 501 on the substrate 100.

[0082] It should be noted that the light emitting layer 202 in the present application can be composed of a plurality of sub-light emitting layers stacked together, and the charge generation layers between the sub-light emitting layers are connected in series. In this way, the color of the light emitted by the light emitting layer 202 can be determined by the plurality of sub-light emitting layers. For example, if the light emitting layer 202 needs to emit white light, a sub-light emitting layer capable of emitting red light, a sub-light emitting layer capable of emitting green light, and a sub-light emitting layer capable of emitting blue light can be stacked to make the light emitting layer 202 emit white light. Here, each sub-light emitting layer can include a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, and an electron injection layer stacked together. In this way, when a voltage is applied to the anode in the light emitting device 200, an electric field formed between the anode and the cathode in the light emitting device 200 causes electrons and holes to combine into high-energy state excitons. The high-energy state excitons are unstable and easily transition to low-energy state excitons and release energy, and in the process of releasing energy, photons are generated to emit light with a certain range of wavelengths. Here, the charge generation layer is usually made of a material with good conductivity, so that each sub-light emitting layer can emit light, thereby improving the light emitting effect of the light emitting layer 202.

[0083] However, the light emitting layer 202 in the display panel 000 is usually formed by whole layer evaporation using an evaporation process, that is, the sub-light emitting layers and the charge generation layers in each light emitting device 200 are connected together. In this way, since the charge generation layers in each light emitting device 200 are also connected together, and the charge generation layers have good conductivity. Therefore, during the light emitting process of a certain light emitting device 200, the charge generation layer in this light emitting device 200 can generate a horizontal leakage current, which can cause the adjacent light emitting device 200 to also emit light, thereby possibly causing the display effect of the display panel 000 to be poor.

[0084] Therefore, it is necessary to add a partition 701 in the display area to separate the charge generation layer in the light emitting layer 202, so as to ensure that during the light emitting process of a certain light emitting device 200, the charge generation layer in this light emitting device 200 can generate a horizontal leakage current that does not flow to the adjacent light emitting device 200, thereby reducing the probability of light leakage in the adjacent light emitting device 200.

[0085] For example, referring to FIG. 4, the inorganic partition layer 700 can be distributed on the side of the first electrode layer 200 facing the substrate 100. Here, the display panel 000 can further include a first planarization layer 800 distributed on the side of the substrate 100, and the inorganic partition layer 700 can be distributed on the side of the first planarization layer 800 facing away from the substrate 100. Since the inorganic partition layer 700 is made of an inorganic insulating material and the first planarization layer 800 is made of an organic insulating material, after the inorganic partition layer 700 is patterned, i.e., after the partition portion 701 is formed in the display area 001, the portion of the first planarization layer 800 not covered by the partition portion 701 can be etched to form a groove structure 801. In this way, the charge generation layer in the subsequent light-emitting layer 202 can be partitioned by the groove structure 801.

[0086] It should be noted that the number of partition portions 701 of the inorganic partition layer 700 in the display area 001 can be multiple, and the multiple partition portions 701 can correspond to the multiple light-emitting devices 200 distributed in the display area one by one. The orthographic projection of each light-emitting device 200 on the substrate 100 can be located in the orthographic projection of the corresponding light-emitting device 200 on the substrate 100.

[0087] In the embodiments of the present application, referring to FIG. 5, the first protection portion 702 of the inorganic partition layer 700 distributed in the non-display area can cover the isolation portion 501 in the peripheral wiring 500. That is, the orthographic projection of the isolation portion 501 in the peripheral wiring 500 on the substrate 100 can be located in the orthographic projection of the first protection portion 702 on the substrate 100. Therefore, between the barrier wall 400 and the bending area 002a, in addition to being able to be covered by the inorganic insulating layer and the organic insulating layer, the conductive layer can also be covered by other conductive layers that can only be covered by the organic insulating layer. Subsequently, let these conductive layers be covered by the first protection portion 702 of the inorganic partition layer 700. For this purpose, the exposed portion 501 in the peripheral wiring 500 can be designed as a multi-layer wiring structure, thereby reducing the resistance of the exposed portion 501 in the peripheral wiring 500 and improving the phenomenon that the exposed portion 501 is easily burned due to overheating, thereby improving the reliability of the display panel 000.

[0088] It should be noted that the role of the inorganic partition layer 700 in the display panel 000 is mainly to partition the light-emitting layer 202 in the display area 001. The present application not only makes the inorganic partition layer 700 play the role of partitioning the light-emitting layer 202 in the display area 001, but also makes the inorganic partition layer 700 play the role of protecting the exposed portion 501 in the peripheral wiring 500 in the non-display area 002, so that the exposed portion 501 can be designed as a multi-layer wiring structure. For this purpose, the present application does not additionally increase the film layer structure and does not additionally increase the manufacturing cost of the display panel 000.

[0089] In the embodiment of the present application, the exposure part 501 can adopt a structure design of two-layer wiring or a structure design of three-layer wiring. Therefore, the embodiment of the present application will be described schematically by taking the following two optional implementation manners as examples.

[0090] In the first optional implementation manner, in the case where the exposure part 501 adopts a structure design of double-layer wiring, as shown in FIG. 5, the exposure part 501 can include: a first exposure wiring 5011 and a second exposure wiring 5012 connected with each other, and the first exposure wiring 5011 and the second exposure wiring 5012 are arranged in a stacked manner in a direction away from the substrate 100. In this case, the first protection part 702 in the inorganic partition layer 700 can be located on a side of the second exposure wiring 5012 away from the substrate 100. Therefore, the first protection part 702 can protect the second exposure wiring 5012 on the side of the second exposure wiring 5012 away from the substrate 100, so as to ensure that the second exposure wiring 5012 will not be etched off in the subsequent preparation process of the first electrode layer 201.

[0091] It should be noted that the first exposure wiring 5011 can be part of the conductive layer in the display panel 000 that can be covered by both the inorganic insulating layer and the organic insulating layer, and the second exposure wiring 5012 can be part of the conductive layer in the display panel that can be covered by only the organic insulating layer.

[0092] In the embodiment of the present application, please refer to FIG. 6, which is another cross-sectional schematic view of the display panel at D-D' shown in FIG. 3. The display panel 000 further includes a passivation layer 1100. The passivation layer 1100 is an inorganic insulating layer for covering the conductive layer. Therefore, the passivation layer 1100 can be arranged between the conductive layer where the first exposure wiring 5011 is located and the conductive layer where the second exposure wiring 5012 is located. Here, the conductive layer where the first exposure wiring 5011 is located can be covered by the passivation layer 1100 and an organic insulating layer, and the conductive layer where the second exposure wiring 5012 is located can be located on a side of the organic insulating layer away from the substrate 100 and can be covered by another organic insulating layer.

[0093] In a possible case, as shown in FIG. 6, there can be a part of the passivation layer 1100 between the first exposure wiring 5011 and the second exposure wiring 5012, and the part of the passivation layer 1100 between the first exposure wiring 5011 and the second exposure wiring 5012 has a first via V1, and the second exposure wiring 5012 is partially overlapped with the first exposure wiring 5011 through the first via V1.

[0094] Here, the part of the passivation layer 1100 between the first exposed trace 5011 and the second exposed trace 5012 can have a plurality of first vias V1, whose orthographic projections on the substrate 100 can be distributed within the orthographic projection on the substrate 100 of the first exposed trace 5011 and within the orthographic projection on the substrate 100 of the second exposed trace 5012. To this end, the second exposed trace 5012 can be overlapped with the first exposed trace 5011 through the respective first vias V1.

[0095] In another possible case, the passivation layer 1100 can also have a hollow groove, and the orthographic projection on the substrate 100 of the exposed part 501 is within the orthographic projection on the substrate 100 of the hollow groove. In this case, as shown in FIG. 5, the side of the first exposed trace 5011 facing away from the substrate 100 and the side of the second exposed trace 5012 facing toward the substrate 100 are entirely overlapped.

[0096] In a second optional implementation, in the case where the exposed part 501 adopts a three-layer trace structure, please refer to FIG. 7, which is a sectional view of the display panel shown in FIG. 3 at E-E'. The exposed part 501 can include, in addition to the first exposed trace 5011 and the second exposed trace 5012 connected to each other, a third exposed trace 5013 connected to the second exposed trace 5012, which can be arranged in a stack with the second exposed trace 5012 and can be distributed on the side of the second exposed trace 5013 facing away from the substrate 100.

[0097] In this case, the first protection part 702 in the inorganic partition layer 700 can be located on the side of the third exposed trace 5013 facing away from the substrate 100. To this end, the first protection part 702 can protect the third exposed trace 5013 on the side of the third exposed trace 5013 facing away from the substrate 100, so as to ensure that the third exposed trace 5013 will not be etched away in the subsequent preparation process of the first electrode layer 201.

[0098] It should be noted that the first exposed trace 5011 can be part of the conductive layer in the display panel 000 that can be covered by both the inorganic insulating layer and the organic insulating layer, the second exposed trace 5012 can be part of the conductive layer in the display panel that can be covered by only one layer of the organic insulating layer, and the third exposed trace 5013 can be part of the conductive layer in the display panel that can be covered by only one layer of the organic insulating layer.

[0099] In the present application, the overlapping relationship between the first exposed trace 5011 and the second exposed trace 5013 in the exposed portion 501 can refer to the corresponding content in the first optional implementation manner described above, and will not be described here again. The second exposed trace 5012 in the exposed portion 501 is fully overlapped with the side of the third exposed trace 5013 facing the substrate 100.

[0100] It should be noted that since the first inorganic packaging layer 301 and the second inorganic packaging layer 303 have a part of the projection on the substrate 100, which can be located between the projection of the barrier wall 400 on the substrate 100 and the projection of the bending area 002a on the substrate 100. Therefore, the part of the first inorganic packaging layer 301 closer to the substrate 100, which is distributed between the barrier wall 400 and the bending area 002b, can be in contact with the first protection portion 701 on the side away from the substrate 100.

[0101] It should also be noted that in a possible implementation manner, the display panel 000 can include a conductive layer that can be covered by both the inorganic insulating layer and the organic insulating layer, and a conductive layer that is only covered by the organic insulating layer. In this case, for the exposed portion 501 of the first power signal 510 in the peripheral trace 500, the exposed portion 501 can include the first exposed trace 5011 and the second exposed trace 5012; for the exposed portion 501 of the second power signal 520 in the peripheral trace 500, the exposed portion 501 can also include the first exposed trace 5011 and the second exposed trace 5012.

[0102] In another possible implementation manner, the display panel 000 can include a conductive layer that can be covered by both the inorganic insulating layer and the organic insulating layer, and two conductive layers that are only covered by the organic insulating layer. In this case, for the exposed portion 501 of the first power signal 510 in the peripheral trace 500, the exposed portion 501 can include the first exposed trace 5011, and the exposed portion 501 can also include at least one of the second exposed trace 5012 and the third exposed trace 5013; for the exposed portion 501 of the second power signal 520 in the peripheral trace 500, the exposed portion 501 can include the first exposed trace 5011, the second exposed trace 5012 and the third exposed trace 5013.

[0103] In the embodiment of the present application, as shown in FIG. 1, the non-display area 002 further includes a binding area 002b located on the side of the bending area 002a away from the display area. In order to more clearly show the structure in the binding area 002b, please refer to FIG. 8, which is a partial enlarged view of a binding area provided in an embodiment of the present application. The display panel 000 further includes a plurality of connection pins 900 located in the binding area 002b.

[0104] Here, the plurality of connecting pins 900 in the binding area 002b are used to be connected to the plurality of output pins in the driving chip one by one. After the plurality of connecting pins 900 in the binding area 002b are connected to the plurality of output pins on the chip one by one, the driving chip can be bound on the binding area 002b of the display panel 000.

[0105] It should be noted that the plurality of connecting pins 900 in the binding area 020b need to be electrically connected to the plurality of data lines distributed in the display area 001 one by one. Here, a column of pixel driving circuits in the display area 001 can be electrically connected to the same data line. In this way, the driving chip can provide a data signal to the corresponding data line through the connecting pin 900, so that the corresponding pixel driving circuit can control the light emitting device 200 to emit light according to the data signal.

[0106] Please refer to FIG. 9, which is a cross-sectional view of a single connecting pin according to an embodiment of the present application. The connecting pin 900 at least includes a first pin portion 910 disposed in the same layer as the exposed portion 501.

[0107] It should be noted that the first pin portion 910 disposed in the same layer as the exposed portion 501 is made of a metal material, and these structures need to be prepared before the first electrode layer 201 is prepared. In the process of preparing the first electrode layer 201, an etching process is usually needed to be performed using silver sulfate solution. Without protection on the side of the first pin portion 910 away from the substrate 100, the silver sulfate solution can have a chemical displacement reaction with the side of the first pin portion 910 away from the substrate 100, thereby causing the first pin portion 910 to also be etched. The chemical displacement reaction can precipitate silver impurities, which are distributed between two adjacent connecting pins 900. In the case that the distance between the two adjacent connecting pins 900 is close, the silver impurities distributed between the two adjacent connecting pins 900 can easily cause short circuit between them.

[0108] Therefore, in the embodiment of the present application, the inorganic partition layer 700 can further include a second protection portion 703 located in the binding area 002b. The second protection portion 703 is located on the side of the first pin portion 910 away from the substrate 100, and the orthographic projection of the second protection portion 703 on the substrate 100 intersects with the orthographic projection of the first pin portion 910 on the substrate 100. In this way, the side of the first pin portion 910 away from the substrate 100 is protected by the second protection portion 703, which can ensure that the probability of the chemical displacement reaction between the first pin portion 910 and the silver sulfate solution is low. Therefore, the probability of short circuit between two adjacent connecting pins 900 caused by the precipitation of silver impurities can be effectively reduced.

[0109] In a possible implementation, referring to FIG. 9, in a case where the exposing part 501 only includes the first exposing trace 5011 and the second exposing trace 5012, the first pin part 910 includes: a first sub-pin 911 and a second sub-pin 912 which are stacked.

[0110] The first sub-pin 911 is arranged in the same layer as the first exposing trace 5011 and is made of the same material, and the second sub-pin 912 is arranged in the same layer as the second exposing trace 5012 and is made of the same material. That is, the first sub-pin 911 and the first exposing trace 5011 are formed by the same patterning process, and the second sub-pin 912 and the second exposing trace 5012 are formed by the same patterning process. In this case, the second protection part 703 is located on a side of the second sub-pin 912 away from the substrate 100.

[0111] In another possible implementation, referring to FIG. 10, which is a schematic cross-sectional view of another single connecting pin provided in an embodiment of the present application. In a case where the exposing part 501 includes the first exposing trace 5011, the second exposing trace 5012 and the third exposing trace 5013, the first pin part 910 includes: a first sub-pin 911, a second sub-pin 912 and a third sub-pin 913 which are stacked.

[0112] The first sub-pin 911 is arranged in the same layer as the first exposing trace 5011 and is made of the same material, the second sub-pin 912 is arranged in the same layer as the second exposing trace 5012 and is made of the same material, and the third sub-pin 913 is arranged in the same layer as the third exposing trace 5013 and is made of the same material. That is, the first sub-pin 911 and the first exposing trace 5011 are formed by the same patterning process, the second sub-pin 912 and the second exposing trace 5012 are formed by the same patterning process, and the third sub-pin 913 and the third exposing trace 5013 are formed by the same patterning process. In this case, the second protection part 703 is located on a side of the third sub-pin 913 away from the substrate 100.

[0113] In the embodiment of the present application, as shown in FIG. 9 and FIG. 10, the connecting pin 900 further includes: a second pin part 920 and / or a third pin part 930.

[0114] In a case where the connecting pin 900 includes the second pin part 920, the second pin part 920 can be located on a side of the second protection part 703 away from the substrate 100, and the second protection part 703 has a second via V2, and the second pin part 920 is partially overlapped with the first pin part 910 through the second via V2.

[0115] Exemplarily, the display panel 000 further includes a touch electrode layer and a touch insulating layer on the side of the encapsulation layer 300 away from the substrate 100. The touch electrode layer can be mainly distributed in the display area 001 of the display panel 000, so that the display panel 000 can have a touch function. Part of the touch insulating layer can be distributed in the display area 001, which can serve as an insulating layer for the touch electrodes and the bridge electrodes in the touch electrode layer. Another part of the touch insulating layer can be distributed in the non-display area 002, which can serve as a pad for the connecting electrodes 900. Here, the part of the touch electrode layer distributed in the non-display area 002 near the connecting electrodes 900 can be referred to as a touch insulating portion 1000.

[0116] The second pin portion 920 in the connecting electrode 900 can be disposed in the same layer as the touch electrode layer and made of the same material. That is, the second pin portion 920 can be formed by the same patterning process as the touch electrode layer. The touch insulating portion 1000 can be distributed on the side of the second pin portion 920 facing the substrate 100 and on the side of the second protective portion 703 away from the substrate 100. The touch insulating portion 1000 can have a third via V3 in communication with the second via V2. To this end, the second pin portion 920 can be in contact with the side of the first pin 910 away from the substrate 100 after sequentially passing through the third via V3 and the second via V2.

[0117] It should be noted that, in order to ensure that the second protective portion 703 can better protect the side of the first pin 910 away from the substrate 100, it is necessary to ensure that the second via V2 on the second protective portion 703 is prepared after the first electrode layer 201 is prepared. Exemplarily, the second via V2 on the second protective portion 703 in communication with the third via V3 in the touch insulating portion 1000 can be formed during the process of forming the third via V3.

[0118] That is, after the second protective portion 703 is prepared, the second via V2 is not directly formed thereon, so as to ensure that the second protective portion 703 can protect each position of the side of the first pin portion 910 away from the substrate 100 during the preparation of the first electrode layer 201.

[0119] In the case where the connecting electrode 900 includes a third pin portion 930, the third pin portion 930 is located on the side of the first pin portion 910 close to the substrate 100, and the side of the third pin portion 930 away from the substrate 100 is in contact with the side of the first pin portion 910 facing the substrate 100.

[0120] It should be noted that the third pin portion 930 can be disposed in the same layer as the gate of the transistor in the pixel driving circuit and made of the same material. That is, the third pin portion 930 can be formed at the same time as the gate.

[0121] In the embodiment of the present application, the display panel 000 can excavate part of the display area 001 according to product requirements and set the opening hole. Please refer to FIG. 1, the display panel 000 can further include an opening hole area 003 and a transition area 004. The display area 001 is located at the periphery of the opening hole area 003, and the transition area 004 is located between the opening hole area 003 and the display area 001. The transition area 004 can be annular, and the transition area 004 can surround the opening hole area 003.

[0122] In order to prevent water and oxygen in the external environment from invading the inside of the display area 001 through the opening hole area 003 and causing the failure of the light emitting device 200 in the display area 001, please refer to FIG. 11, which is a schematic diagram of the film layer structure of the display panel at F-F'. The display panel 000 can further include a plurality of conductive isolation columns L arranged on one side of the substrate 100. The conductive isolation columns L are located in the transition area 004, are arranged in the same layer as the third exposed trace 5013 and are made of the same material. The plurality of conductive isolation columns L are annular and surround the opening hole area 003, and each conductive isolation column L is used to isolate part of the light emitting layer 202 distributed in the transition area 004. For example, the side surface of the conductive isolation column L can be away from the isolation groove U, and the isolation groove U can isolate part of the light emitting layer 202 distributed in the transition area 004. That is, part of the light emitting layer 202 on the side of the conductive isolation column L away from the substrate 100 can be disconnected from other parts.

[0123] In this case, even if water and oxygen in the external environment invade the light emitting layer 202 in the transition area 004 through the opening hole area 003, the invasion of water and oxygen can be blocked by the isolated light emitting layer 202 in the transition area 004, so as to prevent water and oxygen in the external environment from invading part of the light emitting layer 202 located in the area 001, thereby ensuring a high service life of each light emitting device 200.

[0124] In the embodiment of the present application, in the case that the display panel 000 has the opening hole area 003 and the transition area 004, the orthogonal projection of the inorganic isolation layer 700 on the substrate 1000 does not overlap with the orthogonal projection of the transition area 004 on the substrate 1000, that is, in the film layer structure of the transition area 004 of the display panel 000, there is no inorganic isolation layer 700.

[0125] Please refer to FIG. 12, which is a schematic diagram of the film layer structure in the display area of a display panel according to an embodiment of the present application. The pixel driving circuit P electrically connected to the light emitting device 200 in the display panel 000 can include at least two transistors and at least one storage capacitor.

[0126] The storage capacitor can include a first capacitor electrode C1 and a second capacitor electrode C2 arranged oppositely. The transistor can include an active layer Act, a gate electrode G, a source electrode S, and a drain electrode D. The active layer Act can be arranged to be insulated from the gate electrode G, and the source electrode S and the drain electrode D can be both overlapped with the active layer Act. The source electrode S can be electrically connected with a data line, and the drain electrode D can be electrically connected with an anode of the light emitting device 200 through a transfer electrode. Here, the transfer electrode can be a single-layer structure or a double-layer structure. In the case of the double-layer structure, the transfer electrode can include a first sub-transfer electrode Z1 and a second sub-transfer electrode Z2 arranged in a stack.

[0127] In the embodiment of the present application, the film layer structure in the display panel 000 can include a substrate 100, a buffer layer 1200, an active layer pattern, a first gate insulating layer 1300, a fifth conductive layer, a second gate insulating layer 1400, a fourth conductive layer, an interlayer boundary layer 1500, a third conductive layer, a passivation layer 1100, a third planarization layer 1600, a second conductive layer, a second planarization layer 1700, a first conductive layer, a first planarization layer 800, an inorganic partition layer 700, a first electrode layer 201, a pixel definition layer 600, a light emitting layer 202, a second electrode layer 203, an encapsulation layer 300, and a touch electrode layer 1800 arranged in a stack on the substrate 100.

[0128] Here, the active layer pattern can include an active layer Act in a transistor.

[0129] The fifth conductive layer can include a gate electrode G in a transistor, a first capacitor electrode C1 in a storage capacitor, and a third pin portion 930 in a connection pin 900.

[0130] The fourth conductive layer can include a second capacitor electrode C2 in a storage capacitor.

[0131] The third conductive layer can include a source electrode S and a drain electrode D in a transistor, a first exposed trace 5011 in an exposed portion 501, and a first sub-pin 911 in a connection pin 900.

[0132] The second conductive layer can include a first sub-transfer electrode Z1, a second exposed trace 5012 in the exposed portion 501, and a second sub-pin 912 in the connection pin 900.

[0133] The first conductive layer can include a second sub-transfer electrode Z2, a third exposed trace 5013 in the exposed portion 501, a third sub-pin 913 in the connection pin 900, and a plurality of conductive isolation columns in a transition area 004. L .

[0134] It should be noted that the first conductive layer, the second conductive layer and the third conductive layer in the above embodiment can be part of the peripheral trace 500. The passivation layer 1100 in the display panel 000 is an inorganic insulating layer, and the first planarization layer 800, the second planarization layer 1700 and the third planarization layer 1600 in the display panel 000 all belong to organic insulating layers. Therefore, the third conductive layer in the display panel 000 can be a conductive layer covered by both an inorganic insulating layer (i.e., the passivation layer 1100) and an organic insulating layer (i.e., the third planarization layer 1600); the second conductive layer in the display panel 000 can be a conductive layer covered by only one layer of organic insulating layer (i.e., the second planarization layer 1700); and the first conductive layer in the display panel 000 can also be a conductive layer covered by only one layer of organic insulating layer (i.e., the first planarization layer 800).

[0135] In summary, since the inorganic partition layer includes the partition part in the display area and the first protection part in the non-display area, the inter-pixel crosstalk can be improved by the partition part in the display area, the display effect of the display panel is improved, the exposed part in the peripheral trace is protected by the first protection part in the non-display area, the exposed part in the peripheral trace can adopt a multi-layer trace structure design, the resistance of the exposed part in the peripheral trace is reduced, and the phenomenon that the exposed part is easily burned due to overheating is improved. In addition, the inorganic partition layer also includes the second protection part in the non-display area, the second protection part can protect the side of the first pin part away from the substrate, so as to avoid the reaction between the first pin part and the etching solution used when the first electrode layer is formed, thereby avoiding the short circuit between two adjacent connecting pins caused by the precipitation of silver impurities. In this way, the reliability of the display panel can be effectively improved.

[0136] The display panel manufacturing method provided by the embodiment of the present application is used to manufacture the display panel shown in the above embodiment. The display panel has a display area and a non-display area located at the periphery of the display area, and the non-display area has a bending area. The display panel manufacturing method comprises:

[0137] forming the first electrode layer, the light-emitting layer, the second electrode layer, the peripheral trace, the barrier wall and the inorganic partition layer on one side of the substrate.

[0138] The first electrode layer, the light-emitting layer and the second electrode layer are stacked on one side of the substrate, and the first electrode layer, the light-emitting layer and the second electrode layer are all distributed in the display area. The barrier wall is located in the non-display area and surrounds the display area; the peripheral trace is distributed in the non-display area, and the peripheral trace has an exposed part, and a projection of the exposed part on the substrate is located between a projection of the barrier wall on the substrate and a projection of the bending area on the substrate; the inorganic partition layer includes a partition part located in the display area and a first protection part located in the non-display area; the partition part is used to partition at least part of the organic light-emitting film in the light-emitting layer, and the first protection part is located on a side of the exposed part away from the substrate, and a projection of the first protection part on the substrate overlaps with a projection of the exposed part on the substrate.

[0139] In the embodiment of the present application, the display panel further has an opening area and a transition area, the display area is located at the periphery of the opening area, and the transition area is located between the opening area and the display area.

[0140] It should be noted that the inorganic partition layer needs to be formed before the first electrode layer is formed, and the inorganic partition layer needs to be formed after the first planar layer in the display panel is formed, and the inorganic partition layer needs to be distributed outside the transition area. That is, a projection of the inorganic partition layer on the substrate is located outside a projection of the transition area on the substrate. That is, the inorganic partition layer does not have a part distributed in the transition area. Therefore, in the related art, in the process of forming the inorganic partition layer on the side of the first planar layer in the display panel away from the substrate, an inorganic film layer needs to be first formed on the side of the first planar layer away from the substrate, and then the inorganic film layer is subjected to a patterning process to remove the part distributed in the transition area.

[0141] However, after the part of the inorganic film layer located in the transition area is removed, there is no other structure on the side of the conductive isolation column distributed in the transition area away from the substrate. In this way, in the subsequent process of forming the first electrode layer, when using silver sulfate solution to perform etching process, the silver sulfate solution may have a chemical displacement reaction with the conductive isolation column, not only causing additional silver impurities to be precipitated in the transition area, but also causing an isolation groove to be formed on the side wall of the conductive isolation column too early. Therefore, in the subsequent process of forming the pixel definition base layer on the side of the first electrode layer away from the substrate, organic residues are easily formed in the isolation groove, resulting in poor partitioning effect of the isolation groove on the conductive isolation column on the light-emitting layer, and thus water and oxygen in the external environment are easily introduced into the display area through the opening area and the light-emitting layer. It should be noted that the organic residues in the isolation groove are the same as the material of the pixel definition layer, and the organic residues are the organic material that is not completely removed during the formation of the pixel definition layer.

[0142] Therefore, the embodiment of the present application provides a new preparation process of the inorganic partition layer. The method for forming the inorganic partition layer on one side of the substrate can include:

[0143] Step S101, forming an inorganic thin film layer on the substrate with the first conductive layer and the first planar layer.

[0144] For example, referring to FIG. 13, which is an effect diagram of forming an inorganic thin film layer on the substrate with the first conductive layer and the first planar layer according to an embodiment of the present application. The inorganic thin film layer 700a can be formed on one side of the substrate 100 with the first conductive layer and the first planar layer 800 by any one of various methods such as deposition, coating, sputtering, etc.

[0145] The first planar layer 800 can be located on the side of the first conductive layer away from the substrate 100, and the first conductive layer can include a plurality of conductive isolation columns L located in the transition area 004. It should be noted that the first conductive layer can also include a second sub-connection electrode Z2, a third exposed trace 5013 in the exposed part 501, and a third sub-lead 913 in the lead 900. The first planar layer 800 can at least cover the second sub-connection electrode Z2 in the first conductive layer located in the display area 001.

[0146] Step S102, patterning the inorganic thin film layer to form an inorganic transition layer.

[0147] For example, referring to FIG. 14, which is an effect diagram of the inorganic transition layer obtained after the inorganic thin film layer is patterned according to an embodiment of the present application. The inorganic thin film layer can be subjected to a one-time patterning process, which can achieve the patterning of the inorganic thin film layer, and thus the inorganic transition layer 700b can be obtained.

[0148] The inorganic transition layer 700b can include the partitioning part 701, the first protection part 702, and the second protection part 703 mentioned in the above embodiments. The inorganic transition layer 700b can also include a transition protection part 704 located in the transition area 004. Here, the transition protection part 704 can cover a plurality of conductive isolation columns L.

[0149] That is, the orthogonal projection of the plurality of conductive isolation columns on the substrate 100 can be located in the orthogonal projection of the transition protection part 704 on the substrate 100.

[0150] Step S103, after forming the first electrode layer and the pixel definition layer on the side of the inorganic transition layer away from the substrate in sequence, removing the transition protection part in the inorganic transition layer to obtain an inorganic partitioning layer.

[0151] For example, refer to FIG. 15, which is an effect diagram of sequentially forming the first electrode layer and the pixel definition layer on the side of the inorganic transition layer away from the substrate. First, a conductive film layer can be formed on the side of the inorganic transition layer 700b away from the substrate, and then a patterning process is performed on the conductive film layer, so as to obtain the first electrode layer 201. Then, an organic film layer is coated on the side of the first electrode layer away from the substrate, and the organic film layer is subjected to exposure and development, so as to obtain the patterned pixel definition layer 600.

[0152] It should be noted that, in the process of forming the first electrode layer 201 and the pixel definition layer 600, the side of the plurality of conductive isolation columns L away from the substrate 100 is protected by the transition protection part 704, so as to ensure that the silver sulfate solution used in the process of forming the first electrode layer 202 does not react with the conductive isolation column L, and thus no additional silver impurities are precipitated in the transition area 004. In the case that the silver sulfate solution does not react with the conductive isolation column L, the side of the conductive isolation column L does not form an isolation groove. Therefore, it can also be avoided that the transition area 004 forms excess organic residues in the process of forming the pixel definition layer 600.

[0153] In the present application, after the first electrode layer 201 and the pixel definition layer 600 are formed, the transition protection part 704 in the inorganic transition layer 700b in the transition area 004 can be removed. For example, the transition protection part 704 in the inorganic transition layer 700b in the transition area 004 can be removed by using a patterning process again.

[0154] For example, refer to FIG. 16, which is a schematic diagram of removing the transition protection part. A photoresist can be coated on the side of the pixel definition layer 600 away from the substrate 100, and after the photoresist is subjected to exposure and development, a photoresist pattern PR can be obtained, which can cover the display area 001 of the display panel 000 and expose the transition area 004 of the display panel 000. In this way, after the transition protection part 704 in the transition area 004 is etched, the transition protection part 704 can be removed, so as to obtain the inorganic isolation layer 700.

[0155] In the present application, refer to FIG. 17, which is an effect diagram of over-etching the conductive isolation column. After the inorganic isolation layer 700 is formed on the display panel 000, the conductive isolation column L can be over-etched, so as to form an isolation groove U on the side wall of the conductive isolation column L. Here, the display panel 000 has formed the pixel definition layer 600, so as to ensure that the isolation groove U in the conductive isolation column L does not contain organic residues.

[0156] It should be noted that after the conductive isolation column L is subjected to the etching process, the photoresist pattern PR on the display panel 000 can be stripped, and a subsequent film forming process can be performed. Here, the subsequent film forming process and the film forming process between the inorganic partition layers 700 can refer to the processes in the related art. Details are not described here.

[0157] It should also be noted that the one-time patterning process provided in the above embodiments can include photoresist coating, exposure, development, etching, and photoresist stripping.

[0158] The present application also provides a display device, which includes a power supply component and a display panel 000 electrically connected to the power supply component. The display panel 000 can include any of the display panels 000 described above. The display device can be a mobile phone, a tablet computer, a television, an advertising machine, a display screen, a digital photo frame, or any other product or component having a display function.

[0159] It should be noted that in the drawings, the sizes of the layers and regions can be exaggerated for clarity. It should also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can also be present. In addition, it should be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or layer, or one or more intervening layers or elements can also be present. In addition, it should be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers or elements can also be present. Similar reference numerals can indicate similar elements throughout the specification.

[0160] In the present application, the terms "first" and "second" are used only for descriptive purposes, and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more, unless otherwise explicitly limited.

[0161] The above description is only optional embodiments of the present application, and should not be used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel has a display area and a non-display area located at the periphery of the display area, and the non-display area has a bending area; the display panel comprises a substrate, a first electrode layer, a light-emitting layer, a second electrode layer, a peripheral trace, a barrier wall and an inorganic partition layer located on one side of the substrate; The first electrode layer, the light-emitting layer and the second electrode layer are stacked on one side of the substrate, and the first electrode layer, the light-emitting layer and the second electrode layer are all distributed at least in the display area; The barrier wall is located in the non-display area and is distributed around the display area; The peripheral trace is distributed in the non-display area, and the peripheral trace has an exposed part, and the orthographic projection of the exposed part on the substrate is located between the orthographic projection of the barrier wall on the substrate and the orthographic projection of the bending area on the substrate; The inorganic partition layer comprises a partition part located in the display area and a first protection part located in the non-display area; the partition part is used to partition at least part of the organic light-emitting film in the light-emitting layer, the first protection part is located on the side of the exposed part away from the substrate, and the orthographic projection of the first protection part on the substrate overlaps with the orthographic projection of the exposed part on the substrate.

2. The display panel of claim 1, wherein, The orthographic projection of the exposed part on the substrate is located in the orthographic projection of the first protection part on the substrate.

3. The display panel of claim 1, wherein, The exposed part comprises a first exposed trace and a second exposed trace connected to each other, and the first exposed trace and the second exposed trace are stacked in a direction away from the substrate; The first protection part is located on the side of the second exposed trace away from the substrate.

4. The display panel of claim 3, wherein, The display panel further comprises an inorganic insulating layer; There is a part between the first exposed trace and the second exposed trace in the inorganic insulating layer, and the part between the first exposed trace and the second exposed trace in the inorganic insulating layer has a first via hole, and the second exposed trace is partially overlapped with the first exposed trace through the first via hole; Alternatively, the inorganic insulating layer has a hollow groove, the orthographic projection of the exposed part on the substrate is located in the orthographic projection of the hollow groove on the substrate, and the side of the first exposed trace away from the substrate and the side of the second exposed trace towards the substrate are fully overlapped. The exposed part further comprises a third exposed trace connected to the second exposed trace, the third exposed trace is stacked with the second exposed trace, and the third exposed trace is located on the side of the second exposed trace away from the substrate; 5. The display panel of claim 3, wherein, The first protection part is located on the side of the third exposed trace away from the substrate. The side of the second exposed trace away from the substrate and the side of the third exposed trace towards the substrate are fully overlapped.

6. The display panel of claim 5, wherein, The non-display area further comprises a binding area, and the binding area is located on the side of the bending area away from the display area; 7. The display panel of any of claims 1 to 6, wherein, ​ The display panel further comprises a plurality of connection pins in the binding area, the connection pins at least comprising: a first pin portion arranged in the same layer as the exposed portion, the inorganic partition layer further comprising a second protection portion in the binding area, the second protection portion being located on the side of the first pin portion away from the substrate, and the second protection portion on the substrate overlaps with the first pin portion on the substrate.

8. The display panel of claim 7, wherein, The connection pin further comprises a second pin portion, the second pin portion being located on the side of the second protection portion away from the substrate, the second protection portion having a second via hole, and the second pin portion partially overlaps with the first pin portion through the second via hole; And / or, the connection pin further comprises a third pin portion, the third pin portion being located on the side of the first pin portion close to the substrate, and the side of the third pin portion away from the substrate overlaps with the side of the first pin portion towards the substrate.

9. The display panel of claim 7, wherein, In the case where the exposed portion comprises a first exposed trace and a second exposed trace, the first pin portion comprises: a first sub-pin and a second sub-pin arranged in layers; wherein the first sub-pin is arranged in the same layer as the first exposed trace and has the same material, and the second sub-pin is arranged in the same layer as the second exposed trace and has the same material; Or, in the case where the exposed portion comprises a first exposed trace, a second exposed trace and a third exposed trace, the first pin portion comprises: the first sub-pin, the second sub-pin and a third sub-pin arranged in layers; wherein the first sub-pin is arranged in the same layer as the first exposed trace and has the same material, the second sub-pin is arranged in the same layer as the second exposed trace and has the same material, and the third sub-pin is arranged in the same layer as the third exposed trace and has the same material.

10. The display panel of any of claims 1-6, 8-9, wherein, The display panel further comprises: a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer arranged in layers on the side of the second electrode layer away from the substrate; The organic encapsulation layer is located in the area surrounded by the barrier wall, and part of the boundary of the first inorganic encapsulation layer and the second inorganic encapsulation layer on the substrate is located between the projection of the barrier wall on the substrate and the projection of the bending area on the substrate; Wherein, the part of the first inorganic encapsulation layer distributed between the barrier wall and the bending area is in contact with the side of the first protection portion away from the substrate.

11. The display panel of any of claims 1 to 6, 8 to 9, wherein, The peripheral trace comprises: a first power signal line and a second power signal line, the potential of the power signal loaded on the first power signal line being higher than the potential of the power signal loaded on the second power signal line; Wherein, the first power signal line has the exposed portion, and / or the second power signal line has the exposed portion.

12. The display panel of any of claims 1 to 6, 8 to 9, wherein, The display panel further has: an opening area and a transition area, the display area being located at the periphery of the opening area, and the transition area being located between the opening area and the display area; The display panel further comprises: a plurality of conductive isolation columns on one side of the substrate, the plurality of conductive isolation columns being distributed in the transition area, the conductive isolation column being annular and surrounding the opening area The conductive isolation column is used to isolate part of the light-emitting layer distributed in the transition region; The orthographic projection of the inorganic isolation layer on the substrate does not coincide with the orthographic projection of the transition region on the substrate.

13. A manufacturing method of a display panel, characterized by, The display panel has a display area and a non-display area located at the periphery of the display area, and the non-display area has a bending area; the manufacturing method of the display panel comprises: A first electrode layer, a light-emitting layer, a second electrode layer, a peripheral trace, a barrier wall and an inorganic isolation layer are formed on one side of a substrate; The first electrode layer, the light-emitting layer and the second electrode layer are stacked on one side of the substrate, and the first electrode layer, the light-emitting layer and the second electrode layer are all distributed at least in the display area; The barrier wall is located in the non-display area and is distributed around the display area; The peripheral trace is distributed in the non-display area, and the peripheral trace has an exposed part, and the orthographic projection of the exposed part on the substrate is located between the orthographic projection of the barrier wall on the substrate and the orthographic projection of the bending area on the substrate; The inorganic isolation layer comprises an isolation part located in the display area and a first protection part located in the non-display area; the isolation part is used to isolate at least part of the organic light-emitting film in the light-emitting layer, the first protection part is located on the side of the exposed part away from the substrate, and the orthographic projection of the first protection part on the substrate overlaps with the orthographic projection of the exposed part on the substrate.

14. The method of claim 13, wherein, The display panel further has an aperture area and a transition area, the display area is located at the periphery of the aperture area, and the transition area is located between the aperture area and the display area; the inorganic isolation layer is formed on one side of the substrate, comprising: An inorganic thin film layer is formed on the substrate with a first conductive layer and a first planar layer, the first conductive layer comprises a plurality of isolation columns located in the transition area, and the first planar layer is located on the side of the first conductive layer away from the substrate; The inorganic thin film layer is subjected to a patterning process to form an inorganic transition layer, the inorganic transition layer comprises the isolation part and the first protection part, and a transition protection part located in the transition area, and the transition protection part covers the plurality of conductive isolation columns; After the first electrode layer and the pixel definition layer are sequentially formed on the side of the inorganic transition layer away from the substrate, the transition protection part in the inorganic transition layer is removed to obtain the inorganic isolation layer.

15. A display device comprising: Comprise: A power supply assembly and a display panel connected with the power supply assembly, the display panel is any one of the display panels in claims 1 to 12. A power supply assembly and a display panel connected with the power supply assembly, the display panel is any one of the display panels in claims 1 to 12.

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