Field effect transistor

Abstract

Disclosed in the present invention is a field effect transistor, comprising: a drain electrode, located at a bottom layer; a base substrate, located on the drain electrode; a semiconductor layer of a first conductivity type, located on the base substrate; a source region of the first conductivity type, located on the semiconductor layer of the first conductivity type; gate trenches, extending from the source region of the first conductivity type into the semiconductor layer of the first conductivity type, and each comprising a gate electrode and a shielding gate electrode; insulating dielectric layers, arranged on the gate trenches and the source region of the first conductivity type; and a source electrode, a first portion of which forms a Schottky contact with the semiconductor layer of the first conductivity type, and a second portion of which forms an Ohmic contact with the source region of the first conductivity type. The semiconductor layer of the first conductivity type is divided into three regions from top to bottom, and the doping concentration of a second doped region is graded or uniform, and is higher than those of the other two regions. The present invention can optimize the distribution of an electric field, so that the electric field exhibits a rectangular distribution, thereby improving the voltage withstand of a device and reducing the on-resistance of the device.

Description

A field effect transistor TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a field effect transistor. BACKGROUND

[0002] Schottky source-drain MOSFET structure was proposed in the 1960s, which uses metal source-drain to replace the semiconductor doped source-drain of traditional pn junction type MOSFET, and a Schottky contact barrier is formed between the metal source-drain and the semiconductor. For the Schottky source-drain MOSFET, when a positive voltage is applied between the drain and the source, the Schottky barrier formed between the source and the semiconductor material is reversed, so that the depletion layer is widened to achieve turn-off, and accordingly, the Schottky source-drain MOSFET is a normally-off device; The conduction of the Schottky source-drain MOSFET is realized by the carrier of the source directly tunneling into the channel under the action of a positive gate bias to form a conductive channel.

[0003] Compared with the traditional pn junction type MOSFET, the Schottky source-drain MOSFET has the following advantages: first, the metal Schottky contact has the characteristics of super-shallow junction, which can effectively suppress the short channel effect and source-drain punchthrough problem of conventional MOSFET when the device size is greatly reduced, providing the possibility for MOSFET to continue to reduce the size; second, the high conductivity of the metal-semiconductor contact can further reduce the drain-source resistance; third, in the Schottky source-drain MOSFET, there is no parasitic body triode effect, and the response speed is faster, which can be more high-frequency; fourth, there is no need for ion implantation to form n+ or P+ source-drain region, and high-temperature annealing is also cancelled, so the process is simple. At the same time, it also avoids the lattice damage problem caused by ion implantation and annealing, which helps to obtain high interface quality, so as to obtain high-quality dielectric layer, and the withstand voltage and reliability will be better.

[0004] However, since the Schottky source-drain MOSFET was born, there have been two major disadvantages: first, the on-state current is small, when the drain-source voltage V DS > 0 of the Schottky source-drain MOSFET, the Schottky contact barrier formed between the Schottky source electrode and the semiconductor is reversed, which widens the depletion region, so that even if a positive gate-source voltage V GSAt the same time, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode and the Schottky source electrode, and a certain Schottky barrier height always exists in the region close to the Schottky source electrode, which limits the transport of electron carriers, so that only a small part of the electron carriers form a current through the tunneling effect. According to the conductivity calculation formula σ = nqu (where n is the electron carrier concentration participating in conduction, q is the electron charge, and u is the mobility under a certain carrier concentration), the lower the carrier concentration n participating in conduction, the lower the conductivity σ. According to the current density J = σE (where E represents the electric field strength), the lower the conductivity σ, the lower the current density J. This is the reason why the on-state current of the Schottky source-drain MOSFET is smaller than that of the pn junction MOSFET under the same conditions. The on-state current of the conventional pn junction MOSFET can reach tens of amperes to hundreds of amperes, while the on-state current of the Schottky source-drain MOSFET under the same conditions can only reach milliamperes or even lower; second, the off-state leakage current is large, and the leakage current includes the hot electron emission current transmitted from the source junction through the substrate and the tunneling current from the source junction.

[0005] These two shortcomings, especially the small on-state current, have not been well solved to this day, which has seriously restricted the use of the Schottky source-drain MOSFET, so that there has been no commercial application of the Schottky source-drain MOSFET to date. SUMMARY

[0006] In order to solve the problems in the prior art, the present application provides a field effect transistor having a Schottky junction type MOSFET structure, which at least solves one of the technical problems in the prior art to some extent.

[0007] To solve the above problems, the embodiment of the field effect transistor provided by the present application has the technical scheme as follows:

[0008] A field effect transistor, comprising:

[0009] a drain electrode located at the bottom layer of the field effect transistor;

[0010] a substrate located above the drain electrode;

[0011] a first-conductivity-type semiconductor layer located above the substrate;

[0012] a first-conductivity-type source region located above the first-conductivity-type semiconductor layer;

[0013] a gate trench extended into the semiconductor layer of the first conductivity type from the source region of the first conductivity type, the gate trench including a gate electrode and a shield gate electrode for creating a lateral depletion effect in the semiconductor layer of the first conductivity type when the field effect transistor is in an off state;

[0014] an insulating dielectric layer disposed on the gate trench and the source region of the first conductivity type;

[0015] a source electrode, a first portion of the source electrode extending inwardly from the source region of the first conductivity type into the semiconductor layer of the first conductivity type with a shallower depth than the gate electrode, the first portion of the source electrode forming a Schottky contact with the semiconductor layer of the first conductivity type; a second portion of the source electrode in contact with the insulating dielectric layer, the source region of the first conductivity type, and the first portion of the source electrode, the second portion of the source electrode forming an Ohmic contact with the source region of the first conductivity type;

[0016] wherein the semiconductor layer of the first conductivity type has a first doped region, a second doped region, and a third doped region; the first doped region is adjacent to the source region from top to bottom, and the bottom of the first doped region is not higher than the bottom of the gate electrode; the second doped region is adjacent to the first doped region from top to bottom, and the bottom of the second doped region is not lower than the bottom of the shield gate electrode; the third doped region is between the second doped region and the substrate; the second doped region is either a graded doped region or a uniform doped region, and the doping concentration of the second doped region is higher than the doping concentration of the first doped region and the doping concentration of the third doped region.

[0017] Preferably, the second doped region is a graded doped region, the doping concentration of the second doped region gradually increases to a certain doping concentration from top to bottom, and then gradually decreases to the doping concentration of the third doped region, and the lowest concentration of the second doped region is higher than the doping concentration of the first doped region and the third doped region.

[0018] Preferably, the second doped region is a uniform doped region, and the doping concentration of the first doped region and the third doped region is less than the doping concentration of the second doped region.

[0019] Preferably, the first doped region is between the source region of the first conductivity type and the bottom of the gate electrode.

[0020] Preferably, the second doped region is between the first doped region and the bottom of the shield gate electrode.

[0021] Preferably, the first conductivity type is n-type.

[0022] Preferably, the shield gate electrode and the gate electrode are both located in the middle of the gate trench, and the shield gate electrode is located below the gate electrode.

[0023] Preferably, the shield gate electrode is located in the middle of the gate trench, and the gate electrode is located on both sides of the upper part of the shield gate electrode.

[0024] Preferably, the width of the semiconductor layer of the first conductive type between the first part of the source electrode and the gate electrode ranges from 3 nm to 200 nm.

[0025] For the above invention content, the present application has the following beneficial effects:

[0026] (1) The field effect transistor of the embodiment of the present application adjusts the pure Schottky source to a combination design of ohmic source and Schottky source, can solve the problem of small on-state current of the Schottky source-drain field effect transistor, improve the current-carrying capacity of the Schottky source-drain field effect transistor, reduce the on-state impedance of the channel region, and thus reduce the on-state loss of the device, while maintaining the normally-off design of the device.

[0027] (2) The field effect transistor of the embodiment of the present application optimizes the distribution of the electric field by controlling the concentration distribution of the semiconductor layer of the first conductive type, so that the electric field is in a rectangular distribution, thereby improving the voltage resistance of the device and reducing the on-state resistance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a vertical cross-sectional view and vertical electric field distribution of a shield gate MOSFET embodiment proposed in the patent application with application number 202310325051.0;

[0029] Figure 2 is a vertical cross-sectional view of one embodiment of a conventional Schottky source-drain MOSFET;

[0030] Figure 3 is a vertical cross-sectional view of a shield gate MOSFET embodiment proposed in the patent application with application number 202310325051.0.

[0031] Figure 4 is a vertical cross-sectional view and vertical doping concentration distribution of one specific embodiment of the MOSFET of the present application.

[0032] Figure 5 is a vertical cross-sectional view, n-type semiconductor layer uniform doping electric field distribution, and n-type semiconductor layer variable doping concentration electric field distribution of one specific embodiment of the MOSFET of the present application.

[0033] Figure 6 is a vertical cross-sectional view and vertical doping concentration distribution of another specific embodiment of the MOSFET of the present application.

[0034] Fig. 7 is a vertical sectional view and a vertical profile of the doping concentration of another embodiment of the MOSFET of the present application.

[0035] Fig. 8 is a vertical sectional view and a vertical profile of the doping concentration of another embodiment of the MOSFET of the present application.

[0036] The technical features corresponding to the reference signs in the figures are:

[0037] 11 drain electrode

[0038] 21 n+ type semiconductor layer

[0039] 31 n- type semiconductor layer

[0040] 31a first doped region

[0041] 31b second doped region

[0042] 31c third doped region

[0043] 41a gate insulating film

[0044] 41b insulating medium layer

[0045] 51a first part of source electrode

[0046] 51b surface layer source electrode

[0047] 51c second part of source electrode

[0048] 61 gate electrode

[0049] 62 shield gate electrode

[0050] 71 source region DETAILED DESCRIPTION

[0051] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the embodiments or prior art descriptions. Obviously, the following drawings are only some of the embodiments of the present application, and the protection scope of the present application is not limited to the embodiments. For those skilled in the art, other drawings can also be obtained from the drawings without creative labor.

[0052] In the following description, specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. However, persons skilled in the art will understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices and methods are omitted so as not to obscure the description of the present application with unnecessary details.

[0053] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0055] In the present application, unless otherwise specified, the orientation words such as "up, down, left, right" and the like are generally directed to the directions shown in the drawings, or the directions of the components themselves in the vertical, perpendicular or gravity aspects; similarly, for the convenience of understanding and description, "inner, outer" refers to the inner and outer relative to the contour of each component itself, but the above orientation words are not used to limit the present application.

[0056] Compared with the conventional Schottky junction MOSFET, the new Schottky junction MOSFET has the following advantages: large on-state current, the on-state current of the conventional Schottky junction MOSFET can only reach the order of milliampere or even lower, and the on-state current of the new Schottky junction MOSFET can reach the order of tens of amperes to hundreds of amperes under the same conditions.

[0057] Fig. 2 is a vertical sectional view of an embodiment of a conventional Schottky source-drain MOSFET. The MOSFET has a drain electrode 11, a substrate (n+ type semiconductor layer) 21, a semiconductor layer of the first conductivity type (n- type semiconductor layer) 31, a gate trench extending into the n- type semiconductor layer 31, a gate electrode 61 in the trench and wrapped by a gate insulating film 41a, a first part of the source electrode 51a forming a Schottky contact with the n- type semiconductor layer 31, and a surface source electrode 51b.

[0058] The conventional Schottky source-drain MOSFET shown in FIG. 2, due to the presence of a Schottky junction formed between the first part of the source electrode 51a and the n-type semiconductor layer 31, when only a forward voltage is applied between the drain electrode 11 and the surface layer source electrode 51b, the Schottky junction is reverse biased to widen the depletion region, so that a complete electron conduction channel cannot be formed between the drain electrode 11 and the surface layer source electrode 51b, and no current passes between the drain and source. Based on this principle, the Schottky junction MOSFET shown in FIG. 2 is a normally-off device; when a positive voltage is applied between the gate electrode 61 and the surface layer source electrode 51b, due to the presence of the Schottky barrier between the first part of the source electrode 51a and the n-type semiconductor layer 31, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode 11 and the surface layer source electrode 51b, at this time even if a positive voltage is applied between the drain electrode 11 and the surface layer source electrode 51b, due to the reverse bias of the Schottky barrier formed between the first part of the source electrode 51a and the n-type semiconductor layer 31, the depletion layer is widened, which inhibits the transport of electron carriers, so that only a small part of the electron carriers pass through the tunneling effect between the drain electrode 11 and the first part of the source electrode 51a to form a current, which results in the poor on-state current-carrying capacity of the conventional Schottky junction MOSFET, which cannot meet the application requirements of current above the safety level.

[0059] Based on the defects of the above-mentioned conventional Schottky junction MOSFET, the applicant and / or associated enterprises of the present application have proposed Chinese invention patent application 202310325051.0, it should be noted that this patent application has not been disclosed before the priority date of the present application, and cannot be used as a prior art document affecting the creativity of the present application.

[0060] The patent application with application number 202310325051.0 proposes a new Schottky junction MOSFET structure, compared with the conventional pn junction MOSFET, this Schottky MOSFET has four advantages: first, the metal Schottky contact has the characteristics of super-shallow junction, which can effectively solve the short channel effect and source-drain punchthrough problem of MOSFET when the device size is greatly reduced, providing the possibility for further reducing the size of MOSFET; second, the high conductivity of metal-semiconductor contact can further reduce the drain-source resistance; third, in the Schottky source-drain MOSFET, there is no parasitic transistor effect, the response speed is faster, and it can be more high-frequency; fourth, there is no need for ion implantation to form n+ or p+ source-drain region, high-temperature annealing is also cancelled, the process is simple, and at the same time, the lattice damage problem caused by ion implantation and annealing is avoided, which helps to obtain high interface quality, thereby obtaining high-quality dielectric layer, and the voltage resistance and reliability will be better.

[0061] A shielding gate MOSFET with large on-state current capability is proposed in patent application No. 202310325051.0. Figure 1 is a vertical cross-sectional view and vertical electric field distribution of a shielding gate MOSFET embodiment proposed in patent application No. 202310325051.0. Figure 3 is a vertical cross-sectional view of a shielding gate MOSFET embodiment proposed in patent application No. 202310325051.0. Specifically, please refer to Figure 3. This MOSFET has: a drain electrode 11 located at the bottom layer of the field effect transistor; an n+ type semiconductor layer 21 located above the drain electrode 11; an n- type semiconductor layer 31 located above the n+ type semiconductor layer 21; a gate trench extending downward from the upper surface of the n- type semiconductor layer 31, further including a shielding gate electrode 62 located at the lower part, a gate electrode 61 located at the upper part, and a gate insulating film 41a wrapped around the outer surface of the gate electrode 61 and the shielding gate electrode 62; a first part source electrode 51a recessed in the n- type semiconductor layer 31 and forming a Schottky contact with the n- type semiconductor layer 31; a second part source electrode 51c located above the source region 71, adjacent to the first part source electrode 51a and the gate trench, and forming an ohmic contact with the source region 71, also located above the insulating dielectric layer 41b and separated from the gate electrode by the insulating dielectric layer 41b, and at the same potential as the shielding gate electrode 62.

[0062] The MOSFET shown in Figure 3 has an optimized source electrode design. The pure first part source electrode 51a in the traditional Schottky source-drain MOSFET is adjusted to a combined design of the second part source electrode 51c and the first part source electrode 51a. When the voltage V GS applied between the gate electrode 61 and the second part source electrode 51c is greater than the threshold voltage V GS（th） , electron carriers will be concentrated in the region adjacent to the gate insulating dielectric layer 41a in the n- type semiconductor layer 31 to form a high concentration electron channel. Since there is no potential barrier between the second part source electrode 51c and the source region 71, when a positive voltage is applied between the drain electrode 11 and the second part source electrode 51c, a complete and high concentration electron channel will be formed between the drain electrode 11 and the second part source electrode 51c, and current will flow between the drain electrode 11 and the second part source electrode 51c; when the voltage V GSWhen =0, the Schottky barrier formed by the first part of the source electrode 51a and the n-type semiconductor layer 31 has a vertical and horizontal depletion effect on the electron carriers. In addition, when there is a work function difference between the material of the gate electrode 61 and the material of the n-type semiconductor layer 31 (i.e., the work function of the material of the gate electrode 61 is greater than the work function of the material of the n-type semiconductor layer 31), the gate electrode 61 also has a horizontal depletion effect on the electron carriers in the n-type semiconductor layer 31. In this way, under the joint action of the first part of the source electrode 51a and the gate electrode 61, the electron carriers in the n-type semiconductor layer 31 between the first part of the source electrode 51a and the gate electrode 61 can be completely depleted, which blocks the electron conduction channel between the drain electrode 11 and the second part of the source electrode 51c. Therefore, the MOSFET shown in FIG. 3 can be a normally-off device, and can be a normally-off device with large on-state current capacity. Compared with FIG. 2, FIG. 3 optimizes the gate electrode 61 into a combination of a lower shield gate electrode 62 and an upper gate electrode 61, which aims to introduce the shield gate electrode 62. When the device is in an off state, the shield gate electrode 62 has a horizontal depletion effect on the carriers in the n-type semiconductor layer 31, so that the off-state leakage of the device can be reduced and the breakdown voltage of the device can be improved.

[0063] In summary, the patent application with application number 202310325051.0 adjusts the pure Schottky source in the Schottky source-drain MOSFET to a combination of ohmic source and Schottky source. In the case of maintaining the normally-off design of the device, the problem of small on-state current of the Schottky source-drain MOSFET can be solved, the current capacity of the Schottky source-drain MOSFET can be improved, the on-state impedance can be reduced, and thus the on-state loss of the device can be reduced.

[0064] Although FIG. 3 has the advantages of low on-state resistance and high withstand voltage compared with the Schottky junction trench gate MOSFET of FIG. 2, it has the problem of uneven electric field distribution. As shown in FIG. 1, two peak electric fields are formed in the mesa region, and the electric field between the two peak electric fields is obviously low. One of the two peak electric fields is formed at the junction of the Schottky metal and the N-type epitaxial layer, and the other is formed at the bottom of the trench. The uneven electric field distribution leads to a decrease in the withstand voltage of the device.

[0065] Therefore, the inventors of the present application continue to improve and propose the present application. By controlling the doping concentration distribution of the n-type semiconductor layer, the distribution of the electric field is optimized, the electric field is rectangularly distributed, the withstand voltage of the device is improved, and the on-state resistance of the device is reduced.

[0066] Fig. 4 is a vertical sectional view and a vertical profile of the doping concentration of a specific embodiment of the MOSFET of the present application, which has: a drain electrode 11 at the bottom layer of the field effect transistor; a substrate base plate (n+ semiconductor layer 21) above the drain electrode 11; a semiconductor layer of the first conductivity type (n- semiconductor layer 31) above the n+ semiconductor layer 21; a source region of the first conductivity type (source region 71) above the n- semiconductor layer 31; a gate trench extending from the source region 71 into the n- semiconductor layer 31, which includes a gate electrode 61 and a shield gate electrode 62; the shield gate electrode 62 and the gate electrode 61 are both in the middle of the gate trench, and the shield gate electrode 62 is below the gate electrode 61; an insulating medium layer 41b above the gate trench and the source region 71; the source electrode includes a first part of the source electrode 51a and a second part of the source electrode 51c, the first part of the source electrode 51a extends inward from the source region 71 into the n- semiconductor layer 31 and the depth of the first part of the source electrode 51a is shallower than the depth of the gate electrode 61, and the first part of the source electrode 51a forms a Schottky contact with the n- semiconductor layer 31; the second part of the source electrode 51c is in contact with the insulating medium layer 41b, the source region 71 and the first part of the source electrode 51a, and the second part of the source electrode 51c forms an ohmic contact with the source region 71.

[0067] In the n- semiconductor layer 31, there are a first doped region 31a, a second doped region 31b and a third doped region 31c, the first doped region 31a is between the source region 71 and the bottom of the gate electrode 61, the second doped region 31b is between the first doped region 31a and the bottom of the shield gate electrode 62, the concentration of the second doped region 31b is higher than that of the first doped region 31a, and the second doped region 31b is either a graded doped region or a uniformly doped region; the third doped region 31c is between the second doped region 31b and the n+ semiconductor layer 21, and the concentration of the third doped region 31c is lower than that of the second doped region 31b.

[0068] The MOSFET field effect transistor in Fig. 4 is further improved on the basis of the structure shown in Fig. 3, specifically, the doping concentration of the n- semiconductor layer 31 is not uniform, and the n- semiconductor layer 31 is sequentially divided into the first doped region 31a, the second doped region 31b and the third doped region 31c from top to bottom, the first doped region 31a and the third doped region 31c are uniformly doped, the doping concentration of the second doped region 31b gradually increases from top to bottom to a certain doping concentration, and then gradually decreases to the doping concentration of the third doped region 31c.

[0069] When a positive voltage V GS is applied between the gate electrode 61 and the second part of the source electrode 51c, electrons will gradually accumulate in the region of the n- semiconductor layer 31 adjacent to the gate insulating film 41a, and when a voltage VGS greater than a threshold voltage V GS（th） In the region of the n-type semiconductor layer 31 adjacent to the gate insulating film 41a, a high concentration electron accumulation channel is formed, because this channel is formed in the n-type semiconductor layer 31, which is equivalent to accumulating electrons to form an accumulation type electron channel, therefore, the MOSFET of the present embodiment is an accumulation channel field effect transistor.

[0070] A positive voltage V GS is applied between the gate electrode 61 and the second part of the source electrode 51c, and the voltage V GS applied by the gate electrode 61 is greater than a threshold voltage V GS（th） , and a forward voltage is applied between the drain electrode 11 and the second part of the source electrode 51c, a high concentration electron accumulation channel is formed in the region of the n-type semiconductor layer 31 adjacent to the gate insulating film 41a, thereby turning on the device, the n-type semiconductor layer 31 of the present embodiment can be divided into a first doped region 31a, a second doped region 31b and a third doped region 31c, having different doping concentrations, the doping concentration of the first doped region 31a and the third doped region 31c is the same as or slightly higher than the doping concentration of the n-type semiconductor layer 31 in Figure 3, the doping concentration of the second doped region 31b is higher than the doping concentration of the n-type semiconductor layer 31 in Figure 3, and the doping concentration increases first and then decreases from top to bottom. Overall, the doping concentration of the n-type semiconductor layer 31 of the present embodiment is higher than the doping concentration of the n-type semiconductor layer 31 in Figure 3, the proportion of the n-type semiconductor layer 31 of the MOSFET field effect transistor in the total on-resistance is higher, so the present embodiment has great advantages in reducing the on-resistance of the device.

[0071] A positive voltage V GSWhen the voltage is zero and a forward voltage is applied between the drain electrode 11 and the second part of the source electrode 51c, the electric field points from the n-type semiconductor layer 31 to the shield gate electrode 62 through the gate insulating film 41a, and the electrons in the n-type semiconductor layer 31 move away from the gate insulating film 41a due to the electric field. The shield gate electrode 62 has a lateral depletion effect on the electron carriers in the n-type semiconductor layer 31, and the first part of the source electrode 51a and the n-type semiconductor layer 31 form a Schottky contact. In the case of reverse voltage, the n-type semiconductor layer 31 has a longitudinal depletion effect on the electron carriers. In summary, when the voltage is applied, the electron carriers are depleted by the lateral and longitudinal depletion effects. The n-type semiconductor 31 in FIG. 5 is a specific embodiment of the MOSFET in FIG. 4, and the n-type semiconductor 31 in FIG. 6 is a specific embodiment of the shield gate MOSFET proposed in the patent with the application number 202310325051.0. By comparison, it can be observed that the electric field distribution of the embodiment of the present application is more uniform, and the area enclosed by the electric field and the X-axis is larger when the electric field reaches the breakdown critical point, that is, the breakdown voltage of the device is larger.

[0072] FIG. 6 is a vertical cross-sectional view and a vertical doping concentration distribution diagram of another specific embodiment of the MOSFET of the present application. Compared with FIG. 4, the difference lies in the second doped region 31b. In this embodiment, the doping concentration of the second doped region 31b first increases to a certain doping concentration from top to bottom, maintains this doping concentration for a distance, and then gradually decreases to the doping concentration of the third doped region 31c. The lowest doping concentration of the second doped region 31b is greater than or equal to the doping concentration of the first doped region 31a and the third doped region 31c.

[0073] FIG. 7 is a vertical cross-sectional view and a vertical doping concentration distribution diagram of another specific embodiment of the MOSFET of the present application. Compared with FIG. 4, the difference lies in the second doped region 31b. In this embodiment, the doping concentration of the second doped region 31b is uniformly distributed, and the doping concentration of the second doped region 31b is greater than the doping concentration of the first doped region 31a and the third doped region 31c.

[0074] The embodiments in FIGS. 6-7 have the same advantages as the embodiment in FIG. 4. By adjusting the doping concentration of the second doped region 31b, the distribution of the electric field is optimized, the electric field is rectangularly distributed, the voltage resistance of the device is improved, and the on-resistance of the device is reduced.

[0075] Fig. 8 is a vertical sectional view and vertical direction doping concentration distribution diagram of a specific embodiment of the MOSFET of the present application, which has: a drain electrode 11 at the bottom layer of the field effect transistor; a substrate substrate (n+ type semiconductor layer 21) above the drain electrode 11; a semiconductor layer of the first conductive type (n- type semiconductor layer 31) above the n+ type semiconductor layer 21; a source region of the first conductive type (source region 71) above the n- type semiconductor layer 31; a gate trench extending from the source region 71 into the n- type semiconductor layer 31, which includes a gate electrode 61 and a shield gate electrode 62; the shield gate electrode 62 is in the middle of the gate trench, the gate electrode 61 is formed on both sides of the upper part of the shield gate electrode 62, and an insulating medium layer 41b is above the gate trench and the source region 71; the source electrode includes a first part source electrode 51a and a second part source electrode 51c, the first part source electrode 51a extends inward from the source region 71 into the n- type semiconductor layer 31 and has a shallower depth than the gate electrode 61, and the first part source electrode 51a forms a Schottky contact with the n- type semiconductor layer 31; the second part source electrode 51c contacts the insulating medium layer 41b, the source region 71 and the first part source electrode 51a, and the second part source electrode 51c forms an ohmic contact with the source region 71.

[0076] The positions of the gate electrode 61 and the shield gate electrode 62 in Fig. 8 are different from those in the embodiment of Fig. 4, and the other structures of the device are the same, have the same advantages as the embodiment of Fig. 4, can optimize the distribution of the electric field, make the electric field present a rectangular distribution, thereby improve the withstand voltage of the device, and reduce the on-resistance of the device.

[0077] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A field effect transistor, characterized by The field effect transistor comprises: a drain electrode located at the bottom layer of the field effect transistor; a substrate substrate located above the drain electrode; a semiconductor layer of a first conductivity type located above the substrate substrate; a source region of the first conductivity type located above the semiconductor layer of the first conductivity type; a gate trench extending from the source region of the first conductivity type into the semiconductor layer of the first conductivity type, the gate trench comprising a gate electrode and a shield gate electrode for generating a lateral depletion effect on the carriers in the semiconductor layer of the first conductivity type when the field effect transistor is in an off state; an insulating dielectric layer disposed on the gate trench and the source region of the first conductivity type; a source electrode, a first part of the source electrode extending inward from the source region of the first conductivity type into the semiconductor layer of the first conductivity type and having a shallower depth than the gate electrode, the first part of the source electrode forming a Schottky contact with the semiconductor layer of the first conductivity type; a second part of the source electrode in contact with the insulating dielectric layer, the source region of the first conductivity type, and the first part of the source electrode, the second part of the source electrode forming an ohmic contact with the source region of the first conductivity type; wherein the semiconductor layer of the first conductivity type has a first doped region, a second doped region, and a third doped region; the first doped region is adjacent to the source region from top to bottom, and the bottom of the first doped region is not higher than the bottom of the gate electrode; the second doped region is adjacent to the first doped region from top to bottom, and the bottom of the second doped region is not lower than the bottom of the shield gate electrode; the third doped region is located between the second doped region and the substrate substrate; the second doped region has a graded doping or a uniform doping, and the doping concentration of the second doped region is higher than the doping concentration of the first doped region and the doping concentration of the third doped region.

2. The field effect transistor of claim 1, wherein: The second doped region is a graded doped region, the doping concentration of the second doped region gradually increases to a certain doping concentration from top to bottom, and then gradually decreases to the doping concentration of the third doped region, and the lowest concentration of the second doped region is higher than the doping concentration of the first doped region and the third doped region.

3. The field effect transistor of claim 1, wherein: The second doped region is uniformly doped, and the doping concentration of the first doped region and the third doped region is less than the doping concentration of the second doped region.

4. The field effect transistor of claim 1, wherein: The first doped region is located between the source region of the first conductivity type and the bottom of the gate electrode.

5. The field effect transistor of claim 1, wherein: The second doped region is located between the first doped region and the bottom of the shield gate electrode.

6. The field effect transistor of claim 1, wherein: The first conductivity type is n-type.

7. The field effect transistor of claim 1, wherein: The shield gate electrode and the gate electrode are both located in the middle of the gate trench, and the shield gate electrode is located below the gate electrode.

8. The field effect transistor of claim 1, wherein: The shield gate electrode is located in the middle of the gate trench, and the gate electrode is located on both sides of the upper part of the shield gate electrode.

9. The field effect transistor of claim 1, wherein: The width of the semiconductor layer of the first conductivity type between the first part of the source electrode and the gate electrode ranges from 3 nm to 200 nm.

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