Bonded wafer polishing method

Abstract

The present invention provides a bonded wafer polishing method, comprising: first, performing a grinding process on a top silicon layer to reduce the thickness of the top silicon layer, the thickness of the top silicon layer after the grinding process being greater than a target thickness of the top silicon layer; on the basis of the thickness distribution of the top silicon layer after the grinding process, obtaining a preset thickness of a carrier; and performing a chemical mechanical polishing process on the top silicon layer by using the carrier having the preset thickness, so that the polishing rate of an area having a larger thickness in the top silicon layer can be greater than the polishing rate of an area having a smaller thickness, thereby increasing the surface flatness of the polished top silicon layer, reducing a surface thickness difference of the top silicon layer, and improving the thickness uniformity of the top silicon layer.

Description

Bonded wafer polishing method TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a bonded wafer polishing method. BACKGROUND

[0002] With the rapid development of integrated circuit technology and the continuous evolution of process nodes, the manufacturing and design costs of integrated circuits have increased significantly, and product yield and production efficiency have begun to decline. Bulk silicon substrate has become an important factor limiting the development of integrated circuits. Therefore, silicon on insulator (SOI) technology is widely used. Compared with bulk silicon substrates, SOI wafers have small parasitic capacitance, small short channel effect, high integration density, high speed, and low power consumption.

[0003] The uneven thickness of the top silicon layer in the SOI wafer can cause unstable device performance, inconsistent current density of local electronic channels, and uneven thermal effects or line width changes. To solve this problem, chemical mechanical polishing (CMP) is one of the main polishing processes in the SOI wafer manufacturing process. It not only further improves the uniformity of the SOI wafer, but also repairs mechanical damage to the surface of the SOI wafer, resulting in a high flatness and low roughness SOI wafer. Currently, when performing chemical mechanical polishing on the top silicon layer in the SOI wafer, the SOI wafer is usually placed in the opening of a carrier, and the top silicon layer is ground using a polishing pad. However, the thickness uniformity of the top silicon layer after the chemical mechanical polishing process is difficult to control, which can cause large thickness differences on the surface of the top silicon layer, thereby affecting the thickness uniformity of the top silicon layer. SUMMARY

[0004] The present application aims to provide a bonded wafer polishing method to improve the thickness uniformity of the top silicon layer after chemical mechanical polishing.

[0005] To achieve the above-mentioned purpose, the present application provides a bonded wafer polishing method, comprising:

[0006] providing a bonded wafer, the bonded wafer comprising a support substrate, an insulating buried layer and a top silicon layer stacked in order from bottom to top;

[0007] performing a grinding process on the top silicon layer to thin the thickness of the top silicon layer, the thickness of the top silicon layer after the grinding process being greater than the target thickness of the top silicon layer;

[0008] obtaining a preset thickness of the carrier according to the thickness distribution of the top silicon layer after the grinding process;

[0009] A carrier with the preset thickness is used to perform a chemical mechanical polishing process on the top silicon layer, so that a polishing rate of a region with a larger thickness in the top silicon layer is greater than a polishing rate of a region with a smaller thickness until the thickness of the top silicon layer is thinned to the target thickness.

[0010] Optionally, the thickness distribution of the top silicon layer is convex, and the preset thickness of the carrier is greater than a sum of the target thickness and the thickness of the support substrate.

[0011] Optionally, a relationship among the preset thickness of the carrier, the thickness of the top silicon layer after the grinding process, the target thickness and the thickness of the support substrate is as follows:

[0012] X+Y-T+2≤C≤X+Y-T+4, wherein X represents the thickness of the support substrate, Y represents the thickness of the top silicon layer after the grinding process, T represents a thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness, and C represents the preset thickness of the carrier.

[0013] Optionally, the thickness distribution of the top silicon layer is concave, and the preset thickness of the carrier is less than or equal to a sum of the target thickness and the thickness of the support substrate.

[0014] Optionally, a relationship among the preset thickness of the carrier, the target thickness and the thickness of the support substrate is as follows:

[0015] X+Y-T-2≤C≤X+Y-T-4, wherein X represents the thickness of the support substrate, Y represents the thickness of the top silicon layer after the grinding process, T represents a thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness, and C represents the preset thickness of the carrier.

[0016] Optionally, the thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness is greater than or equal to 2 μm and less than or equal to 4 μm.

[0017] Optionally, a surface thickness difference of the top silicon layer after the grinding process is less than 0.6 μm.

[0018] Optionally, the carrier has an opening for carrying the bonded wafer, and the bonded wafer is placed in the opening of the carrier when the chemical mechanical polishing process is performed.

[0019] Optionally, before the grinding process is performed on the top silicon layer, the bonded wafer polishing method further comprises: performing a reinforcement heat treatment on the bonded wafer.

[0020] Optionally, the temperature of the reinforcing heat treatment is 900-1250℃, and the gas used in the reinforcing heat treatment includes at least one of oxygen, hydrogen, argon and helium.

[0021] In the method for polishing a bonded wafer provided by the application, a grinding process is performed on the top silicon layer to reduce the thickness of the top silicon layer, and the thickness of the top silicon layer after the grinding process is greater than the target thickness of the top silicon layer; the preset thickness of the carrier is obtained according to the thickness distribution of the top silicon layer after the grinding process, and when the chemical mechanical polishing process is performed on the top silicon layer by using the carrier with the preset thickness, the polishing rate of the area with greater thickness in the top silicon layer is greater than the polishing rate of the area with smaller thickness, thereby increasing the surface flatness of the top silicon layer after polishing, effectively reducing the surface thickness difference of the top silicon layer, and further improving the thickness uniformity of the top silicon layer. BRIEF DESCRIPTION OF DRAWINGS

[0022] Fig. 1 is a flowchart of the method for polishing a bonded wafer provided by an embodiment of the application;

[0023] Figs. 2-4 are schematic diagrams of the structure formed in the method for polishing a bonded wafer provided by an embodiment of the application;

[0024] Fig. 5 is a schematic diagram of the principle when the preset thickness of the carrier is greater than the sum of the target thickness of the top silicon layer and the thickness of the support substrate in the method for polishing a bonded wafer provided by an embodiment of the application;

[0025] Fig. 6 is a schematic diagram of the principle when the preset thickness of the carrier is less than the sum of the target thickness of the top silicon layer and the thickness of the support substrate in the method for polishing a bonded wafer provided by an embodiment of the application;

[0026] Fig. 7 is a schematic diagram of the principle when the preset thickness of the carrier is equal to the sum of the target thickness of the top silicon layer and the thickness of the support substrate in the method for polishing a bonded wafer provided by an embodiment of the application;

[0027] Fig. 8 is a schematic diagram of the relationship between the preset thickness of the carrier and the thickness distribution of the top silicon layer in the process of performing the chemical mechanical polishing process in the method for polishing a bonded wafer provided by an embodiment of the application;

[0028] Fig. 9 is a schematic diagram of the relationship between the surface thickness difference of the top silicon layer before and after the chemical mechanical polishing process in the method for polishing a bonded wafer provided by an embodiment of the application.

[0029] In the drawings, the reference signs are explained as follows: 100-bonded wafer; 110-support substrate; 120-insulating buried layer; 130-top silicon layer; 140-isolation layer; 200-carrier; 210-upper polishing pad; 220-lower polishing pad. DETAILED DESCRIPTION

[0030] The bonding wafer polishing method provided by the present application will be described in further detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0031] Fig. 1 is a flowchart of the bonding wafer polishing method provided by the embodiment of the present application. As shown in Fig. 1, the bonding wafer polishing method provided by the present embodiment comprises:

[0032] Step S1: providing a bonding wafer, wherein the bonding wafer comprises a support substrate, an insulating buried layer and a top silicon layer stacked in sequence from bottom to top.

[0033] Step S2: performing a grinding process on the top silicon layer to thin the thickness of the top silicon layer, wherein the thickness of the top silicon layer (average value of thicknesses of multiple measuring points) after the grinding process is greater than a target thickness of the top silicon layer.

[0034] Step S3: obtaining a preset thickness of the carrier according to the thickness distribution of the top silicon layer after the grinding process.

[0035] Step S4: performing a chemical mechanical polishing process on the top silicon layer by using a carrier with the preset thickness, so as to make the polishing rate of the area with greater thickness in the top silicon layer greater than the polishing rate of the area with smaller thickness, until the thickness of the top silicon layer is thinned to the target thickness.

[0036] Figs. 2-4 are schematic diagrams of structures formed in the bonding wafer polishing method provided by the embodiment of the present application; Fig. 5 is a schematic diagram of the principle when the preset thickness of the carrier is greater than the sum of the target thickness of the top silicon layer and the thickness of the support substrate in the bonding wafer polishing method provided by the embodiment of the present application; Fig. 6 is a schematic diagram of the principle when the preset thickness of the carrier is less than the sum of the target thickness of the top silicon layer and the thickness of the support substrate in the bonding wafer polishing method provided by the embodiment of the present application; Fig. 7 is a schematic diagram of the principle when the preset thickness of the carrier is equal to the sum of the target thickness of the top silicon layer and the thickness of the support substrate in the bonding wafer polishing method provided by the embodiment of the present application; the bonding wafer polishing method provided by the present embodiment will be described in further detail below in combination with Figs. 2-7.

[0037] Referring to Fig. 2, Step S1 is performed to provide a bonding wafer 100, wherein the bonding wafer 100 comprises a support substrate 110, an insulating buried layer 120 and a top silicon layer 130 stacked in sequence from bottom to top, i.e., the bonding wafer 100 is an SOI (Silicon-On-Insulator) wafer.

[0038] The support substrate 110 is isolated from the top silicon layer 130 by the insulating buried layer 120, and the support substrate 110 is bonded to the top silicon layer 130 by a bonding process. The material of the support substrate 110 is the same as that of the top silicon layer 130, i.e., the material of the support substrate 110 is silicon and the material of the top silicon layer 130 is also silicon, and the material of the insulating buried layer 120 is silicon oxide.

[0039] In a further aspect, the back surface of the support substrate 110, i.e., the surface of the support substrate 110 away from the top silicon layer 130, is formed with an isolation layer 140, and the material of the isolation layer 140 is the same as that of the insulating buried layer 120, i.e., the material of the isolation layer 140 can also be silicon oxide.

[0040] In this embodiment, the thickness of the support substrate 110 can be 775 μm to 780 μm, such as 776 μm, 777 μm, or 778 μm.

[0041] Next, an edge chamfering process is performed on the bonded wafer 100 to chamfer the un-bonded area of the top silicon layer 130 to prevent edge chipping.

[0042] Next, a reinforcement heat treatment is performed on the bonded wafer 100 to enhance the strength of the bonding surface between the support substrate 110 and the top silicon layer 130, and to eliminate dislocation defects in the bonded wafer 100. Specifically, the temperature of the reinforcement heat treatment is 900 °C to 1250 °C, and the gas used in the reinforcement heat treatment includes at least one of oxygen, hydrogen, argon, and helium. The time of the reinforcement heat treatment can be 0.5 h to 3 h.

[0043] Next, step S2 is performed, and a grinding process is performed on the top silicon layer 130 to thin the thickness of the top silicon layer 130. The thickness of the top silicon layer 130 after the grinding process is greater than the target thickness of the top silicon layer 130. The thickness difference between the thickness of the top silicon layer 130 after the grinding process and the target thickness can be greater than or equal to 2 μm and less than or equal to 4 μm, which is beneficial to making the thickness of the top silicon layer 130 have better uniformity through a subsequent chemical mechanical polishing process.

[0044] Preferably, the surface thickness difference of the top silicon layer 130 after the grinding process is less than 0.6 μm, i.e., the thickness range of the top silicon layer 130 is less than 0.6 μm. If the surface thickness difference of the top silicon layer 130 after the grinding process is large, for example, greater than 0.6 μm, the subsequent chemical mechanical polishing process will be limited by the removal amount, which will cause the surface thickness difference of the top silicon layer 130 after the chemical mechanical polishing process to be difficult to reach the preset threshold (less than 0.2 μm), thereby affecting the uniformity of the top silicon layer 130. The surface thickness difference of the top silicon layer 130 is the difference between the maximum and minimum values of the thicknesses of a plurality of measurement points (e.g., 49 measurement points) on the surface of the top silicon layer 130.

[0045] In this embodiment, as shown in FIG. 3, the thickness distribution of the top silicon layer 130 after the grinding process is convex, i.e., the thickness of the central region of the top silicon layer 130 is greater than the thickness of the edge region. Alternatively, as shown in FIG. 4, the thickness distribution of the top silicon layer 130 after the grinding process is concave, i.e., the thickness of the central region of the top silicon layer 130 is less than the thickness of the edge region. During the execution of the grinding process, the thickness distribution of the top silicon layer 130 can be adjusted to be convex or concave by adjusting the inclination angle of the grinding and based on the load effect of the grinding process, so as to facilitate subsequent processing.

[0046] Next, as shown in FIG. 5, step S3 is performed to obtain a preset thickness of the carrier 200 according to the thickness distribution of the top silicon layer 130 after the grinding process. The carrier 200 is used to carry the bonded wafer 100 in the subsequent chemical mechanical polishing process.

[0047] In this embodiment, as shown in FIG. 3, the thickness distribution of the top silicon layer 130 is convex, and thus the preset thickness of the carrier 200 is greater than the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110. In this way, in the subsequent chemical mechanical polishing process, the pressure of the central region of the top silicon layer 130 can be greater than the pressure of the edge region, so that the polishing rate of the central region of the top silicon layer 130 can be greater than the polishing rate of the edge region.

[0048] In this embodiment, the thickness distribution of the top silicon layer 130 is convex, and thus the relationship among the preset thickness of the carrier, the target thickness of the top silicon layer 130, and the thickness of the support substrate 110 is as follows:

[0049] X + Y - T + 2 ≤ C ≤ X + Y - T + 4, wherein X represents the thickness of the support substrate, Y represents the thickness of the top silicon layer after the grinding process, T represents the thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness, and C represents the preset thickness of the carrier.

[0050] In another embodiment, as shown in FIG. 4, the thickness distribution of the top silicon layer 130 is concave, and the preset thickness of the carrier is less than or equal to the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110. Thus, in the subsequent chemical mechanical polishing process, the pressure of the edge region of the top silicon layer 130 can be greater than that of the center region, so that the polishing rate of the edge region of the top silicon layer 130 can be greater than that of the center region.

[0051] The surface shape of the top silicon layer 130 is concave, and the relationship among the preset thickness of the carrier 200, the target thickness of the top silicon layer 130 and the thickness of the support substrate 110 is:

[0052] X+Y-T-2≤C≤X+Y-T-4, wherein X represents the thickness of the support substrate 110, Y represents the thickness of the top silicon layer 130 after the polishing process, T represents the thickness difference between the target thickness of the top silicon layer 130 after the polishing process and the thickness of the top silicon layer 130 after the polishing process, and C represents the preset thickness of the carrier.

[0053] In this embodiment, the preset thickness of the carrier is calculated by the thickness distribution of the top silicon layer 130 after the polishing process, the thickness of the top silicon layer 130 after the polishing process, the target thickness of the top silicon layer 130 and the thickness of the support substrate 110, so as to realize the accurate setting of the carrier thickness in the subsequent chemical mechanical polishing process.

[0054] Then, as shown in FIG. 5, step S4 is performed, and the carrier 200 with the preset thickness is used to perform the chemical mechanical polishing process on the top silicon layer 130, so that the polishing rate of the region with greater thickness in the top silicon layer 130 is greater than that of the region with smaller thickness, until the thickness of the top silicon layer 130 is thinned to the target thickness. The polishing removal thickness of the top silicon layer 130 in the chemical mechanical polishing process is the thickness difference between the thickness of the top silicon layer 130 after the polishing process and the target thickness.

[0055] In this embodiment, the chemical mechanical polishing process can be a double-sided polishing process, that is, the top silicon layer 130 on the upper surface of the bonded wafer 100 and the isolation layer 140 on the lower surface can be polished at the same time.

[0056] In this embodiment, the carrier 200 has an opening for carrying the bonded wafer 100, and the shape of the opening is circular. The carrier 200 has at least one opening. An inlay is arranged on the sidewall of each opening of the carrier 200, and the inlay can fix the bonded wafer 100 in the carrier 200 and prevent the bonded wafer 100 from being taken out of the opening of the carrier 200. The carrier 200 is a star wheel.

[0057] As shown in FIG. 5, during the chemical mechanical polishing process, the carrier 200 is located between the lower polishing pad 220 and the upper polishing pad 210, i.e., the carrier 200 is mounted on the lower polishing pad 220, and a plurality of carriers 200 can be mounted on the lower polishing pad 220 to carry a plurality of bonded wafers 100. The bonded wafer 100 is placed in the opening of the carrier 200, and the surface of the top silicon layer 130 of the bonded wafer 100 faces the upper polishing pad 210. The polishing liquid is supplied to the surface of the top silicon layer 130, and the bonded wafer 100 is rotated, so that the polishing of the top silicon layer 130 is realized by the upper polishing pad 210.

[0058] As shown in FIG. 5, the thickness distribution of the top silicon layer 130 is convex (the thickness of the central region of the top silicon layer 130 is greater than the thickness of the edge region), and during the chemical mechanical polishing process, the preset thickness of the carrier 200 is greater than the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110, and when the bonded wafer 100 is placed in the opening of the carrier 200, there is a certain height difference between the surface of the carrier 200 and the top surface of the bonded wafer 100 (or the preset thickness of the carrier 200 has a thickness difference with the thickness of the bonded wafer 100).

[0059] Therefore, the central region of the bonded wafer 100 is closer to the surface of the carrier 200 than the edge region, so that the central region of the top silicon layer 130 is subjected to greater pressure from the upper polishing pad 210 during polishing. That is, the pressure of the central region of the top silicon layer 130 is greater than the pressure of the edge region, so that the polishing rate of the central region of the top silicon layer 130 is greater than the polishing rate of the edge region, that is, the polishing rate of the region with greater thickness in the top silicon layer 130 is greater than the polishing rate of the region with smaller thickness, so that the rate deviation between the polishing rate of the central region and the polishing rate of the edge region eliminates the surface thickness difference of the top silicon layer 130, increases the surface flatness of the top silicon layer 130 after polishing, thereby effectively reducing the surface thickness difference of the top silicon layer 130, and further improving the thickness uniformity of the top silicon layer 130.

[0060] Referring to FIG. 6 and in combination with FIG. 7, the thickness distribution of the top silicon layer 130 is concave (the thickness of the central region of the top silicon layer 130 is less than the thickness of the edge region), and during the chemical mechanical polishing process, the preset thickness of the carrier 200 is less than or equal to the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110, and the upper polishing pad (pad) 220 for polishing the top silicon layer 130 is relatively soft, so that the edge region of the top silicon layer 130 is subjected to greater pressure during polishing, i.e., the pressure of the edge region of the top silicon layer 130 is greater than the pressure of the central region.

[0061] Meanwhile, since the edge region of the top silicon layer 130 is more prone to collect the polishing liquid, the polishing rate of the edge region of the top silicon layer 130 is further increased, thereby making the polishing rate of the edge region of the top silicon layer 130 greater than that of the central region. That is, the polishing rate of the region with greater thickness in the top silicon layer 130 can be made greater than that of the region with smaller thickness, thereby increasing the surface flatness of the top silicon layer 130 after polishing through the rate deviation between the polishing rate of the central region and that of the edge region, effectively reducing the surface thickness difference of the top silicon layer 130, and further improving the thickness uniformity of the top silicon layer 130. The polishing liquid can be a silica polishing liquid.

[0062] In addition, as shown in FIG. 8, the vertical coordinate in FIG. 8 represents the thickness of the top silicon layer 130, 0 on the vertical coordinate represents the reference thickness, and the thickness of the top silicon layer 130 being negative represents that the thickness of the top silicon layer 130 is less than the reference thickness, and the thickness of the top silicon layer 130 being positive represents that the thickness of the top silicon layer 130 is greater than the reference thickness. Curve a in FIG. 8 represents the thickness variation of the top silicon layer 130 at different radius positions after the chemical mechanical polishing process when the top silicon layer has a flat surface before the chemical mechanical polishing process and the preset thickness of the carrier 200 is greater than the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110. It can be known that when the preset thickness of the carrier 200 is greater than the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110, the thickness distribution of the top silicon layer 130 after the chemical mechanical polishing process is concave.

[0063] Curve b in FIG. 8 represents the thickness variation of the top silicon layer 130 at different radius positions after the chemical mechanical polishing process when the top silicon layer has a flat surface before the chemical mechanical polishing process and the preset thickness of the carrier 200 is less than or equal to the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110. It can be known that when the preset thickness of the carrier 200 is less than or equal to the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110, the thickness distribution of the top silicon layer 130 after the chemical mechanical polishing process is convex. Thus, in the embodiment, when the thickness distribution of the top silicon layer 130 is convex, the carrier 200 with the preset thickness greater than the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110 is used to perform the chemical mechanical polishing process, and when the thickness distribution of the top silicon layer 130 is concave, the carrier 200 with the preset thickness less than or equal to the sum of the target thickness of the top silicon layer 130 and the thickness of the support substrate 110 is used to perform the chemical mechanical polishing process, which can increase the surface flatness of the top silicon layer 130 after polishing, thereby effectively reducing the surface thickness difference of the top silicon layer 130.

[0064] Table 1 Parameter table of support substrate thickness, surface thickness difference of top silicon layer before polishing and surface thickness difference of top silicon layer after polishing

[0065] Please refer to Table 1 and in combination with Fig. 9, the support substrate 110 thickness, the surface thickness difference of the top silicon layer 130 before polishing and the surface thickness difference of the top silicon layer 130 after polishing in Table 1 are obtained after measuring based on actual manufacturing process. For example, taking the support substrate thickness of 775 μm, the top silicon layer 130 thickness (i.e. the thickness of the top silicon layer after the grinding process) of 8 μm before polishing and the surface thickness difference of the top silicon layer 130 of 0.5 μm before polishing as an example, in combination with Example 1, Example 2, Example 3 and Example 4 in Table 1, it can be known that the surface thickness difference of the top silicon layer 130 after polishing is less than 0.2 μm, which reduces the surface thickness difference of the top silicon layer 130 and improves the thickness uniformity of the top silicon layer 130.

[0066] In summary, in the wafer bonding polishing method provided by the present application, the grinding process is first performed on the top silicon layer to thin the thickness of the top silicon layer, and the thickness of the top silicon layer after the grinding process is greater than the target thickness of the top silicon layer. According to the thickness distribution of the top silicon layer after the grinding process, the preset thickness of the carrier is obtained. When the chemical mechanical polishing process is performed on the top silicon layer by using the carrier with the preset thickness, the polishing rate of the region with larger thickness in the top silicon layer is greater than the polishing rate of the region with smaller thickness, thereby increasing the surface flatness of the top silicon layer after polishing, effectively reducing the surface thickness difference of the top silicon layer, and further improving the thickness uniformity of the top silicon layer.

[0067] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or modification made by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

[0068] In addition, it should be recognized that although the present application has been disclosed as above with the preferred embodiments, the above embodiments are not intended to limit the present application. For any person skilled in the art, many possible changes and modifications or equivalent embodiments of the above disclosed technical content can be made without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solutions of the present application, are still within the protection scope of the technical solutions of the present application.

Claims

1. A method of polishing a bonded wafer, the method comprising: The application provides a bonding wafer polishing method, which comprises the following steps: providing a bonding wafer, wherein the bonding wafer comprises a support substrate, an insulating buried layer and a top silicon layer which are sequentially stacked from bottom to top; performing a grinding process on the top silicon layer to thin the thickness of the top silicon layer, wherein the thickness of the top silicon layer after the grinding process is greater than a target thickness of the top silicon layer; obtaining a preset thickness of a carrier according to the thickness distribution of the top silicon layer after the grinding process; performing a chemical mechanical polishing process on the top silicon layer by using the carrier with the preset thickness, so that the polishing rate of a region with a greater thickness in the top silicon layer is greater than the polishing rate of a region with a smaller thickness, until the thickness of the top silicon layer is thinned to the target thickness.

2. The bonded wafer polishing method of claim 1, wherein, When the thickness distribution of the top silicon layer is convex, the preset thickness of the carrier is greater than the sum of the target thickness and the thickness of the support substrate.

3. The bonded wafer polishing method of claim 2, wherein, The relationship among the preset thickness of the carrier, the thickness of the top silicon layer after the grinding process, the target thickness and the thickness of the support substrate is as follows: X+Y-T+2≤C≤X+Y-T+4, wherein X represents the thickness of the support substrate, Y represents the thickness of the top silicon layer after the grinding process, T represents the thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness, and C represents the preset thickness of the carrier.

4. The bonded wafer polishing method of claim 1, wherein, When the thickness distribution of the top silicon layer is concave, the preset thickness of the carrier is less than or equal to the sum of the target thickness and the thickness of the support substrate.

5. The bonded wafer polishing method of claim 4, wherein, The relationship among the preset thickness of the carrier, the target thickness and the thickness of the support substrate is as follows: X+Y-T-2≤C≤X+Y-T-4, wherein X represents the thickness of the support substrate, Y represents the thickness of the top silicon layer after the grinding process, T represents the thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness, and C represents the preset thickness of the carrier.

6. The bonded wafer polishing method of claim 1, wherein, The thickness difference between the thickness of the top silicon layer after the grinding process and the target thickness is greater than or equal to 2 μm and less than or equal to 4 μm.

7. The bonded wafer polishing method of claim 1, wherein, The surface thickness difference of the top silicon layer after the grinding process is less than 0.6 μm.

8. The bonded wafer polishing method of claim 1, wherein, The carrier has an opening for carrying the bonding wafer, and the bonding wafer is placed in the opening of the carrier when the chemical mechanical polishing process is performed.

9. The bonded wafer polishing method of claim 1, wherein, Before the grinding process is performed on the top silicon layer, the bonding wafer polishing method further comprises a reinforcing heat treatment on the bonding wafer.

10. The bonded wafer polishing method of claim 9, wherein, The temperature of the reinforcing heat treatment is 900-1250 ℃, and the gas used in the reinforcing heat treatment comprises at least one of oxygen, hydrogen, argon and helium.

Images