Semiconductor integrated circuit device

Abstract

This semiconductor integrated circuit device comprises: an active region (Act1) in which a logic circuit (10) is disposed; a wiring region (WL2) on a back surface side of the active region (Act1) and in which power supply wiring lines (VDD, VSS) are present; and an active region (Act2) in a layer below the wiring region (WL2) and in which an ESD protection circuit (20) is disposed. The power supply wiring line (VDD) is connected to the logic circuit (10) through a via and is connected to the ESD protection circuit (20) through a via. The power supply wiring line (VSS) is connected to the logic circuit (10) through a via and is connected to the ESD protection circuit (20) through a via.

Description

Semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device.

[0002] In a semiconductor integrated circuit device including a semiconductor chip, an ESD (Electro-static Discharge) protection circuit is arranged between a power supply wiring and a ground wiring in order to prevent destruction of a transistor circuit due to ESD stress.

[0003] In Patent Document 1, a technique (chiplet technique) for configuring a semiconductor device by arranging a plurality of semiconductor chips on an interposer is disclosed.

[0004] In Patent Document 2, a technique (Back side contact technique) for providing wiring on the back side of a substrate of an active region where transistors are arranged and connecting the source / drain of the transistors is disclosed in order to achieve high integration of circuits.

[0005] U.S. Patent No. 9,245,852 Specification, U.S. Patent Application Publication No. 2022 / 0037252 Specification

[0006] Due to the miniaturization of semiconductor chips, the risk of device destruction caused by overvoltage (current) due to ESD has increased. In order to avoid this risk, if the discharge capacity of the ESD protection circuit is increased, there is a risk that the area of the circuit and the area of the semiconductor chip on which the circuit is mounted will increase.

[0007] Also, in a chiplet, when a power supply wiring or the like is arranged in an interposer, the discharge path of the ESD current becomes long via microbumps or TSVs (Through Silicon Vias) that connect the semiconductor chip and the interposer. As a result, an increase in wiring resistance may occur, and there is a risk that the discharge capacity of the ESD protection circuit will decrease.

[0008] Furthermore, prior art regarding ESD protection utilizing the back side of the substrate of the active region has not been disclosed.

[0009] The present disclosure realizes an effective ESD protection function in a semiconductor integrated circuit device without increasing the area of the circuit or the semiconductor chip.

[0010] In a first aspect of this disclosure, the semiconductor integrated circuit device comprises a first active region on which logic circuits are arranged, a first power supply wiring located in a wiring region on the back side of the first active region and supplying a first power supply voltage, a second power supply wiring located in the wiring region and supplying a second power supply voltage, and a second active region located below the wiring region on which an ESD (Electro-static Discharge) protection circuit is arranged, wherein the first power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias, and the second power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias.

[0011] According to this embodiment, the semiconductor integrated circuit device comprises a first active region on which logic circuits are arranged, a wiring region located on the back side of the first active region and containing first and second power supply wiring, and a second active region located below the wiring region and on which an ESD protection circuit is arranged. The first power supply wiring is connected to the logic circuits via vias and also connected to the ESD protection circuit via vias. The second power supply wiring is connected to the logic circuits via vias and also connected to the ESD protection circuit via vias. That is, the discharge path for ESD current is formed as a path from the first and second power supply wiring to the ESD protection circuit via vias. As a result, the wiring resistance in the discharge path is suppressed, and the discharge capability of the ESD current is improved. This makes it possible to reduce the area of ​​the ESD protection circuit and the area of ​​the semiconductor chip on which it is mounted. In addition, since the discharge path for ESD current does not pass through the first active region, the risk of element failure in the logic circuits is reduced. This allows for the manufacture of logic circuits using a fine manufacturing process and reduces the need for ESD protection circuits, thereby enabling higher circuit integration and space savings.

[0012] In a second aspect of this disclosure, the semiconductor integrated circuit device comprises a first active region on which logic circuits are arranged, a first power supply wiring located in a wiring region on the back side of the first active region and supplying a first power supply voltage, a second power supply wiring located in the wiring region and supplying a second power supply voltage, and a second active region located above the wiring region and below the first active region, on which an ESD (Electro-static Discharge) protection circuit is arranged, wherein the first power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias, and the second power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias.

[0013] According to this embodiment, the semiconductor integrated circuit device comprises a first active region on which logic circuits are arranged, a wiring region located on the back side of the first active region and containing first and second power supply wiring, and a second active region located above the wiring region and below the first active region, on which an ESD protection circuit is arranged. The first power supply wiring is connected to the logic circuits via vias and also connected to the ESD protection circuit via vias. The second power supply wiring is connected to the logic circuits via vias and also connected to the ESD protection circuit via vias. That is, the discharge path for ESD current is formed as a path from the first and second power supply wiring to the ESD protection circuit via vias. As a result, the wiring resistance in the discharge path is suppressed, and the discharge capability of the ESD current is improved. This makes it possible to reduce the area of ​​the ESD protection circuit and the area of ​​the semiconductor chip on which it is mounted. In addition, since the discharge path for ESD current does not pass through the first active region, the risk of element failure in the logic circuits is reduced. This allows for the manufacture of logic circuits using a fine manufacturing process and reduces the need for ESD protection circuits, thereby enabling higher circuit integration and space savings.

[0014] According to this disclosure, an effective ESD protection function can be realized in a semiconductor integrated circuit device without increasing the area of ​​the circuit or semiconductor chip.

[0015] Cross-sectional diagrams (a) to (c) showing the general structure of a semiconductor chip according to the first embodiment are shown in the cross-sectional diagrams (a) and (b) showing an example of the arrangement of circuit blocks and wiring formed on the semiconductor chip of Figure 1, respectively. The cross-sectional diagram (a) shows an example of the circuit configuration of a circuit block, where (a) is a logic circuit and (b) is an ESD protection circuit. Cross-sectional diagrams showing the general structure of a semiconductor chip according to a modified example of the first embodiment are shown in the cross-sectional diagrams (a) and (b) showing an example of the arrangement of circuit blocks and wiring formed on the semiconductor chip of Figure 5, respectively. The cross-sectional diagram (a) and (b) show an example of the configuration of a semiconductor integrated circuit device according to the second embodiment are shown in the cross-sectional diagrams (a) and (b) showing an example of the arrangement of circuit blocks and wiring formed on the semiconductor integrated circuit device of Figure 8, respectively.

[0016] The embodiments will be described below with reference to the drawings. In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply wiring that supplies that power supply voltage.

[0017] (First Embodiment) Figure 1 is a cross-sectional view showing the schematic structure of a semiconductor chip according to the first embodiment. The semiconductor chip in Figure 1 is an example of a semiconductor integrated circuit device in this disclosure.

[0018] The semiconductor chip shown in Figure 1 comprises an active region Act1 and a wiring region WL1 located above the active region Act1 (front side). The active region Act1 is where elements such as transistors are arranged. The wiring region WL1 includes multiple wiring layers WL1a, WL1b, ... The semiconductor chip shown in Figure 1 also comprises a wiring region WL2 located on the back side of the active region Act1 and an active region Act2 located below the wiring region WL2 (back side). The wiring region WL2 includes multiple wiring layers WL2a, WL2b, ... The active region Act2 is where elements such as transistors are arranged. The transistors arranged are, for example, fin FETs (Field Effect Transistors), nanosheet FETs, and planar FETs.

[0019] Figure 2 is a plan view showing an example of the arrangement of circuit blocks and wiring formed on the semiconductor chip shown in Figure 1. In Figure 2, (a) shows the active region Act1 and wiring layer WL2a, (b) shows wiring layers WL2a and WL2b, and (c) shows wiring layer WL2b and active region Act2. Note that wiring region WL2 includes wiring layers WL2a and WL2b. The wiring of wiring region WL1 is omitted from the illustration.

[0020] Figure 3 is a cross-sectional view showing the cross-sectional structure in the configuration of Figure 2. In Figure 3, (a) is the cross-sectional structure along the line X1-X1' in Figure 2, and (b) is the cross-sectional structure along the line Y1-Y1' in Figure 2.

[0021] As shown in Figures 2 and 3, a logic circuit (labeled "CIR" in the figures) 10 is arranged in the active region Act1 as a circuit block, and an ESD protection circuit (labeled "CLMP" in the figures) 20 is arranged in the active region Act2. Note that the number, position, and size of the logic circuit 10 and ESD protection circuit 20 shown in Figures 2 and 3 are examples only and are not limited to those shown.

[0022] Figure 4 shows an example of a circuit configuration of a circuit block, where (a) is an inverter as an example of a logic circuit, and (b) is a clamp transistor as an example of an ESD protection circuit. The inverter in Figure 4(a) is equipped with a P-type transistor P1 and an N-type transistor N1, with the P-type transistor P1 and the N-type transistor N1 connected in series between node vd1 and node vs1. The clamp transistor in Figure 4(b) is equipped with an N-type transistor N2, with the drain of the N-type transistor N2 connected to node vd2, and the source and gate connected to node vs2. Note that the circuit configurations of the logic circuit and ESD protection circuit are not limited to those shown in Figure 4.

[0023] In the wiring region WL2, a power wiring VDD supplying VDD as the first power supply voltage and a power wiring VSS supplying VSS as the second power supply voltage are formed. In wiring layer WL2a, power wirings VDD and VSS extending in the Y direction are arranged alternately with spacing in the X direction. In wiring layer WL2b, power wirings VDD and VSS extending in the X direction are arranged alternately with spacing in the Y direction. The power wiring VDD in wiring layer WL2a and the power wiring VDD in wiring layer WL2b are connected via via Via2 at a position where they intersect in a plan view. The power wiring VSS in wiring layer WL2a and the power wiring VSS in wiring layer WL2b are connected via via Via2 at a position where they intersect in a plan view.

[0024] The logic circuit 10 in the active region Act1 overlaps with the power supply wirings VDD and VSS in the wiring layer WL2a in a plan view. Node vd1 of the logic circuit 10 is connected to the power supply wiring VDD via via Via1. Node vs1 of the logic circuit 10 is connected to the power supply wiring VSS via via Via1. In the layout structure, for example, the power supply wiring VDD is electrically connected to the underside of the source portion of the P-type transistor P1 via via Via1. Also, the power supply wiring VSS is electrically connected to the underside of the source portion of the N-type transistor N1 via via Via1.

[0025] The ESD protection circuit 20 in the active region Act2 overlaps with the power supply wirings VDD and VSS in the wiring layer WL2b in a plan view. Node vd2 of the ESD protection circuit 20 is connected to the power supply wiring VDD via via Via3. Node vs2 of the ESD protection circuit 20 is connected to the power supply wiring VSS via via Via3. In the layout structure, for example, the power supply wiring VDD is electrically connected to the upper surface of the drain portion of the N-type transistor N2 via via Via3. Also, the power supply wiring VSS is electrically connected to the upper surface of the source portion of the N-type transistor N2 via via Via3.

[0026] According to this embodiment, the ESD current discharge path is formed only on the back side, without passing through the front side. Therefore, compared to a discharge path that passes through the semiconductor chip and interposer in a chiplet, for example, the wiring resistance in the discharge path can be suppressed, thereby improving the ESD current discharge capability. As a result, the area of ​​the ESD protection circuit and the area of ​​the semiconductor chip on which it is mounted can be reduced in a semiconductor integrated circuit device.

[0027] Furthermore, since the risk of element failure due to ESD on the front side is reduced, the front side can be manufactured using a finer manufacturing process than the back side, allowing for a reduction in ESD protection circuits. This enables higher circuit integration and area saving. In addition, by manufacturing the back side using a low-cost manufacturing process, high integration and lower costs can be achieved for the semiconductor integrated circuit device as a whole.

[0028] <Modification> Figure 5 is a cross-sectional view showing the general structure of a semiconductor chip according to a modification of the first embodiment. As shown in Figure 5, in this modification, the relative positions of the active region Act2 and the wiring region WL2 are reversed in the semiconductor chip. That is, in this modification, the active region Act2 is located above the wiring region WL2 and below the active region Act1.

[0029] Figure 6 is a plan view showing an example of the arrangement of circuit blocks and wiring formed on the semiconductor chip shown in Figure 5. Figure 6 shows the active regions Act1 and Act2 and the wiring layer WL2a. The arrangement of power supply wiring VDD and VSS in wiring layers WL2a and WL2b is the same as in Figure 2(b).

[0030] Figure 7 is a cross-sectional view showing the cross-sectional structure in the configuration of Figure 6. In Figure 7, (a) is the cross-sectional structure along the line X1-X1' in Figure 6, and (b) is the cross-sectional structure along the line Y1-Y1' in Figure 6.

[0031] As shown in Figures 6 and 7, the logic circuit 10 is arranged in the active region Act1 as a circuit block, and the ESD protection circuit 20 is arranged in the active region Act2. Note that, as with the embodiments described above, the number, position, and size of the logic circuit 10 and the ESD protection circuit 20 shown in Figures 6 and 7 are examples only and are not limited to those shown.

[0032] The logic circuit 10 in the active region Act1 overlaps with the power supply wirings VDD and VSS in the wiring layer WL2a in a plan view. Node vd1 of the logic circuit 10 is connected to the power supply wiring VDD via via Via1. Node vs1 of the logic circuit 10 is connected to the power supply wiring VSS via via Via1. In the layout structure, for example, the power supply wiring VDD is electrically connected to the lower surface of the source portion of the P-type transistor P1 via via Via1. The power supply wiring VSS is electrically connected to the lower surface of the source portion of the N-type transistor N1 via via Via1. In this modified example, via Via1 is larger in size in the Z direction compared to the embodiment described above.

[0033] The ESD protection circuit 20 in the active region Act2 overlaps with the power supply wirings VDD and VSS in the wiring layer WL2a in a plan view. Node vd2 of the ESD protection circuit 20 is connected to the power supply wiring VDD via via Via4. Node vs2 of the ESD protection circuit 20 is connected to the power supply wiring VSS via via Via4. In the layout structure, for example, the power supply wiring VDD is electrically connected to the underside of the drain portion of the N-type transistor N2 via via Via4. The power supply wiring VSS is electrically connected to the underside of the source portion of the N-type transistor N2 via via Via4.

[0034] According to this modified example, the same effects as those of the above-described embodiment can be obtained. That is, the discharge path for the ESD current is formed only on the back side, without passing through the front side. As a result, the wiring resistance in the discharge path can be suppressed, and the discharge capacity of the ESD current is improved. This makes it possible to reduce the area of ​​the ESD protection circuit and the area of ​​the semiconductor chip on which it is mounted in a semiconductor integrated circuit device.

[0035] Furthermore, since the risk of element failure due to ESD on the front side is reduced, the front side can be manufactured using a finer manufacturing process than the back side, allowing for a reduction in ESD protection circuits. This enables higher circuit integration and area saving. In addition, by manufacturing the back side using a low-cost manufacturing process, high integration and lower costs can be achieved for the semiconductor integrated circuit device as a whole.

[0036] (Second Embodiment) Figure 8 shows an example of the configuration of a semiconductor integrated circuit device according to the second embodiment. The semiconductor integrated circuit device 100 shown in Figure 8 comprises a first semiconductor chip (chip A) 101 and a second semiconductor chip (chip B) 102. The second semiconductor chip 102 is bonded to the back surface of the first semiconductor chip 101 using bumps or the like. In Figure 8, the first semiconductor chip 101 and the second semiconductor chip 102 are depicted as being the same size, but they may be of different sizes.

[0037] In the semiconductor integrated circuit device shown in Figure 8, the general structure of the semiconductor chip in the first embodiment is such that the front side is made up of the first semiconductor chip 101 and the back side is made up of the second semiconductor chip 102. That is, the first semiconductor chip 101 comprises an active region Act1 and a wiring region WL1 located above the active region Act1. The second semiconductor chip 102 comprises a wiring region WL2 and an active region Act2 located below the wiring region WL2.

[0038] The arrangement of circuit blocks and wiring formed in the semiconductor integrated circuit device shown in Figure 8 is the same as in Figure 2. Specifically, a logic circuit 10 is arranged in the active region Act1 of the first semiconductor chip 101 as a circuit block, and an ESD protection circuit 20 is arranged in the active region Act2 of the second semiconductor chip 102. The arrangement and configuration of the power supply wiring VDD and power supply wiring VSS in the wiring region WL2 of the second semiconductor chip 102 is the same as in the first embodiment.

[0039] Figure 9 is a cross-sectional view showing the cross-sectional structure in this modified example. In Figure 9, (a) is the cross-sectional structure along the line X1-X1' in Figure 2, and (b) is the cross-sectional structure along the line Y1-Y1' in Figure 2.

[0040] Similar to the first embodiment, power supply wiring VDD and power supply wiring VSS are formed in the wiring region WL2 of the second semiconductor chip (chip B) 102. In wiring layer WL2a, power supply wirings VDD and VSS extending in the Y direction are arranged alternately with spacing in the X direction. In wiring layer WL2b, power supply wirings VDD and VSS extending in the X direction are arranged alternately with spacing in the Y direction. Power supply wiring VDD in wiring layer WL2a and power supply wiring VDD in wiring layer WL2b are connected via via Via2 at a position where they intersect in a plan view. Power supply wiring VSS in wiring layer WL2a and power supply wiring VSS in wiring layer WL2b are connected via via Via2 at a position where they intersect in a plan view.

[0041] The logic circuit 10 in the active region Act1 of the first semiconductor chip 101 overlaps, in a plan view, with the power supply wirings VDD and VSS in the wiring layer WL2a. Node vd1 of the logic circuit 10 is connected to the power supply wiring VDD via via Via1. Node vs1 of the logic circuit 10 is connected to the power supply wiring VSS via via Via1. In the layout structure, for example, the power supply wiring VDD is electrically connected to the underside of the source portion of the P-type transistor P1 via via Via1. The power supply wiring VSS is electrically connected to the underside of the source portion of the N-type transistor N1 via via Via1.

[0042] The ESD protection circuit 20 located in the active region Act2 of the second semiconductor chip 102 overlaps, in a plan view, with the power supply wirings VDD and VSS located in the wiring layer WL2b. Node vd2 of the ESD protection circuit 20 is connected to the power supply wiring VDD via via Via3. Node vs2 of the ESD protection circuit 20 is connected to the power supply wiring VSS via via Via3. In the layout structure, for example, the power supply wiring VDD is electrically connected to the upper surface of the drain portion of the N-type transistor N2 via via Via3. The power supply wiring VSS is electrically connected to the upper surface of the source portion of the N-type transistor N2 via via Via3.

[0043] According to this embodiment, the ESD current discharge path is formed solely by the second semiconductor chip 102, without passing through the first semiconductor chip 101. Therefore, compared to a discharge path that passes through the semiconductor chip and interposer in a chiplet, for example, the wiring resistance in the discharge path can be suppressed, thereby improving the ESD current discharge capability. As a result, the area of ​​the ESD protection circuit and the area of ​​the semiconductor chip on which it is mounted can be reduced in a semiconductor integrated circuit device.

[0044] Also, in order to reduce the risk of device breakdown due to ESD in the first semiconductor chip 101, the first semiconductor chip 101 can be manufactured using a finer manufacturing process than the second semiconductor chip 102, and the ESD protection circuit can be reduced. As a result, high integration and area reduction of the circuit can be achieved. Further, by manufacturing the second semiconductor chip 102 using a low-cost manufacturing process, high integration and low cost can be realized for the entire semiconductor integrated circuit device.

[0045] <Modification Example> In this modification example, with respect to the second embodiment, the front and back of the second semiconductor chip 102 are reversed and attached to the first semiconductor chip 101. This configuration corresponds to a configuration in which, in the second semiconductor chip 102, the vertical relationship between the active region Act2 and the wiring region WL2 is reversed, and the active region Act2 is located in the upper layer of the wiring region WL2.

[0046] FIG. 10 is a cross-sectional view showing the cross-sectional structure in this modification example. In FIG. 10, (a) is the cross-sectional structure along the line X1-X1' of FIG. 2, and (b) is the cross-sectional structure along the line Y1-Y1' of FIG. 2.

[0047] As shown in FIG. 10, as a circuit block, a logic circuit 10 is arranged in the active region Act1 of the first semiconductor chip 101, and an ESD protection circuit 20 is arranged in the active region Act2 of the second semiconductor chip 102.

[0048] The logic circuit 10 in the active region Act1 of the first semiconductor chip 101 overlaps with the power supply wirings VDD and VSS in the wiring layer WL2a in a plan view. The node vd1 of the logic circuit 10 is connected to the power supply wiring VDD via the via Via1. The node vs1 of the logic circuit 10 is connected to the power supply wiring VSS via the via Via1. In the layout structure, the power supply wiring VDD is electrically connected to the lower surface of the source portion of the P-type transistor P1 via the via Via1. The power supply wiring VSS is electrically connected to the lower surface of the source portion of the N-type transistor N1 via the via Via1. In this modification example, the via Via1 has a larger size in the Z direction than in the above-described embodiment.

[0049] The ESD protection circuit 20 located in the active region Act2 of the second semiconductor chip 102 overlaps, in a plan view, with the power supply wirings VDD and VSS located in the wiring layer WL2a. Node vd2 of the ESD protection circuit 20 is connected to the power supply wiring VDD via via Via4. Node vs2 of the ESD protection circuit 20 is connected to the power supply wiring VSS via via Via4. In the layout structure, the power supply wiring VDD is electrically connected to the underside of the drain portion of the N-type transistor N2 via via Via4. The power supply wiring VSS is electrically connected to the underside of the source portion of the N-type transistor N2 via via Via4.

[0050] According to this modified example, the same effects as those of the above-described embodiment can be obtained. That is, the discharge path for the ESD current is formed only by the second semiconductor chip 102, without passing through the first semiconductor chip 101. As a result, the wiring resistance in the discharge path can be suppressed, and the discharge capacity of the ESD current is improved. This makes it possible to reduce the area of ​​the ESD protection circuit and the area of ​​the semiconductor chip on which it is mounted in a semiconductor integrated circuit device.

[0051] Furthermore, to reduce the risk of device failure due to ESD in the first semiconductor chip 101, the first semiconductor chip 101 can be manufactured using a finer manufacturing process than the second semiconductor chip 102, thereby reducing the ESD protection circuit. This enables higher circuit integration and area reduction. In addition, by manufacturing the second semiconductor chip 102 using a low-cost manufacturing process, the entire semiconductor integrated circuit device can be made highly integrated and cost-effective.

[0052] This disclosure demonstrates how to achieve effective ESD protection in semiconductor integrated circuit devices without increasing the area of ​​circuits or semiconductor chips, and is therefore useful, for example, for improving the performance and reducing the cost of SoCs (System on Chip).

[0053] 10 Logic circuit 20 ESD protection circuit 100 Semiconductor integrated circuit device 101 First semiconductor chip 102 Second semiconductor chip Act1 First active region Act2 Second active region WL2 Wiring region P1, N1, N2 Transistors VDD First power supply voltage, first power supply wiring VSS Second power supply voltage, second power supply wiring Via1, Via2, Via3, Via4 Via

Claims

1. A semiconductor integrated circuit device comprising: a first active region on which logic circuits are arranged; a first power supply wiring located in a wiring region on the back side of the first active region and supplying a first power supply voltage; a second power supply wiring located in the wiring region and supplying a second power supply voltage; and a second active region located in a lower layer of the wiring region and on which an ESD (Electro-static Discharge) protection circuit is arranged, wherein the first power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias; and the second power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias.

2. A semiconductor integrated circuit apparatus according to claim 1, wherein the logic circuit comprises a first transistor of a first conductivity type and a second transistor of a second conductivity type, the ESD protection circuit comprises a third transistor of the second conductivity type, the first power supply wiring is connected via a via to the lower surface of the source portion of the first transistor and via to the upper surface of the drain portion of the third transistor, and the second power supply wiring is connected via a via to the lower surface of the source portion of the second transistor and via to the upper surface of the source portion of the third transistor.

3. A semiconductor integrated circuit apparatus according to claim 1, comprising a first semiconductor chip and a second semiconductor chip bonded to the back side of the first semiconductor chip, wherein the first active region is formed on the first semiconductor chip, and the wiring region and the second active region are formed on the second semiconductor chip.

4. A semiconductor integrated circuit device comprising: a first active region on which logic circuits are arranged; a first power supply wiring located in a wiring region on the back side of the first active region and supplying a first power supply voltage; a second power supply wiring located in the wiring region and supplying a second power supply voltage; and a second active region located above the wiring region and below the first active region, on which an ESD (Electro-static Discharge) protection circuit is arranged, wherein the first power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias; and the second power supply wiring overlaps with the logic circuit in a plan view and is connected to the logic circuit via vias, and overlaps with the ESD protection circuit in a plan view and is connected to the ESD protection circuit via vias.

5. A semiconductor integrated circuit apparatus according to claim 4, wherein the logic circuit comprises a first transistor of a first conductivity type and a second transistor of a second conductivity type, the ESD protection circuit comprises a third transistor of the second conductivity type, the first power supply wiring is connected via a via to the lower surface of the source portion of the first transistor and to the lower surface of the drain portion of the third transistor, and the second power supply wiring is connected via a via to the lower surface of the source portion of the second transistor and to the lower surface of the source portion of the third transistor.

6. A semiconductor integrated circuit apparatus according to claim 4, comprising a first semiconductor chip and a second semiconductor chip bonded to the back side of the first semiconductor chip, wherein the first active region is formed on the first semiconductor chip, and the second active region and the wiring region are formed on the second semiconductor chip.

Images