Semiconductor module

Abstract

This semiconductor module comprises a semiconductor device, a heat dissipation member, and a first bonding material. The semiconductor device includes a semiconductor element and a support substrate. The semiconductor device is mounted on the heat dissipation member. The first bonding material bonds the semiconductor device and the heat dissipation member. The support substrate includes: an insulating layer having a back surface facing the thickness direction; and a back surface metal layer bonded to the back surface. The first bonding material has a first bonding surface to which the semiconductor device is bonded and a second bonding surface to which the heat dissipation member is bonded. The first bonding surface has a first recess recessed in the thickness direction. The back surface metal layer has a portion that is located in the first recess.

Description

Semiconductor module

[0005]

[0001] The present disclosure relates to a semiconductor module.

[0002] Conventionally, semiconductor modules equipped with semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) are widely known. Patent Document 1 discloses an example of a conventional semiconductor module. The semiconductor module described in Patent Document 1 includes a plurality of semiconductor elements, a conductive substrate, a plurality of input terminals, a plurality of output terminals, and a sealing resin. The plurality of semiconductor elements are, for example, MOSFETs and are joined to the conductive substrate. The sealing resin covers the plurality of semiconductor elements. The plurality of input terminals and the plurality of output terminals are electrically connected to any of the plurality of semiconductor elements. The plurality of input terminals and the plurality of output terminals are both power terminals that handle the power supply voltage. The plurality of input terminals and the plurality of output terminals each protrude from any of the plurality of resin side surfaces of the sealing resin. [[ID=​​​​​​​One objective of this disclosure is to provide a semiconductor module that has been improved from conventional modules. In particular, in view of the above circumstances, one objective of this disclosure is to provide a semiconductor module that improves the bonding strength between the semiconductor device and the heat dissipation member.

[0006] A semiconductor module provided by a first aspect of this disclosure comprises a semiconductor device including a semiconductor element and a support substrate for supporting the semiconductor element; a heat dissipation member on which the semiconductor device is mounted; and a first bonding material for bonding the semiconductor device and the heat dissipation member, wherein the support substrate has an insulating layer having a back surface facing one side in the thickness direction of the semiconductor element and a back metal layer bonded to the back surface; the first bonding material has a first bonding surface to which the semiconductor device is bonded and a second bonding surface to which the heat dissipation member is bonded; the first bonding surface has a first recess that is recessed in the thickness direction; and a portion of the back metal layer is located inside the first recess.

[0007] Other features and advantages of this disclosure will become more apparent from the detailed description below, based on the accompanying drawings.

[0008] Figure 1 is a perspective view showing a semiconductor module according to the first embodiment. Figure 2 is a plan view showing a semiconductor module according to the first embodiment. Figure 3 is a view of the plan view of Figure 2, with the sealing member indicated by dashed lines. Figure 4 is a partially enlarged plan view of a part of Figure 3. Figure 5 is a partially enlarged plan view of a part of Figure 4. Figure 6 is a front view showing a semiconductor module according to the first embodiment. Figure 7 is a bottom view showing a semiconductor module according to the first embodiment. Figure 8 is a view of the bottom view of Figure 7, with the heat dissipation member indicated by dashed lines. Figure 9 is a left side view showing a semiconductor module according to the first embodiment. Figure 10 is a right side view showing a semiconductor module according to the first embodiment. Figure 11 is a cross-sectional view along the line XI-XI in Figure 3. Figure 12 is a partially enlarged cross-sectional view of a part of Figure 11. Figure 13 is a cross-sectional view along the line XIII-XIII in Figure 3. Figure 14 is a cross-sectional view along the line XIV-XIV in Figure 3. Figure 15 is a cross-sectional view along the line XV-XV in Figure 3. Figure 16 is a cross-sectional view along the line XVI-XVI in Figure 3. Figure 17 is a cross-sectional view along the line XVII-XVII in Figure 3. Figure 18 is a cross-sectional view along the line XVIII-XVIII in Figure 3. Figure 19 is a cross-sectional view along the line XIX-XIX in Figure 3. Figure 20 is a cross-sectional view along the line XX-XX in Figure 3. Figure 21 is a cross-sectional view along the line XXI-XXI in Figure 4. Figure 22 is a partially enlarged cross-sectional view, an enlarged portion of Figure 21. Figure 23 is a cross-sectional view along the line XIII-XXIII in Figure 4. Figure 24 is a partially enlarged cross-sectional view, an enlarged portion of Figure 23. Figure 25 is a front view showing a power conversion unit equipped with a semiconductor module according to the first embodiment. Figure 26 is a cross-sectional view of the power conversion unit shown in Figure 25, corresponding to the cross-section in Figure 11. Figure 27 is a cross-sectional view of the power conversion unit shown in Figure 25, corresponding to the cross-section in Figure 16. Figure 28 is a cross-sectional view of the power conversion unit shown in Figure 25, corresponding to the cross-section in Figure 17. Figure 29 is an enlarged cross-sectional view of the main part of the power conversion unit shown in Figure 25. Figure 30 is a schematic diagram of a vehicle equipped with a power conversion unit comprising a semiconductor module according to the first embodiment. Figure 31 is an enlarged cross-sectional view of the main part showing a semiconductor module according to a first modification of the first embodiment, corresponding to the cross-section in Figure 22.Figure 32 is an enlarged cross-sectional view of a main part showing a semiconductor module according to a second modification of the first embodiment, corresponding to the cross-section in Figure 22. Figure 33 is an enlarged cross-sectional view of a main part showing a semiconductor module according to a third modification of the first embodiment, corresponding to the cross-section in Figure 21. Figure 34 is a cross-sectional view showing a semiconductor module according to a fourth modification of the first embodiment, corresponding to the cross-section in Figure 11. Figure 35 is a cross-sectional view showing a semiconductor module according to a fifth modification of the first embodiment, corresponding to the cross-section in Figure 11. Figure 36 is a perspective view showing a semiconductor module according to the second embodiment. Figure 37 is a front view showing a semiconductor module according to the second embodiment. Figure 38 is a bottom view showing a semiconductor module according to the second embodiment. Figure 39 is a cross-sectional view showing a semiconductor module according to the second embodiment, corresponding to the cross-section in Figure 11. Figure 40 is a perspective view showing a semiconductor module according to the third embodiment. Figure 41 is a perspective view showing a semiconductor module according to a first modification of the third embodiment. Figure 42 is a perspective view showing a semiconductor module according to a second modification of the third embodiment. Figure 43 is a perspective view showing a semiconductor module according to a third modification of the third embodiment. Figure 44 is a perspective view showing a semiconductor module according to a fourth modification of the third embodiment.

[0009] [Detailed Description] Preferred embodiments of the semiconductor modules of this disclosure are described below with reference to the drawings. Hereafter, identical or similar components are denoted by the same reference numerals, and redundant descriptions are omitted. The terms "first," "second," "third," etc., in this disclosure are used merely as labels and are not necessarily intended to assign a sequence to the objects.

[0010] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is in contact with object B and located on object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, "object A overlaps with object B when viewed in a certain direction" includes, unless otherwise specified, "object A overlaps with all of object B" and "object A overlaps with a part of object B." Also, "object A (or its material) contains material C" includes "object A (or its material) consists of material C" and "the main component of object A (or its material) is material C." Furthermore, "a surface A faces a certain direction B (one side or the other side)" is not limited to cases where the angle of surface A with respect to direction B is 90°, but also includes cases where surface A is inclined with respect to direction B. Furthermore, "a surface A is perpendicular to surface B" is not limited to cases where the angle of surface A with respect to surface B is 90°, but also includes cases where surface A is inclined with respect to surface B. Furthermore, unless otherwise specified, the phrase "object A (surface A) is parallel to object B (surface B)" is not limited to strictly parallel objects, but includes cases where object A (surface A) is tilted relative to object B (surface B) (for example, a slight deviation due to manufacturing tolerances).

[0011] First Embodiment: Figures 1 to 24 show a semiconductor module A10 according to the first embodiment. The semiconductor module A10 comprises a plurality of semiconductor devices B10, a heat dissipation member C10, a plurality of positioning pins D1, a sealing member 50, and a plurality of bonding materials 80. In the illustrated example, the semiconductor module A10 comprises three semiconductor devices B10, six bonding materials 80, and two positioning pins D1, but the number of semiconductor devices B10, bonding materials 80, and positioning pins D1 is not limited thereto. For example, the semiconductor module A10 may have fewer than three (one or two) semiconductor devices B10, or more than three (four or more) semiconductor devices B10. The semiconductor module A10 is used, for example, in an inverter for driving a three-phase AC motor, but the applications of the semiconductor module A10 are not limited thereto.

[0012] For the sake of explanation, we will refer to the mutually orthogonal thickness direction z, the first direction x, and the second direction y. The thickness direction z corresponds to the thickness direction of the semiconductor module A10. Also, "plan view" refers to the view as seen in the thickness direction z. The first direction x is orthogonal to the thickness direction z. The second direction y is orthogonal to both the thickness direction z and the first direction x. One side of the first direction x is called the x1 side of the first direction x, and the other side of the first direction x is called the x2 side of the first direction x. Similarly, one side of the second direction y is called the y1 side of the second direction y, and the other side of the second direction y is called the y2 side of the second direction y. Also, one side of the thickness direction z is called the z1 side of the thickness direction z, and the other side of the thickness direction z is called the z2 side of the thickness direction z. Furthermore, the z1 side of the thickness direction z is sometimes called the upper side, and the z2 side of the thickness direction z is sometimes called the lower side. Note that terms such as "up," "down," "upper," "downward," "upper surface," and "lower surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define a relationship with the direction of gravity.

[0013] Each of the three semiconductor devices B10 is joined to a heat dissipation member C10. In a plan view, the heat dissipation member C10 has a rectangular shape with the first direction x as its longitudinal direction. The plan view shape of the heat dissipation member C10 is not limited to the illustrated example. The three semiconductor devices B10 are arranged on the heat dissipation member C10 along the first direction x. Detailed configuration examples of each semiconductor device B10 will be described later.

[0014] Each of the three semiconductor devices B10 comprises a plurality of semiconductor elements (a plurality of semiconductor elements 21, 22, described later). The plurality of semiconductor elements are, for example, switching elements such as MOSFETs and IGBTs, and each of the three semiconductor devices B10 constitutes, for example, a half-bridge type switching circuit. In addition, each of the three semiconductor devices B10 comprises a power terminal 15, a power terminal 16, a power terminal 17, and a plurality of signal terminals 19, as shown in Figures 1 to 9. In each of the three semiconductor devices B10, the plurality of semiconductor elements are covered by a sealing member 50. A portion of the power terminal 15, a portion of the power terminal 16, a portion of the power terminal 17, and a portion of the plurality of signal terminals 19 are exposed from the sealing member 50.

[0015] The heat dissipation member C10 supports the three semiconductor devices B10. The heat dissipation member C10 is, for example, a heat sink. The majority of the heat dissipation member C10 is located below the three semiconductor devices B10 in the thickness direction z (on the z1 side). The heat dissipation member C10 faces the lower surface (the surface facing the z1 side in the thickness direction z) of each of the three semiconductor devices B10. The material of the heat dissipation member C10 includes, for example, aluminum. The material is not limited to aluminum, but may be other metal materials or resin materials (preferably those with good thermal conductivity). The heat dissipation member C10 includes a base portion 71 and a heat dissipation portion 75.

[0016] The base portion 71 is a plate material. Three semiconductor devices B10 are each mounted on the base portion 71. Each of the three semiconductor devices B10 is joined to the base portion 71 via a bonding material 80. The three semiconductor devices B10 are arranged on the base portion 71 along a first direction x. The base portion 71 faces the lower surface of each of the three semiconductor devices B10. The base portion 71 is in contact with each semiconductor device B10. The base portion 71 is, for example, rectangular in plan view, but the plan view shape of the base portion 71 is not limited in any way.

[0017] The base portion 71 has a mounting surface 71a and a back surface 71b. As shown in Figures 5, 7, and 8, the mounting surface 71a and the back surface 71b are separated in the thickness direction z. The mounting surface 71a and the back surface 71b face opposite each other in the thickness direction z. The mounting surface 71a faces upward in the thickness direction z, and the back surface 71b faces downward in the thickness direction z. The three semiconductor devices B10 are joined to the mounting surface 71a. At least the area of ​​the mounting surface 71a to which each semiconductor device B10 is joined is plated with metal. The plating is, for example, silver plating. However, the plating is not required.

[0018] As shown in Figures 2, 3, 7, and 14, the base portion 71 has a plurality of through holes 713. Each of the multiple through holes 713 penetrates the base portion 71 in the thickness direction z. Each of the multiple through holes 713 extends from the mounting surface 71a to the back surface 71b in the thickness direction z. In the illustrated example, the plan view shape of each of the multiple through holes 713 is circular, but it may also be elliptical, rectangular, polygonal, etc. Each of the multiple through holes 713 can be used as a mounting hole when attaching the semiconductor module A10 to the housing (frame, etc.) of electronic equipment and electric vehicles.

[0019] The heat dissipation section 75 protrudes downward in the thickness direction z from the back surface 71b of the base section 71. With respect to the base section 71, the heat dissipation section 75 is located on the opposite side from each semiconductor device B10 in the thickness direction z.

[0020] The heat dissipation section 75 includes a plurality of heat dissipation fins 751. The plurality of heat dissipation fins 751 are in contact with the back surface 71b. The plurality of heat dissipation fins 751 extend downward in the thickness direction z from the back surface 71b. In the semiconductor module A10, each end face 751a of the plurality of heat dissipation fins 751 is exposed to the outside of the heat dissipation member C10. The end face 751a of each heat dissipation fin 751 is the surface facing downward in the thickness direction z, and is the surface of the heat dissipation fin 751 opposite to the side connected to the base 71. In this embodiment, the plurality of heat dissipation fins 751 are plate-shaped (for example, flat or corrugated) metal bodies. The plurality of heat dissipation fins 751 (heat dissipation section 75) are integrally formed with the base 71. In the example shown in Figure 7, the plurality of heat dissipation fins 751 are arranged in three regions downward in the thickness direction z of the three semiconductor devices B10. Unlike this example, each of the heat dissipation fins 751 may extend so as to overlap the three semiconductor devices B10 in a plan view. In the illustrated example, each of the heat dissipation fins 751 is a strip extending in the second direction y in a plan view. In this example, the heat dissipation fins 751 may be spaced apart from each other in the first direction x and arranged parallel to the first direction x. Unlike the illustrated example, each of the heat dissipation fins 751 may be a strip extending in the first direction x in a plan view. In this example, the heat dissipation fins 751 may be arranged parallel to each other in the second direction y. Also, the heat dissipation fins 751 may be rod-shaped metal bodies (pin fins). In this example, each heat dissipation fin 751 may be circular, elliptical, polygonal (triangle, rectangle, rhombus, hexagon, etc.), Y-shaped, or X-shaped in a plan view.

[0021] The six bonding materials 80 bond three semiconductor devices B10 to the heat dissipation member C10. In the illustrated example, two bonding materials 80 are provided for each semiconductor device B10. The six bonding materials 80 are sandwiched between the corresponding semiconductor devices B10 (support substrates 10A, 10B described later) and the heat dissipation member C10 (base portion 71). Therefore, the bonding materials 80 are in contact with the base portion 71 (mounting surface 71a). The sides of the six bonding materials 80 are covered by a sealing member 50. The thickness (dimension z in the thickness direction) of each bonding material 80 is not limited, but is for example 50 μm or more and 200 μm or less. Each bonding material 80 is, for example, an insert metal used in solid-phase diffusion bonding. Each bonding material 80 includes a metal base layer 80a, a bonding layer 80b, and a bonding layer 80c, as shown in Figures 22 and 24.

[0022] The metal substrate 80a occupies most of the volume of the corresponding bonding material 80. The thickness (dimension z in the thickness direction) of the metal substrate 80a is, for example, 50 μm or more and 200 μm or less. The metal substrate 80a includes, for example, at least one of aluminum (Al), titanium (Ti), zinc (Zn), hafnium (Hf), and erbium (Er). However, the constituent material of the metal substrate 80a is not limited in any way.

[0023] The bonding layer 80b is interposed between the metal substrate layer 80a and the semiconductor device B10 (support substrate 10A or support substrate 10B described later). The bonding layer 80b includes, for example, at least one of silver (Ag), copper (Cu), and gold (Au). However, the constituent materials of the bonding layer 80b are not limited in any way. The bonding layer 80b is bonded to the semiconductor device B10 (support substrate 10A or support substrate 10B described later) by solid-phase diffusion of the metal. In the case of bonding by solid-phase diffusion, there may be no interface between the bonding layer 80b and each semiconductor device B10 (support substrate 10A or support substrate 10B described later).

[0024] The bonding layer 80c is interposed between the metal substrate layer 80a and the heat dissipation member C10 (base portion 71). The bonding layer 80c includes, for example, at least one of silver (Ag), copper (Cu), and gold (Au). However, the constituent material of the bonding layer 80c is not limited in any way. The bonding layer 80c is bonded to the heat dissipation member C10 (base portion 71) by solid-phase diffusion of the metal. In the case of bonding by solid-phase diffusion, there may be no interface between the bonding layer 80c and the base portion 71 (more specifically, the metal plating applied to the mounting surface 71a).

[0025] The sealing member 50 is electrically insulating. The sealing member 50 includes, for example, a black epoxy resin. The sealing member 50 can be formed, for example, by molding. The sealing member 50 is formed on the base 71 of the heat dissipation member C10. The sealing member 50 covers a portion of each of the plurality of semiconductor devices B10. For example, the sealing member 50 covers a plurality of semiconductor elements (a plurality of semiconductor elements 21, 22 described later) of each semiconductor device B10. As shown in Figures 1, 2, 6, 9, and 10, the sealing member 50 includes three sealing portions 501 and a plurality of columnar portions 502.

[0026] The three sealing portions 501 correspond individually to each of the three semiconductor devices B10. One sealing portion 501 is provided for each of the multiple semiconductor devices B10. The three sealing portions 501 cover multiple semiconductor elements (multiple semiconductor elements 21, 22 described later) of the corresponding semiconductor device B10.

[0027] As shown in Figures 2, 6, and 11, the sealing portion 501 includes a top surface 51, a bottom surface 52, and a plurality of side surfaces 531 to 534. The top surface 51, bottom surface 52, and the plurality of side surfaces 531 to 534 described below are common to each sealing portion 501 unless otherwise specified.

[0028] The top surface 51 and the bottom surface 52 are separated in the thickness direction z. The top surface 51 and the bottom surface 52 face opposite each other in the thickness direction z. The top surface 51 faces upward in the thickness direction z (towards z1 in the thickness direction z), and the bottom surface 52 faces downward in the thickness direction z (towards z2 in the thickness direction z). In this embodiment, the end face of the power terminal 15 (cylindrical portion 156 described later) on the thickness direction z, the end face of the power terminal 16 (cylindrical portion 166 described later) on the thickness direction z, and the end face of the power terminal 17 (cylindrical portion 176 described later) on the thickness direction z are exposed on the top surface 51. Each of the multiple signal terminals 19 protrudes upward in the thickness direction z from the top surface 51. As can be seen from Figure 8, the lower surface of the bonding material 80 is exposed from the bottom surface 52. The bottom surface 52 is in contact with the base portion 71 (mounting surface 71a) together with each bonding material 80. The bottom surface 52 is a rectangular ring surrounding the joining material 80 in a plan view.

[0029] Multiple sides 531 to 534 are connected to the top surface 51 and the bottom surface 52, respectively. As shown in Figure 2, a pair of sides 531 and 532 are separated in the first direction x. The pair of sides 531 and 532 face opposite sides with respect to the first direction x. Side 531 faces the x1 side of the first direction x, and side 532 faces the x2 side of the first direction x. The pair of sides 531 and 532 each extend in the second direction y. As shown in Figure 2, a pair of sides 533 and 534 are separated in the second direction y. The pair of sides 533 and 534 face opposite sides with respect to the second direction y. Side 533 faces the y1 side of the second direction y, and side 534 faces the y2 side of the second direction y. The pair of sides 533 and 534 each extend in the first direction x.

[0030] Multiple columnar portions 502 are located at the four corners of each of the three sealing portions 501. As shown in Figure 2 and other figures, two sealing portions 501 adjacent to each other in the second direction y are connected by multiple columnar portions 502 sandwiched between them. Each columnar portion 502 is cylindrical and has a circular shape in plan view. The top of each columnar portion 502 (a part above the thickness direction z) protrudes from the sealing portion 501 (top surface 51). Note that the shape of each columnar portion 502 is not limited to the illustrated example. Each of the multiple columnar portions 502 has a recess formed therein that is recessed in the thickness direction z from the top surface above the thickness direction z.

[0031] In semiconductor module A10, the three sealing portions 501 are integrally formed (as a single sealing member 50) by a plurality of columnar portions 502. Unlike this example, the three sealing portions 501 may be spaced apart from each other. In other words, semiconductor module A10 may have separate sealing members 50 for each of the three semiconductor devices B10.

[0032] In the semiconductor module A10, as shown in Figure 1 and other figures, protrusions are appropriately formed on the top surface 51. The protrusions extend upward in the thickness direction z from the top surface 51. By providing these protrusions, the creepage distance (the distance along the surface of the sealing member 50) between the three power terminals 15, 16, and 17 exposed from the top surface 51 and the multiple signal terminals 19 can be increased.

[0033] As shown in Figures 1, 6, 9, and 10, the positioning pin D1 protrudes upward in the thickness direction z from the sealing member 50. In the illustrated example, the positioning pin D1 is attached separately to the sealing member 50. Unlike this example, the positioning pin D1 may be integrally formed with the sealing member 50. As shown in Figure 14, the positioning pin D1 is fitted into a recess provided in one of the plurality of columnar portions 502. A portion of the positioning pin D1 protrudes upward in the thickness direction z from the top surface (end face upward in the thickness direction z) of the corresponding columnar portion 502.

[0034] Next, a detailed configuration example of each semiconductor device B10 will be described. As shown in Figures 1 to 24, each of the multiple semiconductor devices B10 comprises two support substrates 10A and 10B, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, a conductive member 32, a conductive substrate 33, a conductor 37, a conductor 38, multiple connecting members 401, 402, 41 to 44, and two signal substrates 601 and 602. In the following description, unless otherwise specified, the two support substrates 10A and 10B, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, a conductive member 32, a conductive substrate 33, a conductor 37, a conductor 38, multiple connecting members 401, 402, 41 to 44, and two signal substrates 601 and 602 are common to each semiconductor device B10. Multiple signal terminals 19 include multiple signal terminals 191, 192, 193, 194, and 199.

[0035] Each semiconductor device B10 converts the DC power supply voltage applied to power terminals 15 and 16 into AC voltage using multiple semiconductor elements 21 and 22. The converted AC voltage is input to a power supply target such as a motor through power terminal 17.

[0036] Support substrate 10A supports multiple semiconductor elements 21. Support substrate 10B supports multiple semiconductor elements 22. The two support substrates 10A and 10B are each covered with a sealing member 50. The two support substrates 10A and 10B are each, for example, AMB (Active Metal Brazing) substrates. In contrast to this example, the two support substrates 10A and 10B may each be DCB (Direct Copper Bonding) substrates. Each support substrate 10A and 10B includes an insulating layer 11, a main surface metal layer 12, and a back surface metal layer 13.

[0037] As shown in Figures 21 to 24, the insulating layer 11 is interposed between the main surface metal layer 12 and the back surface metal layer 13 in the thickness direction z. The insulating layer 11 supports multiple semiconductor elements 21 and multiple semiconductor elements 22 via the main surface metal layer 12. The insulating layer 11 contains a material with relatively high thermal conductivity. The insulating layer 11 is made of, for example, ceramics (for example, aluminum nitride (AlN)). In addition to ceramics, the insulating layer 11 may also contain an insulating resin sheet. The thickness of the insulating layer 11 (dimension in the thickness direction z) is not limited, but is for example 150 μm or more and 500 μm or less.

[0038] The insulating layer 11 has a main surface 11a and a back surface 11b. As shown in Figures 21 to 24, the main surface 11a and the back surface 11b are separated in the thickness direction z. The main surface 11a and the back surface 11b face opposite each other in the thickness direction z. The main surface 11a faces upward in the thickness direction z, and the back surface 11b faces downward in the thickness direction z. The main surface 11a of the insulating layer 11 of the support substrate 10A faces the plurality of semiconductor elements 21, and the back surface 11b of the insulating layer 11 of the support substrate 10B faces the plurality of semiconductor elements 22.

[0039] As shown in Figures 21 to 24, the main surface metal layer 12 is located above the insulating layer 11 in the thickness direction z. The main surface metal layer 12 is in contact with and bonded to the main surface 11a. The composition of the main surface metal layer 12 includes copper (Cu), but other metals may also be used. In a plan view, the main surface metal layer 12 is surrounded by the periphery of the insulating layer 11. The thickness of the main surface metal layer 12 (dimension in the thickness direction z) is not limited, but for example, it is 300 μm or more and 1000 μm or less. In this embodiment, the main surface metal layer 12 of the support substrate 10A includes conductor portion 121 and conductor portion 123, and the main surface metal layer 12 of the support substrate 10B includes conductor portion 122. These three conductor portions 121 to 123 are spaced apart from each other.

[0040] Conductor portion 121 and conductor portion 122 are separated in the first direction x. Conductor portion 121 and conductor portion 122 are aligned in the first direction x. Conductor portion 123 is located on the y1 side of the second direction y with respect to a part of conductor portion 121. The thickness z dimension of conductor portion 121, the thickness z dimension of conductor portion 122, and the thickness z dimension of conductor portion 123 are the same as each other.

[0041] As shown in Figures 4 and 5, the conductor portion 121 is located on the x1 side of the first direction x relative to the conductor portion 122. The conductor portion 121 is located on the power terminal 15 side of the conductor portion 122 with respect to the first direction x. The plan view shape of the conductor portion 121 is not limited, but in the illustrated example it is L-shaped. Multiple semiconductor elements 21, a signal substrate 601, and power terminals 15 are bonded to the conductor portion 121. A conductive substrate 33 is also bonded to the conductor portion 121.

[0042] As shown in Figures 4 and 5, the conductor portion 122 is located on the x2 side of the first direction x relative to the conductor portion 121. The conductor portion 122 is located on the power terminal 17 side of the conductor portion 121 with respect to the first direction x. The plan view shape of the conductor portion 122 is not limited, but in the illustrated example it is rectangular. Multiple semiconductor elements 22, a signal substrate 602, and a power terminal 17 are bonded to the conductor portion 123.

[0043] As shown in Figure 4 and other figures, the conductor portion 123 is located on the x1 side in the first direction x with respect to a part of the conductor portion 121 (the part to which the signal board 601 and the multiple semiconductor elements 21 are joined), and on the y1 side in the second direction y with respect to the other part of the conductor portion 121 (the part to which the power terminal 15 is joined). With respect to the first direction x, the conductor portion 123 is located on the power terminal 16 side of the part of the conductor portion 121 (the part to which the signal board 601 and the multiple semiconductor elements 21 are joined). The power terminal 16 is joined to the conductor portion 123. In addition, one end of the conductive member 32 is joined to the conductor portion 123.

[0044] As shown in FIGS. 21 to 24 and the like, the back metal layer 13 is located below (on the z1 side) the insulating layer 11 in the thickness direction z. The back metal layer 13 is in contact with the back surface 11b and is joined to the back surface 11b. The composition of the back metal layer 13 includes copper (Cu), similar to the front metal layer 12, but other metals may also be used. Different from this example, the composition of the back metal layer 13 may be different from that of the front metal layer 12. In the illustrated example, the back metal layer 13 is rectangular in plan view. The back metal layer 13 is surrounded by the periphery of the insulating layer 11 in plan view. The thickness (dimension in the thickness direction z) of the back metal layer 13 is not limited in any way, but for example, it is 300 μm or more and 1000 μm or less.

[0045] The front metal layer 12 and the back metal layer 13 are metal bodies individually joined to both surfaces of the insulating layer 11 in the thickness direction z. In the front metal layer 12 of the support substrate 10A, the metal body is divided into a conductor part 121 and a conductor part 123 by patterning. That is, the conductor part 121, the conductor part 122, and the conductor part 123 are patterns of the metal body formed on the front surface 11a of the insulating layer 11. In an example where each of the support substrates 10A and 10B is an AMB substrate, the front metal layer 12 and the back metal layer 13 are joined by an active metal bonding method. Different from this example, in an example where each of the support substrates 10A and 10B is a DCB substrate, the front metal layer 12 and the back metal layer 13 are joined to the insulating layer 11 by a direct bonding method.

[0046] The conductors 37 and 38 are, for example, plate-like members made of metal. This metal includes, for example, copper, but is not limited to copper. As shown in FIGS. 4 and 5 and the like, the conductors 37 and 38 are each rectangular in plan view. Note that the plan view shapes of the conductors 37 and 38 are not limited to rectangles. The conductor 37 and the conductor 38 are separated in the first direction x. The conductor 37 and the conductor 38 overlap each other when viewed in the first direction x. The thickness (dimension in the thickness direction z) of the conductor 37 and the thickness (dimension in the thickness direction z) of the conductor 38 are not limited in any way, but for example, they are 1500 μm or more and 2000 μm or less.

[0047] The conductor 37 is joined to the conductor part 121. A plurality of semiconductor elements 21 are joined to the conductor 37. The conductor 37 is interposed between the conductor part 121 and the plurality of semiconductor elements 21 in the thickness direction z. The conductor part 121 and the plurality of semiconductor elements 21 (the back electrode 211 described later) are electrically connected via the conductor 37. The conductor 37 includes, for example, a base layer and bonding layers disposed on both surfaces in the thickness direction z of the base layer (the surface facing the plurality of semiconductor elements 21 and the surface facing the conductor part 121). For example, the base layer contains copper, and the bonding layer contains silver. In this example, the conductor 37 has metal plating on both surfaces in the thickness direction z of a plate-like member made of copper. The metal plating is, for example, silver plating.

[0048] The conductor 38 is joined to the conductor part 122. A plurality of semiconductor elements 22 are joined to the conductor 38. The conductor 38 is interposed between the conductor part 122 and the plurality of semiconductor elements 22 in the thickness direction z. The conductor part 122 and the plurality of semiconductor elements 22 (the back electrode 221 described later) are electrically connected via the conductor 38. The conductor 38 includes, for example, a base layer and bonding layers disposed on both surfaces in the thickness direction z of the base layer (the surface facing the plurality of semiconductor elements 22 and the surface facing the conductor part 122). For example, the base layer contains copper, and the bonding layer contains silver. In this example, the conductor 38 has metal plating on both surfaces in the thickness direction z of a plate-like member made of copper. The metal plating is, for example, silver plating.

[0049] Each semiconductor device B10 further comprises bonding material 379 and bonding material 389. Bonding material 379 and bonding material 389 are, for example, insert metals used for solid-phase diffusion. In addition, bonding material 379 and bonding material 389 may each contain solder or contain a sintered body of metal particles. As shown in Figure 21, the conductor 37 is bonded to the conductor portion 121 by bonding material 379. Bonding material 379 is interposed between the conductor 37 and the conductor portion 121, allowing them to conduct electricity. As shown in Figure 23, the conductor 38 is bonded to the conductor portion 122 by bonding material 389. Bonding material 389 is interposed between the conductor 38 and the conductor portion 122, allowing them to conduct electricity. The thickness of bonding material 379 (dimension in the thickness direction z) and bonding material 389 (dimension in the thickness direction z) are not limited in any way, but for example, they are 50 μm or more and 200 μm or less.

[0050] Each of the multiple semiconductor elements 21 and 22 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Alternatively, each of the multiple semiconductor elements 21 and 22 may be other transistors such as IGBTs (Insulated Gate Bipolar Transistors) and bipolar transistors, or diodes. In this embodiment, each of the multiple semiconductor elements 21 and 22 is an n-channel type MOSFET with a vertical structure.

[0051] Each of the multiple semiconductor elements 21 and 22 includes a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon (Si), a wide-bandgap semiconductor with a wider bandgap than Si, or an ultra-wide-bandgap semiconductor with an even wider bandgap than a wide-bandgap semiconductor. Wide-bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Ultra-wide-bandgap semiconductors include, but are not limited to, gallium oxide (Ga2O3), diamond, and aluminum nitride (AlN). In this embodiment, the composition of each compound semiconductor substrate of the multiple semiconductor elements 21 and 22 includes SiC. Note that the types and compositions of the multiple semiconductor elements 21 and 22 are not limited to being the same, but may be different.

[0052] Multiple semiconductor elements 21 are mounted on a conductor 37, as shown in Figures 4, 5, 11, 12, 17, and 21. The multiple semiconductor elements 21 are arranged along the second direction y. In the illustrated example, each semiconductor device B10 has three semiconductor elements 21, but the number of semiconductor elements 21 is not limited to three and can be appropriately changed according to the specifications of the semiconductor module A10 (each semiconductor device B10).

[0053] As shown in Figures 12 and 21, each of the multiple semiconductor elements 21 has an element main surface 21a and an element back surface 21b. The element main surface 21a and the element back surface 21b are separated in the thickness direction z. The element main surface 21a and the element back surface 21b face opposite each other in the thickness direction z. The element main surface 21a faces upward in the thickness direction z, and the element back surface 21b faces downward in the thickness direction z. The element main surface 21a faces the same direction as the main surface 11a in the thickness direction z. The element back surface 21b faces the support substrate 10A and the conductor 37.

[0054] Each of the multiple semiconductor elements 21 has a back electrode 211, a main electrode 212, and a main electrode 213. The back electrode 211, main electrode 212, and main electrode 213 described below are common to each semiconductor element 21 unless otherwise specified.

[0055] As shown in Figures 12 and 21, the back electrode 211 is located on the back surface 21b of the element and is exposed on the back surface 21b. As shown in Figures 12 and 21, the main surface electrodes 212 and 213 are located on the main surface 21a of the element and are exposed on the main surface 21a. In the illustrated example, the main surface electrode 212 includes a power pad 2121 and two signal pads 2122. The two signal pads 2122 are each located on one side of the power pad 2121 in the second direction y. The two signal pads 2122 are spaced apart in the second direction y. The planar area of ​​the power pad 2121 is larger than the planar area of ​​each of the two signal pads 2122. The planar area of ​​the main surface electrode 213 is smaller than the planar area of ​​the power pad 2121 of the main surface electrode 212. The main surface electrode 213 is sandwiched between the two signal pads 2122 in the second direction y. Unlike the illustrated example, the power pad 2121 of the main surface electrode 212 may be divided into two or more regions. Also, the main surface electrode 212 may include only one of the two signal pads 2122, or it may not include either of the two signal pads 2122. As shown in Figure 5, the main surface electrode 213 and the two signal pads 2122 are located on the same side as the signal substrate 601 with respect to the power pad 2121 in the first direction x.

[0056] Each semiconductor element 21 switches between an ON state and an OFF state in response to a first drive signal input to the main surface electrode 213. The alternating switching between the ON and OFF states of each semiconductor element 21 is called switching operation. In the ON state, the back surface electrode 211 and the main surface electrode 212 (especially the power pad 2121) are conductive, and in the OFF state, the back surface electrode 211 and the main surface electrode 212 (especially the power pad 2121) are not conductive. In each semiconductor element 21, current flows from the back surface electrode 211 to the main surface electrode 212 (especially the power pad 2121) in response to the first drive signal input to the main surface electrode 213. In the main surface electrode 212, the two signal pads 2122 are each short-circuited to the power pad 2121 inside each semiconductor element 21. In this example, the potentials of the two signal pads 2122 are equal to the potential of the power pad 2121. In the example where each semiconductor element 21 is a MOSFET, the back electrode 211 is the drain electrode, the main surface electrode 212 is the source electrode, and the main surface electrode 213 is the gate electrode. Here, in the main surface electrode 212, the power pad 2121 is the source pad, and each signal pad 2122 is a source sense pad.

[0057] Each semiconductor device B10 further comprises a plurality of bonding materials 219. As shown in Figure 21, each of the plurality of semiconductor elements 21 is bonded to the conductor 37 by a corresponding one of the plurality of bonding materials 219. Each of the plurality of bonding materials 219 is interposed between the back electrode 211 of the corresponding semiconductor element 21 and the conductor 37, allowing them to conduct electricity. Each bonding material 219 is, for example, an insert metal used for solid-phase diffusion. In addition, each bonding material 219 may contain solder or a sintered body of metal particles. The thickness (dimension z in the thickness direction) of each bonding material 219 is not limited in any way, but for example it is 50 μm or more and 200 μm or less.

[0058] Multiple semiconductor elements 22 are mounted on a conductor 38, as shown in Figures 4, 5, 11, 12, 18, and 23. The multiple semiconductor elements 22 are arranged along the second direction y. In the illustrated example, each semiconductor device B10 has three semiconductor elements 22, but the number of semiconductor elements 22 is not limited to three and can be appropriately changed according to the specifications of the semiconductor module A10 (each semiconductor device B10).

[0059] As shown in Figures 12 and 23, each of the multiple semiconductor elements 22 has an element main surface 22a and an element back surface 22b. The element main surface 22a and the element back surface 22b are separated in the thickness direction z. The element main surface 22a and the element back surface 22b face opposite each other in the thickness direction z. The element main surface 22a faces upward in the thickness direction z, and the element back surface 22b faces downward in the thickness direction z. The element main surface 22a faces the same direction as the main surface 11a in the thickness direction z. The element back surface 22b faces the support substrate 10B and the conductor 38.

[0060] Each of the multiple semiconductor elements 22 has a back electrode 221, a main electrode 222, and a main electrode 223. The back electrode 211, main electrode 222, and main electrode 223 described below are common to each semiconductor element 22 unless otherwise specified.

[0061] As shown in Figures 12 and 23, the back electrode 221 is located on the back surface 22b of the element and is exposed on the back surface 22b. As shown in Figures 12 and 23, the main surface electrodes 222 and 223 are located on the main surface 22a of the element and are exposed on the main surface 22a. In the illustrated example, the main surface electrode 222 includes a power pad 2221 and two signal pads 2222. The two signal pads 2222 are each located on one side of the power pad 2221 in a first direction x. The two signal pads 2222 are separated in a second direction y. The planar area of ​​the power pad 2221 is larger than the planar area of ​​each of the two signal pads 2222. The planar area of ​​the main surface electrode 223 is smaller than the planar area of ​​the power pad 2221 of the main surface electrode 222. The main surface electrode 223 is sandwiched between the two signal pads 2222 in the second direction y. Unlike the illustrated example, the power pad 2221 of the main surface electrode 222 may be divided into two or more regions. Also, the main surface electrode 222 may include only one of the two signal pads 2222, or it may not include either of the two signal pads 2222. As shown in Figure 6, the main surface electrode 223 and the two signal pads 2222 are located on the same side as the signal substrate 602 with respect to the power pad 2221 in the first direction x.

[0062] Each semiconductor element 22 switches between an on state and an off state in response to a second drive signal input to the main surface electrode 223. The alternating on and off state of each semiconductor element 22 is called switching operation. In the on state, the back surface electrode 221 and the main surface electrode 222 (especially the power pad 2221) are conductive, and in the off state, the back surface electrode 221 and the main surface electrode 222 (especially the power pad 2221) are non-conductive. In each semiconductor element 22, current flows from the back surface electrode 221 to the main surface electrode 222 (especially the power pad 2221) in response to the second drive signal input to the main surface electrode 223. In the main surface electrode 212, the two signal pads 2222 are each short-circuited to the power pad 2221 inside each semiconductor element 22. In this example, the potentials of the two signal pads 2222 are equal to the potential of the power pad 2121. In the example where each semiconductor element 22 is a MOSFET, the back electrode 221 is the drain electrode, the main electrode 222 is the source electrode, and the main electrode 223 is the gate electrode. Here, in the main electrode 222, the power pad 2221 is the source pad, and each signal pad 2222 is a source sense pad.

[0063] Each semiconductor device B10 further comprises a plurality of bonding materials 229. As shown in Figure 23, each of the plurality of semiconductor elements 22 is bonded to the conductor 38 by a corresponding one of the plurality of bonding materials 229. Each of the plurality of bonding materials 229 is interposed between the back electrode 221 of the corresponding semiconductor element 22 and the conductor 38, allowing them to conduct electricity. Each bonding material 229 is, for example, an insert metal used for solid-phase diffusion. In addition, each bonding material 229 may contain solder or a sintered body of metal particles. The thickness (dimension z in the thickness direction) of each bonding material 229 is not limited in any way, but for example it is 10 μm or more and 100 μm or less.

[0064] In semiconductor module A10, the back electrodes 211 (drain electrodes) of each semiconductor element 21 are electrically connected, and the power pads 2121 of each main electrode 212 (source electrode) are electrically connected. In other words, the multiple semiconductor elements 21 are electrically connected in parallel with each other. In multiple semiconductor elements 22, the back electrodes 221 (drain electrodes) of each semiconductor element 22 are electrically connected, and the power pads 2221 of each main electrode 222 (source electrode) are electrically connected. In other words, the multiple semiconductor elements 22 are electrically connected in parallel with each other. Furthermore, in semiconductor module A10, the power pads 2121 of each main electrode 212 (source electrode) of each semiconductor element 21 and the back electrodes 221 (drain electrodes) of each semiconductor element 22 are electrically connected. In other words, the multiple semiconductor elements 21 and the multiple semiconductor elements 22 are electrically connected in series. Semiconductor module A10 configures a half-bridge circuit with the multiple semiconductor elements 21 as an upper arm circuit and the multiple semiconductor elements 22 as a lower arm circuit.

[0065] Each of the power terminals 15, 16, and 17 conducts to one of the semiconductor elements 21 and 22. Each of the power terminals 15, 16, and 17 carries a current corresponding to the power before conversion or the power after conversion by the switching operations of the semiconductor elements 21 and 22. Each of the power terminals 15, 16, and 17 contains copper, but is not limited to copper; they may also contain gold, silver, or aluminum. The shapes of the power terminals 15, 16, and 17 are not limited to the illustrated examples and can be appropriately modified according to the specifications of each semiconductor device B10.

[0066] The power terminal 15 is joined to the conductor portion 121. The power terminal 15 is supported by the conductor portion 121. The power terminal 15 conducts electrical connections to the back surface electrodes 211 (drain electrodes of the upper arm circuit) of each of the multiple semiconductor elements 21 via the conductor portion 121. The power terminal 15 is the P terminal (positive terminal) to which the DC power supply voltage to be converted is applied. As shown in Figure 4, the power terminal 15 is located on the opposite side of the multiple semiconductor elements 22, with respect to the first direction x, with the multiple semiconductor elements 21 in between.

[0067] As shown in Figures 4 and 15, the power terminal 15 includes a plate portion 155 and a cylindrical portion 156. In the illustrated example, the plate portion 155 and the cylindrical portion 156 are integrally formed, but they may be separate. The plate portion 155 is joined to the conductor portion 121. This joining is not limited in any way and may be done using a conductive joining material, laser welding, crimping, or solid-phase diffusion bonding. The cylindrical portion 156 is located on the plate portion 155. In a plan view, the periphery of the cylindrical portion 156 is located inward from the periphery of the plate portion 155 in a plan view. In the illustrated example, the top surface of the cylindrical portion 156 (the surface facing upward in the thickness direction z) is exposed from the sealing member 50 (corresponding sealing portion 501). In the illustrated example, the cylindrical portion 156 has a through hole that penetrates in the thickness direction z. This through hole is exposed from the sealing member 50 (corresponding sealing portion 501). Unlike this example, the cylindrical portion 156 may have a recess formed in the thickness direction z from the top surface as described above.

[0068] The power terminal 16 is joined to the conductor portion 123. The power terminal 16 is supported by the conductor portion 123. The power terminal 16 is electrically connected to the main surface electrodes 222 (source electrodes of the lower arm circuit) of each of the multiple semiconductor elements 22 via the conductor portion 123, the conductive member 32, the conductive substrate 33, and the multiple connecting members 402. The power terminal 16 is the N terminal (negative terminal) to which the DC power supply voltage to be converted is applied. As shown in Figure 4, the power terminal 16 is located on the opposite side of the multiple semiconductor elements 22, with respect to the first direction x, with the multiple semiconductor elements 21 in between.

[0069] As shown in Figures 4 and 15, the power terminal 16 includes a plate portion 165 and a cylindrical portion 166. In the illustrated example, the plate portion 165 and the cylindrical portion 166 are integrally formed, but they may be separate. The plate portion 165 is joined to the conductor portion 123. This joining is not limited in any way and may be done using a conductive joining material, laser welding, crimping, or solid-phase diffusion bonding. The cylindrical portion 166 is located on the plate portion 165. In a plan view, the periphery of the cylindrical portion 166 is located inward from the periphery of the plate portion 165 in a plan view. In the illustrated example, the top surface of the cylindrical portion 166 (the surface facing upward in the thickness direction z) is exposed from the sealing member 50 (corresponding sealing portion 501). In the illustrated example, the cylindrical portion 166 has a through hole that penetrates in the thickness direction z. This through hole is exposed from the sealing member 50 (corresponding sealing portion 501). Unlike this example, the cylindrical portion 166 may have a recess formed in the thickness direction z from the top surface as described above.

[0070] The power terminal 17 is joined to the conductor portion 122. The power terminal 17 is supported by the conductor portion 122. The power terminal 17 is electrically connected to the back electrodes 221 (drain electrodes of the lower arm circuit) of the plurality of semiconductor elements 22 via the conductor portion 122, and is also electrically connected to the main surface electrodes 222 (source electrodes of the upper arm circuit) of the plurality of semiconductor elements 22 via the conductor portion 122 and the plurality of connecting members 401. AC power converted by the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 is output from the power terminal 17. In other words, the power terminal 17 is the output terminal of the AC power. As shown in Figure 4, the power terminal 17 is located on the opposite side of the plurality of semiconductor elements 21 from the plurality of semiconductor elements 22 in the first direction x.

[0071] As shown in Figures 4 and 20, the power terminal 17 includes a plate portion 175 and a cylindrical portion 176. In the illustrated example, the plate portion 175 and the cylindrical portion 176 are integrally formed, but they may be separate. The plate portion 175 is joined to the conductor portion 122. This joining is not limited to any particular method, and may be done using a conductive joining material, laser welding, crimping, or solid-phase diffusion bonding. The cylindrical portion 176 is located on the plate portion 175. In a plan view, the periphery of the cylindrical portion 176 is located inward from the periphery of the plate portion 175 in a plan view. In the illustrated example, the top surface of the cylindrical portion 176 (the surface facing upward in the thickness direction z) is exposed from the sealing member 50 (corresponding sealing portion 501). In the illustrated example, the cylindrical portion 176 has a through hole that penetrates in the thickness direction z. This through hole is exposed from the sealing member 50 (corresponding sealing portion 501). Unlike this example, the cylindrical portion 176 may have a recess formed therein that extends in the thickness direction z from the top surface as described above.

[0072] The pair of signal boards 601 and 602 constitute a part of the conductive path between the plurality of signal terminals 19 and the plurality of semiconductor elements 21 and 22. As shown in Figure 5 and other figures, the signal board 601 is located on the x1 side of the first direction x relative to the plurality of semiconductor elements 21. The signal board 601 is bonded to the conductor 37, as shown in Figure 5 and other figures. The signal board 601 may also be bonded to the conductor portion 121. As shown in Figure 5 and other figures, the signal board 602 is located on the x2 side of the first direction x relative to the plurality of semiconductor elements 22. The signal board 602 is bonded to the conductor 38, as shown in Figure 5 and other figures. The signal board 602 may also be bonded to the conductor portion 122. The pair of signal boards 601 and 602 are, for example, DCB boards or AMB boards. Unlike this example, the pair of signal boards 601 and 602 may each be printed circuit boards.

[0073] Each of the pair of signal boards 601 and 602 has an insulating layer 61, a wiring layer 62, a metal layer 63, and a plurality of sleeves 64. Each of the pair of signal boards 601 and 602 is covered by a sealing member 50, except for a portion of each of the plurality of sleeves 64. The insulating layer 61, wiring layer 62, metal layer 63, and plurality of sleeves 64 described below are common to each of the pair of signal boards 601 and 602 unless otherwise specified.

[0074] The insulating layer 61 is interposed between the wiring layer 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 may be made of, for example, ceramics. In addition to ceramics, the insulating layer 61 may be made of an insulating resin sheet.

[0075] As shown in Figure 12 and other figures, the wiring layer 62 is located above the insulating layer 61 in the thickness direction z. The composition of the wiring layer 62 is not limited in any way, but it may contain copper. As shown in Figure 5, the wiring layer 62 includes a plurality of wiring sections 621, 622, and 629. The plurality of wiring sections 621, 622, and 629 are spaced apart from each other. The planar shape, arrangement, and size of each wiring section 621, 622, and 629 are not limited to the illustrated examples.

[0076] As shown in Figure 12 and other figures, the metal layer 63 is located on the opposite side of the wiring layer 62 with respect to the thickness direction z, with the insulating layer 61 in between. The composition of the metal layer 63 is not limited in any way, but may contain copper. The metal layer 63 of the signal substrate 601 is bonded to the conductor 37 by an adhesive layer (not shown). The metal layer 63 of the signal substrate 602 is bonded to the conductor 38 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. These adhesive layers are, for example, solder.

[0077] As shown in Figures 11, 12, 16, and 19, each of the plurality of sleeves 64 is joined to the wiring layer 62 by a conductive bonding layer (e.g., solder) not shown. The plurality of sleeves 64 are made of a conductive material such as metal. Each of the plurality of sleeves 64 is cylindrical and extends along the thickness direction z. One end of the plurality of sleeves 64 in the thickness direction z (the edge on the z1 side in the thickness direction z) is conductively bonded to the wiring layer 62. As shown in Figures 11, 12, 16, and 19, the other end of the plurality of sleeves 64 in the thickness direction z (the edge on the z2 side in the thickness direction z) is exposed from the sealing member 50.

[0078] Each of the multiple signal terminals 19 (multiple signal terminals 191-194, 199) is composed of a metal pin and extends in the thickness direction z. The multiple signal terminals 19 protrude from the sealing member 50 (top surface 51, described later). The multiple signal terminals 19 (multiple signal terminals 191-194, 199) are individually press-fitted into multiple sleeves 64 of a pair of signal substrates 601, 602. As a result, each of the multiple signal terminals 19 is supported by one of the multiple sleeves 64 and is electrically connected to one of the wiring layers 62 of the pair of signal substrates 601, 602. Each of the multiple signal terminals 191-194 is electrically connected to one of the multiple semiconductor elements 21 and multiple semiconductor elements 22. Each of the multiple signal terminals 199 is not electrically connected to any of the multiple semiconductor elements 21 and multiple semiconductor elements 22 (it is non-conductive).

[0079] As shown in Figure 5, the signal terminal 191 is press-fitted into a sleeve 64 joined to the wiring portion 621 of the signal board 601. This supports the signal terminal 191 in the sleeve 64 and provides electrical connectivity to the wiring portion 621 of the signal board 601. The signal terminal 191 provides electrical connectivity to each main surface electrode 213 of the multiple semiconductor elements 21. A first drive signal (a gate voltage) is input to the signal terminal 191 to drive each semiconductor element 21.

[0080] As shown in Figure 5, the signal terminal 192 is press-fitted into a sleeve 64 joined to the wiring portion 621 of the signal board 602. This supports the signal terminal 192 in the sleeve 64 and provides electrical connectivity to the wiring portion 621 of the signal board 602. The signal terminal 192 provides electrical connectivity to the main surface electrodes 223 of the multiple semiconductor elements 22. A second drive signal (a gate voltage) is input to the signal terminal 192 to drive each semiconductor element 22.

[0081] As shown in Figure 5, signal terminal 193 is located next to signal terminal 191 in the second direction y. As shown in Figure 5, signal terminal 193 is press-fitted into a sleeve 64 joined to the wiring portion 622 of the signal board 601. As a result, signal terminal 193 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal board 601. Signal terminal 193 is electrically connected to one of the two signal pads 2122 of the main surface electrodes 212 of the plurality of semiconductor elements 21. A voltage corresponding to the maximum current flowing through each of the main surface electrodes 212 of the plurality of semiconductor elements 21 is applied to signal terminal 193.

[0082] As shown in Figure 5, signal terminal 194 is located next to signal terminal 192 in the second direction y. As shown in Figure 5, signal terminal 194 is press-fitted into a sleeve 64 joined to the wiring portion 622 of the signal board 602. As a result, signal terminal 194 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal board 602. Signal terminal 194 is electrically connected to one of the two signal pads 2222 of the main surface electrodes 222 of the plurality of semiconductor elements 22. A voltage corresponding to the maximum current flowing through each of the main surface electrodes 222 of the plurality of semiconductor elements 22 is applied to signal terminal 194.

[0083] As shown in Figure 5, each of the multiple signal terminals 199 is located on the opposite side of signal terminal 191 with signal terminal 193 in between, or on the opposite side of signal terminal 192 with signal terminal 194 in between, with respect to the second direction y. As shown in Figure 5, each of the multiple signal terminals 199 is joined to one of the multiple wiring sections 629 of the signal board 601 or one of the multiple wiring sections 629 of the signal board 602 and individually press-fitted into the sleeve 64. As a result, each of the multiple signal terminals 199 is supported by the corresponding sleeve 64 and is electrically connected to the wiring section 629 of either the signal board 601 or the signal board 602.

[0084] The conductive substrate 33 constitutes part of the conductive path between the power terminal 16 and the plurality of semiconductor elements 22. As shown in Figure 5 and other figures, the conductive substrate 33 is located between the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 in the first direction x. The conductive substrate 33 is bonded to the conductor 37 together with the plurality of semiconductor elements 21. In plan view, the conductive substrate 33 is, for example, rectangular with the second direction y as the longitudinal direction, but the plan view shape of the conductive substrate 33 is not limited in any way. The conductive substrate 33 is, for example, a DCB substrate or an AMB substrate. Unlike this example, the conductive substrate 33 may be a printed circuit board. The conductive substrate 33 includes an insulating layer 331, a conductive layer 332, and a conductive layer 333.

[0085] The insulating layer 331 is interposed between the two conductive layers 332 and 333 in the thickness direction z. The insulating layer 331 is made of, for example, ceramics (for example, AlN). In addition to ceramics, the insulating layer 331 may also include an insulating resin sheet.

[0086] The conductive layer 332 is located above the insulating layer 331 in the thickness direction z. The conductive layer 332 is bonded to the upper surface (the surface facing upward in the thickness direction z) of the insulating layer 331. The composition of the conductive layer 332 includes Cu, but other metals may also be used. In a plan view, the conductive layer 332 is surrounded by the periphery of the insulating layer 331.

[0087] The conductive layer 333 is located below the insulating layer 331 in the thickness direction z. The conductive layer 333 is bonded to the lower surface (the surface facing downward in the thickness direction z) of the conductive layer 332. The composition of the conductive layer 333 includes Cu, but other metals may also be used. In a plan view, the conductive layer 333 is surrounded by the periphery of the insulating layer 331.

[0088] As shown in Figures 4 and 13, the conductive member 32 is bonded to the conductor portion 123 of the support substrate 10A and the conductive layer 332 of the conductive substrate 33. The conductor portion 123 is electrically connected to the conductive layer 332 via the conductive member 32. The composition of the conductive member 32 may include copper. The conductive member 32 is a metal clip. As shown in Figures 4 and 13, the conductive member 32 has a main body portion 321, a joint portion 322, and a joint portion 323.

[0089] The main body portion 321 constitutes the main part of the conductive member 32. As shown in Figures 4 and 13, the main body portion 321 extends in the first direction x. As shown in Figures 4 and 13, in a plan view, the main body portion 321 intersects between the conductor portion 121 and the conductor portion 123. The main body portion 321 may have at least one through hole. This through hole penetrates the main body portion 321 in the thickness direction z. By providing this through hole, the inflow of the sealing member 50 into the main body portion 321 in the thickness direction z is improved when the sealing member 50 is formed.

[0090] As shown in Figures 4 and 13, the joint portion 322 is joined to the conductor portion 123. The joint portion 322 faces the conductor portion 123. In plan view, the joint portion 322 extends from the main body portion 321 towards x1 in the first direction x. The tip of the joint portion 322 (the end opposite to the side connected to the main body portion 321) is located below the main body portion 321 in the thickness direction z (towards the z2 side of the thickness direction z). The base end of the joint portion 322 (the end connected to the main body portion 321) is bent in the thickness direction z so as to connect the tip of the joint portion 322 and the main body portion 321, where their positions in the thickness direction z are different.

[0091] As shown in Figures 4 and 13, the joint portion 323 is bonded to the conductive layer 332 of the conductive substrate 33. The joint portion 323 faces the conductive layer 332. In a plan view, the joint portion 323 extends from the main body portion 321 towards the x2 side in the first direction x. The tip of the joint portion 323 (the end opposite to the side connected to the main body portion 321) is located below the main body portion 321 in the thickness direction z (towards the z2 side of the thickness direction z). The base end of the joint portion 323 (the end connected to the main body portion 321) is bent in the thickness direction z so as to connect the tip of the joint portion 323 and the main body portion 321, where their positions in the thickness direction z are different.

[0092] Each semiconductor device B10 further comprises a conductive bonding layer 3229 and a conductive bonding layer 3239, as shown in Figure 13. The conductive bonding layer 3229 is interposed between the joint 322 and the conductor 123. The conductive bonding layer 3229 conductively bonds the joint 322 and the conductor 123. The conductive bonding layer 3239 is interposed between the joint 323 and the conductive layer 332. The conductive bonding layer 3239 conductively bonds the joint 323 and the conductive layer 332. The conductive bonding layers 3229 and 3239 are, for example, solder. Alternatively, the conductive bonding layers 3229 and 3239 may each contain a sintered metal body or be an insert metal used in solid-phase diffusion bonding. Unlike this example, each semiconductor device B10 does not necessarily have to include the conductive bonding layers 3229 and 3239. In this example, the joint 322 and the conductor 123 can be directly joined by laser bonding, pressure bonding, or crimping. Furthermore, the joint 323 and the conductive layer 332 can also be directly joined by laser bonding, pressure bonding, or crimping.

[0093] Note that the shapes of the conductive member 32 are not limited to the illustrated examples. The conductive member 32 only needs to provide electrical conductivity between the conductor portion 123 and the conductive layer 332 of the conductive substrate 33. Also, unlike the illustrated example, in each semiconductor device B10, the joint portion 323 of the conductive member 32 may be joined to the main surface electrode 222 (power pad 2221) of each semiconductor element 22, rather than being joined to the conductive substrate 33. In other words, the conductor portion 123 and the main surface electrode 222 (power pad 2221) of each semiconductor element 22 may be connected by the conductive member 32 without going through the conductive substrate 33. In this example, each semiconductor device B10 does not need to have a conductive substrate 33.

[0094] The multiple connecting members 401, 402, 41-44 each electrically connect parts that are separated from each other. Each of the multiple connecting members 401, 402, 41-44 is, for example, a bonding wire. Unlike this example, each of the multiple connecting members 401, 402, 41-44 may be a bonding ribbon or a metal plate (metal clip). The composition of each of the multiple connecting members 401, 402, 41-44 includes gold (Au). The composition of each of the multiple connecting members 401, 402, 41-44 may also include copper or aluminum. In the illustrated example, the wire diameter of each of the multiple connecting members 401 and 402 is larger than the wire diameter of each of the multiple connecting members 41-44, but they may be the same. Note that in Figures 2 and 16, the multiple connecting members 401, 402, 41-44 are omitted.

[0095] As shown in Figure 5, each of the multiple connecting members 401 is electrically connected to the power pad 2121 of the main surface electrode 212 of one of the multiple semiconductor elements 21 and to the conductor 38. As a result, the main surface electrode 212 (power pad 2121) of each semiconductor element 21 is electrically connected to the back surface electrode 221 of each of the multiple semiconductor elements 22 via the conductor 38.

[0096] As shown in Figure 5, each of the multiple connecting members 402 is electrically connected to the power pad 2221 of the main surface electrode 222 of one of the multiple semiconductor elements 22 and to the conductive layer 332 of the conductive substrate 33. As a result, the main surface electrode 222 (power pad 2221) of each semiconductor element 22 is electrically connected to the power terminal 16 via the conductive layer 332 of the conductive substrate 33 and the conductive members 32, etc.

[0097] As shown in Figure 5, each of the multiple connecting members 41 is electrically connected to the main surface electrode 213 of the corresponding semiconductor element 21 and to the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is electrically connected to the main surface electrode 213 of the multiple semiconductor elements 21.

[0098] As shown in Figure 5, each of the multiple connecting members 42 is electrically connected to the main surface electrode 223 of the corresponding semiconductor element 22 and to the wiring portion 621 of the signal substrate 602. As a result, the signal terminal 192 is electrically connected to the main surface electrode 223 of the multiple semiconductor elements 22.

[0099] As shown in Figure 5, each of the multiple connecting members 43 is electrically connected to one of the two signal pads 2122 of the main surface electrode 212 of the corresponding semiconductor element 21 and to the wiring portion 622 of the signal board 601. As a result, the signal terminal 193 is electrically connected to the main surface electrode 212 (signal pad 2122) of the multiple semiconductor elements 21. If the main surface electrode 212 of each semiconductor element 21 does not include either of the two signal pads 2122, each of the multiple connecting members 43 is connected to the power pad 2121 of the main surface electrode 212 of the corresponding semiconductor element 21.

[0100] As shown in Figure 5, each of the multiple connecting members 44 is electrically connected to one of the two signal pads 2222 of the main surface electrode 212 of the corresponding semiconductor element 22 and to the wiring portion 622 of the signal board 602. As a result, the signal terminal 194 is electrically connected to the main surface electrodes 222 (signal pads 2222) of the multiple semiconductor elements 22. If the main surface electrode 222 of each semiconductor element 22 does not include either of the two signal pads 2222, each of the multiple connecting members 44 is connected to the power pad 2221 of the main surface electrode 222 of the corresponding semiconductor element 22.

[0101] As shown in Figures 21 to 24, in the semiconductor module A10, the bonding material 80 includes two bonding surfaces 81 and 82. Bonding surfaces 81 and 82 are separated in the thickness direction z and face opposite directions in the thickness direction z. Bonding surface 81 faces upward in the thickness direction z, and bonding surface 82 faces downward in the thickness direction z. Bonding surface 81 is in contact with the support substrate 10A or the support substrate 10B. Bonding surface 82 is in contact with the mounting surface 71a of the base portion 71.

[0102] As shown in Figures 22 and 24, the bonding surface 81 includes a recess 811. The recess 811 is recessed downward in the thickness direction z. A portion of the metal layer 13 on the back surface of the support substrate 10A is located inside the recess 811 of the bonding material 80 that bonds the support substrate 10A to the base 71 of the heat dissipation member C10. Similarly, a portion of the metal layer 13 on the back surface of the support substrate 10B is located inside the recess 811 of the bonding material 80 that bonds the support substrate 10B to the base 71 of the heat dissipation member C10. In the illustrated example, the outer edge of the recess 811 in plan view overlaps with the insulating layer 11. In plan view, the recess 811 has a shape that follows the lower surface of the metal layer 13 on the back surface.

[0103] As shown in Figures 22 and 24, the recess 811 has a bottom surface 811a and a side wall 811b. The bottom surface 811a faces the support substrate 10A or the support substrate 10B in the thickness direction z. The bottom surface 811a extends along a plane perpendicular to the thickness direction z. The side wall 811b connects to the bottom surface 811a. In the illustrated example, the side wall 811b is inclined with respect to the plane perpendicular to the thickness direction z (the first plane).

[0104] As shown in Figures 22 and 24, in the semiconductor module A10, the mounting surface 71a of the base 71 has a recess 711. The recess 711 is recessed downward in the thickness direction z. A portion of the bonding material 80 is located inside the recess 711. In a plan view, the recess 711 has a shape that follows the lower surface of the back metal layer 13.

[0105] As shown in Figures 22 and 24, the recess 711 has a bottom surface 711a and a side wall 711b. The bottom surface 711a faces the support substrate 10A or the support substrate 10B in the thickness direction z. The bottom surface 711a extends along a plane perpendicular to the thickness direction z. The side wall 711b connects to the bottom surface 711a. In the illustrated example, the side wall 711b is inclined with respect to a plane perpendicular to the thickness direction z (the second plane). The first and second planes are parallel. The angle of inclination of the side wall 711b with respect to the second plane is smaller than the angle of inclination of the side wall 711b with respect to the first plane.

[0106] In semiconductor module A10, recesses 811 and 711 can be formed by the pressing force applied when performing solid-phase diffusion bonding using the bonding material 80. Therefore, recess 811 is formed when the bonding material 80 is pressed against each support substrate 10A, 10B, and recess 711 is formed when the base 71 is pressed against the bonding material 80 and each support substrate 10A, 10B. As can be seen from Figures 22 and 24, in semiconductor module A10, the outer edge of the bottom surface 811a of recess 811 and the outer edge of the bottom surface 711a of recess 711 in a plan view are offset from each other. In particular, in semiconductor module A10, the outer edge of the bottom surface 811a in a plan view is located inside the outer edge of the bottom surface 711a in a plan view. Unlike this example, these outer edges may overlap in a plan view. On the other hand, the outer edge of the side wall 811b of the recess 811 in plan view is located outside the side wall 711b of the recess 711 in plan view. Figures 22 and 24 show auxiliary lines indicating the outer edge of the bottom surface 711a and the outer edge of the side wall 711b of the recess 711.

[0107] During the manufacturing of the semiconductor module A10, for example, the heat dissipation member C10, the support substrates 10A and 10B, the conductors 37 and 38, and the multiple semiconductor elements 21 and 22 are joined in the following order. First, the support substrates 10A and 10B are placed on the base 71 of the heat dissipation member C10 with a bonding material 80 in between. Next, the conductor 37 is placed on the support substrate 10A with a bonding material 379 in between, and the conductor 38 is placed on the support substrate 10B with a bonding material 389 in between. Next, each semiconductor element 21 is placed on the conductor 37 with a bonding material 219 in between, and each semiconductor element 22 is placed on the conductor 38 with a bonding material 229 in between. Subsequently, the bonding materials 80, 379, 389, 219, and 229 are subjected to high-temperature and high-pressure treatment together, thereby solid-phase diffusion bonding between the two parts using these bonding materials. In contrast to this example, the bonding materials 80, 379 and 389, and 219 and 229 may also be subjected to high-temperature and high-pressure treatment separately, and solid-phase diffusion bonding may be achieved in that order.

[0108] Power Conversion Unit U10 of the First Embodiment: Next, a power conversion unit U10 comprising a semiconductor module A10 will be described with reference to Figures 25 to 29. The power conversion unit U10 comprises a semiconductor module A10 and a control board E1.

[0109] As shown in Figures 25 to 28, the control board E1 is provided in common for the three semiconductor devices B10. Alternatively, multiple control boards E1 may be provided individually for each of the three semiconductor devices B10. As can be seen from Figures 25 to 28, each signal terminal 19 of the three semiconductor devices B10 is inserted through the control board E1. The control board E1 is electrically connected to each signal terminal 19. The control board E1 includes, for example, a control circuit that controls the driving of each of the multiple semiconductor elements 21 and 22 of the three semiconductor devices B10. In an example where each semiconductor element 21 and each semiconductor element 22 are MOSFETs or IGBTs, the control board E1 is a gate driver. The control board E1 faces the upper surface (top surface 51) of each sealing member 50 of the three semiconductor devices B10. The control board E1 is located on the opposite side of the base 71 of the heat dissipation member C10 from the three semiconductor devices B10. In a plan view, the control board E1 overlaps each of the sealing members 50 of the three semiconductor devices B10. In the illustrated example, the control board E1 is held by a plurality of columnar portions 502 of the sealing member 50 at a constant distance in the thickness direction z from the top surface 51 of the sealing member 50.

[0110] As shown in Figure 29, the control board E1 has a base material 91, main wiring 92, back wiring 93, and internal wiring 94. The base material 91 is provided with a plurality of through-holes 911 that penetrate in the thickness direction z. The main wiring 92 is formed on the upper surface of the base material 91 (the surface facing the z1 side in the thickness direction z). The back wiring 93 is formed on the lower surface of the base material 91 (the surface facing the z2 side in the thickness direction z). The internal wiring 94 is arranged on the inner surfaces of the plurality of through-holes 911. The internal wiring 94 is connected to the main wiring 92 and the back wiring 93. The main wiring 92 forms a path for the back wiring 93 and internal wiring 94 and the circuit provided on the control board E1 to be electrically connected to each other.

[0111] Each signal terminal 19 of the three semiconductor devices B10 is inserted into a corresponding through-hole 911 of the control board E1. Figure 29 shows the state in which the signal terminal 19 of any of the three semiconductor devices B10 is inserted into a through-hole 911 of the base material 91. As can be seen from Figure 29, all of the signal terminals 19 of the three semiconductor devices B10 are inserted into the through-holes 911 of the base material 91.

[0112] As shown in Figure 29, each signal terminal 19 includes a tip portion 190. The tip portion 190 is the end of each signal terminal 19 that is away from the sealing member 50. The tip portion 190 has a bulge portion 190A. As shown in Figure 29, the bulge portion 190A bulges out in the signal terminal 19 in a direction perpendicular to the thickness direction z. In the illustrated example, the bulge portion 190A of each signal terminal 19 is located above any of the power terminals 15, 16, and 17 in the thickness direction z.

[0113] As shown in Figure 29, the bulge 190A of each signal terminal 19 is press-fitted into one of the multiple through-holes 911 of the control board E1. As a result, the internal wiring 94 located in one of the multiple through-holes 911 is pressed against the bulge 190A of the signal terminal 19 that is inserted into the through-hole 911. Therefore, each signal terminal 19 is electrically connected to the control board E1 (and its control circuit) by being press-fitted into the through-hole 911 in the thickness direction z. The control board E1 is supported by each signal terminal 19 as each signal terminal 19 is press-fitted into the corresponding one of the multiple through-holes 911. As can be seen from this configuration, the control board E1 is attached to the tip 190 of each signal terminal 19. In contrast to this configuration, each signal terminal 19 does not have to include a bulge 190A. That is, each signal terminal 19 may be a straight pin with no change in thickness. In this case, each signal terminal 19 is inserted through a through-hole 911 and then soldered to the control board E1.

[0114] The configuration of the power conversion unit U10 is not limited to the examples shown in Figures 25 to 28. For example, the control board E1 may have a configuration comprising two circuit boards spaced apart in the thickness direction z. In other words, the control board E1 may have two circuit boards arranged in two stages in the thickness direction z.

[0115] Vehicle F1 of the First Embodiment: Next, a vehicle F1 equipped with a semiconductor module A10 will be described with reference to Figure 30. Vehicle F1 is, for example, an electric vehicle (EV). In Figure 30, the semiconductor module A10 is described as being mounted on vehicle F1 as the power conversion unit U10, but it may also be mounted on vehicle F1 as a semiconductor module A10. In this case, a control board E1 is provided separately on vehicle F1.

[0116] As shown in Figure 30, the vehicle F1 includes an onboard charger F11, a battery F12, and a drive system F13. Power is supplied to the onboard charger F11 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, the means of supplying power from the power supply facility to the onboard charger F11 may be wired. The onboard charger F11 is configured with a boost-type DC-DC converter. The voltage of the power supplied to the onboard charger F11 is boosted by the converter and then supplied to the battery F12. The boosted voltage is, for example, 600V.

[0117] The drive system F13 drives the vehicle F1. The drive system F13 includes an inverter F131 and a drive source F132. The power conversion unit U10 (semiconductor module A10) constitutes part of the inverter F131. Power stored in the battery F12 is supplied to the inverter F131. The power supplied from the battery F12 to the inverter F131 is DC power. In addition, unlike the power system shown in Figure 30, a boost DC-DC converter may be further provided between the battery F12 and the inverter F131. The inverter F131 converts DC power to AC power. The inverter F131, including the power conversion unit U10 (semiconductor module A10), is connected to the drive source F132. The drive source F132 includes an AC motor and a transmission. When the AC power converted by the inverter F131 is supplied to the drive source F132, the AC motor rotates, and this rotation is transmitted to the transmission. The transmission reduces the rotational speed transmitted from the AC motor as appropriate and then rotates the drive shaft of the vehicle F1. This drives the vehicle F1. In driving the vehicle F1, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation of the accelerator pedal. Therefore, the power conversion unit U10 (semiconductor module A10) in the inverter F131 is necessary to output AC power whose frequency is appropriately changed in order to correspond to the required rotational speed of the AC motor.

[0118] The operation and effects of semiconductor module A10 are as follows:

[0119] In the semiconductor module A10, the bonding material 80 has a bonding surface 81 to which the semiconductor device B10 is bonded and a bonding surface 82 to which the heat dissipation member C10 is bonded. The bonding surface 81 has a recess 811 that is recessed in the thickness direction z, and a part of the back metal layer 13 is located inside the recess 811. With this configuration, a part of the back metal layer 13 is embedded in the bonding material 80. This suppresses the peeling of the back metal layer 13 from the bonding material 80. Therefore, the semiconductor module A10 can improve the bonding strength between the semiconductor device B10 and the heat dissipation member C10 by the bonding material 80. In other words, the semiconductor module A10 can suppress the deterioration of heat transfer from the semiconductor device B10 to the heat dissipation member C10.

[0120] In the semiconductor module A10, the heat dissipation member C10 has a mounting surface 71a that contacts the bonding surface 82 of the bonding material 80. The mounting surface 71a has a recess 711 that is recessed in the thickness direction z, and a part of the bonding material 80 is located inside the recess 711. With this configuration, a part of the bonding material 80 is embedded in the heat dissipation member C10. This suppresses the delamination of the bonding material 80 from the heat dissipation member C10. Therefore, the semiconductor module A10 can improve the bonding strength between the semiconductor device B10 and the heat dissipation member C10 by using the bonding material 80. In other words, the semiconductor module A10 can suppress the deterioration of heat transfer from the semiconductor device B10 to the heat dissipation member C10.

[0121] In semiconductor module A10, the bonding material 80 joins the semiconductor device B10 and the heat dissipation member C10 by solid-phase diffusion bonding. In this configuration, the bonding material 80 deforms due to the pressure applied during solid-phase diffusion bonding. Therefore, the semiconductor device B10 and the heat dissipation member C10 are pressed together with enough pressure to deform the bonding material 80, thereby improving the adhesion between the bonding material 80 and the semiconductor device B10, and between the bonding material 80 and the heat dissipation member C10. Consequently, semiconductor module A10 can improve the bonding strength between the semiconductor device B10 and the heat dissipation member C10 by using the bonding material 80.

[0122] In the semiconductor module A10, the bonding material 80 includes a metal substrate layer 80a, a bonding layer 80b, and a bonding layer 80c. The bonding layer 80b is bonded to the back metal layer 13 by solid-phase diffusion bonding of metal. With this configuration, the bonding layer 80b and the back metal layer 13 are bonded by atomic reactions, thereby increasing the bonding strength between the metal substrate layer 80a and the back metal layer 13 (support substrates 10A, 10B). Furthermore, the bonding layer 80c is bonded to the heat dissipation member C10 by solid-phase diffusion bonding of metal. With this configuration, the bonding layer 80c and the heat dissipation member C10 are bonded by atomic reactions, thereby increasing the bonding strength between the metal substrate layer 80a and the heat dissipation member C10 (base portion 71).

[0123] In the semiconductor module A10, the heat dissipation member C10 includes a plurality of heat dissipation fins 751. The plurality of heat dissipation fins 751 are positioned below each semiconductor device B10. With this configuration, heat from each of the plurality of semiconductor elements 21 and plurality of semiconductor elements 22 can be efficiently discharged. In other words, the semiconductor module A10 can improve its heat dissipation performance.

[0124] In semiconductor module A10, each semiconductor device B10 is equipped with a conductor 37, which is interposed between each semiconductor element 21 and the support substrate 10A. With this configuration, heat from each semiconductor element 21 can be diffused over a wide area by the conductor 37, so that heat from each semiconductor element 21 can be efficiently dissipated. In addition, the concentration of heat from each semiconductor element 21 can be suppressed. Similarly, in semiconductor module A10, each semiconductor device B10 is equipped with a conductor 38, which is interposed between each semiconductor element 22 and the support substrate 10B. With this configuration, heat from each semiconductor element 22 can be diffused over a wide area by the conductor 38, so that heat from each semiconductor element 22 can be efficiently dissipated. In addition, the concentration of heat from each semiconductor element 22 can be suppressed.

[0125] In the semiconductor module A10, the sides of the bonding material 80 are covered by the sealing member 50, and the bottom surface 52 of the sealing member 50 is in contact with the mounting surface 71a of the base 71. With this configuration, since the bonding material 80 is not exposed to the outside, the bonding strength between each semiconductor device B10 and the heat dissipation member C10 can be increased. In addition, since the bonding material 80 is not exposed to the outside, deterioration of the bonding material 80 is suppressed.

[0126] Other embodiments and modifications of the semiconductor module of this disclosure are described below. The configurations of the parts in each embodiment and each modification are interchangeable to the extent that no technical inconsistencies arise.

[0127] Figure 31 shows a semiconductor module A11 according to a first modification of the first embodiment. Compared to semiconductor module A10, semiconductor module A11 includes semiconductor device B11 instead of semiconductor device B10. Semiconductor device B11 differs from semiconductor device B10 in the following respects. Firstly, the bonding material 379 of semiconductor device B11 is deformed. Secondly, the bonding material 219 of semiconductor device B11 is deformed. The bonding material 379 and each bonding material 219 will be described below using Figure 31, but the bonding material 389 and each bonding material 229 can be configured similarly.

[0128] In semiconductor device B11, each bonding material 379 is an insert metal used for solid-phase diffusion bonding. The thickness (dimension z in the thickness direction) of each bonding material 379 is not limited, but is, for example, 100 μm or more and 200 μm or less. The bonding material 379 includes a metal substrate layer 379a, a bonding layer 379b, and a bonding layer 379c.

[0129] The metal substrate 379a occupies most of the volume of the corresponding bonding material 379. The thickness (dimension z in the thickness direction) of the metal substrate 379a is, for example, 100 μm or more and 200 μm or less. The metal substrate 379a includes, for example, at least one of aluminum (Al), titanium (Ti), zinc (Zn), hafnium (Hf), and erbium (Er). However, the constituent material of the metal substrate 379a is not limited in any way.

[0130] The bonding layer 379b is interposed between the metal substrate layer 379a and the conductor 37. The bonding layer 379b includes, for example, at least one of silver (Ag), copper (Cu), and gold (Au). However, the constituent material of the bonding layer 379b is not limited in any way. The bonding layer 379b is bonded to the conductor 37 by solid-phase diffusion of the metal. In the case of bonding by solid-phase diffusion, there may be no interface between the bonding layer 379b and the conductor 37.

[0131] The bonding layer 379c is interposed between the metal substrate layer 379a and the support substrate 10A (main surface metal layer 12). The bonding layer 379c includes, for example, at least one of silver (Ag), copper (Cu), and gold (Au). However, the constituent material of the bonding layer 379c is not limited in any way. The bonding layer 379c is bonded to the support substrate 10A (main surface metal layer 12) by solid-phase diffusion of the metal. In the case of bonding by solid-phase diffusion, there may be no interface between the bonding layer 379c and the main surface metal layer 12 (or the metal plating applied to the upper surface of the main surface metal layer 12).

[0132] As shown in Figure 31, the bonding material 379 has an opposing surface 3790 that faces the conductor 37. The opposing surface 3790 faces upward in the thickness direction z. A recess 3791 is formed in the opposing surface 3790. The recess 3791 is recessed downward in the thickness direction z on the opposing surface 3790. A part of the conductor 37 is located inside the recess 3791. Also, as shown in Figure 31, a recess 120 is formed on the upper surface of the main surface metal layer 12. The recess 120 is recessed downward in the thickness direction z on the upper surface of the main surface metal layer 12. A part of the bonding material 379 is located inside the recess 120. In this configuration, the bonding material 379 deforms in the same way as the bonding material 80. In other words, the recess 3791 on the opposing surface 3790 of the bonding material 379 and the recess 120 on the upper surface of the main surface metal layer 12 have the same relationship as the recess 811 and the recess 711.

[0133] In semiconductor device B11, each bonding material 219 is an insert metal used for solid-phase diffusion bonding. The thickness (dimension z in the thickness direction) of each bonding material 219 is not limited, but is, for example, 50 μm or more and 200 μm or less. Each bonding material 219 includes a metal substrate layer 219a, a bonding layer 219b, and a bonding layer 219c.

[0134] The metal substrate layer 219a occupies most of the volume of the corresponding conductive bonding layer. The thickness (dimension z in the thickness direction) of the metal substrate layer 219a is, for example, 50 μm or more and 200 μm or less. The metal substrate layer 379a includes, for example, at least one of aluminum (Al), titanium (Ti), zinc (Zn), hafnium (Hf), and erbium (Er). However, the constituent material of the metal substrate layer 219a is not limited in any way.

[0135] The bonding layer 219b is interposed between the metal substrate layer 219a and the semiconductor element 21. The bonding layer 219b includes, for example, at least one of silver (Ag), copper (Cu), and gold (Au). However, the constituent material of the bonding layer 219b is not limited in any way. The bonding layer 219b is bonded to the semiconductor element 21 (back electrode 211) by solid-phase diffusion of the metal. In the case of bonding by solid-phase diffusion, there may be no interface between the bonding layer 219b and the semiconductor element 21 (back electrode 211).

[0136] The bonding layer 219c is interposed between the metal substrate layer 219a and the conductor 37. The bonding layer 219c includes, for example, at least one of silver (Ag), copper (Cu), and gold (Au). However, the constituent material of the bonding layer 219c is not limited in any way. The bonding layer 219c is bonded to the conductor 37 by solid-phase diffusion of the metal. In the case of bonding by solid-phase diffusion, there may be no interface between the bonding layer 219c and the conductor 37 (or the metal plating applied to the upper surface of the conductor 37).

[0137] As shown in Figure 31, the bonding material 219 has a facing surface 2190 that faces the semiconductor element 21. The facing surface 2190 faces upward in the thickness direction z. A recess 2191 is formed on the facing surface 2190. The recess 2191 is recessed downward in the thickness direction z on the facing surface 2190. A part of the semiconductor element 21 is located inside the recess 2191. Also, as shown in Figure 31, a recess 370 is formed on the upper surface of the conductor 37. The recess 370 is recessed downward in the thickness direction z on the upper surface of the conductor 37. A part of the bonding material 219 is located inside the recess 370. In this configuration, the bonding material 219 deforms in the same way as the bonding material 80. In other words, the recess 2191 formed on the facing surface 2190 of the bonding material 219 and the recess 370 formed on the upper surface of the conductor 37 have the same relationship as the recess 811 and the recess 711.

[0138] Similar to semiconductor module A10, semiconductor module A11 can improve the bonding strength between semiconductor device B10 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B10 to heat dissipation member C10. Furthermore, semiconductor module A11 can increase the bonding strength between support substrate 10A and conductor 37, and the bonding strength between conductor 37 and each semiconductor element 21. Therefore, semiconductor module A11 is preferable to semiconductor module A10 in suppressing deterioration of heat transfer from semiconductor element 21 to heat dissipation member C10. The same applies to the relationship between support substrate 10B and conductor 38.

[0139] Figure 32 shows a semiconductor module A12 according to a second modification of the first embodiment. Compared to semiconductor module A10, semiconductor module A12 includes a semiconductor device B12 instead of semiconductor device B10. Semiconductor device B12 differs from semiconductor device B10 in the following respect: the shape of the bonding material 80 of semiconductor device B12 is different from the shape of the bonding material 80 of semiconductor device B10. In the following, the bonding material 80 between the support substrate 10A and the base 71 will be described using Figure 32, but the bonding material 80 between the support substrate 10B and the base 71 can be configured similarly.

[0140] In the semiconductor device B12, no recess 711 is formed on the mounting surface 71a of the heat dissipation member C10 (base portion 71). Therefore, the lower surface of the bonding material 80 (the lower surface of the bonding layer 80c) is flat. For example, depending on the pressure applied when solid-phase diffusion is performed between the support substrate 10A and the heat dissipation member C10 (base portion 71) using the bonding material 80 (for example, if the pressure is low), only the upper surface of the bonding material 80 may deform in this way.

[0141] Like semiconductor module A10, semiconductor module A12 can improve the bonding strength between semiconductor device B10 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B10 to heat dissipation member C10. However, semiconductor module A10 is preferable to semiconductor module A12 in terms of increasing the bonding strength between semiconductor device B10 and heat dissipation member C10.

[0142] Figure 33 shows a semiconductor module A13 according to a third modification of the first embodiment. Compared to semiconductor module A10, semiconductor module A13 includes semiconductor device B13 instead of semiconductor device B10. Semiconductor device B13 differs from semiconductor device B10 in the following respect: In semiconductor device B13, deformation occurs in the heat dissipation member C10 and the support substrate 10A. The deformation of the heat dissipation member C10 and the support substrate 10A will be explained below using Figure 33, but the heat dissipation member C10 and the support substrate 10B can also deform in a similar manner.

[0143] As shown in Figure 33, the mounting surface 71a is curved convexly upward in the thickness direction z such that the portion overlapping the center of the support substrate 10A in a plan view is higher. Although not shown in the figure, the entire heat dissipation member C10 may also be curved convexly upward in the thickness direction z. Furthermore, along the curvature of the mounting surface 71a, the support substrate 10A is also curved convexly upward in the thickness direction z such that the area near the center in a plan view is higher. In the illustrated example, the conductor 37 located above the support substrate 10A is not deformed, but the conductor 37 may also be curved convexly upward in the thickness direction z. Such curvature of the mounting surface 71a and the support substrate 10A can occur due to strain generated when the heat dissipation member C10 and the support substrate 10A are solid-phase diffusion bonded with the bonding material 80. In contrast to the illustrated example, the support substrate 10A may not be curved convexly upward in the thickness direction z, and only the heat dissipation member C10 (mounting surface 71a) may be curved convexly upward in the thickness direction z.

[0144] Similar to semiconductor module A10, semiconductor module A13 can improve the bonding strength between semiconductor device B10 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B10 to heat dissipation member C10.

[0145] Figure 34 shows a semiconductor module A14 according to a fourth modification of the first embodiment. Compared to semiconductor module A10, semiconductor module A14 includes semiconductor device B14 instead of semiconductor device B10. Semiconductor device B14 differs from semiconductor device B10 in the following respect: In semiconductor device B14, support substrate 10A and support substrate 10B are integrally formed and constitute a support substrate 10.

[0146] In the semiconductor device B14, multiple semiconductor elements 21 and multiple semiconductor elements 22 are supported on a common support substrate 10. Both conductors 37 and 38 are bonded to the support substrate 10. The support substrate 10 includes an insulating layer 11, a main surface metal layer 12, and a back surface metal layer 13. The main surface metal layer 12 of the support substrate 10 includes conductor portions 121, conductor portions 122, and conductor portions 123.

[0147] Similar to semiconductor module A10, semiconductor module A14 can improve the bonding strength between semiconductor device B10 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B10 to heat dissipation member C10. As can be seen from semiconductor module A14, the semiconductor module of this disclosure is not limited to a configuration in which semiconductor element 21 and semiconductor element 22 are supported on different support substrates 10A and 10B, but may be supported on a common support substrate 10.

[0148] Figure 35 shows a semiconductor module A15 according to a fifth modification of the first embodiment. Compared to semiconductor module A10, semiconductor module A15 includes semiconductor device B15 instead of semiconductor device B10. Semiconductor device B15 differs from semiconductor device B10 in the following respect: It differs in that semiconductor device B15 does not include the two conductors 37 and 38.

[0149] In semiconductor device B15, each semiconductor element 21 is bonded to the conductor portion 121 by bonding material 219. In addition to each semiconductor element 21, the signal substrate 601 and the conductive substrate 33 are also bonded to the conductor portion 121. Each semiconductor element 22 is bonded to the conductor portion 122 by bonding material 229. In addition to each semiconductor element 22, the signal substrate 602 is also bonded to the conductor portion 122.

[0150] Similar to semiconductor module A10, semiconductor module A15 can improve the bonding strength between semiconductor device B10 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B10 to heat dissipation member C10. In semiconductor module A15, semiconductor device B15 does not have two conductors 37 and 38, so it is possible to reduce the height of semiconductor device B15. As can be understood from semiconductor module A15, in the semiconductor module of this disclosure, there is no limitation on whether or not a conductor 37 is interposed between each semiconductor element 21 and the support substrate 10A, and whether or not a conductor 38 is interposed between each semiconductor element 22 and the support substrate 10B.

[0151] Second Embodiment: Figures 36 to 39 show a semiconductor module A20 according to the second embodiment. The semiconductor module A20 differs from the semiconductor module A10 in the following respect: The semiconductor module A20 includes a heat dissipation member C20 instead of a heat dissipation member C10. In the illustrated example, the semiconductor module A20 includes the semiconductor device B10, but it may also include other semiconductor devices B11 to B15 instead of semiconductor device B10.

[0152] The heat dissipation member C20 includes a base portion 71 and a heat dissipation portion 75, as well as an inlet portion 72, an outlet portion 73, and a case portion 74.

[0153] The case portion 74 is attached to the base portion 71 below in the thickness direction z. The base portion 71 and the case portion 74 give the heat dissipation member C20 a hollow box shape. Thus, a gap is formed inside the heat dissipation member C20. The heat dissipation section 75 can be housed in this gap. In the illustrated example, the outer edge of the base portion 71 and the outer edge of the case portion 74 in a plan view overlap in a plan view, but they may be offset from each other in a plan view. For example, the outer edge of the case portion 74 in a plan view may be inward of the outer edge of the base portion 71 in a plan view.

[0154] As shown in Figure 39, the case portion 74 includes a bottom plate 741. The bottom plate 741 is located on the opposite side of the base portion 71 in the thickness direction z, with a plurality of heat dissipation fins 751 in between. The end faces 751a (surfaces facing downward in the thickness direction z) of the plurality of heat dissipation fins 751 are in contact with the bottom plate 741 in the above-mentioned gap.

[0155] The inlet 72 and outlet 73 are located on opposite sides of the case portion 74 with respect to the second direction y. In the illustrated example, the inlet 72 is located on the y2 side of the second direction y of the case portion 74, and the outlet 73 is located on the y1 side of the second direction y of the case portion 74, but they may be reversed. The inlet 72 and outlet 73 are both cylindrical and have holes formed in them. The holes in the inlet 72 and the holes in the outlet 73 are connected to the gap formed by the base portion 71 and the case portion 74, respectively.

[0156] In the heat dissipation member C10, a cooling medium (which may be a gas or a liquid) is introduced from the inlet 72, and the cooling medium comes into contact with the heat dissipation section 75 in the void. As a result, the heat transferred to the heat dissipation section 75 is transferred to the cooling medium. The cooling medium that has received heat from the heat dissipation section 75 is then discharged to the outside of the heat dissipation member C20 from the outlet 73. The cooling medium that has been discharged to the outside may be cooled again and then introduced again from the inlet 72, thereby circulating the cooling medium.

[0157] The operation and effects of semiconductor module A20 are as follows:

[0158] Like semiconductor module A10, semiconductor module A20 can improve the bonding strength between semiconductor device B10 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B10 to heat dissipation member C10. In addition, semiconductor module A20 achieves the same effects as semiconductor modules A10 to A15 by having a configuration common to those modules. As can be seen from semiconductor module A20, in the semiconductor module of this disclosure, the heat dissipation member is not limited to a configuration in which the heat dissipation section 75 (multiple heat dissipation fins 751) is exposed to the outside.

[0159] Third Embodiment: Figure 40 shows a semiconductor module A30 according to the third embodiment. Semiconductor module A30 differs from semiconductor module A10 in the following respect: Semiconductor module A30 has multiple semiconductor devices B20 instead of multiple semiconductor devices B10. In other words, semiconductor module A30 differs from semiconductor module A10 in the structure of each semiconductor device.

[0160] In semiconductor module A30, multiple openings are provided on the top surface 51 of the sealing member 50, and one of the multiple conductive parts 121, 122, and 123 is exposed from each of the multiple openings. In semiconductor device B20, a portion of each of the three power terminals 15, 16, and 17 is inserted through the openings of the sealing member 50 and bonded to the main surface metal layer 12, so that each power terminal 15, 16, and 17 protrudes upward in the thickness direction z.

[0161] The operation and effects of semiconductor module A30 are as follows:

[0162] Like semiconductor module A10, semiconductor module A30 can improve the bonding strength between semiconductor device B20 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B20 to heat dissipation member C10. In addition, semiconductor module A30 has a configuration common to the other semiconductor modules A10 to A15 and A20, and thus achieves the same effects as those semiconductor modules A10 to A15 and A20.

[0163] Figure 41 shows a semiconductor module A31 according to a first modification of the third embodiment. Semiconductor module A31 differs from semiconductor module A30 in the following respect: Semiconductor module A31 includes a semiconductor device B21. In the example shown in Figure 41, semiconductor module A31 includes one semiconductor device B21, but it may also be configured to include multiple semiconductor devices B21.

[0164] The semiconductor device B21 of semiconductor module A31 includes a power terminal 15, two power terminals 16, and two power terminals 17. In the illustrated example, with respect to the second direction y, power terminal 15 is located between the two power terminals 16. That is, in the illustrated example, the arrangement on the side surface 531 of the sealing member 50 is N terminal, P terminal, N terminal. Unlike this example, the semiconductor device of the present disclosure may have two power terminals 15 and one power terminal 15, and with respect to the second direction y, power terminal 16 may be located between the two power terminals 15. That is, the arrangement on the side surface 531 of the sealing member 50 may be P terminal, N terminal, P terminal. Power terminal 15, the two power terminals 16, and the two power terminals 17 are each exposed on the top surface 51 of the sealing member 50.

[0165] Figure 42 shows a semiconductor module A32 according to a second modification of the third embodiment. Semiconductor module A32 differs from semiconductor module A30 in the following respect: semiconductor module A32 includes a semiconductor device B22. In the example shown in Figure 42, semiconductor module A32 includes one semiconductor device B22, but it may also be configured to include multiple semiconductor devices B22.

[0166] In semiconductor device B22 of semiconductor module A32, all of the signal terminals 19 are located biased toward the two power terminals 17. In contrast to this example, all of the signal terminals 19 may be located biased toward the power terminal 15 and the two power terminals 16.

[0167] Similar to semiconductor module A30 (semiconductor module A10), semiconductor module A32 can improve the bonding strength between semiconductor device B20 and heat dissipation member C10 using bonding material 80, thereby suppressing deterioration of heat transfer from semiconductor device B20 to heat dissipation member C10.

[0168] Figure 43 shows a semiconductor module A33 according to a third modification of the third embodiment. Semiconductor module A33 differs from semiconductor module A30 in the following respect: semiconductor module A33 includes a semiconductor device B23. In the example shown in Figure 43, semiconductor module A33 includes one semiconductor device B23, but it may also be configured to include multiple semiconductor devices B23.

[0169] In the semiconductor device B23 of semiconductor module A33, power terminal 15 and the two power terminals 16 each protrude from the side surface 531 of the sealing member 50, and the two power terminals 17 each protrude from the side surface 532 of the sealing member 50.

[0170] Figure 44 shows a semiconductor module A34 according to a fourth modification of the third embodiment. The semiconductor module A34 differs from the semiconductor module A30 in the following respect: the semiconductor module A34 includes a semiconductor device B24. In the example shown in Figure 44, the semiconductor module A34 includes one semiconductor device B24, but it may also be configured to include multiple semiconductor devices B24.

[0171] In the semiconductor device B24 of semiconductor module A34, all of the signal terminals 19 protrude from the side surface 531. Unlike the illustrated example, some of the signal terminals 19 may protrude from the side surface 531, while the remaining signal terminals 19 protrude from the side surface 532. Also, all of the signal terminals 19 extend from the side surface 532 towards the x2 side of the first direction x, but some of the signal terminals 19 may extend from 432 towards the x2 side of the first direction x, then bend and bend in the thickness direction z (upward or downward).

[0172] The semiconductor modules A31 to A34 according to each of the modifications of the third embodiment described above, like semiconductor module A30 (semiconductor module A10), can improve the bonding strength between the semiconductor devices B21 to B24 and the heat dissipation member C10 by using the bonding material 80, thereby suppressing deterioration of heat transfer from the semiconductor devices B21 to B24 to the heat dissipation member C10. Furthermore, as can be understood from semiconductor module A30 and semiconductor modules A31 to A34, various configurations can be adopted for the semiconductor device in the semiconductor module of this disclosure.

[0173] The semiconductor module relating to this disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor module relating to this disclosure can be modified in various ways. For example, the semiconductor module relating to this disclosure includes embodiments relating to the following appendices. Examples of each component in the following appendices are shown in parentheses using the reference numerals from the embodiments (including modified examples) described above, but are not limited thereto. Appendix 1. A semiconductor device (B10 to B15) comprising a semiconductor element (21) and a support substrate (10A) supporting the semiconductor element (21); a heat dissipation member (C10) on which the semiconductor device (B10 to B15) is mounted; and a first bonding material (80) that bonds the semiconductor device (B10 to B15) and the heat dissipation member (C10), wherein the support substrate (10A) has an insulating layer (11) having a back surface (11b) facing one side (downward) in the thickness direction (z) of the semiconductor element (21), and a back surface metal layer (13) bonded to the back surface (11b); and the first bonding material (80) has a first bonding surface (81) to which the semiconductor device (B10 to B15) is bonded and a second bonding surface (82) to which the heat dissipation member (C10) is bonded. The semiconductor module (A10-A15, A20, A30-A34) described in Appendix 1, wherein the first bonding surface (81) has a first recess (811) recessed in the thickness direction (z), and a portion of the back metal layer (13) is located inside the first recess (811). Appendix 2. The heat dissipation member (C10) has a mounting surface (71a) in contact with the second bonding surface (82), the mounting surface (71a) has a second recess (711) recessed in the thickness direction (z), and a portion of the first bonding material (80) is located inside the second recess (711). Appendix 2-1. The semiconductor module (A10, A11) described in Appendix 2, wherein the second recess (711) overlaps the back metal layer (13) when viewed in the thickness direction (z).Note 3. The semiconductor module (A10, A11) described in Note 2, wherein the first recess (811) has a first bottom surface (811a) facing the support substrate (10A) in the thickness direction (z) and a first side wall (811b) connected to the first bottom surface (811a), and the first side wall (811b) is inclined with respect to a first plane perpendicular to the thickness direction (z). Note 4. The semiconductor module (A10, A11) described in Note 3, wherein the second recess (711) has a second bottom surface (711a) facing the support substrate (10A) in the thickness direction (z) and a second side wall (711b) connected to the second bottom surface (711a), and the second side wall (711b) is inclined with respect to a second plane perpendicular to the thickness direction (z). Note 5. The semiconductor module (A10, A11) described in Appendix 4, wherein, when viewed in the thickness direction (z), the outer edge of the first bottom surface (711a) and the outer edge of the second bottom surface (711a) are offset. Appendix 6. The semiconductor module (A10, A11) described in Appendix 5, wherein, when viewed in the thickness direction (z), the outer edge of the second bottom surface (711a) is located inward of the outer edge of the first bottom surface (711a). Appendix 7. The semiconductor module (A10, A11) described in any of Appendix 4 to Appendix 6, wherein the inclination angle of the second side wall (711b) with respect to the second plane is smaller than the inclination angle of the first side wall (811b) with respect to the first plane. Appendix 8. The semiconductor module (A13) described in any of Appendix 2 to Appendix 7, wherein each of the heat dissipation member (C10) and the support substrate (10A) is curved convexly in the other direction of the thickness direction (z). Appendix 9. The heat dissipation member (C10) includes a base (71) in contact with the second bonding surface (82) and a plurality of fins (751) protruding from the base (71) in one direction in the thickness direction (z), each of the plurality of fins (751) has an end face (751a) facing in one direction in the thickness direction (z), and in each of the plurality of fins (751), the end face (751a) is exposed to the outside of the heat dissipation member (C10), as described in any of Appendix 2 to Appendix 8, semiconductor module (A10 to A15).Note 10. The heat dissipation member (C10) includes a base (71) in contact with the second bonding surface (82), a plurality of fins (751) protruding from the base (71) in one direction in the thickness direction (z), and a bottom plate (741) located on the opposite side of the base (71) with respect to the thickness direction (z), wherein each of the plurality of fins (751) has an end face (751a) facing in one direction in the thickness direction (z), and in each of the plurality of fins (751), the end face (751a) is in contact with the bottom plate (741), the semiconductor module (A20) as described in Note 1. Note 11. The semiconductor module (A10 to A15, A20) as described in any of Notes 1 to 10, wherein, viewed in the thickness direction (z), the outer edge of the first recess (811) completely overlaps the insulating layer (11). Note 12. The semiconductor module (A10 to A15, A20) according to any one of Notes 1 to 11, wherein the first bonding material (80) includes a metal substrate layer (80a), a first bonding layer (80b), and a second bonding layer (80c), the first bonding layer (80b) is interposed between the metal substrate layer (80a) and the back metal layer (13) and is bonded to the back metal layer (13) by solid-phase diffusion of metal, and the second bonding layer (80c) is interposed between the metal substrate layer (80a) and the heat dissipation member (C10) and is bonded to the heat dissipation member (C10) by solid-phase diffusion of metal. Note 13. The semiconductor module (A10 to A15, A20, A30 to A34) according to any one of Notes 1 to 12, wherein the heat dissipation member (C10) includes aluminum. Note 14. The semiconductor module (A10 to A15, A20, A30 to A34) according to Appendix 13, wherein the back metal layer (13) contains copper. Appendix 15. The semiconductor module (A10 to A14, A20) according to any one of Appendix 1 to 14, wherein the insulating layer (11) has a main surface (11a) facing the opposite side from the back surface (11b) in the thickness direction (z), the support substrate (10A) has a main surface metal layer (12) bonded to the main surface (11a), and the semiconductor device (B10 to B15) comprises a conductor (37) interposed between the main surface metal layer (12) and the semiconductor element (21).Note 16. The semiconductor module (A10 to A14, A20) according to Note 15, wherein the semiconductor device (B10 to B15) comprises a second bonding material (379) interposed between the conductor (37) and the main surface metal layer (12) and joining the conductor (37) and the main surface metal layer (12). Note 16-1. The semiconductor module (A11) according to Note 16, wherein the second bonding material (379) has a first opposing surface (3790) facing the conductor (37), the first opposing surface (3790) has a third recess (3791) recessed in the thickness direction (z), and a part of the conductor (37) is located inside the third recess (3791). Note 17. The semiconductor device (B10 to B15) comprises a third bonding material (219) interposed between the semiconductor element (21) and the conductor (37) to bond the semiconductor element (21) and the conductor (37), as described in Appendix 15 or Appendix 16, semiconductor module (A10 to A14, A20). Appendix 17-1. The third bonding material (219) has a second opposing surface (2190) facing the semiconductor element (21), the second opposing surface (2190) has a fourth recess (2191) recessed in the thickness direction (z), and a part of the semiconductor element (21) is located inside the fourth recess (2191), as described in Appendix 17, semiconductor module (A11). Appendix 18. A semiconductor module (A10-A15, A20, A30-A34) according to any one of Appendix 1 to 17, further comprising a sealing member that covers the semiconductor element (21) and the support substrate (10A). Appendix 19. A semiconductor module (A10-A15, A20, A30-A34) according to Appendix 18, wherein the sealing member is in contact with the heat dissipation member (C10) around the back metal layer (13) as viewed in the thickness direction (z).

[0174] A10-A15, A20, A30-A34: Semiconductor module B10-B15, B20-B24: Semiconductor device 10, 10A, 10B: Support substrate 11: Insulating layer 11a: Main surface 11b: Back surface 12: Main surface metal layer 120: Recess 121, 122, 123: Conductor part 13: Back surface metal layer 15, 16, 17: Power terminals 155, 165, 175: Plate part 156, 166, 176: Cylindrical part 19, 191-191, 199: Signal terminal 190: Tip part 190A: Bulge part 21: Semiconductor element 21a: Element main surface 21b: Element back surface 211: Back surface electrode 212, 213: Main surface electrode 2121: Power pad 2122: Signal pad 219: Bonding material 219a: Metal substrate 219b: Bonding layer 219c: Bonding layer 2190: Opposing surface 2191: Recess 22: Semiconductor element 22a: Main surface of element 22b: Back surface of element 221: Back surface electrode 222, 223: Main surface electrode 2221: Power pad 2222: Signal pad 229: Bonding material 32: Conductive member 321: Main body 322, 323: Bonding part 3229, 3239: Conductive bonding layer 33: Conductive substrate 331: Insulating layer 332, 333: Conductive layer 37: Conductor 370: Recess 379: Bonding material 3790: Opposing surface 3791: Recess 379a: Metal substrate 379b: Bonding layer 379c: Bonding layer 38: Conductor 389: Bonding material 401, 402, 41-44: Connecting members 50: Sealing members 501: Sealing part 502: Columnar part 51: Top surface 52: Bottom surface 531-534: Side surfaces 601, 602: Signal board 61: Insulating layer 62: Wiring layer 621, 622,629: Wiring section 63: Metal layer 64: Sleeve 71: Base 71a: Mounting surface 71b: Back surface 711: Recess 711a: Bottom surface 711b: Side wall 713: Through hole 72: Inlet 73: Outlet 74: Case section 741: Bottom plate 75: Heat dissipation section 751: Heat dissipation fin 751a: End surface 80: Bonding material 80a: Metal base layer 80b: Bonding layer 80c: Bonding layer 81: Bonding surface 811: Recess 811a: Bottom surface 811b: Side wall 82: Bonding surface 91: Base material 911: Through hole 92: Main wiring 93: Back wiring 94: Internal wiring C10, C20: Heat dissipation member D1: Positioning pin E1: Control board F1: Vehicle F11: On-board charger F12: Battery; F13: Drive system; F131: Inverter; F132: Power source; U10: Power conversion unit.

Claims

1. A semiconductor module comprising: a semiconductor device comprising a semiconductor element and a support substrate for supporting the semiconductor element; a heat dissipation member on which the semiconductor device is mounted; and a first bonding material for bonding the semiconductor device and the heat dissipation member, wherein the support substrate has an insulating layer having a back surface facing one side in the thickness direction of the semiconductor element and a back metal layer bonded to the back surface; the first bonding material has a first bonding surface to which the semiconductor device is bonded and a second bonding surface to which the heat dissipation member is bonded; the first bonding surface has a first recess that is recessed in the thickness direction; and a part of the back metal layer is located inside the first recess.

2. The semiconductor module according to claim 1, wherein the heat dissipation member has a mounting surface in contact with the second bonding surface, the mounting surface has a second recess that is recessed in the thickness direction, and a portion of the first bonding material is located inside the second recess.

3. The semiconductor module according to claim 2, wherein the first recess has a first bottom surface facing the support substrate in the thickness direction and a first side wall connected to the first bottom surface, and the first side wall is inclined with respect to a first plane perpendicular to the thickness direction.

4. The semiconductor module according to claim 3, wherein the second recess has a second bottom surface facing the support substrate in the thickness direction and a second side wall connected to the second bottom surface, and the second side wall is inclined with respect to a second plane perpendicular to the thickness direction.

5. The semiconductor module according to claim 4, wherein, when viewed in the thickness direction, the outer edge of the first bottom surface and the outer edge of the second bottom surface are offset.

6. The semiconductor module according to claim 5, wherein, viewed in the thickness direction, the outer edge of the second bottom surface is located inward of the outer edge of the first bottom surface.

7. The semiconductor module according to any one of claims 4 to 6, wherein the inclination angle of the second side wall with respect to the second plane is smaller than the inclination angle of the first side wall with respect to the first plane.

8. The semiconductor module according to any one of claims 2 to 7, wherein each of the heat dissipation member and the support substrate is curved convexly in the other direction in the thickness direction.

9. The heat dissipation member comprises a base that contacts the second bonding surface and a plurality of fins that protrude from the base in one direction in the thickness direction, each of the plurality of fins having an end face that faces one direction in the thickness direction, and in each of the plurality of fins, the end face is exposed to the outside of the heat dissipation member, the semiconductor module according to any one of claims 2 to 8.

10. The heat dissipation member includes a base that contacts the second bonding surface, a plurality of fins that protrude from the base in one direction in the thickness direction, and a bottom plate located on the opposite side of the base with respect to the plurality of fins in the thickness direction, each of the plurality of fins having an end face that faces one direction in the thickness direction, and in each of the plurality of fins, the end face is in contact with the bottom plate, the semiconductor module according to claim 1.

11. The semiconductor module according to any one of claims 1 to 10, wherein, when viewed in the thickness direction, the outer edge of the first recess completely overlaps the insulating layer.

12. The semiconductor module according to any one of claims 1 to 11, wherein the first bonding material comprises a metal substrate, a first bonding layer, and a second bonding layer, the first bonding layer being interposed between the metal substrate and the back metal layer and bonded to the back metal layer by solid-phase diffusion of metal, and the second bonding layer being interposed between the metal substrate and the heat dissipation member and bonded to the heat dissipation member by solid-phase diffusion of metal.

13. The semiconductor module according to any one of claims 1 to 12, wherein the heat dissipation member includes aluminum.

14. The semiconductor module according to claim 13, wherein the metal layer on the back surface contains copper.

15. The semiconductor module according to any one of claims 1 to 14, wherein the insulating layer has a main surface facing away from the back surface in the thickness direction, the support substrate has a main surface metal layer bonded to the main surface, and the semiconductor device comprises a conductor interposed between the main surface metal layer and the semiconductor element.

16. The semiconductor module according to claim 15, wherein the semiconductor device comprises a second bonding material interposed between the conductor and the main surface metal layer, and bonding the conductor and the main surface metal layer.

17. The semiconductor module according to claim 15 or 16, wherein the semiconductor device comprises a third bonding material interposed between the semiconductor element and the conductor, and bonding the semiconductor element and the conductor.

18. The semiconductor module according to any one of claims 1 to 17, further comprising a sealing member that covers the semiconductor element and the support substrate.

19. The semiconductor module according to claim 18, wherein the sealing member is in contact with the heat dissipation member around the back metal layer as viewed in the thickness direction.

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