Array substrate, light-regulated panel, and display apparatus

Abstract

An array substrate, a light-regulated panel, and a display apparatus. The array substrate comprises: a base substrate (101); a plurality of pixel electrodes (102) arranged in an array on the base substrate (101), every two pixel electrodes (102) arranged in a row direction serving as a pixel electrode group; a plurality of data lines (104) each extending at a column gap between the two pixel electrodes (102) in a pixel electrode group; and a plurality of transistors (105), the two pixel electrodes (102) in a same pixel electrode group being electrically connected to first electrodes of different transistors (105), gates of the two transistors (105) electrically connected to the same pixel electrode group being shared, and second electrodes of the two transistors (105) electrically connected to the same pixel electrode group being electrically connected to a same data line (104).

Description

Array substrate, dimming panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a dimming panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, dimming panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, the present disclosure provides an array substrate, comprising:

[0006] Substrate;

[0007] Multiple pixel electrodes are arranged in an array on the substrate, and each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group.

[0008] Multiple data lines extend at the column gap between two pixel electrodes within the pixel electrode group;

[0009] Multiple transistors, two pixel electrodes of the same pixel electrode group are electrically connected to the first electrodes of different transistors, the gates of two transistors electrically connected to the same pixel electrode group are multiplexed, and the second electrodes of two transistors electrically connected to the same pixel electrode group are electrically connected to the same data line.

[0010] In some embodiments, in the array substrate provided in the present disclosure, the gates of two transistors electrically connected to the same pixel electrode group include a central axis extending along the column direction;

[0011] The first electrodes of the two transistors electrically connected to the same pixel electrode group are approximately symmetrical about the central axis, and the second electrodes of the two transistors electrically connected to the same pixel electrode group are approximately symmetrical about the central axis.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the second electrode of the transistor is a "U"-shaped structure.

[0013] In some embodiments, in the array substrate provided in the present disclosure, in two transistors electrically connected to the same pixel electrode group, the openings of the two "U"-shaped structures are arranged opposite to each other in the row direction, and the bottoms of the two "U"-shaped structures are reused.

[0014] In some embodiments, the array substrate provided in this disclosure further includes a gate line extending at the row gap between adjacent pixel electrodes, and the gate of the transistor is electrically connected to the gate line.

[0015] In the two transistors electrically connected in the same pixel electrode group, the openings of the two "U"-shaped structures are located away from the gate line, and the adjacent sidewalls of the two "U"-shaped structures are reused.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the first electrode of the transistor extends from the opening of the "U"-shaped structure toward a direction away from the "U"-shaped structure.

[0017] In some embodiments, in the array substrate provided in the present disclosure, in two transistors electrically connected to the same pixel electrode group, the openings of the two "U"-shaped structures face the electrically connected pixel electrodes, and the two "U"-shaped structures are inclined relative to the central axis.

[0018] In some embodiments, in the array substrate provided in this disclosure, the first electrode of the transistor includes a first portion, a second portion, and a third portion connected in sequence; wherein...

[0019] At least a portion of the first part is located within the opening of the "U"-shaped structure, and the extension direction of the first part is approximately the same as the extension direction of the sidewall of the "U"-shaped structure. The second part extends along the column direction, and the third part extends along the row direction.

[0020] In some embodiments, in the array substrate provided in the present disclosure, the first portion and the second portion form an obtuse angle; and / or, the second portion is substantially perpendicular to the third portion.

[0021] In some embodiments, the array substrate provided in this disclosure further includes a plurality of first common electrode lines disposed on the same layer as the plurality of data lines, the first common electrode lines extending at the column gaps between adjacent pixel electrode groups.

[0022] In some embodiments, the array substrate provided in this disclosure further includes gate lines and a plurality of second common electrode lines disposed on the same layer as the gate lines, the second common electrode lines extending at the row gaps between adjacent pixel electrodes.

[0023] In some embodiments, the array substrate provided in this disclosure further includes a plurality of third common electrode lines located on the side of the layer where the plurality of data lines are located away from the substrate, wherein the orthographic projection of the third common electrode lines on the substrate overlaps with the orthographic projection of the data lines on the substrate.

[0024] On the other hand, this disclosure provides a dimming panel, including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0025] In some embodiments, in the dimming panel provided in the present disclosure, the opposing substrate includes a light-shielding pattern, and the orthographic projection of the light-shielding pattern on the substrate does not overlap with the orthographic projection of the data line between adjacent transistors in the column direction on the substrate.

[0026] In some embodiments, in the dimming panel provided in the present disclosure, the opposing substrate includes a light-shielding pattern, and the orthographic projection of the light-shielding pattern on the substrate does not overlap with the orthographic projection of the gate line between adjacent transistors in the row direction on the substrate.

[0027] In some embodiments, in the dimming panel provided in the present disclosure, the orthographic projection of the light-shielding pattern on the substrate overlaps with the orthographic projection of the transistor on the substrate.

[0028] On the other hand, embodiments of this disclosure provide a display device, including a display panel and a dimming panel stacked together, wherein the dimming panel is the dimming panel provided in the embodiments of this disclosure.

[0029] In some embodiments, in the display device provided in the present disclosure, the display panel includes a plurality of pixels arranged in an array, and the orthographic projection of the data line on the substrate overlaps with the central region of the pixel.

[0030] In some embodiments, in the display device provided in the present disclosure, the orthographic projection of the data line on the substrate overlaps with the orthographic projection of the central axis of the pixel extending along the column direction on the substrate.

[0031] In some embodiments, in the display device provided in the present disclosure, the pixel includes a plurality of sub-pixels, and the orthographic projection of the data line on the substrate overlaps with the orthographic projection of at least a portion of the sub-pixels on the substrate.

[0032] In some embodiments, in the display device provided in the present disclosure, the pixel electrode group and the pixel are stacked in a one-to-one correspondence.

[0033] In some embodiments, in the display device provided in the present disclosure, the display panel includes a black matrix, and the orthographic projection of the black matrix on the substrate does not overlap with the orthographic projection of the data lines between adjacent transistors in the column direction on the substrate. Attached Figure Description

[0034] Figure 1 is a schematic diagram of a structure at 2*2 pixel electrodes in an array substrate provided in an embodiment of this disclosure;

[0035] Figure 2 is a magnified structural diagram of region Z in Figure 1;

[0036] Figure 3 is a schematic diagram of the wide viewing angle display of the dimming panel provided in the embodiment of this disclosure;

[0037] Figure 4 is a schematic diagram of the cross-sectional structure along line I-I' in Figure 1;

[0038] Figure 5 is a schematic diagram of the cross-sectional structure along line II-II' in Figure 1;

[0039] Figure 6 is a schematic diagram of the cross-sectional structure along line III-III' in Figure 1;

[0040] Figure 7 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 1;

[0041] Figure 8 is a schematic diagram of the structure of the layer containing the grid lines in Figure 1;

[0042] Figure 9 is a schematic diagram of the active layer in Figure 1;

[0043] Figure 10 is a schematic diagram of the structure of the layer where the data line is located in Figure 1;

[0044] Figure 11 is a schematic diagram of the structure of the layer where the vias are located in Figure 1;

[0045] Figure 12 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 1;

[0046] Figure 13 is a schematic diagram of a transistor structure provided in an embodiment of this disclosure;

[0047] Figure 14 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0048] Figure 15 is a schematic diagram of another structure at the 2*2 pixel electrodes in the array substrate provided in the embodiment of this disclosure;

[0049] Figure 16 is a schematic diagram of the structure of the layer containing the grid lines in Figure 15;

[0050] Figure 17 is a schematic diagram of the structure of the layer where the data line is located in Figure 15;

[0051] Figure 18 is a schematic diagram of the structure of the array substrate shown in Figure 1 during the fabrication process according to an embodiment of this disclosure;

[0052] Figure 19 is a schematic diagram of the structure of a pixel electrode group area in a dimming panel provided in an embodiment of the present disclosure;

[0053] Figure 20 is a structural diagram of an area containing a light-blocking pattern in a dimming panel;

[0054] Figure 21 is a schematic diagram of the cross-sectional structure along line IV-IV' in Figure 19;

[0055] Figure 22 is a schematic diagram of the spliced ​​cross-sectional structure along the V-V' line and the V'-V” line in Figure 19;

[0056] Figure 23 is a schematic diagram of the cross-sectional structure along line VI-VI' in Figure 19;

[0057] Figure 24 is a schematic diagram of the structure of a display unit in a display device provided in an embodiment of the present disclosure;

[0058] Figure 25 is a schematic diagram of the structure of one pixel in the display panel of Figure 24;

[0059] Figure 26 is a schematic diagram of the array substrate included in the display panel in Figure 25;

[0060] Figure 27 is a schematic diagram of the structure of the black matrix contained in the display panel in Figure 25;

[0061] Figure 28 is a schematic diagram of the cross-sectional structure along line VII-VII' in Figure 24. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0063] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0064] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0065] Dual-cell display devices consist of two display cells with pixel structures (Main Cell and Sub Cell). The Main Cell has RGB color resist for color display, while the Sub Cell may lack RGB color resist and is used for local dimming, enabling high contrast. Therefore, dual-cell display products, with their contrast ratio comparable to OLED and their delicate dynamic display, are widely used in high-end medical, smart devices, and automotive fields.

[0066] Each sub-pixel (Dot) in a Sub-Cell is driven by a single transistor TFT, and each column of sub-pixels is electrically connected to a data line. This limits the overall aperture ratio of the Sub-Cell. When the Main Cell and Sub-Cell are bonded together, the obstruction of multiple data lines leads to a significant decrease in brightness at wide viewing angles. By merging the three RGB sub-pixel Dots of the Sub-Cell and electrically connecting a single data line to one side of the merged pixel via a transistor TFT, the number of data lines can be effectively reduced, thereby improving the pixel aperture ratio and alleviating the brightness problem at wide viewing angles. However, since the storage capacitance (Cst) of the merged RGB sub-pixel Dots becomes three times that of a single sub-pixel Dot, the pixel charging rate of a single transistor TFT decreases. Furthermore, after merging the RGB sub-pixel Dots, the pixel electrode area increases threefold, resulting in poor uniformity of pixel voltage control by a single transistor TFT, affecting display performance. Therefore, with increasing power consumption and increasingly demanding application scenarios, the requirements for transmittance and brightness at wide viewing angles in dual-cell display products are becoming increasingly stringent, and the Sub-Cell pixel structure can no longer meet these demands.

[0067] To improve the above-mentioned technical problems, this disclosure provides an array substrate, a dimming panel, and a display device. Figure 1 is a structural schematic diagram of the 2*2 pixel electrodes in the array substrate provided in this disclosure embodiment; Figure 2 is a magnified structural schematic diagram of the Z region in Figure 1; Figure 3 is a schematic diagram of the wide-viewing-angle display of the dimming panel provided in this disclosure embodiment; Figure 4 is a cross-sectional structural schematic diagram along line I-I' in Figure 1; Figure 5 is a cross-sectional structural schematic diagram along line II-II' in Figure 1; Figure 6 is a cross-sectional structural schematic diagram along line III-III' in Figure 1; Figure 7 is a structural schematic diagram of the layer containing the pixel electrodes in Figure 1; Figure 8 is a structural schematic diagram of the layer containing the gate lines in Figure 1; Figure 9 is a structural schematic diagram of the active layer in Figure 1; Figure 10 is a structural schematic diagram of the layer containing the data lines in Figure 1; Figure 11 is a structural schematic diagram of the layer containing the vias in Figure 1; and Figure 12 is a structural schematic diagram of the layer containing the common electrode in Figure 1. As shown in Figures 1 to 12, the array substrate provided in this disclosure embodiment may include:

[0068] Optionally, the substrate 101 is a substrate that allows visible light to pass through, such as being made of glass, quartz, plastic, or other materials.

[0069] Multiple pixel electrodes 102 are arranged in an array on a substrate 101, with each pair of pixel electrodes 102 arranged along the row direction X forming a pixel electrode group P. In some embodiments, brightness adjustment can be performed on a unit of pixel electrode group P, and a pixel electrode group P can correspond to a pixel PX of the display panel (which may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel). Optionally, the array substrate of this disclosure may also include a common electrode 103, where one of the pixel electrode 102 and the common electrode 103 can be a block electrode, and the other is a slit electrode. The slit of the slit electrode can have multiple extending directions, thereby forming multiple domain regions with different orientations to improve the display effect. The materials of the pixel electrode 102 and the common electrode 103 include, but are not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO).

[0070] Multiple data lines 104 extend at the column gaps between two pixel electrodes 102 within the pixel electrode group P. Each data line 104 may include a zigzag portion with the same extension trend as the slit electrode. The material used for the data lines 104 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). In some embodiments, the layer containing the data lines 104 may be a single-layer structure or a multilayer structure. For example, the layer containing the data lines 104 may be a multilayer structure composed of a molybdenum metal layer, an aluminum metal layer, and a molybdenum metal layer.

[0071] Multiple transistors 105 are provided. The gate g of each transistor 105 is integrally disposed with the gate line 106. The first electrode d of each transistor 105 is electrically connected to the pixel electrode 102 through a first via V1. Optionally, a transition electrode 111 on the same layer as the common electrode 103 is provided at the first via V1. The first via V1 passes through a first insulating layer 108 and a second insulating layer 109 at the point where it overlaps with the pixel electrode 102. The second insulating layer 109 passes through the first via V1 at the point where it overlaps with the first electrode d1 of the transistor 105, so that the pixel electrode 102 is electrically connected to the first electrode d of the transistor 105 through the transition electrode 111 at the first via V1. The second electrode s of each transistor 105 is integrally disposed with the data line 104. Two pixel electrodes 102 of the same pixel electrode group P are electrically connected to the first electrodes d of different transistors 105. The gate g of the two transistors 105 electrically connected in the same pixel electrode group P is multiplexed. The second electrodes s of the two transistors 105 electrically connected in the same pixel electrode group P are electrically connected to the same data line 104. Transistor 105 can be a bottom-gate transistor, a top-gate transistor, or a dual-gate transistor. The active layer s material of transistor 105 can be monocrystalline silicon a-si, polycrystalline silicon poly, indium gallium zinc oxide IGZO, etc.

[0072] In the array substrate provided in this embodiment, the three RGB sub-pixels (Dots) of the relevant Sub Cell are merged into a single pixel electrode group P. Data lines 104 are only provided between the two pixel electrodes 102 contained in pixel electrode group P. This reduces the number of data lines 104 to one-third of that in related products, increasing the pixel aperture ratio from 66.2% to 79.5%, significantly improving brightness at wide viewing angles. For example, at a 45° wide viewing angle, the viewing angle brightness increases from 47% to 53%. Furthermore, by saving two-thirds of the data lines 104, this disclosure reduces the use of key circuit materials such as the COF (Chip-on-Foil) film electrically connected to the data lines 104, lowering the cost of the display module. Additionally, this disclosure uses two transistors 105 sharing a common gate g to charge the two pixel electrodes 102 of pixel electrode group P, which improves the pixel charging rate reduction problem caused by the increased area of ​​the pixel electrodes 102 after merging the three RGB sub-pixels (Dots), thus improving pixel voltage uniformity.

[0073] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG2, the gate g of the two transistors 105 electrically connected to the same pixel electrode group P includes a central axis MM' extending along the column direction Y; the first electrode d of the two transistors 105 electrically connected to the same pixel electrode group P can be approximately symmetrical about the central axis MM', and the second electrode s of the two transistors 105 electrically connected to the same pixel electrode group P can also be approximately symmetrical about the central axis MM'; that is, the two transistors 105 electrically connected to the pixel electrode group P in this disclosure are symmetrically arranged. This can satisfy the simultaneous activation of the two transistors 105 electrically connected to the same pixel electrode group P, ensuring the brightness uniformity of the pixel electrode group P. It is understood that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "approximate symmetry" may be completely symmetrical or may have some deviation. Therefore, as long as the "approximate symmetry" relationship between the above features meets the allowable error, it is within the protection scope of this disclosure.

[0074] In some embodiments, in the array substrate provided in the present disclosure, the orientation and size of the transistor 105 can be flexibly set according to wiring space, charging rate requirements, etc. Figures 2, 13, and 14 respectively show a schematic diagram of a structure of the transistor 105 of the present disclosure. As shown in Figures 2, 13, and 14, the second electrode s of the transistor 105 can be a "U"-shaped structure, which can make reasonable use of space to increase the channel width-to-length ratio of the transistor 105 and improve the charging rate. Optionally, when the horizontal wiring space is sufficient and the vertical wiring space is limited, as shown in Figure 2, in two transistors 105 electrically connected in the same pixel electrode group P, the openings of the two "U"-shaped structures are opposite to each other in the row direction X, the bottoms of the two "U"-shaped structures are reused, and the first electrode d of the transistor 105 extends from the opening of the "U"-shaped structure toward the direction away from the "U"-shaped structure. When vertical wiring space is sufficient but horizontal wiring space is limited, as shown in Figure 13, the openings of the two "U"-shaped structures in the two transistors 105 electrically connected to the same pixel electrode group P can be positioned away from the gate line 106, and the adjacent sidewalls of the two "U"-shaped structures can be reused. When both horizontal and vertical wiring spaces are limited, as shown in Figure 14, the openings of the two "U"-shaped structures in the two transistors 105 electrically connected to the same pixel electrode group P can be positioned facing the electrically connected pixel electrode 102, and the two "U"-shaped structures can be tilted relative to the central axis MM'.

[0075] Referring to Figures 2 and 13, to simplify the design, the first electrode d of transistor 105 can be set to extend from the opening of the "U"-shaped structure in a direction away from the "U"-shaped structure. Furthermore, to ensure electrical connection, the first electrode d of transistor 105 can be widened at the first via V1 that overlaps with the pixel electrode 102. Referring to Figure 14, to effectively utilize space, the first electrode d of transistor 105 can be configured to include a first portion d1, a second portion d2, and a third portion d3 connected sequentially. At least a portion of the first portion d1 is located within the opening of the "U"-shaped structure, and the extension direction of the first portion d1 is approximately the same as the extension direction of the sidewall of the "U"-shaped structure (e.g., the angle between their extension directions is 0° to 5°). The second portion d2 extends along the column direction Y, and the third portion d3 extends along the row direction X. Optionally, an obtuse angle is formed between the first portion d1 and the second portion d2; and / or, the second portion d2 and the third portion d3 are approximately perpendicular (e.g., the angle between them is 85° to 95°).

[0076] In some embodiments, in the array substrate provided in the present disclosure, FIG15 shows another structural schematic diagram at the 2*2 pixel electrodes, FIG16 is a structural schematic diagram of the layer where the gate lines are located in FIG15, and FIG17 is a structural schematic diagram of the layer where the data lines are located in FIG15. The structures of the pixel electrode layer, the active layer, and the common electrode layer in FIG15 can be referred to FIG7, 9, and 12. As can be seen from FIG15 to FIG17, the array substrate of the present disclosure may further include multiple first common electrode lines 107 disposed on the same layer as the multiple data lines 104. The first common electrode lines 107 may extend at the column gaps of adjacent pixel electrode groups P, and the first common electrode lines 107 may be electrically connected to the common electrode 103 through the second via V2 penetrating the second insulating layer 109. In the embodiment shown in Figure 1, the layer containing the gate line 106 can have multiple second common electrode lines 110. The second common electrode lines 110 extend at the row gaps between adjacent pixel electrodes 102, and the second common electrode lines 110 can be electrically connected to the common electrode 103 through a third via V3 penetrating the first insulating layer 108 and the second insulating layer 109. Compared to the embodiment shown in Figure 1, the embodiment shown in Figure 15 makes full use of the gaps in the pixel electrode group P to arrange the first common electrode lines 107, saving the wiring space of the second common electrode lines 110 and improving the pixel aperture ratio; at the same time, the first common electrode lines 107 connect the common electrodes 103 of two adjacent rows together, which also helps to improve the uniformity of the common voltage.

[0077] Of course, in some embodiments, this disclosure may also add a metal layer to provide common electrode lines. Specifically, in the array substrate provided in the embodiments of this disclosure, multiple third common electrode lines may be included between the layer containing the multiple data lines 104 and the layer containing the common electrode 103. The orthographic projection of the third common electrode line on the substrate 101 may overlap with the orthographic projection of the data line 104 on the substrate 101. For example, the orthographic projection of the third common electrode line on the substrate 101 may cover the orthographic projection of the data line 104 on the substrate 101, and the orthographic projection of the third common electrode line on the substrate 101 may not overlap with the pixel aperture area. In this way, the third common electrode lines can be used to connect the common electrodes 103 in two adjacent rows, improving the uniformity of the common voltage. At the same time, since the second common electrode line 110 can be saved, the third common electrode line does not occupy the pixel aperture area, thus also helping to improve the pixel aperture ratio.

[0078] In some embodiments, this disclosure also provides a method for fabricating the array substrate shown in FIG1 above, as shown in FIG18, which may specifically include the following steps:

[0079] The first step involves a process of coating → exposure → development → coating → exposure → development → wet etching to form an ITO material with a thickness of [missing information]. Pixel electrode 102.

[0080] The second step involves a process of coating, exposure, development, and wet etching to form a Mo / Al / Mo material with a thickness of [missing information]. The gate g, gate line 106, and second common electrode line 110.

[0081] The third step is to set the thickness of the entire layer on the layer containing gate line 106 to be [value missing]. The first insulating layer 108 is made of SiNx.

[0082] The fourth step involves a process of coating, exposure, development, and etching to form a film with a thickness of [thickness value missing]. The active layer s is made of a-Si material.

[0083] Step 5: Through the processes of coating → exposure → development → wet etching, a material of Mo / Al / Mo with a thickness of [missing information] is formed. The first pole d, the second pole s, and the data line 104.

[0084] The sixth step involves a coating exposure → development → etching process to form a film with a thickness of [thickness value missing]. The second insulating layer 109 is made of SiNx and includes a first via V1 connecting the first electrode d and the pixel electrode 102, and a third via V3 connecting the second common electrode line 110 and the subsequent common electrode 103.

[0085] The seventh step involves a process of coating, exposure, development, and wet etching to form an ITO material with a thickness of [missing information]. The common electrode 103, and the adapter electrode 111 connecting the first electrode d and the pixel electrode 102.

[0086] It should be noted that in the fabrication method provided in the embodiments of this disclosure, the patterning process involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and is not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0087] Based on the same inventive concept, this disclosure provides a dimming panel. Figure 19 is a structural schematic diagram of the area where a pixel electrode group is located in the dimming panel; Figure 20 is a structural schematic diagram of the area where a light-shielding pattern is located in the dimming panel; Figure 21 is a cross-sectional structural schematic diagram along line IV-IV' in Figure 19; Figure 22 is a cross-sectional structural schematic diagram along the spliced ​​cross-section of lines V-V' and V'-V'' in Figure 19; and Figure 23 is a cross-sectional structural schematic diagram along line VI-VI' in Figure 19. As can be seen from Figures 19 to 23, the dimming panel provided in this disclosure includes an array substrate 001 and a facing substrate 002 placed opposite each other. The array substrate 001 is the array substrate 001 provided in this disclosure. Since the principle of solving the problem by this dimming panel is similar to the principle of solving the problem by the array substrate 001, the implementation of this dimming panel can refer to the embodiment of the array substrate 001, and the repeated parts will not be described again.

[0088] In some embodiments, as shown in Figures 19 to 22, the common electrode 103 in this disclosure can be a slit electrode. Compared to the width of the common electrode 103 between the two slits overlapping with the same pixel electrode 102, the common electrode 103 is widened on the side overlapping with the data line 104 and completely covers the data line 104, so as to shield the influence of the pixel electrode 102 and the data line 104, etc.

[0089] In some embodiments, as shown in Figures 19 to 23, the opposing substrate 002 includes a substrate 201 and a light-shielding pattern 202 located on the side of the substrate 201 facing the array substrate 001. The orthographic projection of the light-shielding pattern 202 on the substrate 101 does not overlap with the orthographic projection of the data line 104 between adjacent transistors 105 in the column direction Y on the substrate 101. The orthographic projection of the light-shielding pattern 202 on the substrate 101 does not overlap with the orthographic projection of the gate line 106 between adjacent transistors 105 in the row direction X on the substrate 101. The orthographic projection of the light-shielding pattern 202 on the substrate 101 overlaps with the orthographic projection of the transistor 105 on the substrate 101. The light-shielding pattern 202 covers the first via V1 and the third via V3. That is, the light-shielding pattern 202 blocking the position of the transistor 105 or exceeding the position of the transistor 105 and overlapping with part of the gate line 106 and part of the data line 104 are all within the protection scope of this application. Compared to a mesh-like light-shielding layer that completely covers the data line 104, transistor 105, gate line 106, first via V1, and third via V3, this disclosure provides a light-shielding pattern 202 that only covers transistor 105, first via V1, and third via V3, which can effectively improve transmittance. It should be understood that in the embodiment shown in FIG. 15 of this disclosure, where the first common electrode line 107 is provided, the light-shielding pattern 202 can only cover transistor 105, first via V1, and second via V2 to improve transmittance.

[0090] Based on the same inventive concept, this disclosure provides a display device. Figure 24 is a structural schematic diagram of a display unit (which may include a pixel electrode group P shown in Figure 19 and a pixel PX shown in Figure 15) in the display device provided in this disclosure embodiment. Figure 25 is a structural schematic diagram of a pixel in the display panel of Figure 24. Figure 26 is a structural schematic diagram of the array substrate included in the display panel of Figure 25. Figure 27 is a structural schematic diagram of the black matrix included in the display panel of Figure 25. Figure 28 is a cross-sectional structural schematic diagram along line VII-VII' in Figure 24. As can be seen from Figures 24 to 28, the display device of this disclosure may include a display panel PNL and a dimming panel LDP stacked together, wherein the dimming panel LDP is the dimming panel LDP provided in the embodiments of this disclosure. Since the principle of solving the problem by this display device is similar to the principle of solving the problem by the array substrate 001 described above, the implementation of this display device can refer to the embodiments of the array substrate 001 described above, and the repeated parts will not be described again.

[0091] In some embodiments, in the display device provided in the present disclosure, as shown in Figures 24 to 28, the display panel PNL includes a plurality of pixels PX arranged in an array. Pixels PX can be stacked one-to-one with pixel electrode groups P. When a pixel PX includes red sub-pixels, green sub-pixels, and blue sub-pixels, the pixel electrode group P and the sub-pixels have a 1:3 correspondence. In some embodiments, the orthographic projection of the data line 104 on the substrate 101 overlaps with the central region of the pixel PX. Optionally, the orthographic projection of the data line 104 on the substrate 101 overlaps with the orthographic projection of the central axis NN' of the pixel PX extending along the column direction Y on the substrate 101. Furthermore, the orthographic projection of the data line 104 on the substrate 101 can overlap with the orthographic projections of at least some sub-pixels on the substrate 101. In some embodiments, the display panel PNL includes a black matrix BM with a grid structure. The orthographic projection of the black matrix BM on the substrate 101 does not overlap with the orthographic projection of the data line 104 between adjacent transistors 105 in the column direction Y on the substrate 101.

[0092] In some embodiments, as shown in Figures 25 and 26, the display panel PNL of this disclosure may also include an array substrate and a counter substrate. The array substrate of the display panel PNL includes a first electrode PE and a second electrode CE for forming a control of liquid crystal rotation. Optionally, the first electrode PE is a pixel electrode, and the second electrode CE is a common electrode. The array substrate of the display panel PNL may also include a first signal line SL (e.g., a data line), a second signal line GL (e.g., a gate line), a switch T (e.g., a transistor), and a third signal line CL (e.g., a common electrode line). Under the control of the second signal line GL (e.g., the gate line), the voltage of the first signal line SL (e.g., the data line) is written to the first electrode PE through the switch T (e.g., the transistor), and a common voltage is applied to the second electrode CE using the third signal line CL (e.g., the common electrode line). Other essential components of the display panel PNL are those that should be understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting the present disclosure.

[0093] In some embodiments, the display panel PNL may further include color resist, while the dimming panel LDP does not have color resist. The display device may further include a backlight module BLU, and the dimming panel LDP may be located between the backlight module BLU and the display panel PNL, or the display panel PNL may be located between the dimming panel LDP and the backlight module BLU. This disclosure illustrates the example of the dimming panel LDP being located between the backlight module BLU and the display panel PNL.

[0094] In some embodiments, the backlight module (BLU) disclosed herein can be a direct-lit backlight module or an edge-lit backlight module. Optionally, an edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism assemblies, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot LEDs (QLEDs) or micro-light-emitting devices (e.g., Mini LEDs, Micro LEDs).

[0095] Among them, micro-light-emitting devices at the sub-millimeter or even micrometer scale, like organic light-emitting devices (OLEDs), belong to the category of self-emissive devices. Like OLEDs, they possess a series of advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices achieve light emission based on more stable and lower-resistance metal semiconductors, they offer advantages over OLEDs based on organic materials, including lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0096] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0097] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0098] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple pixel electrodes are arranged in an array on the substrate, and each pair of pixel electrodes arranged along the row direction constitutes a pixel electrode group. Multiple data lines extend at the column gap between two pixel electrodes within the pixel electrode group; Multiple transistors, two pixel electrodes of the same pixel electrode group are electrically connected to the first electrodes of different transistors, the gates of two transistors electrically connected to the same pixel electrode group are multiplexed, and the second electrodes of two transistors electrically connected to the same pixel electrode group are electrically connected to the same data line.

2. The array substrate as claimed in claim 1, wherein, The gates of two transistors electrically connected to the same pixel electrode group include a central axis extending along the column direction; The first electrodes of the two transistors electrically connected to the same pixel electrode group are approximately symmetrical about the central axis, and the second electrodes of the two transistors electrically connected to the same pixel electrode group are approximately symmetrical about the central axis.

3. The array substrate as described in claim 1 or 2, wherein, The second electrode of the transistor is a "U" shaped structure.

4. The array substrate as claimed in claim 3, wherein, In the two transistors electrically connected to the same pixel electrode group, the openings of the two "U"-shaped structures are arranged opposite to each other in the row direction, and the bottoms of the two "U"-shaped structures are reused.

5. The array substrate as claimed in claim 3, wherein, It also includes a gate line extending at the row gap between adjacent pixel electrodes, the gate of the transistor being electrically connected to the gate line; In the two transistors electrically connected in the same pixel electrode group, the openings of the two "U"-shaped structures are located away from the gate line, and the adjacent sidewalls of the two "U"-shaped structures are reused.

6. The array substrate as claimed in claim 4 or 5, wherein, The first electrode of the transistor extends from the opening of the "U"-shaped structure toward a direction away from the "U"-shaped structure.

7. The array substrate as claimed in claim 3, wherein, In the two transistors electrically connected to the same pixel electrode group, the openings of the two "U"-shaped structures face the electrically connected pixel electrodes, and the two "U"-shaped structures are inclined relative to the central axis.

8. The array substrate as claimed in claim 7, wherein, The first electrode of the transistor comprises a first part, a second part, and a third part connected in sequence; wherein... At least a portion of the first part is located within the opening of the "U"-shaped structure, and the extension direction of the first part is approximately the same as the extension direction of the sidewall of the "U"-shaped structure. The second part extends along the column direction, and the third part extends along the row direction.

9. The array substrate as claimed in claim 8, wherein, The first portion and the second portion form an obtuse angle; and / or, the second portion is substantially perpendicular to the third portion.

10. The array substrate according to any one of claims 1 to 9, wherein, It also includes multiple first common electrode lines disposed on the same layer as the multiple data lines, the first common electrode lines extending at the column gaps between adjacent pixel electrode groups.

11. The array substrate according to any one of claims 1 to 10, wherein, It also includes gate lines and multiple second common electrode lines disposed on the same layer as the gate lines, the second common electrode lines extending at the row gaps between adjacent pixel electrodes.

12. The array substrate according to any one of claims 1 to 11, wherein, It also includes multiple third common electrode lines located on the side of the layer where the multiple data lines are located away from the substrate, and the orthographic projection of the third common electrode lines on the substrate overlaps with the orthographic projection of the data lines on the substrate.

13. A dimming panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 12.

14. The dimming panel as claimed in claim 13, wherein, The opposing substrate includes a light-shielding pattern, the orthographic projection of the light-shielding pattern on the substrate and the orthographic projection of the data line between adjacent transistors in the column direction on the substrate do not overlap.

15. The dimming panel as claimed in claim 13 or 14, wherein, The opposing substrate includes a light-shielding pattern, the orthographic projection of the light-shielding pattern on the substrate and the orthographic projection of the gate line between adjacent transistors in the row direction on the substrate do not overlap.

16. The dimming panel as claimed in claim 14 or 15, wherein, The orthographic projection of the light-shielding pattern on the substrate overlaps with the orthographic projection of the transistor on the substrate.

17. A display device, wherein, It includes a display panel and a dimming panel stacked together, wherein the dimming panel is the dimming panel as described in any one of claims 13 to 16.

18. The display device as claimed in claim 17, wherein, The display panel includes multiple pixels arranged in an array, and the orthographic projection of the data line on the substrate overlaps with the central region of the pixel.

19. The display device as claimed in claim 18, wherein, The orthographic projection of the data line on the substrate overlaps with the orthographic projection of the central axis of the pixel extending along the column direction on the substrate.

20. The display device as claimed in claim 18 or 19, wherein, The pixel includes multiple sub-pixels, and the orthographic projection of the data line on the substrate overlaps with the orthographic projection of at least some of the sub-pixels on the substrate.

21. The display device according to any one of claims 18 to 20, wherein, The pixel electrode group is stacked in a one-to-one correspondence with the pixel.

22. The display device according to any one of claims 17 to 21, wherein, The display panel includes a black matrix, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the data lines between adjacent transistors in the column direction on the substrate.

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