Clock regeneration circuit and serial data transmission device

Abstract

This clock regeneration circuit generates, using the frequency division ratio of a frequency divider in a phase loop lock circuit, a regeneration clock to be used at a timing when data is outputted from a buffer for buffering received data. The clock regeneration circuit comprises: a counter that counts up a count value in response to reception of the data and counts down the count value in response to the regeneration clock; a lag lead filter that executes lag lead filter processing on the count value from the counter so as to amplify a gain in a low frequency band of a control band of a transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value on which the lag lead filter processing has been executed and calculates the frequency division ratio of the frequency divider on the basis of the count value after the predetermined calculation. Consequently, the clock regeneration circuit capable of suppressing jitter of the regeneration clock is provided.

Description

Clock recovery circuit and serial data transmission device

[0006]

[0001] The present disclosure relates to a clock recovery circuit and a serial data transmission device.

[0002] In recent years, serial data transmission devices having a FIFO (First In, First Out) type data buffer for buffering received data are known. The serial data transmission device is daisy-chain connected to another serial data transmission device and serially transmits the data buffered in the data buffer to the other serial data transmission device by a time-division multiplexing method. Further, a clock recovery circuit in the serial data transmission device generates a reproduction clock used when outputting the data buffered in the data buffer.

[0003] In a serial data transmission device, when a plurality of serial data transmission devices are daisy-chain connected and serial data is transmitted to another serial data transmission device, the data can be multiplexed by a time-division multiplexing method while dynamically switching the bandwidth and the data transmission path. Further, in the serial data transmission device, the failure stability can be enhanced.

[0004] Japanese Patent Application Laid-Open No. 2009-20905 International Publication No. 2019 / 111554

[0005] However, in a conventional clock recovery circuit, the reproduction clock fluctuates, and the fluctuation of the reproduction clock becomes an obstacle to the daisy-chain operation.

[0006] Therefore, the present disclosure proposes a clock recovery circuit and a serial data transmission device capable of suppressing the fluctuation of the reproduction clock.

[0007] According to this disclosure, a clock regeneration circuit is provided that generates a regeneration clock used for timing the output of data from a buffer that buffers received data, using the division ratio of a frequency divider in a phase loop lock circuit, the clock regeneration circuit comprising: a counter that counts up a count value in response to the reception of the data and counts down the count value in response to the regeneration clock; a lag-read filter that performs lag-read filtering on the count value from the counter to amplify the gain in the low-frequency band of the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the lag-read filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation.

[0008] Furthermore, according to this disclosure, a serial data transmission device is provided, comprising: a receiving unit that receives data transmitted serially by time division multiplexing in a daisy-chain configuration with other devices; a transmitting unit that serially transmits data by time division multiplexing in a daisy-chain configuration with other devices; a buffer that buffers the data received by the receiving unit and outputs the buffered data to the transmitting unit according to a regeneration clock; and a clock regeneration circuit that generates the regeneration clock using the division ratio of a frequency divider in a phase loop lock circuit, wherein the clock regeneration circuit comprises: a counter that counts up a count value in response to the reception of the data and counts down the count value according to the regeneration clock; a lag-read filter that performs lag-read filtering on the count value from the counter so as to amplify the gain in the low-frequency band of the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the lag-read filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation.

[0009] This is a block diagram showing an example of a serial data transmission device according to this embodiment. This is a block diagram showing an example of a clock regeneration circuit according to the first embodiment. This is a Bode plot showing an example of gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit according to the first embodiment. This is a Bode plot showing an example of gain characteristics and data counter fluctuation characteristics related to the transfer function of the clock regeneration circuit according to the first embodiment. This is an explanatory diagram showing an example of frequency change of the regenerated clock by the multiplier of the clock regeneration circuit of the comparative example. This is a block diagram showing an example of a clock regeneration circuit according to the second embodiment. This is an explanatory diagram showing an example of frequency change of the regenerated clock by the multiplier of the clock regeneration circuit according to the second embodiment. This is a Bode plot showing an example of gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit according to the second embodiment. This is a block diagram showing an example of a clock regeneration circuit according to the third embodiment. This is a Bode plot showing an example of gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit according to the third embodiment. This is a Bode plot showing an example of gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit of the comparative example. This is an explanatory diagram showing an example of the relationship between the count value and the amount of data stored in the clock regeneration circuit of the comparative example. This is an explanatory diagram showing an example of the relationship between the amount of jitter of the reference clock of the fractional PLL circuit in the clock regeneration circuit of the comparative example and the frequency of the regenerated clock. This Bode plot shows an example of the gain characteristics and data counter fluctuation characteristics related to the transfer function of the clock regeneration circuit in the comparative example.

[0010] Preferred embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0011] The explanation will be given in the following order: 1. First Embodiment 1.1. Overview 1.2. Configuration and Operation Examples 2. Second Embodiment 2.1. Overview 2.2. Configuration and Operation Examples 3. Third Embodiment 3.1. Overview 3.2. Configuration and Operation Examples 4. Summary

[0012] <1. First Embodiment> <1.1. Overview> First, an overview of the first embodiment of this disclosure will be described. In recent years, serial data transmission devices have been known that include a receiving unit, a data buffer, a transmitting unit, and a clock regeneration circuit, and are daisy-chained with other serial data transmission devices to send and receive data transmitted serially using a time-division multiplexing scheme. The receiving unit is daisy-chained with other serial data transmission devices and receives data transmitted serially from other serial data transmission devices using a time-division multiplexing scheme. The data buffer is a FIFO (First In, First Out) type buffer that buffers the data received by the receiving unit. The transmitting unit is daisy-chained with other serial data transmission devices and serially transmits the data buffered in the data buffer to other serial data transmission devices using a time-division multiplexing scheme.

[0013] Furthermore, the clock regeneration circuit generates a regeneration clock used when outputting data buffered in the data buffer. The clock regeneration circuit includes a frequency division ratio calculation circuit and a fractional PLL (Phase Locked Loop) circuit, and the fractional PLL circuit generates the regeneration clock based on the frequency division ratio calculated by the frequency division ratio calculation circuit.

[0014] The frequency division ratio calculation circuit comprises a data counter and an arithmetic unit. The data counter is a counter that increments its count value at the timing of data reception by the receiving unit and counts down its count value at the timing of the regeneration clock. The arithmetic unit calculates the frequency division ratio of the fractional frequency divider of the fractional PLL circuit from the value obtained by calculating the count value of the data counter. The arithmetic unit comprises a multiplier that multiplies the count value by a predetermined gain correction value and an adder that adds a reference value to the multiplied count value, and calculates the frequency division ratio from the added count value.

[0015] In the clock regeneration circuit, the count value is incremented by the number of received data points, and the regeneration clock is used to decrement the count value. The clock regeneration circuit multiplies the count value by a predetermined gain correction value, adds a predetermined reference value to the multiplied count value, and then sets the resulting count value to the division ratio of the fractional frequency divider. The voltage-controlled oscillator in the fractional PLL circuit then generates a regeneration clock so that the count value becomes constant, that is, a regeneration clock that matches the data arrival period is obtained.

[0016] In serial data transmission devices, when multiple serial data transmission devices are daisy-chained and serial data is transmitted to other serial data transmission devices, data can be multiplexed using time-division multiplexing while dynamically switching bandwidth and data transmission paths. Furthermore, serial data transmission devices can improve fault stability.

[0017] Furthermore, in a clock regeneration circuit, for example, if the regeneration clock is slower than the data arrival at the data buffer, the count value increases and the frequency of the regeneration clock increases. Conversely, in a clock regeneration circuit, for example, if the regeneration clock is faster than the data arrival at the data buffer, the count value decreases and the frequency of the regeneration clock decreases. As a result, the serial data transmission device can output data seamlessly in accordance with the regeneration clock without data overflowing from the data buffer.

[0018] However, in a clock regeneration circuit, phase noise in the low-frequency range of the reference clock used in the phase comparator within the fractional PLL circuit causes fluctuations in the regenerated clock, and these fluctuations in the regenerated clock interfere with daisy-chain operation. Therefore, a clock source capable of generating a low-jitter reference clock using a crystal is required.

[0019] Therefore, we consider the loop transfer function of the control loop from generating a regenerative clock in response to the update of the count value in the clock regeneration circuit, to updating the count value in response to the generated regenerative clock. Figure 11 is a Bode plot showing an example of the gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit of the comparative example. The gain characteristics of the transfer function have a linear integral structure as shown in Figure 11.

[0020] The control bandwidth is determined by the loop gain, and as shown in the phase characteristics of the transfer function in Figure 11, the phase margin corresponding to the gain crossover frequency, which is the frequency at which the gain becomes zero, is always 90 degrees. As a result, by ensuring a phase margin of 90 degrees at all times, a stable control loop can be constructed, and stable operation can be achieved.

[0021] In the comparative example's clock regeneration circuit, the count value of the data counter used to generate the regeneration clock fluctuates according to the amount of data buffered in the data buffer. Therefore, the range of fluctuation in the data counter's count value is limited to at most the maximum amount of data buffered. Figure 12 is an explanatory diagram showing an example of the relationship between the count value and the amount of data stored in the comparative example's clock regeneration circuit. In other words, in order to continuously output data, the count value must be kept within (± maximum amount of data / 2).

[0022] However, in the comparative example's clock regeneration circuit, the count value must be kept within (± maximum storage amount / 2), which restricts the frequency range in which the regeneration clock can be adjusted. The frequency of the regeneration clock is (reference clock frequency × division ratio) = {reference clock frequency × (count value × gain correction value + reference value)}. As long as the count value is within the range of (± maximum storage amount / 2), the regeneration clock can only change up to the reference clock frequency × (± maximum storage amount / 2 × gain correction value + reference value) at its maximum. In other words, in the comparative example's clock regeneration circuit, the count value must be kept within the range of (± maximum storage amount / 2), so the frequency range in which the regeneration clock frequency can be changed cannot be widened.

[0023] Figure 13 is an explanatory diagram showing an example of the relationship between the amount of jitter of the reference clock in the fractional PLL circuit within the comparative example's clock regeneration circuit and the frequency of the regenerated clock. In the comparative example's clock regeneration circuit, the clock source that oscillates the reference clock used in the fractional PLL circuit has thermal noise, so the amount of jitter of the reference clock takes on a first-order integral structure as shown in Figure 13.

[0024] Figure 14 is a Bode plot showing an example of the gain characteristics and data counter fluctuation characteristics related to the transfer function of the comparative example clock regeneration circuit. Here, the gain characteristics of the loop transfer function have a first-order integral structure. The amount of jitter in the reference clock is suppressed by the amount of the gain in the frequency band with positive gain. As a result, as shown in Figure 14, the remaining amount of jitter affects the count value of the data counter and leads to fluctuations in the data counter. Therefore, a method to improve the jitter tolerance of the regenerated clock is required. Accordingly, in the comparative example clock regeneration circuit, a high-precision clock source that oscillates the reference clock is required to improve the jitter tolerance of the regenerated clock.

[0025] Therefore, in the first embodiment, a clock regeneration circuit and serial data transmission device are provided that not only suppress fluctuations in the regeneration clock but also widen the frequency range over which the regeneration clock's frequency is varied, while improving the jitter tolerance of the regeneration clock.

[0026] <1.2. Configuration and Operation Examples> Figure 1 is a block diagram showing an example of a serial data transmission device 1 according to this embodiment. Each serial data transmission device 1 connected in a daisy-chain configuration as shown in Figure 1 has a receiving unit 2, a transmitting unit 3, a data buffer 4, and a clock regeneration circuit 5. The serial data transmission device 1 is a transmission device that transmits and receives data transmitted serially using a time-division multiplexing method when connected in a daisy-chain configuration with other serial data transmission devices 1.

[0027] The receiving unit 2 is a serial receiving unit that receives data from the preceding serial data transmission device 1, which is daisy-chained, using a time-division multiplexing method.

[0028] The data buffer 4 buffers the data received by the receiving unit 2, for example, the data destined for the subsequent serial data transmission device 1. The data buffer 4 is a FIFO (First In, First Out) type data buffer that outputs the buffered data to the transmitting unit 3 in a FIFO manner. In other words, the data buffer 4 buffers the data to be output to the transmitting unit 3 from the data received by the receiving unit 2, and outputs the buffered data to the transmitting unit 3 based on the regenerated clock generated by the clock regeneration circuit 5.

[0029] The transmission unit 3 is a serial transmission unit that serially transmits data for the daisy-chained downstream serial data transmission device 1, i.e., data buffered in the data buffer 4, using a time-division multiplexing method.

[0030] Figure 2 is a block diagram showing an example of a clock regeneration circuit 5 according to the first embodiment. The clock regeneration circuit 5 shown in Figure 2 includes a frequency division ratio calculation circuit 10 and a fractional PLL (Phase Locked Loop) circuit 20. The frequency division ratio calculation circuit 10 calculates the frequency division ratio of the output clock to be used in the fractional PLL circuit 20 and sets the calculated frequency division ratio in the fractional frequency divider 21 within the fractional PLL circuit 20. The fractional PLL circuit 20 is a PLL circuit that generates a regeneration clock based on a reference clock and the output clock after frequency division.

[0031] The fractional PLL circuit 20 includes a fractional frequency divider 21, a PFD (Phase Frequency Detector) 22, a CP (Charge Pump) 23, and a VCO (Voltage Controlled Oscillator) 24.

[0032] The fractional frequency divider 21 divides the output clock, which is a regenerated clock generated by the VCO 24, based on the frequency division ratio obtained from the frequency division ratio calculation circuit 10, and inputs the divided output clock to the PFD 22.

[0033] PFD22 is a phase comparator that calculates the phase difference between a reference clock from a clock source (not shown) and the output clock after division by the fractional divider 21, and outputs the calculated phase difference to CP23. CP23 is a charge pump circuit that generates a control voltage according to the phase difference from PFD22. VCO24 is a voltage-controlled oscillator that generates a regenerated clock by changing the oscillation frequency according to the control voltage from CP23, and outputs the generated regenerated clock to the data buffer 4, the data counter 11 (described later), and the fractional divider 21.

[0034] The frequency division ratio calculation circuit 10 includes a data counter 11, a lag-read filter 12, a multiplier 13, and an adder 14. First, the data buffer 4 buffers the received data from the receiving unit 2 and outputs the buffered data to the transmitting unit 3 according to the regenerated clock received from the fractional PLL circuit 20.

[0035] The data counter 11 is a counter that, when it receives data from the receiving unit 2, increments a count value indicating the number of data to be buffered in the data buffer 4, and counts down the count value in accordance with the regeneration clock from the fractional PLL circuit 20.

[0036] The lag-read filter 12 performs lag-read filtering on the count value from the data counter 11 to amplify the gain in the low-frequency band of the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock, as described later. The lag-read filter 12 outputs the count value after lag-read filtering to the multiplier 13. The multiplier 13 is, for example, an arithmetic unit that multiplies the count value after lag-read filtering by a predetermined gain correction value and outputs the multiplied count value to the adder 14.

[0037] The adder 14 is, for example, an arithmetic unit that adds a predetermined reference value to the count value after multiplication, calculates the count value after addition as a frequency division ratio, and sets the calculated frequency division ratio to the fractional frequency divider 21. Note that when the frequency division ratio of the fractional frequency divider 21 increases, the frequency of the regenerated clock increases. Also, when the frequency division ratio of the fractional frequency divider 21 decreases, the frequency of the regenerated clock decreases.

[0038] Figure 3 is a Bode plot showing an example of the gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit 5 in the first embodiment. The control loop of the transfer function of the clock regeneration circuit 5 is a control loop that generates a regeneration clock in response to the update of the count value in the clock regeneration circuit 5, and updates the count value in response to the generated regeneration clock. The control bandwidth of the clock regeneration circuit 5 is the frequency bandwidth of the regeneration clock that can be controlled by adjusting the gain on the positive side. The lag-read filtering of the lag-read filter 12 amplifies the gain in the low-frequency band within the control bandwidth, as shown in Figure 3.

[0039] The lag-lead filter processing of the lag-lead filter 12 amplifies the gain in the low-frequency range within the control band, resulting in a smaller phase margin in the low-frequency range. Therefore, to ensure sufficient phase margin, the zero-point frequency within the filter frequency range of the lag-lead filter 12 is adjusted. In other words, to ensure sufficient phase margin, the zero-point frequency of the lag-lead filter 12 is set to the low-frequency range within the loop band (control band), thereby ensuring a phase margin corresponding to the gain crossover frequency.

[0040] In the lag-read filter processing of the lag-read filter 12, the configuration is such that the gain in the low-frequency range is amplified. As a result, feedback occurs between the count value of the data counter 11 and the amount stored in the data buffer 4, always returning the count value and the amount stored to their center value (0). This allows data output to continue without problems even if the frequency change exceeds the frequency range defined by the number of FIFO stages of the data buffer 4, i.e., the range of (± maximum storage amount / 2). In other words, since the change in the count value is the same as the change in the amount stored in the data buffer 4, by suppressing the fluctuation amount of the count value, data buffer 4 does not overflow / underflow, and the frequency range can be widened.

[0041] Figure 4 is a Bode plot showing an example of the gain characteristics and data counter fluctuation characteristics related to the transfer function of the clock regeneration circuit 5 of the first embodiment. Note that when an oscillator with thermal noise is used as the reference clock, the jitter amount of the reference clock has a frequency characteristic of a first-order integral structure, as shown in Figure 13.

[0042] However, in the clock regeneration circuit 5, the lag-read filter processing of the lag-read filter 12 is used to amplify the gain in the low-frequency band within the control band, so that the amount of jitter in the low-frequency band with high gain is suppressed by that amount of gain, as shown in Figure 4. As a result, the amount of residual edge is reduced as shown in Figure 4 compared to the amount of residual edge shown in Figure 14. By reducing the amount of residual jitter, the influence on the count value of the data counter 11 is suppressed, and fluctuations in the data counter 11 can be suppressed.

[0043] The clock regeneration circuit 5 uses lag-read filtering to amplify only the gain in the low-frequency band compared to the loop bandwidth within the transfer function. This ensures the stability of the control loop while eliminating frequency fluctuations in the output and reducing errors caused by negative feedback.

[0044] Next, the operation of the clock reproduction circuit 5 of the first embodiment will be described. The data counter 11 counts up the count value in accordance with the buffering of the received data to the data buffer 4. The loop delay filter 12 executes a loop delay filter process on the count value of the data counter 11, and outputs the count value on which the loop delay filter process has been executed to the multiplier 13.

[0045] The multiplier 13 multiplies the count value on which the loop delay filter process has been executed by a predetermined gain correction value, and outputs the multiplied count value to the adder 14. The adder 14 adds a predetermined reference value to the multiplied count value, calculates the added count value as a division ratio, and sets the calculated division ratio in the fractional divider 21.

[0046] The fractional divider 21 divides the output clock, which is the reproduction clock from the VCO 24, based on the set division ratio. The fractional divider 21 outputs the divided output clock to the PFD 22. The PFD 22 calculates the phase difference between the reference clock from a clock source not shown and the divided output clock from the fractional divider 21, and outputs the calculated phase difference to the CP 23.

[0047] The CP 23 generates a control voltage in accordance with the phase difference from the PFD 22. The VCO 24 changes the oscillation frequency in accordance with the control voltage from the CP 23 to generate a reproduction clock, and outputs the generated reproduction clock to the data buffer 4, the data counter 11, and the fractional divider 21.

[0048] The data buffer 4 outputs the buffered data to the transmission unit 3 in accordance with the reproduction clock from the VCO 24. The transmission unit 3 serially transmits the data from the data buffer 4 to the serial data transmission device 1 in the subsequent stage. Also, the data counter 11 counts down the count value of the data counter in accordance with the reproduction clock from the VCO 24.

[0049] In the clock regeneration circuit 5 of the first embodiment, lag-read filtering is performed on the count value from the data counter 11, and a predetermined calculation is performed on the count value after lag-read filtering. The clock regeneration circuit 5 calculates the division ratio of the fractional frequency divider 21 based on the count value after the predetermined calculation. As a result, by amplifying the gain in the low-frequency band within the control band with lag-read filtering, the amount of jitter in the low-frequency band of the control band is suppressed by the amount of the amplified gain, thereby suppressing fluctuations in the data counter 11. Furthermore, by amplifying the gain in the low-frequency band with lag-read filtering, changes in the count value are suppressed, eliminating the occurrence of overflow and underflow in the data buffer 4, and thus widening the frequency range of the regenerated clock.

[0050] The lag-lead filter 12 sets its zero-point frequency to the low-frequency band within the control band. As a result, by setting the zero-point frequency of the lag-lead filter 12 to the low-frequency band within the control band, a phase margin corresponding to the gain crossover frequency within the control band can be secured.

[0051] <2. Second Embodiment> <2.1. Overview> First, an overview of the second embodiment of this disclosure will be described. In the comparative example clock regeneration circuit, it is also possible to increase the amount by which the frequency of the regeneration clock is changed while maintaining the count value within (± maximum accumulation amount / 2), that is, to widen the frequency range of the regeneration clock, by increasing the correction gain value of the multiplier. Figure 5 is an explanatory diagram showing an example of the frequency change of the regeneration clock by the multiplier of the comparative example clock regeneration circuit.

[0052] However, in the comparative example clock regeneration circuit, since the count value used to generate the regeneration clock is an integer, when the gain correction value multiplied by the count value is increased, the frequency change of the regeneration clock increases in a stepwise manner according to the gain correction value, as shown in Figure 5. As a result, the fluctuation of the regeneration clock increases.

[0053] Therefore, in the second embodiment, a clock regeneration circuit 5A and a serial data transmission device 1 are provided that can slow down the frequency change of the regeneration clock and suppress fluctuations in the regeneration clock.

[0054] <2.2. Configuration Examples and Operation Examples> Figure 6 is a block diagram showing an example of the clock regeneration circuit 5A of the second embodiment. The difference between the clock regeneration circuit 5 of the first embodiment and the clock regeneration circuit 5A of the second embodiment is that an LPF (Low Pass Filter) 15 is placed instead of the lag reed filter 12.

[0055] The LPF 15 generates a regeneration clock in response to the count value update and performs LPF processing on the count value from the data counter 11 to attenuate the gain in the high-frequency band above the control bandwidth of the transfer function until the count value is updated in response to the generated regeneration clock. The LPF processing removes quantization noise generated by fluctuations in the count value update of the data counter 11 in order to smooth the frequency change of the regeneration clock. Furthermore, the LPF processing performs an operation to increase the number of digits by padding on the LSB (Least Significant Bit) side of the count value and then filters out the quantization noise. As a result, the quantization noise of the count value is suppressed and the frequency change of the regeneration clock becomes smooth.

[0056] Figure 7 is an explanatory diagram showing an example of frequency change of the regenerated clock by the multiplier 13 of the clock regeneration circuit 5A in the second embodiment. The amount by which the frequency of the regenerated clock is changed is increased while maintaining the count value of the data counter 11 within (± maximum accumulation amount / 2), that is, the correction gain value of the multiplier 13 is increased in order to widen the frequency range of the regenerated clock.

[0057] In the clock regeneration circuit 5A, when the gain correction value of the multiplier 13 is increased, the frequency change of the regeneration clock increases in a stepwise manner according to the gain correction value, resulting in increased fluctuations in the regeneration clock, as shown in Figure 7.

[0058] Therefore, in the clock regeneration circuit 5A, even when the gain correction value multiplied by the count value is increased, the LPF processing of the LPF 15 is performed as shown in Figure 7, which makes the frequency change of the regeneration clock gradual and suppresses fluctuations in the regeneration clock.

[0059] Figure 8 is a Bode plot showing an example of the gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit 5A in the second embodiment. The clock regeneration circuit 5A slows down the frequency change of the regenerated clock and suppresses fluctuations in the regenerated clock by attenuating the gain in the high-frequency band, which includes quantization noise generated by fluctuations in the count value update of the data counter 11.

[0060] The LPF15 changes the phase characteristics of the loop transfer function, eliminating the phase margin in the high-frequency band cut off by the LPF15. Therefore, in the clock regeneration circuit 5A, the cutoff frequency of the LPF15 is set to be above the control band in order to secure the phase margin. As a result, by setting the cutoff frequency of the LPF15 to be above the control band, it is possible to secure the phase margin corresponding to the gain crossover frequency within the control band.

[0061] Next, the operation of the clock regeneration circuit 5A of the second embodiment will be described. The data counter 11 increments its count value in accordance with the buffering of received data into the data buffer 4. The LPF 15 performs LPF processing on the count value of the data counter 11 and outputs the count value after LPF processing to the multiplier 13.

[0062] The multiplier 13 multiplies the count value after LPF processing by a predetermined gain correction value and outputs the multiplied count value to the adder 14. The adder 14 adds a predetermined reference value to the multiplied count value, calculates the added count value as a frequency division ratio, and sets the calculated frequency division ratio in the fractional frequency divider 21.

[0063] The fractional frequency divider 21 divides the output clock, which is the regenerated clock from the VCO 24, based on the set frequency division ratio. The fractional frequency divider 21 outputs the divided output clock to the PFD 22. The PFD 22 calculates the phase difference between the reference clock from a clock source (not shown) and the divided output clock from the fractional frequency divider 21, and outputs the calculated phase difference to the CP 23.

[0064] CP23 generates a control voltage according to the phase difference from PFD22. VCO24 generates a regenerated clock by changing the oscillation frequency according to the control voltage from CP23, and outputs the generated regenerated clock to data buffer 4, data counter 11, and fractional frequency divider 21.

[0065] The data buffer 4 outputs buffered data to the transmission unit 3 in accordance with the regeneration clock from the VCO 24. The transmission unit 3 serially transmits the data from the data buffer 4 to the subsequent serial data transmission device 1. The data counter 11 counts down its count value in accordance with the regeneration clock from the VCO 24.

[0066] In the clock regeneration circuit 5A of the second embodiment, LPF processing is performed on the count value from the data counter 11, a predetermined calculation is performed on the count value after LPF processing, and the division ratio of the fractional frequency divider 21 is calculated based on the count value after the predetermined calculation. As a result, by attenuating the gain in the high-frequency band within the control band with LPF processing, quantization noise caused by update fluctuations of the count value in the high-frequency band is suppressed, and fluctuations in the regeneration clock can be suppressed by making the frequency change of the regeneration clock gradual.

[0067] The LPF15 is configured with a cutoff frequency that is above the control band. As a result, a phase margin corresponding to the gain crossover frequency within the control band can be secured.

[0068] In the clock regeneration circuit 5A of the second embodiment, the example shown is one in which the gain correction value of the multiplier 13 is increased. However, even without increasing the gain correction value, LPF processing may be performed on the count value from the data counter 11, and this can be changed as appropriate.

[0069] <3. Third Embodiment> <3.1. Overview> First, an overview of the third embodiment of the present disclosure will be described. In the third embodiment, a clock regeneration circuit is provided that uses the lag reed filter 12 of the first embodiment and the LPF 15 of the second embodiment in combination.

[0070] Therefore, in the third embodiment, a clock regeneration circuit 5B and serial data transmission device 1 are provided that can widen the frequency range over which the regeneration clock's frequency is varied, improve the jitter tolerance of the regeneration clock, and also slow down the frequency change of the regeneration clock, thereby suppressing fluctuations in the regeneration clock.

[0071] <3.2. Configuration and Operation Examples> Figure 9 is a block diagram showing an example of the clock regeneration circuit 5B of the third embodiment. The same reference numerals are used for components identical to those of the clock regeneration circuit 5 of the first embodiment, and the explanation of the redundant components and operations is omitted. The difference between the clock regeneration circuit 5 of the first embodiment and the clock regeneration circuit 5B of the third embodiment is that an LPF 15A is placed between the data counter 11 and the lag read filter 12A.

[0072] The LPF 15A performs LPF processing on the count value of the data counter 11 and outputs the LPF-processed count value to the lag-read filter 12A. The LPF processing generates a regeneration clock in accordance with the count value update and attenuates the gain in the high-frequency band within the control band until the count value is updated, according to the generated regeneration clock. The LPF processing removes quantization noise generated by fluctuations in the data counter 11's count value update in order to smooth the frequency change of the regeneration clock. The LPF processing performs an operation to increase the number of digits by padding on the LSB side of the count value and then filters out the quantization noise. As a result, the quantization noise of the count value is suppressed and the regeneration clock has a smooth frequency change.

[0073] The lag-read filter 12A applies lag-read filtering to the count value after LPF processing and outputs the lag-read filtered count value to the multiplier 13. By amplifying the gain in the low-frequency band within the control band, the lag-read filtering process allows data output to continue without problems even if the frequency changes exceed the frequency range defined by the number of FIFO stages of the data buffer 4, i.e., the range of (± maximum storage amount / 2). In other words, since the change in the count value is the same as the change in the storage amount of the data buffer 4, by suppressing the amount of fluctuation in the count value, data buffer 4 does not overflow / underflow, and the frequency range can be widened.

[0074] However, the lag-read filter process amplifies the gain in the low-frequency band within the control band, thereby suppressing the amount of jitter in the low-frequency band with high gain by that amount, as shown in Figure 4. As a result, by reducing the amount of residual jitter, the influence on the count value of the data counter 11 is suppressed, and fluctuations in the data counter 11 can be suppressed.

[0075] Figure 10 is a Bode plot showing an example of the gain characteristics and phase characteristics related to the transfer function of the clock regeneration circuit 5B of the third embodiment. In lag-lead filtering, the gain in the low-frequency band within the control band is amplified, which reduces the phase margin in the low-frequency band. Therefore, in order to secure the phase margin, the zero-point frequency within the filter frequency of the lag-lead filter 12A is adjusted. In other words, in order to secure the phase margin, the zero-point frequency of the lag-lead filter 12A is set to the low-frequency band within the loop band (control band), thereby securing the phase margin corresponding to the gain crossover frequency.

[0076] In LPF processing, the cutoff frequency of LPF15A is set to be above the control band to ensure phase margin. As a result, by setting the cutoff frequency of LPF15A above the control band, a phase margin corresponding to the gain crossover frequency within the control band can be ensured.

[0077] Next, the operation of the clock regeneration circuit 5B of the third embodiment will be described. The data counter 11 increments its count value in accordance with the buffering of received data into the data buffer 4. The LPF 15A performs LPF processing on the count value of the data counter 11 and outputs the count value after LPF processing to the lag read filter 12A.

[0078] The lag-read filter 12A performs lag-read filtering on the count value after LPF processing and outputs the lag-read filtered count value to the multiplier 13. The multiplier 13 multiplies the lag-read filtered count value by a predetermined gain correction value and outputs the multiplied count value to the adder 14. The adder 14 adds a predetermined reference value to the multiplied count value, calculates the added count value as a frequency division ratio, and sets the calculated frequency division ratio in the fractional frequency divider 21.

[0079] The fractional frequency divider 21 divides the output clock, which is the regenerated clock from the VCO 24, based on the set frequency division ratio. The fractional frequency divider 21 outputs the divided output clock to the PFD 22. The PFD 22 calculates the phase difference between the reference clock from a clock source (not shown) and the divided output clock from the fractional frequency divider 21, and outputs the calculated phase difference to the CP 23.

[0080] CP23 generates a control voltage according to the phase difference from PFD22. VCO24 generates a regenerated clock by changing the oscillation frequency according to the control voltage from CP23, and outputs the generated regenerated clock to data buffer 4, data counter 11, and fractional frequency divider 21.

[0081] The data buffer 4 outputs buffered data to the transmission unit 3 in accordance with the regeneration clock from the VCO 24. The transmission unit 3 serially transmits the data from the data buffer 4 to the subsequent serial data transmission device 1. The data counter 11 counts down its count value in accordance with the regeneration clock from the VCO 24.

[0082] In the clock regeneration circuit 5B of the third embodiment, LPF processing is performed on the count value from the data counter 11, and lag-read filtering is performed on the count value after LPF processing. In the clock regeneration circuit 5B, predetermined calculations are performed on the count value after lag-read filtering, and the division ratio of the fractional frequency divider 21 is calculated based on the count value after predetermined calculations. As a result, by attenuating the gain in the high-frequency band within the control band with LPF processing, quantization noise due to update fluctuations of the count value in the high-frequency band is suppressed, and fluctuations in the regeneration clock can be suppressed by making the frequency change of the regeneration clock gradual. By amplifying the gain in the low-frequency band within the control band with lag-read filtering, the amount of jitter in the low-frequency band of the control band is suppressed by the amount of the amplified gain, thereby suppressing fluctuations in the data counter 11. In addition, by amplifying the gain in the low-frequency band with lag-read filtering, changes in the count value are suppressed, eliminating the occurrence of overflow and underflow of the data buffer 4, and thus widening the frequency range of the regeneration clock.

[0083] For the sake of explanation, the arrangement of the LPF 15A, lag-read filter 12A, and multiplier 13 between the data counter 11 and the adder 14 has been illustrated as an example, but the arrangement order can be changed as appropriate. For example, the arrangement order may be lag-read filter 12A, LPF 15A, and multiplier 13. Alternatively, the arrangement order may be multiplier 13, LPF 15A, and lag-read filter 12A, or multiplier 13, lag-read filter 12A, and LPF 15A. Furthermore, the arrangement order may be lag-read filter 12A, multiplier 13, and LPF 15A, or LPF 15A, multiplier 13, and lag-read filter 12A, and can be changed as appropriate.

[0084] <4. Summary> As described above, according to the first embodiment of this disclosure, by amplifying the gain of the low-frequency band within the control band using lag-read filtering, the amount of jitter in the low-frequency band of the control band is suppressed by the amount of the amplified gain, thereby providing a clock regeneration circuit 5 and serial data transmission device 1 that can suppress fluctuations in the data counter 11.

[0085] Furthermore, according to the first embodiment of this disclosure, by amplifying the gain in the low-frequency band using lag-read filtering, it is possible to provide a clock regeneration circuit 5 and a serial data transmission device 1 that can widen the frequency range of the regenerated clock by suppressing changes in the count value and eliminating the occurrence of overflow and underflow in the data buffer 4.

[0086] Furthermore, according to the second embodiment of this disclosure, a clock regeneration circuit 5A and a serial data transmission device 1 can be provided that suppress quantization noise caused by fluctuations in the update of the count value in the high-frequency band by attenuating the gain in the high-frequency band within the control band using LPF processing, and suppress fluctuations in the regeneration clock by making the frequency change of the regeneration clock gradual.

[0087] Furthermore, according to the third embodiment of this disclosure, a clock regeneration circuit 5B and serial data transmission device 1 can be provided that suppress quantization noise caused by fluctuations in the update of the count value in the high-frequency band by attenuating the gain in the high-frequency band within the control band using LPF processing, and suppress fluctuations in the regeneration clock by making the frequency change of the regeneration clock gradual.

[0088] Furthermore, according to the third embodiment of this disclosure, by amplifying the gain of the low-frequency band within the control band using lag-read filtering, the amount of jitter in the low-frequency band of the control band is suppressed by the amount of the amplified gain, thereby providing a clock regeneration circuit 5B and serial data transmission device 1 that can suppress fluctuations in the data counter 11.

[0089] Furthermore, according to the third embodiment of this disclosure, a clock regeneration circuit 5B and serial data transmission device 1 can be provided that can widen the frequency range of the regenerated clock by amplifying the gain in the low frequency band with lag read filtering, thereby suppressing changes in the count value and eliminating the occurrence of overflow and underflow of the data buffer 4.

[0090] While preferred embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear to any person with ordinary skill in the art of the present disclosure that various modifications or alterations may be conceived within the scope of the technical idea set forth in the claims, and these will naturally also fall within the technical scope of the present disclosure.

[0091] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that will be apparent to those skilled in the art from the description herein, in addition to or in lieu of the effects described herein.

[0092] The following configurations also fall within the technical scope of this disclosure: (1) A clock regeneration circuit that generates a regeneration clock used for timing the output of data from a buffer that buffers received data, using the division ratio of a frequency divider in a phase loop lock circuit, comprising: a counter that counts up a count value in response to the reception of data and counts down the count value in response to the regeneration clock; a lag-read filter that performs lag-read filtering on the count value from the counter so as to amplify the gain in the low-frequency band of the control band of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the lag-read filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation. (2) The clock regeneration circuit according to (1), wherein the zero point frequency of the lag-read filter is set to the low-frequency band within the control band. (3) The clock regeneration circuit according to (1), comprising a low-pass filter that performs low-pass filtering on the count value from the counter so as to attenuate the gain in the high-frequency band above the control band of the transfer function, wherein the calculation unit performs a predetermined calculation on the count value after the lag-read filtering and low-pass filtering have been performed, and calculates the frequency division ratio of the frequency divider based on the count value after the predetermined calculation. (4) The clock regeneration circuit according to (3), wherein the low-pass filter performs low-pass filtering on the count value after padding on the least significant bit side of the count value to increase the number of digits. (5) The clock regeneration circuit according to (3), wherein the cut frequency of the low-pass filter is set to be above the control band.(6) A clock regeneration circuit that generates a regeneration clock used for timing the output of data from a buffer that buffers received data, using the division ratio of a frequency divider in a phase loop lock circuit, comprising: a counter that counts up a count value in response to the reception of the data and counts down the count value in response to the regeneration clock; a low-pass filter that performs low-pass filtering on the count value from the counter so as to attenuate the gain in the high-frequency band above the control band of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the low-pass filtering has been performed and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation. (7) The clock regeneration circuit according to (6), wherein the low-pass filter performs low-pass filtering on the count value after padding on the least significant bit side of the count value to increase the number of digits. (8) The clock regeneration circuit according to (6), wherein the cut frequency of the low-pass filter is set to be above the control band.(9) A serial data transmission device comprising: a receiving unit that receives data transmitted serially by time division multiplexing in a daisy-chain configuration with other devices; a transmitting unit that transmits data serially by time division multiplexing in a daisy-chain configuration with other devices; a buffer that buffers the data received by the receiving unit and outputs the buffered data to the transmitting unit in accordance with a regeneration clock; and a clock regeneration circuit that generates the regeneration clock using the division ratio of a frequency divider in a phase loop lock circuit, wherein the clock regeneration circuit comprises: a counter that counts up a count value in accordance with the reception of the data and counts down the count value in accordance with the regeneration clock; a lag-read filter that performs lag-read filtering on the count value from the counter so as to amplify the gain in the low-frequency band of the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the lag-read filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation. (10) The serial data transmission device according to (9), wherein the lag-read filter has its zero-point frequency set to the low-frequency band within the control band. (11) The serial data transmission device according to (9), further comprising a low-pass filter that performs low-pass filtering on the count value from the counter so as to attenuate the gain in the high-frequency band above the control band of the transfer function, wherein the calculation unit performs a predetermined calculation on the count value after the lag-read filtering and low-pass filtering have been performed, and calculates the frequency division ratio of the frequency divider based on the count value after the predetermined calculation. (12) The serial data transmission device according to (11), wherein the cut-off frequency of the low-pass filter is set to above the control band. (13) The serial data transmission device according to (11), wherein the low-pass filter performs low-pass filtering on the count value after padding is performed on the least significant bit side of the count value to increase the number of digits.

[0093] 1. Serial data transmission device 2. Receiver 4. Data buffer 5. 5A. 5B. Clock regeneration circuit 10. Frequency division ratio calculation circuit 11. Data counter 12. 12A. Lag-read filter 13. Multiplier 14. Adder 15. 15A. LPF 20. Fractional PLL circuit 21. Fractional frequency divider

Claims

1. A clock regeneration circuit that generates a regeneration clock used for timing the output of data from a buffer that buffers received data, using the division ratio of a frequency divider in a phase loop lock circuit, comprising: a counter that counts up a count value in response to the reception of the data and counts down the count value in response to the regeneration clock; a lag-read filter that performs lag-read filtering on the count value from the counter so as to amplify the gain in the low-frequency band of the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the lag-read filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation.

2. The clock regeneration circuit according to claim 1, wherein the lag-read filter has its zero-point frequency set to the low-frequency band within the control band.

3. A clock regeneration circuit according to claim 1, comprising a low-pass filter that performs low-pass filtering on the count value from the counter so as to attenuate the gain in the high-frequency band above the control bandwidth of the transfer function, wherein the calculation unit performs a predetermined calculation on the count value after the lag-read filtering and low-pass filtering have been performed, and calculates the frequency division ratio of the frequency divider based on the count value after the predetermined calculation.

4. The clock regeneration circuit according to claim 3, wherein the low-pass filter performs low-pass filtering on the count value after padding on the least significant bit side of the count value to increase the number of digits.

5. The clock regeneration circuit according to claim 3, wherein the low-pass filter has a cut frequency set to be equal to or greater than the control bandwidth.

6. A clock regeneration circuit that generates a regeneration clock used for timing the output of data from a buffer that buffers received data, using the division ratio of a frequency divider in a phase loop lock circuit, comprising: a counter that counts up a count value in response to the reception of the data and counts down the count value in response to the regeneration clock; a low-pass filter that performs low-pass filtering on the count value from the counter so as to attenuate the gain in the high-frequency band above the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the low-pass filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation.

7. The clock regeneration circuit according to claim 6, wherein the low-pass filter performs low-pass filtering on the count value after padding on the least significant bit side of the count value to increase the number of digits.

8. The clock regeneration circuit according to claim 6, wherein the low-pass filter has a cut frequency set to be equal to or greater than the control bandwidth.

9. A serial data transmission device comprising: a receiving unit that receives data transmitted serially by time division multiplexing in a daisy-chain configuration with other devices; a transmitting unit that serially transmits data by time division multiplexing in a daisy-chain configuration with other devices; a buffer that buffers the data received by the receiving unit and outputs the buffered data to the transmitting unit according to a regeneration clock; and a clock regeneration circuit that generates the regeneration clock using the division ratio of a frequency divider in a phase loop lock circuit, wherein the clock regeneration circuit comprises: a counter that counts up a count value in response to the reception of the data and counts down the count value according to the regeneration clock; a lag-read filter that performs lag-read filtering on the count value from the counter so as to amplify the gain in the low-frequency band of the control bandwidth of the transfer function from the update of the count value to the generation of the regeneration clock; and a calculation unit that performs a predetermined calculation on the count value after the lag-read filtering and calculates the division ratio of the frequency divider based on the count value after the predetermined calculation.

10. The serial data transmission device according to claim 9, wherein the lag-read filter has its zero-point frequency set to the low-frequency band within the control band.

11. A serial data transmission device according to claim 9, comprising a low-pass filter that performs low-pass filtering on the count value from the counter so as to attenuate the gain in the high-frequency band above the control bandwidth of the transfer function, wherein the calculation unit performs a predetermined calculation on the count value after the lag-read filtering and low-pass filtering have been performed, and calculates the frequency division ratio of the frequency divider based on the count value after the predetermined calculation.

12. The serial data transmission device according to claim 11, wherein the low-pass filter has a cut frequency set to be equal to or greater than the control bandwidth.

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