Pulse generation with adjustable pulse width using supply and amplitude variations

Abstract

A pulse generator (100), for generating a periodic square wave signal in response to a periodic input signal, includes a front-end inverting gate (106), a negative-feedback circuit (108), a variable supply rail inverting gate (110), and a duty cycle control circuit (114). The front-end inverting gate is configured to invert the periodic input signal, thereby generating a periodic wave. The negative-feedback circuit is configured to couple an output of the front-end inverting gate to an input of the front-end inverting gate, thereby setting the front-end inverting gate in a linear mode. The variable supply rail inverting gate is connected in series with the front-end inverting gate and is configured to generate the periodic square wave signal. The duty cycle control circuit is configured to supply an adjustable supply voltage to the variable supply rail inverting gate, thereby controlling a duty cycle of the periodic square wave signal.

Description

[0001] PULSE GENERATION WITH ADJUSTABLE PULSE WIDTH USING SUPPLY AND

[0002] AMPLITUDE VARIATIONS

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application claims the benefit of U.S. Provisional Patent Application 63 / 706,756, filed October 14, 2024, whose disclosure is incorporated herein by reference.

[0005] FIELD OF THE INVENTION

[0006] The present disclosure relates to pulse generation circuits, and more particularly to a pulse generator that uses variable supply voltages and amplitude variations to generate variable-width pulses from a periodic input signal.

[0007] BACKGROUND OF THE INVENTION

[0008] Pulse generation circuits are widely used in electronic systems for various applications including clock generation, signal conditioning, power management, and others. These circuits typically convert periodic input signals, such as sinusoidal waveforms, into square wave pulses with controllable characteristics. The ability to generate pulses with variable width or duty cycle is particularly valuable in applications such as pulse width modulation (PWM) for motor control, switching power supplies, and digital signal processing.

[0009] Conventional pulse generators often rely on digital logic to achieve pulse width control. This approach, however, may be limited at high frequencies and / or consume substantial power. Another approach used in conventional pulse generators is comparatorbased circuits; such circuits, however, also consume substantial power due to their continuous operation and current requirements.

[0010] SUMMARY OF THE INVENTION

[0011] An embodiment of the present invention that is described herein provides a pulse generator for generating a periodic square wave signal in response to a periodic input signal. The pulse generator includes a front-end inverting gate, a negative-feedback circuit, a variable supply rail inverting gate, and a duty cycle control circuit. The front-end inverting gate is configured to invert the periodic input signal, thereby generating a periodic wave. The negative-feedback circuit is configured to couple an output of the front-end inverting gate to an input of the front-end inverting gate, thereby setting the front-end inverting gate in a linear mode. The variable supply rail inverting gate is connected in series with the front-end inverting gate and is configured to generate the periodic square wave signal. The duty cycle control circuit is configured to supply an adjustable supply voltage to the variable supply rail inverting gate, thereby controlling a duty cycle of the periodic square wave signal.

[0012] In some embodiments, the negative-feedback circuit includes a resistor. In some embodiments, the pulse generator further includes at least one additional inverting gate, and the duty cycle control circuit is configured to adjust respective supply voltages of one or both of the variable supply rail inverting gate and the additional inverting gate.

[0013] In a disclosed embodiment, the duty cycle control circuit is configured to further modify the duty cycle by adjusting an amplitude of the periodic input signal, thereby modifying a trip point of the variable supply rail inverting gate.

[0014] There is additionally provided, in accordance with an embodiment that is described herein, a method for generating a periodic square wave signal in response to a periodic input signal. The method includes inverting the periodic input signal using a front-end inverting gate, thereby generating a periodic wave. An output of the front-end inverting gate is coupled to an input of the front-end inverting gate using a negative-feedback circuit, thereby setting the front-end inverting gate in a linear mode. The periodic square wave signal is generated using a variable supply rail inverting gate, which is connected in series with the front-end inverting gate. An adjustable supply voltage is supplied to the variable supply rail inverting gate, thereby controlling a duty cycle of the periodic square wave signal.

[0015] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0016] BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Fig. 1 is a block diagram that schematically illustrates an adjustable duty cycle pulse generator (ADCPG), in accordance with an embodiment of the present invention;

[0018] Fig. 2 is a graph that schematically illustrates the waveform of an ADCPG, in accordance with an embodiment of the present invention;

[0019] Fig. 3 is a block diagram that schematically illustrates a multistage ADCPG, in accordance with an embodiment of the present invention;

[0020] Fig. 4 is a graph that schematically illustrates waveforms of the inverting gates of the multistage ADCPG illustrated in Fig. 3, in accordance with an embodiment of the present invention;

[0021] Fig. 5 is a duty cycle control graph that schematically illustrates the duty cycle of the multistage ADCPG illustrated in Fig. 3, in two locations, in accordance with an embodiment of the present invention; and Fig. 6 is a flowchart that schematically illustrates a method for duty cycle control of a pulse generator, in accordance with an embodiment of the present invention.

[0022] DETAILED DESCRIPTION OF EMBODIMENTS

[0023] OVERVIEW

[0024] Conventional duty-cycle control circuits are often limited in their frequency response and may consume substantial power, particularly in applications requiring continuous operation. Embodiments of the present invention described herein provide for low power high frequency duty cycle control circuits that address these limitations.

[0025] In an embodiment, a pulse generator receives a periodic input signal through an amplitude control circuit and processes it using two cascaded inverting gates with different supply voltages; a feedback resistor provides negative feedback to the first inverting gate, setting it in the linear-mode. Duty cycle control is achieved through coordinated adjustment of both the input signal amplitude and the supply voltages of the second inverting gate.

[0026] In embodiments, by increasing the input amplitude, the point in which the input signal crosses the linear-mode inverter trip point is changed, increasing or decreasing the duty cycle. In other embodiments, changing the supply voltages of the subsequent inverting gate changes the trip-point of the second inverter, further increasing or decreasing the duty cycle.

[0027] In another disclosed embodiment, a multistage configuration employs three or more inverting gates operating at progressively different supply voltage levels to provide enhanced control over pulse generation characteristics.

[0028] In addition, simulated timing waveforms and duty cycle graphs are disclosed.

[0029] SYSTEM DESCRIPTION

[0030] Fig. 1 is a block diagram that schematically illustrates an adjustable duty cycle pulse generator (ADCPG) 100, in accordance with an embodiment of the present invention. The ADCPG receives a periodic input signal from an amplitude-controlled sinewave generator 102. The amplitude-controlled signal is coupled through a coupling capacitor 104 to a first inverting gate 106. In some embodiments, the first inverting gate may comprise an inverter.

[0031] A feedback resistor 108 is connected between the input and output of the first inverting gate, to apply negative feedback and, thus, set inverting gate 106 in a linear mode operation. The output of the first inverting gate connects to a second inverting gate 110 (e.g., an inverter), which further processes the signal to generate an adjustable duty cycle square wave. While the power supply of first inverting gate 106 is set to Vddl, the power supply of the second inverting gate, designated Vdd2, is generated by a variable voltage power supply 112.

[0032] In embodiments, the duty cycle of ADCPG 100 may be controlled by modifying Vdd2, which change the trip point of second inverting gate 110, increasing or decreasing the hightime (and, hence, the duty-cycle) of the periodic signal generated by inverting gate 106. In an embodiment, by modifying the amplitude of the sine wave at the input to the first inverting gate, the duty cycle can be further modified.

[0033] According to the example embodiment illustrated in Fig. 1, ADCPG 100 further comprises a duty-cycle control circuit 114, which provides control signals to both the amplitude-controlled sinewave generator and to the variable voltage power supply, as indicated by the dashed control lines. The duty-cycle control circuit is, thus, configured to control the duty cycle of ADCPG 100.

[0034] The configuration of ADCPG 100 illustrated in Fig. 1 and described hereinabove is cited by way of example. Other configurations may be used in alternative embodiments. For example, in some embodiments, the periodic input signal that amplitude-controlled sinewave generator 102 generates may be a triangle wave, or any other suitable periodic signal. In some embodiments, amplitude-controlled sinewave generator 102 may output a constant amplitude (and, in this case, duty cycle control is achieved only by vdd2 variations). In an embodiment, there is no amplitude-controlled sinewave generator 102 and / or coupling capacitor 104; rather, first inverting gate 106 is configured to spontaneously oscillate, e.g., according to a resonance frequency of a crystal oscillator that is connected thereto. In some embodiments, Vdd2 is constant and Vddl is supplied by variable voltage power supply 112.

[0035] In an alternative embodiment, instead of generating the periodic input signal by amplitude-controlled sinewave generator 102, ADCPG 100 receives a constant-amplitude periodic input signal from an external sinewave generator. In this embodiment, ADCPG 100 may comprise a variable-gain stage (e.g., amplifier or attenuator) that adjusts the amplitude of the periodic input signal. The gain of the variable-gain stage applies a variable gain to the constant-amplitude signal, according to the amplitude-control signal from duty-cycle control circuit 114.

[0036] It should be noted that, unlike traditional duty-cycle control circuits, ADCPG 100 does not include digital counters to digitally control the duty cycles, and, hence, ADCPG can work at higher frequencies. Fig. 2 is a graph that schematically illustrates a waveform 200 of an ADCPG, in accordance with an embodiment of the present invention. The horizontal axis represents time, while the vertical axis represents voltage levels.

[0037] A sinusoidal input waveform is shown intersecting with two different voltage threshold lines labeled as Vth-inverter 106 and Vth-inverter 110. These threshold crossings create distinct switching points that determine the pulse width characteristics. The shaded region between the Vth-inverter 110 crossings indicates the time interval during which the output pulse remains in a logic-low state.

[0038] The graph demonstrates how varying the voltage thresholds affects the timing characteristics of the pulse generator. When the input signal crosses Vth-inverter 106, it triggers a transition of inverter 106, and when it crosses Vth-inverter 110, it triggers a transition of inverter 110. The time difference between the crossings of Vth-inverter 110 determines the pulse width or duty cycle of the output signal.

[0039] The vertical arrow in the graph indicates that an increase Vth-inverter 110, caused by an increase in Vdd2, brings about an increase in the duty cycle of the ADCPG.

[0040] Fig. 3 is a block diagram that schematically illustrates a multistage ADCPG 300, in accordance with an embodiment of the present invention. Multistage ADCPG 300 receives a periodic input signal from a sinusoidal source 302. The input signal is coupled through a coupling capacitor 304 to a first inverting gate 306, which may comprise an inverter operating at a first supply voltage level.

[0041] The output of the first inverting gate 306 connects to a second inverting gate 308, which operates at a second supply voltage level that may be different from the first supply voltage. The second inverting gate 308 is followed by a third inverting gate 310, which operates at a third supply voltage level. In some embodiments, the supply voltages may be set adaptively by duty-cycle control circuit 114 to progressively stepped values, such as 0.65V for the first inverting gate, 0.75V for the second inverting gate, and 0.9V for the third inverting gate. Other suitable voltage levels may be used in alternative embodiments.

[0042] The supply voltages values of 0.65V, 0.75V and 0.95V quoted above are cited by way of example. Other voltages may be used in alternative embodiments by duty-cycle control circuit 114, according to the desired duty-cycle. In some embodiments, any or all the supply voltages of inverters 306, 308 and 310 may be adjustable, to provide in-site duty cycle control.

[0043] This multistage configuration allows for enhanced control over the pulse generation characteristics by utilizing multiple threshold levels. Each inverting gate may have a different switching threshold based on its respective supply voltage, creating multiple decision points as the signal propagates through the circuit. A feedback resistor 312 (e.g., 5KQ) may be connected between the input and output of first inverting gate 306 to establish linear mode operation.

[0044] The coupling capacitor provides DC decoupling of the input signal, allowing the circuit to process AC components while blocking DC offsets. In some embodiments, coupling capacitor 304 may have a capacitance value of approximately IpF (other suitable values may be used in alternative embodiments). The multistage approach enables wide range control of the duty cycle characteristics through the coordinated adjustment of multiple supply voltage levels, wherein each may further extend the duty cycle extension range, providing greater flexibility in duty cycle adjustments as compared to single-stage configurations.

[0045] The configuration of multistage ADCPG 300 illustrated in Fig. 3 and described hereinabove is cited by way of example. Other configurations may be used in alternative embodiments. For example, in some embodiments, more than three stages are used. In embodiments, capacitor 304 value may be more or less than IpF, e.g., for frequency ranges of 10 to 50Mhz, a 50pF capacitor may be preferred.

[0046] Fig. 4 is a graph that schematically illustrates waveforms 400 of the inverting gates of multistage ADCPG 300 (Fig. 3). The graph displays three separate waveform plots arranged vertically, each representing the signal characteristics at different stages of the multistage ADCPG.

[0047] A waveform 402 shows the output of first inverting gate 306, displaying sinusoidal- like signals with normalized amplitude values ranging from approximately 0.15 to 0.45. Multiple overlapping traces are shown, representing the circuit response to various amplitudes of the input signal. Two horizontal dashed lines are depicted, the lower one indicating the trip point of first inverting gate 306, and the other indicating the trip points of the subsequent inverting gate 308. The area marked with diagonal dotted lines represents the period in which the output of the first inverting gate is higher than the trip point of the subsequent second inverting gate.

[0048] A Waveform 404 illustrates the output of inverting gate 308, showing signal transitions with larger amplitude variations between approximately 0.2 and 0.7 normalized amplitude. The horizontal line, at V3 / 2 represent the trip points of the subsequent inverting gate 310, and an area marked by horizontal dotted lines represents the time period in which the output of the second inverting gate is higher than the trip point of the subsequent third inverting gate.

[0049] Lastly, a waveform 406 depicts the output of the third inverting gate 308, showing more digitized pulse-like signals with steeper transitions and normalized amplitudes ranging from 0 to approximately 0.85. The waveforms exhibit square-wave characteristics compared to the analog-looking signals in the upper plots, indicating the progressive signal conditioning through the multistage configuration.

[0050] Fig. 5 is a duty cycle control graph 500 that schematically illustrates the duty cycle of multistage ADCPG 300 (Fig. 3), in two locations, in accordance with an embodiment of the present invention. The graph presents two separate plots showing how duty cycle percentage varies with input voltage amplitude for different inverter stages in the multistage configuration.

[0051] A plot 502 displays the duty cycle characteristics as a function of the Vin amplitude at the output of second inverting gate 308 (Fig. 3), having a 0.75 power supply. Following a short increasing-duty-cycle region, this plot demonstrates a decreasing trend in duty cycle as the input amplitude increases from approximately 45m V to lOOmV, with duty cycle values ranging from about 56.5% down to 55%. The relationship exhibits a gradual decline, indicating that, generally higher input amplitudes result in reduced duty cycles at this stage.

[0052] A plot 504 then displays the duty cycle characteristics as a function of the Vin amplitude at the output of third inverting gate 310 (Fig. 3), having a 0.9 power supply. This plot exhibits an increasing trend, with duty cycle values rising from approximately 33% to 46% as the input voltage amplitude increases from approximately 40mV to lOOmV. This upward trend demonstrates that the third stage responds differently to input amplitude variations compared to the second stage, with higher input amplitudes producing increased duty cycles.

[0053] Graph 500 also demonstrates how the addition of inverting-gate stages with different supply voltages increases the range of duty cycle control.

[0054] Fig. 6 is a flowchart 600 that schematically illustrates a method for duty cycle control of a pulse generator, in accordance with an embodiment of the present invention. The flowchart is executed by duty-cycle control circuit 114 of ADCPG 100 (Fig. 1).

[0055] The flowchart begins with a supply-adjusting operation 602, wherein the duty-cycle control circuit adjusts the power supply voltage of inverting gate 110 (fig. 1). This operation provides the primary mechanism for duty cycle variation by modifying the switching threshold of the inverter stage.

[0056] The flowchart concludes with an amplitude-controlling operation 604, wherein the duty-cycle control circuit adjusts the AC input amplitude of sinewave generator 120, to achieve further control of the duty cycle. This final operation may provide wider-range capabilities for the pulse generation characteristics. The configuration of flowchart 600 illustrated in Fig. 6 and described hereinabove is cited by way of example. Other configurations may be used in alternative embodiments. For example, in embodiments, additional inverting gates are added, to create a multistage ADCPG with any suitable number of stages.

[0057] The configurations, graphs and methods described hereinabove, with reference to Figs 1 through 6, including all units and subunits thereof, are example configurations, graphs and methods that are shown purely for the sake of conceptual clarity. Any other suitable methods, graphs and configurations may be used in alternative embodiments.

[0058] In various embodiments, ADCPGs 100, and 300, including subunits thereof, may be implemented using suitable hardware, such as one or more Application-Specific Integrated Circuits (ASIC) or Field-Programmable Gate Arrays (FPGA), or a combination of ASIC and FPGA.

[0059] Although the embodiments described herein mainly address adjustable pulse generators, the methods and systems described herein can also be used in any other suitable application.

[0060] It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

CLAIMS1. A pulse generator, to generate a periodic square wave signal in response to a periodic input signal, the pulse generator comprising: a front-end inverting gate, configured to invert the periodic input signal, thereby generating a periodic wave; a negative-feedback circuit, configured to couple an output of the front-end inverting gate to an input of the front-end inverting gate, thereby setting the front-end inverting gate in a linear mode; a variable supply rail inverting gate, connected in series with the front-end inverting gate and configured to generate the periodic square wave signal; and a duty cycle control circuit, configured to supply an adjustable supply voltage to the variable supply rail inverting gate, thereby controlling a duty cycle of the periodic square wave signal.

2. The pulse generator according to claim 1, wherein the negative-feedback circuit comprises a resistor.

3. The pulse generator according to claim 1 or 2, further comprising at least one additional inverting gate, wherein the duty cycle control circuit is configured to adjust respective supply voltages of one or both of the variable supply rail inverting gate and the additional inverting gate.

4. The pulse generator according to claim 1 or 2, wherein the duty cycle control circuit is configured to further modify the duty cycle by adjusting an amplitude of the periodic input signal, thereby modifying a trip point of the variable supply rail inverting gate.

5. A method for generating a periodic square wave signal in response to a periodic input signal, the method comprising: inverting the periodic input signal using a front-end inverting gate, thereby generating a periodic wave; using a negative-feedback circuit, coupling an output of the front-end inverting gate to an input of the front-end inverting gate, thereby setting the front-end inverting gate in a linear mode; generating the periodic square wave signal using a variable supply rail inverting gate, which is connected in series with the front-end inverting gate; andsupplying an adjustable supply voltage to the variable supply rail inverting gate, thereby controlling a duty cycle of the periodic square wave signal.

6. The method according to claim 5, wherein the negative-feedback circuit comprises a resistor.

7. The method according to claim 5 or 6, wherein controlling the duty cycle comprises adjusting respective supply voltages of one or both of (i) the variable supply rail inverting gate and (ii) at least one additional inverting gate.

8. The method according to claim 5 or 6, wherein controlling the duty cycle further comprises adjusting an amplitude of the periodic input signal, thereby modifying a trip point of the variable supply rail inverting gate.

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