Field-effect transistor

Abstract

[Problem] To suppress dielectric breakdown caused by electric field concentration in an OFF state in a field-effect transistor which has a fin-type structure and in which a current flows in the thickness direction of a substrate. [Solution] A field-effect transistor 100 comprises: a semiconductor substrate 10; a drift layer 20 provided on an upper surface 11 of the semiconductor substrate 10 and having a plurality of fin structure parts 23; a gate electrode 62 covering at least side surfaces 23S of the plurality of fin structure parts 23 via a first insulating film 61; a source electrode 30 connected to upper surfaces 23T of the plurality of fin structure parts 23; and a drain electrode 40 connected to a rear surface 12 of the semiconductor substrate 10. The gate electrode 62 includes a body part 60 and a terminal part 63. The distance between the terminal part 63 and the drift layer 20 is greater than the thickness of a portion of the first insulating film 61 that covers a bottom 22 of a trench region 21 and is located between the body part 60 and the drift layer 20.

Description

Field-effect transistor

[0001] This disclosure relates to a field-effect transistor, and more particularly to a field-effect transistor having a fin-type structure in which current flows in the thickness direction of the substrate.

[0002] Non-patent document 1 discloses a field-effect transistor having a fin-type structure in which current flows in the thickness direction of the substrate.

[0003] "Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV" 2019 IEEE International Electron Devices Meeting (IEDM) (San Francisco, CA, USA, 2019) pp.12.4.1 - 12.4.4

[0004] The field-effect transistor disclosed in Non-Patent Document 1 had a problem in that when a high voltage was applied between the source and drain while the transistor was off, the electric field concentrated at the edge of the gate electrode, making dielectric breakdown likely to occur in this area.

[0005] This disclosure describes a technique for suppressing dielectric breakdown caused by electric field concentration during the off state in a field-effect transistor having a fin-type structure in which current flows in the thickness direction of the substrate.

[0006] A field-effect transistor according to one aspect of the present disclosure comprises a semiconductor substrate, a drift layer provided on one surface of the semiconductor substrate and having a trench region and a plurality of fin structures, a first insulating film covering at least a portion of the sides of the plurality of fin structures and the bottom of the trench region, a gate electrode including a main body portion that covers at least a portion of the sides of the plurality of fin structures and the bottom of the trench region via the first insulating film, and a terminal portion connected to the main body portion, a source electrode connected to the upper surface of the plurality of fin structures, and a drain electrode connected to the other surface of the semiconductor substrate, wherein the plurality of fin structures are provided so as to protrude from the bottom of the trench region, the terminal portion of the gate electrode includes an edge portion of the gate electrode, at least a portion of the terminal portion of the gate electrode is exposed without being covered by the source electrode, and the distance between the terminal portion of the gate electrode and the drift layer is greater than the thickness of the portion of the first insulating film that covers the bottom of the trench region and is located between the main body portion of the gate electrode and the drift layer.

[0007] According to this disclosure, a technology is provided for suppressing dielectric breakdown caused by electric field concentration when the transistor is off, in a field-effect transistor having a fin-type structure in which current flows in the thickness direction of the substrate.

[0008] Figure 1 is a schematic plan view showing the configuration of a field-effect transistor 100 according to a first embodiment of the technology according to this disclosure. Figures 2(a) to 2(c) are approximate cross-sectional views along the lines A-A, B-B, and C-C shown in Figure 1, respectively. Figure 3 is a process diagram illustrating the manufacturing method of the field-effect transistor 100. Figure 4 is a process diagram illustrating the manufacturing method of the field-effect transistor 100. Figure 5 is a process diagram illustrating the manufacturing method of the field-effect transistor 100. Figure 6 is a process diagram illustrating the manufacturing method of the field-effect transistor 100. Figures 7(a) to 7(c) are approximate cross-sectional views showing the configuration of a field-effect transistor 200 according to a second embodiment of the technology according to this disclosure. Figure 8 is a process diagram illustrating the manufacturing method of the field-effect transistor 200. Figure 9 is a process diagram illustrating the manufacturing method of the field-effect transistor 200. Figure 10 is a schematic plan view showing the configuration of a field-effect transistor 300 according to a third embodiment of the technology according to this disclosure. Figure 11 is a schematic plan view showing the configuration of a field-effect transistor 400 according to a fourth embodiment of the technology according to this disclosure. Figure 12 is a schematic plan view showing the configuration of a field-effect transistor 500 according to a fifth embodiment of the technology according to this disclosure. Figure 13 is a substantially cross-sectional view along the line D-D shown in Figure 12. Figure 14 is a schematic plan view showing the configuration of a field-effect transistor 600 according to a sixth embodiment of the technology according to this disclosure. Figure 15 is a substantially cross-sectional view along the line E-E shown in Figure 14. Figure 16 is a process diagram illustrating the manufacturing method of the field-effect transistor 600. Figure 17 is a process diagram illustrating the manufacturing method of the field-effect transistor 600. Figure 18 is a process diagram illustrating the manufacturing method of the field-effect transistor 600. Figure 19 is a schematic plan view showing the configuration of a field-effect transistor 700 according to a seventh embodiment of the technology according to this disclosure. Figure 20 is a substantially cross-sectional view along the line F-F shown in Figure 19.

[0009] The embodiments of the technology described herein will be described in detail below with reference to the attached drawings.

[0010] <First Embodiment>

[0011] Figure 1 is a schematic plan view showing the configuration of a field-effect transistor 100 according to a first embodiment of the technology described herein. Figures 2(a) to 2(c) are approximate cross-sectional views along lines A-A, B-B, and C-C shown in Figure 1, respectively.

[0012] The field-effect transistor 100 according to this embodiment is a field-effect type power transistor in which current flows in the thickness direction of the substrate, and all of them are gallium oxide (β-Ga ２ O ３ The semiconductor substrate 10 and drift layer 20 are made of the same material. Silicon (Si) or tin (Sn) is introduced as an n-type dopant into the semiconductor substrate 10 and the drift layer 20. The dopant concentration is higher in the semiconductor substrate 10 than in the drift layer 20, and as a result the semiconductor substrate 10 is n ＋ The layer, drift layer 20 is n － It functions as a layer. For example, the dopant concentration of the semiconductor substrate 10 is 1 × 10⁻¹⁶. １９ cm －３ Therefore, the dopant concentration in the drift layer 20 is 1 × 10⁻⁶. １６ cm －３ That is the case.

[0013] The semiconductor substrate 10 is formed by cutting a bulk crystal that has been grown using a method such as melt growth, and its thickness is, for example, 250 μm. The planar size of the semiconductor substrate 10 is not particularly limited, but is generally selected according to the amount of current flowing through the device, and if the maximum on-current is about 20 A, it may be about 2.4 mm x 2.4 mm in a planar view from the Z direction.

[0014] The semiconductor substrate 10 has an upper surface 11 located on the upper side and a back surface 12 located on the opposite side of the upper surface 11. Both the upper surface 11 and the back surface 12 constitute the XY plane. A drift layer 20 is formed on the upper surface 11 of the semiconductor substrate 10. The drift layer 20 is a thin film of gallium oxide epitaxially grown on the upper surface 11 of the semiconductor substrate 10 using reactive sputtering, PLD method, MBE method, MOCVD method, HVPE method, etc. The thickness of the drift layer 20 in the Z direction is not particularly limited, but for example it may be about 10 μm.

[0015] On the surface of the drift layer 20 located on the opposite side of the semiconductor substrate 10, a trench region 21 is provided. The trench region 21 is a region where the thickness of the drift layer 20 in the Z direction becomes thinner. The depth of the trench region 21 in the Z direction is, for example, 2 μm. In the trench region 21, a plurality of fin structure portions 23 are provided so as to protrude in the Z direction from the bottom portion 22 of the trench region 21. The fin structure portion 23 is a part of the drift layer 20 and is a protruding portion that protrudes in the Z direction from the bottom portion 22 of the trench region 21.

[0016] In the example shown in FIGS. 1 and 2(a) to (c), a plurality of fin structure portions 23 extending in the Y direction are arranged in the X direction. The width of the fin structure portion 23 in the X direction is, for example, 0.4 μm. The thickness of the drift layer 20 in the fin structure portion 23 may be the same as the thickness of the drift layer 20 outside the trench region 21. In this case, the height of the fin structure portion 23 in the Z direction from the bottom portion 22 of the trench region 21 is, for example, 2 μm.

[0017] At least a part (a part in this embodiment) of the side surface 23S of the fin structure portion 23 and the bottom portion 22 of the trench region 21 are covered with the main body portion 60 of the gate electrode 62 via an insulating film 61. The insulating film 61 covers at least a part (all in this embodiment) of the side surface 23S of the fin structure portion 23 and the bottom portion 22 of the trench region 21. The insulating film 61 may be made of, for example, Al with a thickness of 50 nm ２ O ３ for example. A portion of the insulating film 61 located between the main body portion 60 of the gate electrode 62 and the drift layer 20 functions as a so-called gate insulating film. The main body portion 60 of the gate electrode 62 may be made of Ni. The side surface 23S of the fin structure portion 23 may be parallel or substantially parallel to the Z direction. The gate electrode 62 includes a main body portion 60 that covers at least a part of the drift layer 20 via the insulating film 61 and a terminal portion 63 connected to the main body portion 60. The surface of the main body portion 60 of the gate electrode 62 is covered with an insulating film 71. The insulating film 71 may be made of, for example, Al with a thickness of 300 nm ２ O ３ for example.

[0018] The upper surface 23T of the fin structure 23 is connected to the source electrode 30. The source electrode 30 may be a Ti / Au laminated film. An insulating film 71 is interposed between the source electrode 30 and the main body 60 of the gate electrode 62, thereby insulating the source electrode 30 from the main body 60 of the gate electrode 62 by the insulating film 71.

[0019] The upper region including the upper surface 23T of the fin structure 23 is n ＋ Constitutes layer 24. ＋ Layer 24 is a portion of the drift layer 20 in which the dopant concentration is locally increased, and the dopant concentration there is, for example, 1 × 10⁻¹⁶. １９ cm －３ The upper surface 23T of the fin structure 23 may be perpendicular or nearly perpendicular to the Z direction (parallel or nearly parallel to the XY plane direction). A portion of the source electrode 30 may cover the side surface 23S of the fin structure 23 via the insulating film 71, the main body 60 of the gate electrode 62, and the insulating film 61.

[0020] The back surface 12 of the semiconductor substrate 10 is connected to the drain electrode 40. The drain electrode 40 may be a Ti / Au multilayer film.

[0021] In the example shown in Figures 1 and 2(a), a portion of the bottom 22 of the trench region 21, specifically the area surrounding the fin structure 23 when viewed from the Z direction, is also covered by the main body 60 of the gate electrode 62 via the insulating film 61. The main body 60 of the gate electrode 62 is connected to the terminal portion 63 of the gate electrode 62. The terminal portion 63 of the gate electrode 62 is a pad electrode for external connection, and at least a portion of it is exposed without being covered by the source electrode 30. The terminal portion 63 of the gate electrode 62 includes the edge portion 62A of the gate electrode 62. The material of the terminal portion 63 of the gate electrode 62 may be the same conductive material as the main body 60 of the gate electrode 62, or it may be a different conductive material. A portion of the insulating film 71 is located between the drift layer 20 and the terminal portion 63 of the gate electrode 62, and the terminal portion 63 of the gate electrode 62 is provided on the insulating film 71 covering the bottom 22 of the trench region 21. The terminal portion 63 of the gate electrode 62 is connected to the main body portion 60 of the gate electrode 62 via a through hole 64 provided in the insulating film 71.

[0022] In a field-effect transistor 100 having such a structure, when an ON voltage is applied to the main body 60 of the gate electrode 62 via the terminal portion 63 of the gate electrode 62, the source electrode 30 and the drain electrode 40 conduct through the drift layer 20, and a drain current flows. On the other hand, when the application of the ON voltage to the main body 60 of the gate electrode 62 via the terminal portion 63 of the gate electrode 62 is stopped, the fin structure 23 pinches off, and almost no drain current flows.

[0023] Here, when the field-effect transistor 100 is in the off state and a high voltage is applied between the source and drain, a high voltage is generated between the gate electrode 62 and the drift layer 20. However, in the field-effect transistor 100 according to this embodiment, the terminal portion 63 of the gate electrode 62 is located outside the edge portion 60A of the main body portion 60 of the gate electrode 62, and there is an Al layer with a thickness of approximately 50 nm between the main body portion 60 of the gate electrode 62 and the drift layer 20. ２ O ３While only an insulating film 61 made of is interposed, between the terminal portion 63 of the gate electrode 62 and the drift layer 20 there is an Al layer with a thickness of approximately 50 nm. ２ O ３ An insulating film 61 made of and an Al with a thickness of approximately 300 nm ２ O ３ A laminated film of insulating film 71 is interposed. In other words, the distance between the terminal portion 63 of the gate electrode 62 and the drift layer 20 is greater than the thickness of the portion of the insulating film 61 that covers the bottom portion 22 of the trench region 21 and is located between the main body portion 60 of the gate electrode 62 and the drift layer 20. As a result, the electric field generated between the edge portion 62A of the terminal portion 63 of the gate electrode 62 and the drift layer 20 is mitigated, making dielectric breakdown less likely.

[0024] As an example, a layer of Al approximately 50 nm thick is placed between the terminal portion 63 of the gate electrode 62 and the drift layer 20. ２ O ３ When only an insulating film 61 is interposed, the electric field strength applied between the edge portion 62A of the terminal portion 63 of the gate electrode 62 and the drift layer 20 is approximately 9.7 MV / cm, whereas in this embodiment, the electric field strength is reduced to approximately 4.0 MV / cm.

[0025] Figures 3 to 6 are process diagrams illustrating the manufacturing method of the field-effect transistor 100 according to this embodiment.

[0026] First, n ＋ After forming the drift layer 20 including layer 24, a trench region 21 is formed by etching the drift layer 20, as shown in Figure 3. Multiple fin structures 23, which are non-etched parts, are provided within the trench region 21. Next, an insulating film 61 is deposited within the trench region 21. As a result, the side surfaces 23S of the fin structures 23 and the bottom 22 of the trench region 21 are covered with the insulating film 61. The insulating film 61 is not formed on the upper surface 23T of the fin structures 23. ＋ Assume that layer 24 is exposed.

[0027] Next, as shown in FIG. 4, the main body portion 60 of the gate electrode 62 is formed on the side surface 23S of the fin structure portion 23 and a part of the bottom portion 22 of the trench region 21 via the insulating film 61. The n ＋ layer 24 constituting the upper surface 23T of the fin structure portion 23 is left exposed.

[0028] Next, as shown in FIG. 5, after covering the entire surface with the insulating film 71, a through hole 64 is provided in the insulating film 71 to expose a part of the main body portion 60 of the gate electrode 62 that covers the bottom portion 22 of the trench region 21. At this time, the n ＋ layer 24 constituting the upper surface 23T of the fin structure portion 23 is left exposed without being covered by the insulating film 71.

[0029] Next, as shown in FIG. 6, the terminal portion 63 of the gate electrode 62 is formed on the surface of the insulating film 71 so as to overlap the through hole 64. Thereby, the terminal portion 63 is connected to the main body portion 60 of the gate electrode 62 through the through hole 64. Thereafter, an n ＋ source electrode 30 is formed so as to contact the layer 24, and a drain electrode 40 is formed on the back surface 12 of the semiconductor substrate 10, whereby the field effect transistor 100 according to the present embodiment is completed.

[0030] As described above, the field effect transistor 100 according to the present embodiment has a configuration in which the main body portion 60 of the gate electrode 62 is connected to the terminal portion 63, and the distance between the terminal portion 63 and the drift layer 20 is such that the insulating film 61 covers the bottom portion 22 of the trench region 21 and is larger than the thickness of the portion located between the main body portion 60 of the gate electrode 62 and the drift layer 20. Therefore, even when a high voltage is applied between the source and the drain at off state, it is possible to relieve the electric field concentration on the edge portion 62A at the terminal portion 63 of the gate electrode 62.

[0031] <Second Embodiment>

[0032] FIGS. 7(a) to 7(c) are schematic cross-sectional views showing the configuration of the field-effect transistor 200 according to the second embodiment of the technology according to the present disclosure. The planar shape of the field-effect transistor 200 according to the second embodiment is the same as the shape shown in FIG. 1, and FIGS. 7(a) to 7(c) respectively correspond to cross-sections along the lines A-A, B-B, and C-C shown in FIG. 1.

[0033] The field-effect transistor 200 according to the second embodiment is different from the field-effect transistor 100 according to the first embodiment in that an insulating film 72 is added. Since the other basic configurations are the same as those of the field-effect transistor 100 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0034] The insulating film 72 is provided between the terminal portion 63 of the gate electrode 62 and the insulating film 71. The insulating film 72 may be a film made of the same insulating material as the insulating film 61 or the insulating film 71. In the present embodiment, the connection portion 65 is included in the main body portion 60 of the gate electrode 62. The connection portion 65 is a portion of the main body portion 60 of the gate electrode 62 that is located on the insulating film 72 without contacting the insulating film 61. And, among the main body portion 60 of the gate electrode 62, the portion that contacts the insulating film 61 is connected to the connection portion 65 of the main body portion 60 of the gate electrode 62 through the through-hole 66 provided in the insulating film 72, and is also connected to the terminal portion 63 of the gate electrode 62 through the through-hole 64 provided in the insulating film 71. By adding such an insulating film 72, a three-layer laminated film composed of the insulating film 61, the insulating film 72, and the insulating film 71 is interposed between the terminal portion 63 of the gate electrode 62 and the drift layer 20, so that the electric field concentrated on the edge portion 62A at the terminal portion 63 of the gate electrode 62 is more relaxed.

[0035] FIGS. 8 and 9 are process diagrams for explaining the manufacturing method of the field-effect transistor 200 according to the present embodiment.

[0036] First, after performing the process described using Figures 3 and 4, the entire surface is covered with an insulating film 72, as shown in Figure 8. Next, by providing through holes 66 in the insulating film 72, a portion of the main body 60 of the gate electrode 62 that covers the bottom 22 of the trench region 21 is exposed. Next, as shown in Figure 9, a connection portion 65 of the main body 60 of the gate electrode 62 is formed on the surface of the insulating film 72 so as to overlap with the through holes 66. As a result, the connection portion 65 of the main body 60 of the gate electrode 62 is connected via the through holes 66 to the portion of the main body 60 of the gate electrode 62 that is in contact with the insulating film 61. After that, as described using Figure 5, the entire surface is covered with an insulating film 71, and then a portion of the connection portion 65 is exposed by providing through holes 64 in the insulating film 71, and further, as described using Figure 6, a terminal portion 63 of the gate electrode 62 is formed on the surface of the insulating film 71 so as to overlap with the through holes 64. Then, n ＋ By forming a source electrode 30 in contact with layer 24 and a drain electrode 40 on the back surface 12 of the semiconductor substrate 10, the field-effect transistor 200 according to this embodiment is completed.

[0037] As illustrated by the field-effect transistor 200 according to the second embodiment, three or more insulating films may be interposed between the terminal portion 63 of the gate electrode 62 and the drift layer 20. This makes it possible to further mitigate the electric field concentrated at the edge portion 62A of the terminal portion 63 of the gate electrode 62.

[0038] <Third Embodiment>

[0039] Figure 10 is a schematic plan view showing the configuration of a field-effect transistor 300 according to a third embodiment of the technology described herein.

[0040] The field-effect transistor 300 according to the third embodiment differs from the field-effect transistor 100 according to the first embodiment in that the gate electrode 62 has two terminal portions 63 and through holes 64. The other basic configurations are the same as those of the field-effect transistor 100 according to the first embodiment, so the same elements are denoted by the same reference numerals and redundant explanations are omitted. As shown in Figure 10, in this embodiment, the terminal portions 63 of the gate electrode 62 and the through holes 64 are provided on both sides in the X direction of the plurality of fin structures 23.

[0041] As illustrated by the field-effect transistor 300 according to the third embodiment, the terminal portions 63 of the gate electrode 62 may be arranged in multiple locations. This increases the flexibility of the layout when mounting the field-effect transistor 300 on a circuit board. Furthermore, if the two terminal portions 63 are arranged symmetrically, the orientation of the product is eliminated, making the assembly work when mounting the field-effect transistor 300 on a circuit board easier.

[0042] <Fourth Embodiment>

[0043] Figure 11 is a schematic plan view showing the configuration of a field-effect transistor 400 according to a fourth embodiment of the technology described herein.

[0044] The field-effect transistor 400 according to the fourth embodiment differs from the field-effect transistor 100 according to the first embodiment in that the plurality of fin structures 23 extend in the X direction and are arranged in the Y direction. Since the other basic configurations are the same as those of the field-effect transistor 100 according to the first embodiment, the same reference numerals are used for the same elements, and redundant explanations are omitted. The X direction is the direction in which the plurality of fin structures 23 and the terminal portion 63 of the gate electrode 62 are arranged.

[0045] As illustrated by the field-effect transistor 400 according to the fourth embodiment, the extension direction and arrangement direction of the plurality of fin structures 23 are not particularly limited.

[0046] <Fifth Embodiment>

[0047] Figure 12 is a schematic plan view showing the configuration of a field-effect transistor 500 according to a fifth embodiment of the technology of this disclosure. Figure 13 is a substantially cross-sectional view along the line D-D shown in Figure 12.

[0048] The field-effect transistor 500 according to the fifth embodiment differs from the field-effect transistor 100 according to the first embodiment in that the terminal portion 63 of the gate electrode 62 is located outside the trench region 21, rather than inside the trench region 21, and that a part of the source electrode 30 is located outside the trench region 21. The other basic configurations are the same as those of the field-effect transistor 100 according to the first embodiment, so the same reference numerals are used for the same elements, and redundant explanations are omitted.

[0049] As illustrated by the field-effect transistor 500 according to the fifth embodiment, the terminal portion 63 of the gate electrode 62 may be located outside the trench region 21. This facilitates connection work such as wire bonding to the terminal portion 63 of the gate electrode 62. In this embodiment, only the insulating film 71 is interposed between the terminal portion 63 of the gate electrode 62 and the drift layer 20, and the insulating film 61 is not interposed between the two. Thus, it is not necessary for the insulating film 61 to be interposed between the terminal portion 63 and the drift layer 20.

[0050] <Sixth Embodiment>

[0051] Figure 14 is a schematic plan view showing the configuration of a field-effect transistor 600 according to a sixth embodiment of the technology described herein. Figure 15 is a substantially cross-sectional view along the line E-E shown in Figure 14.

[0052] The field-effect transistor 600 according to the sixth embodiment differs from the field-effect transistor 100 according to the first embodiment in that an insulating film 73 is added and the terminal portion 63 of the gate electrode 62 is located on the insulating film 73. Since the other basic configurations are the same as those of the field-effect transistor 100 according to the first embodiment, the same reference numerals are used for the same elements, and redundant explanations are omitted.

[0053] The insulating film 73 is located on the insulating film 61 and is selectively positioned at a location away from the multiple fin structures 23 at the bottom 22 of the trench region 21. The insulating film 73 may be a film made of the same insulating material as the insulating film 61, insulating film 72, or insulating film 72. In this embodiment, a part of the gate electrode 62 exposed through a through hole 64 provided in the insulating film 71 is used as the terminal portion 63. The portion of the gate electrode 62 that constitutes the terminal portion 63 is provided on the insulating film 73. As a result, a laminated film consisting of the insulating film 61 and the insulating film 73 is interposed between the terminal portion 63 of the gate electrode 62 and the drift layer 20.

[0054] Figures 16 to 18 are process diagrams illustrating the manufacturing method of the field-effect transistor 600 according to this embodiment.

[0055] First, after performing the process described using Figure 3, an insulating film 73 is formed at the bottom 22 of the trench region 21, away from the multiple fin structures 23, as shown in Figure 16. Next, as shown in Figure 17, a gate electrode 62 is formed so that a portion of it overlaps with the insulating film 73. Next, as shown in Figure 18, after covering the entire surface with the insulating film 71, a through hole 64 is provided in the insulating film 71, thereby exposing a portion of the gate electrode 62 located on the insulating film 73. The portion of the gate electrode 62 exposed through the through hole 64 is used as a terminal portion 63. After that, n ＋ By forming a source electrode 30 in contact with layer 24 and a drain electrode 40 on the back surface 12 of the semiconductor substrate 10, the field-effect transistor 100 according to this embodiment is completed.

[0056] As exemplified by the field-effect transistor 600 according to the sixth embodiment, a portion of the gate electrode 62 located on the insulating film 73 may be used as a terminal portion 63. This eliminates the need for a separate step of forming the terminal portion 63 from the main body portion 60 of the gate electrode 62.

[0057] <Seventh Embodiment>

[0058] Figure 19 is a schematic plan view showing the configuration of a field-effect transistor 700 according to a seventh embodiment of the technology described herein. Figure 20 is a substantially cross-sectional view along the line F-F shown in Figure 19.

[0059] The field-effect transistor 700 according to the seventh embodiment differs from the field-effect transistor 500 according to the fifth embodiment in that the source electrode 30 is formed not only in the portion overlapping with the trench region 21, but also outside the trench region 21 so as to surround the terminal portion 63 of the gate electrode 62, and the terminal portion 63 of the gate electrode 62 and the source electrode 30 are insulated by an insulating film 74. Since the other basic configurations are the same as those of the field-effect transistor 500 according to the fifth embodiment, the same reference numerals are used for the same elements, and redundant explanations are omitted.

[0060] As illustrated by the field-effect transistor 700 according to the seventh embodiment, the source electrode 30 may be provided so as to surround the terminal portion 63 of the gate electrode 62, or a part of the terminal portion 63 of the gate electrode 62 may be covered by the source electrode 30 via an insulating film 74. In this case, a part of the source electrode 30 is located outside the terminal portion 63 of the gate electrode 62 with respect to the trench region 21, so that the electric field is less likely to concentrate at the edge portion 62A of the terminal portion 63 of the gate electrode 62.

[0061] While embodiments of the technology described herein have been explained above, it goes without saying that the technology described herein is not limited to the embodiments described above, and various modifications are possible without departing from its spirit, and these modifications are also included within the scope of the technology described herein.

[0062] For example, in each of the above embodiments, gallium oxide was used as the material for the semiconductor substrate 10 and the drift layer 20. However, the material for the semiconductor substrate 10 and the drift layer 20 is not limited to gallium oxide. Other materials such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), diamond (C), silicon (Si), germanium (Ge), silicon germanium (SiGe), and gallium arsenide (GaAs) may also be used. Even when these materials are used as the material for the semiconductor substrate 10 and the drift layer 20, the same effect can be obtained by the same principle as when gallium oxide is used.

[0063] The technology relating to this disclosure includes, but is not limited to, the following configuration examples.

[0064] A field-effect transistor according to one aspect of the present disclosure comprises a semiconductor substrate, a drift layer provided on one surface of the semiconductor substrate and having a trench region and a plurality of fin structures, a first insulating film covering at least a portion of the sides of the plurality of fin structures and the bottom of the trench region, a gate electrode including a main body portion that covers at least a portion of the sides of the plurality of fin structures and the bottom of the trench region via the first insulating film, and a terminal portion connected to the main body portion, a source electrode connected to the upper surface of the plurality of fin structures, and a drain electrode connected to the other surface of the semiconductor substrate, wherein the plurality of fin structures are provided so as to protrude from the bottom of the trench region, the terminal portion of the gate electrode includes an edge portion of the gate electrode, at least a portion of the terminal portion of the gate electrode is exposed without being covered by the source electrode, and the distance between the terminal portion of the gate electrode and the drift layer is greater than the thickness of the portion of the first insulating film that covers the bottom of the trench region and is located between the main body portion of the gate electrode and the drift layer. This reduces electric field concentration at the edge portion of the terminal portion of the gate electrode.

[0065] The above-described field-effect transistor further comprises a second insulating film having a portion that covers the main body of the gate electrode, and the source electrode may be insulated from the main body of the gate electrode by the second insulating film. This facilitates the insulation of the gate electrode and the source electrode.

[0066] In the field-effect transistor described above, the terminal portion of the gate electrode may be connected to the main body of the gate electrode through a through-hole provided in the second insulating film. This makes it possible to further increase the distance between the terminal portion of the gate electrode and the drift layer.

[0067] In the field-effect transistor described above, the second insulating film may further have a portion located between the drift layer and the terminal portion of the gate electrode. This makes it possible to further increase the distance between the terminal portion of the gate electrode and the drift layer.

[0068] In the field-effect transistor described above, a first insulating film and a second insulating film may be interposed between the drift layer and the terminal portion of the gate electrode. This makes it possible to further increase the distance between the terminal portion and the drift layer.

[0069] The field-effect transistor described above further comprises a third insulating film different from the first and second insulating films, and the terminal portion of the gate electrode may be provided on the third insulating film. This makes it possible to select the film thickness and material of the second and third insulating films separately.

[0070] In the field-effect transistor described above, the gate electrode terminal may be located within the trench region or outside the trench region. Thus, the location of the terminal can be freely selected.

[0071] In the field-effect transistor described above, a portion of the source electrode may be located outside the terminal portion of the gate electrode with respect to the trench region. This further reduces the electric field applied to the terminal portion of the gate electrode.

[0072] In the field-effect transistor described above, the semiconductor substrate and drift layer may be made of gallium oxide. Gallium oxide has a very large bandgap of 4.8 to 4.9 eV and a large dielectric breakdown field of approximately 8 MV / cm, making it possible to achieve high performance as a switching element for power devices.

[0073] This application claims the interests of Japanese Patent Application No. 2024-194852, filed on 7 November 2024, the full disclosure of which is incorporated herein by reference.

[0074] 10 Semiconductor substrate 11 Top surface of semiconductor substrate 12 Back surface of semiconductor substrate 20 Drift layer 21 Trench region 22 Bottom of trench region 23 Fin structure 23S Side of fin structure 23T Top surface of fin structure 24 n ＋ Layer 30 Source electrode 40 Drain electrode 60 Main body 60A Edge portion 61 Insulating film 62 Gate electrode 62A Edge portion 63 Terminal portion 64 Through hole 65 Connection portion 66 Through hole 71-74 Insulating film 100, 200, 300, 400, 500, 600, 700 Field-effect transistor

Claims

1. A field-effect transistor comprising: a semiconductor substrate; a drift layer provided on one surface of the semiconductor substrate and having a trench region and a plurality of fin structures; a first insulating film covering at least a portion of the sides of the plurality of fin structures and at least a portion of the bottom of the trench region; a gate electrode including a main body portion that covers at least a portion of the sides of the plurality of fin structures and the bottom of the trench region via the first insulating film, and a terminal portion connected to the main body portion; a source electrode connected to the upper surface of the plurality of fin structures; and a drain electrode connected to the other surface of the semiconductor substrate, wherein the plurality of fin structures are provided so as to protrude from the bottom of the trench region; the terminal portion of the gate electrode includes an edge portion of the gate electrode; at least a portion of the terminal portion of the gate electrode is exposed without being covered by the source electrode; and the distance between the terminal portion of the gate electrode and the drift layer is greater than the thickness of the portion of the first insulating film that covers the bottom of the trench region and is located between the main body portion of the gate electrode and the drift layer.

2. The field-effect transistor according to claim 1, further comprising a second insulating film having a portion that covers the main body of the gate electrode, wherein the source electrode is insulated from the main body of the gate electrode by the second insulating film.

3. The field-effect transistor according to claim 2, wherein the terminal portion of the gate electrode is connected to the main body portion of the gate electrode through a through hole provided in the second insulating film.

4. The field-effect transistor according to claim 2, wherein the second insulating film further has a portion located between the drift layer and the terminal portion of the gate electrode.

5. The field-effect transistor according to claim 4, wherein the first insulating film and the second insulating film are interposed between the drift layer and the terminal portion of the gate electrode.

6. The field-effect transistor according to claim 2, further comprising a third insulating film different from the first and second insulating films, wherein the terminal portion of the gate electrode is provided on the third insulating film.

7. The field-effect transistor according to claim 1, wherein the terminal portion of the gate electrode is located within the trench region.

8. The field-effect transistor according to claim 1, wherein the terminal portion of the gate electrode is located outside the trench region.

9. The field-effect transistor according to claim 8, wherein a portion of the source electrode is located outside the terminal portion of the gate electrode with respect to the trench region.

10. The field-effect transistor according to any one of claims 1 to 9, wherein the semiconductor substrate and the drift layer are made of gallium oxide.

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