Input network for wideband analog front end (AFE) using parallel inductors

Abstract

An analog front-end circuit (AFE – 100) includes differential input terminals (102), a differential amplifier (120), termination resistors (106), and parallel inductors (104). The differential input terminals are configured to receive a differential signal. The differential amplifier is configured to amplify the differential signal. The termination resistors are configured to terminate the differential signal with a termination resistance. The parallel inductors are connected between the differential input terminals and the termination resistors, thereby setting a DC impedance presented at the differential input terminals to match the termination resistance of the termination resistors.

Description

[0001] INPUT NETWORK FOR WIDEBAND ANALOG FRONT END (AFE) USING PARALLEL

[0002] INDUCTORS

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application claims the benefit of U.S. Provisional Patent Application 63 / 717,303, filed November 7, 2024, whose disclosure is incorporated herein by reference.

[0005] FIELD OF THE INVENTION

[0006] The present disclosure relates to analog front end circuits for wideband signal processing, and more particularly to impedance matching of wideband differential receivers.

[0007] BACKGROUND OF THE INVENTION

[0008] Wideband analog front-end systems play a fundamental role in modem communication receivers, where maintaining signal integrity across wide frequency ranges is a primary design goal. These systems should portray a well-matched input impedance and a stable gain across a wide frequency range.

[0009] Traditional analog front-end input networks face several challenges in achieving consistent performance across broad bandwidths. Impedance matching represents a particular area of difficulty, as conventional designs struggle to maintain stable input impedance characteristics across a wide frequency spectrum. Variations in impedance can lead to signal reflections, which degrade overall system performance and reduce signal quality.

[0010] Voltage gain consistency presents another challenge in wideband analog front-end design. Many existing approaches experience gain variations across the specified bandwidth of the frond end circuit, which can result in signal reflections and introduce unwanted distortion.

[0011] Electrostatic discharge protection adds another layer of complexity to analog front-end design. Protection circuits must be integrated without compromising the primary signal processing functions, while ensuring that sensitive amplifier stages remain protected from potentially damaging static charges.

[0012] SUMMARY OF THE INVENTION

[0013] An embodiment that is described herein provides an analog front-end circuit (AFE) including differential input terminals, a differential amplifier, termination resistors, and parallel inductors. The differential input terminals are configured to receive a differential signal. The differential amplifier is configured to amplify the differential signal. The termination resistors are configured to terminate the differential signal with a termination resistance. The parallel inductors are connected between the differential input terminals and the termination resistors, thereby setting a DC impedance presented at the differential input terminals to match the termination resistance of the termination resistors.

[0014] In an embodiment, the AFE further includes a high frequency (HF) shorting capacitor that is connected between the termination resistors, the impedance of the HF-shorting capacitor being smaller than the impedance of the termination resistors for frequencies of the differential signal that are above a preset mid-frequency threshold.

[0015] In a disclosed embodiment, the AFE further includes serial capacitors that are connected between the differential input terminals and inputs of the differential amplifier, such that an impedance of the serial capacitors, when connected in parallel with the parallel inductors, sets the impedance of the analog AFE at a preset medium frequency range, within preset limits.

[0016] In an example embodiment, the AFE further includes one or more electrostatic discharge (ESD) protection circuits connected to respective termination resistors.

[0017] There is additionally provided, in accordance with an embodiment that is described herein, a method in an analog front-end circuit (AFE). The method includes receiving a differential signal over differential input terminals, and amplifying the differential signal using a differential amplifier. The differential signal is terminated with a termination resistance using termination resistors. A DC impedance, presented at the differential input terminals, is set to match the termination resistance of the termination resistors using parallel inductors that are connected between the differential input terminals and the termination resistors.

[0018] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0019] BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Fig. l is a block diagram that schematically illustrates an analog front end (AFE) circuit, in accordance with an embodiment of the present invention;

[0021] Fig. 2 is a block diagram that schematically illustrates a DC response analysis of the AFE circuit, in accordance with an embodiment of the present invention;

[0022] Fig. 3 is a block diagram that schematically illustrates a mid-range and high-range frequency response analysis of the AFE circuit, in accordance with an embodiment of the present invention;

[0023] Fig. 4 is a block diagram that schematically illustrates an ESD path analysis of the AFE circuit, in accordance with an embodiment of the present invention; and

[0024] Fig. 5 is a flowchart that schematically illustrates a method for designing a wideband AFE circuit, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS

[0025] OVERVIEW

[0026] A wideband analog front-end circuit (AFE) is presented, featuring stable input impedance and gain, across a wide frequency spectrum. In an embodiment, the AFE comprises parallel inductors that connect differential signal inputs of the AFE to termination resistors and to ESD devices. The combination of the inductors and the input capacitance of a high impedance differential amplifier improves the mid to high frequency characteristics of the AFE. Comprehensive analyses are provided, including DC, mid-band, and high-frequency performance, along with an evaluation of the ESD current path.

[0027] SYSTEM DESCRIPTION

[0028] The following detailed description presents an embodiment of a wideband analog frontend circuit (AFE) that employs parallel inductors for low-frequency impedance matching and achieves good impedance matching and gain characteristics over a wideband spectrum of input frequencies.

[0029] We will use the terms low frequency, medium-frequency (also referred to hereinbelow as mid-band) and high frequency in the descriptions hereinbelow. In embodiments, the numerical values, in Hertz, for the border points between low and medium frequencies, and between medium and high frequencies may vary, according to the characteristics of the input signal.

[0030] In embodiments, the disclosed AFE may be used in any wideband receiver application; for example, in an embodiment, the disclosed AFE is used in a receiver of an optical communication system.

[0031] In an example embodiment, the low frequency range is DC to 3G, the mid-frequency range is between 3G and 60G, and the high frequency range is greater than 60G. The nominal impedance in this example is 50Q, with variations of ±5% in the low frequency range, ±20% in the mid frequency range and ±25% in the high frequency range. The gain is 1 in the low and medium frequency ranges, and approaches 0 at the maximum frequency. All these numerical values are given purely by way of non-limiting example.

[0032] Fig. l is a block diagram that schematically illustrates an analog front end (AFE) circuit 100, in accordance with an embodiment of the present invention. AFE 100 includes input terminals 102 configured as differential inputs, labeled Vin± and Vin- for receiving a differential wideband signal. A pair of inductors 104 provides DC paths from the input terminals through a pair of termination resistors 106 to a common-mode voltage source. In some embodiments, each of resistors 106 is a 50 resistor; other values, e.g., 75Q, may be used in alternative embodiments. A High Frequency (HF) shorting capacitor 108 shorts the termination resistors in medium to high frequencies.

[0033] For Electrostatic Discharge (ESD) protection, AFE 100 comprises a pair of diodes 110 and a pair of diodes 112, providing, respectively, a discharge path for high voltage and low voltage charges that may be applied at the input terminals.

[0034] AFE 100 further comprises a pair of Rtune resistors 114, a pair of Ctune capacitors 116, and a high impedance differential amplifier 120. Ctune capacitors 116 are connected in the signal paths to provide frequency -dep endent impedance control. The input impedances of the positive and negative inputs of amplifier 120 are modelled by a pair of resistors 122 and a pair of capacitors 124.

[0035] In embodiments, the resistances of R103 and Rtune 114, the capacitances of C106 and Ctune 116 and the inductances of inductors 104 are set according to the characteristics of the differential input signal, including its frequency spectrum and characteristic impedance.

[0036] In some embodiments, the resistances of R103, the capacitance of Cl 06, and the inductances of inductors 104 are predetermined during the design stage, while the resistance of Rtune 114 and the capacitances of Ctune 116 may be calibrated post-fabrication to compensate for process variations. In other embodiments, various combinations of design-set and calibration-set resistance, capacitance, and inductance parameters may be employed. In certain embodiments, one or more component parameters (such as the resistance of Rtune) may be dynamically tuned during run time (e.g., by selectively connecting one of several available resistances), thereby enabling adaptation to real-time variations in power supply, temperature, and / or input signal conditions.

[0037] Fig. 2 is a block diagram that schematically illustrates a DC response analysis 200 of and AFE circuit 100, in accordance with an embodiment of the present invention. As indicated in Fig. 2, for DC response, the impedances of inductors 104 are zero, and the impedances of capacitor 106, Ctune capacitors 116 and capacitors 124 are infinity. The DC path is illustrated using a pair of dashed arrows; the DC input impedance of AFE 100 is, thus, equal to the resistance of resistor 106.

[0038] Fig. 3 is a block diagram that schematically illustrates a mid-range and high-range frequency response analysis 300 of an AFE circuit 100, in accordance with an embodiment of the present invention. For mid-band Impedance Control, capacitor 108 shorts the termination resistors, bypassing their impact on the input impedance. Additionally, Ctune capacitors 116 short the series resistors Rtune 114, leaving the parallel tank 302 circuit formed by inductors 104 and the input capacitances of differential amplifier 120 (modeled by capacitors 124) as the dominant impedance contributors.

[0039] This parallel tank circuit stabilizes the impedance at mid-band frequencies around the impedance of the termination resistors (e.g., 50Q), providing a smooth transition from low to mid-band frequency response.

[0040] At high frequencies, the input capacitance of differential amplifier 120 (modelled by capacitors 124) dominate the impedance response. In embodiments, the impedance of capacitor 124 limits the high-frequency gain, optimizing the bandwidth while preserving impedance characteristics.

[0041] Fig. 4 is a block diagram that schematically illustrates an ESD path analysis 400 of an AFE circuit 100, in accordance with an embodiment of the present invention. Diodes 110 and 112 provide ESD discharge paths to a positive and a negative supply rail, respectively.

[0042] Tuning Resistors Rtune 114 are placed in series in each input path and, in embodiments, have a significantly higher impedance than the path of the ESD currents. This configuration mitigates the hazard that some of the electrostatic charge energy, not dissipated in the diodes, will reach the differential amplifier through Rtune resistors, and damage the input circuitry. This is achieved without impacting normal signal performance.

[0043] The configuration of AFE circuit 100 illustrated in Figs 1 through 4 and described hereinabove is cited by way of example. Other configurations may be used in alternative embodiments. For example, in an embodiment, the AFE is single-ended rather than differential, with only a single one of each of the pairs inductors 104, termination resistors 106 Rtune resistors 114, Ctune capacitors 116; the differential amplifier is replaced by a single-ended amplifier and capacitor 108 is coupled to ground. In another configuration, resistors are placed in series to Ctune capacitors 116, to mitigate the risk that an electrostatic charge will reach the differential amplifier through the Ctune capacitor.

[0044] In some embodiments, a second set of EDS protection diodes is places adjacent to the input of the first AFE amplifier, for extra ESD protection.

[0045] Fig. 5 is a flowchart 500 that schematically illustrates a method for designing a wideband AFE circuit, in accordance with an embodiment of the present invention. The flowchart is executed by AFE circuits 100 (Fig. 1), and the components thereof. The flowchart starts at a set-DC-characteristics operation 502, wherein the DC impedance is set according to termination resistors 106, which are DC-shorted through inductors 104 to input terminals 102. Assuming the input resistance R122 of the differential amplifier is substantially higher than the resistance of Rtune R114, the DC attenuation is close to 1.

[0046] Next, at a set-mid-band-characteristics operation 504, the midband input impedance and gain are set according to the LC tanks comprising inductors 104 and capacitors 124 (Note that termination resistors 108 are shorted by capacitor 106 and Rtune resistors 114 are shorted by Ctune capacitors 116).

[0047] Now, at a set-high-frequency-characteristics operation 506, the high frequency input impedance is set according to the resistance of Rtune 124 and the capacitance 124. The attenuation is set according to the ratio between capacitor 124 impedance and Ctune 116 impedance.

[0048] Lastly, at a set-ESD-path operation 508, ESD paths are defined through inductors 104 and diodes 110 (for positive charges) and 112 (for negative charges). The inputs of the differential amplifier are further protected against ESD by Rtune resistors 114, which have a significantly higher impedance than the path of ESD currents.

[0049] The configurations, analyses and method described hereinabove, with reference to Figs 1 through 5, including all units and subunits thereof, are example configurations, analyses and method that are shown purely for the sake of conceptual clarity. Any other suitable configurations, analyses and methods may be used in alternative embodiments.

[0050] In various embodiments, any subunits of AFE 100 may be implemented using suitable hardware, such as one or more Application-Specific Integrated Circuits (ASIC) or Field- Programmable Gate Arrays (FPGA), or a combination of ASIC and FPGA.

[0051] It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

CLAIMS1. An analog front-end circuit (AFE), comprising: differential input terminals, configured to receive a differential signal; a differential amplifier configured to amplify the differential signal; termination resistors, configured to terminate the differential signal with a termination resistance; and parallel inductors, connected between the differential input terminals and the termination resistors, thereby setting a DC impedance presented at the differential input terminals to match the termination resistance of the termination resistors.

2. The AFE according to claim 1, further comprising a high frequency (HF) shorting capacitor that is connected between the termination resistors, wherein the impedance of the HF- shorting capacitor is smaller than the impedance of the termination resistors for frequencies of the differential signal that are above a preset mid-frequency threshold.

3. The AFE according to claim 1 or 2, further comprising serial capacitors that are connected between the differential input terminals and inputs of the differential amplifier, wherein an impedance of the serial capacitors, when connected in parallel with the parallel inductors, sets the impedance of the analog AFE at a preset medium frequency range, within preset limits.

4. The AFE according to claim 1 or 2, further comprising one or more electrostatic discharge (ESD) protection circuits, that are connected to respective termination resistors.

5. A method in an analog front-end circuit (AFE), the method comprising: receiving a differential signal over differential input terminals; amplifying the differential signal using a differential amplifier; using termination resistors, terminating the differential signal with a termination resistance; and using parallel inductors, connected between the differential input terminals and the termination resistors, setting a DC impedance presented at the differential input terminals to match the termination resistance of the termination resistors.

6. The AFE according to claim 5, further comprising applying a high frequency (HF) shorting capacitor that is connected between the termination resistors, wherein the impedance of the HF-shorting capacitor is smaller than the impedance of the termination resistors for frequencies of the differential signal that are above a preset mid-frequency threshold.

7. The AFE according to claim 5 or 6, further comprising applying serial capacitors that are connected between the differential input terminals and inputs of the differential amplifier, wherein an impedance of the serial capacitors, when connected in parallel with the parallel inductors, sets the impedance of the analog AFE at a preset medium frequency range, within preset limits.

8. The AFE according to claim 5 or 6, further comprising applying one or more electrostatic discharge (ESD) protection circuits, that are connected to respective termination resistors.

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