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一种基于高层次综合的QC-LDPC编码器
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CN117375633B
reduce overhead
reduce consumption
本发明公开了一种基于高层次综合的QC‑LDPC编码器,属于编码器设计领域,包括:依次连接的数据输入模块、编码计算模块和数据输出模块;编码计算模块包括:矩阵乘结果寄存器,以及M×N个子矩阵编码单元形成的M行N列的编码阵列;各子矩阵编码单元包括:z位循环移位寄存器和计算门电路,用于实现z×z子矩阵循环编码;数据输入模块用于整体读入一帧待编码数据字;编码计算模块用于:循环从待编码数据字中每隔z‑1位挑选出一位数据,对筛选出的数据进行并行编码,直至完成对待编码数据字的循环并行编码,输出编码后的校验位,组合待编码数据字和校验位得到编码后数据字并通过数据输出模块输出。降低了QC‑LDPC编码器的硬件消耗,并提高其编码速率。
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HUAZHONG UNIV OF SCI & TECH
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