A control chip power disconnection device and operation method thereof

Abstract

The present invention provides a control chip power on-off device and an operation method thereof. The control chip power on-off device includes a control register, a logic control circuit and a power switch, wherein the control register includes N special registers; 2≤N≤6; the special register includes a write enable generation circuit, a selector and a D flip-flop, the write enable generation circuit is connected to the selector, and the selector is connected to the D flip-flop; the logic control circuit includes N power request generation circuits and N power switches, the N power request generation circuits correspond to each other and are connected to the N power switches in sequence, and the N power switches output their respective power supplies. The present invention has a power domain switch selection function, and selects the power domain to be turned off or on through a special register. Under the configuration of the special register, the selected power domains are turned on or off successively, thereby reducing the overall power consumption of the chip and achieving the purpose of reducing instantaneous current impact.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit digital design, and in particular to a control chip power disconnection device and an operation method thereof. Background Art

[0002] As the requirements of consumer electronics for power consumption become increasingly stringent, low-power technology is an essential part of SOC design. Currently mature low-power technologies include gating technology, multi-threshold voltage technology, power-off technology, etc. Among them, the power-off technology is to turn off the power supply of some digital logic when it does not need to work, so as to achieve the purpose of saving power consumption.

[0003] like Figure 1 As shown in the figure, it is a structural diagram of the existing chip power disconnection device. The function of the power switch device is to turn on the power supply VCC of the module device connected to it after receiving the power enable signal. Each power domain has an independent request signal (pw_gating_req) and response signal (pw_gating_ack). For example: pw_gating_req=1'b1 represents a power off request; pw_gating_ack=1'b1 represents the completion of the power operation, and each power switch is independent of each other. When multiple power supplies are turned on or off at the same time, for example: the chip wakes up from sleep and turns on or off the power at the same time, it will cause a current surge, which not only consumes power but also damages the devices in the chip. Summary of the invention

[0004] In view of the deficiencies in the above-mentioned prior art, the object of the present invention is to provide a device for controlling chip power supply disconnection and an operating method thereof, which can turn on or off the power domain to be controlled in a serial manner during the power switching process, and has a power domain switch selection function, which can select the power domain to be turned off or on through a special register, thereby reducing the overall power consumption of the chip and reducing instantaneous current shocks.

[0005] In order to achieve the above technical purpose, the technical solution adopted by the present invention is:

[0006] A control chip power supply disconnection device, characterized in that the power supply disconnection device comprises a control register, a logic control circuit and a power switch, wherein the control register comprises N special registers; 2≤N≤6; the special register is connected to the logic control circuit, and the logic control circuit outputs power;

[0007] The special register includes a write enable generation circuit, a selector and a D flip-flop, the write enable generation circuit is connected to the selector, and the selector is connected to the D flip-flop;

[0008] The logic control circuit includes N power request generating circuits and N power switches, the N power request generating circuits correspond to and are connected to the N power switches in sequence, and the N power switches output respective power supplies;

[0009] The N D flip-flops in the N special registers correspond one by one in sequence and are connected to the N power request generating circuits;

[0010] When the power disconnect device is working, the external write signal sfr_wr and the address signal sfr_addr are input into the write enable generation circuit. When the address signal sfr_addr is equal to the address of the special register SFRPD and the write signal sfr_wr is at a high level, the write enable generation circuit outputs the write enable signal wr, and the write enable signal wr enters the selector for judgment; if the write enable signal wr is judged to be valid, the external input write data signal sfr_wdata reaches the D port of the D flip-flop in the special register SFRPD through the selector, and the Q port of the D flip-flop outputs the control signal of the special register; if the write enable signal wr is judged to be invalid, the Q port of the D flip-flop in the special register SFRPD enables the write enable signal wr to reach the D port of the D flip-flop through the selector, and the Q port of the D flip-flop outputs the control signal of the special register;

[0011] The control signal output by the special register SFRPD reaches the corresponding power request generating circuit in the logic control circuit. The power request generating circuit REG_GEN generates a corresponding power request signal pw_gating_req. The corresponding power request signal pw_gating_req enters and controls the corresponding power switch PW. After the corresponding power switch PW turns off or turns on the corresponding power supply VCC, the corresponding power switch PW generates a corresponding power response signal pw_gateing_ack signal.

[0012] When the external input reset signal Reset is enabled, the D flip-flop of the special register SFRPD is reset.

[0013] An operating method for controlling a chip power disconnection device, the operating method is divided into the following specific steps:

[0014] Step S1: After the power disconnection device is started, the external write signal sfr_wr and the address signal sfr_addr are input into the special register in the control register, and the write enable generation circuit in the special register judges the write signal sfr_wr and the address signal sfr_addr. When the address signal sfr_addr is equal to the address of the special register SFRPD and the write signal sfr_wr is at a high level, the write enable generation circuit outputs the write enable signal wr, and the write enable signal wr enters the selection port of the selector for judgment;

[0015] Step S2: If the selector determines that the write enable signal wr is valid, the external input write data signal sfr_wdata reaches the D port of the D flip-flop in the special register SFRPD through the selector, and the Q port of the D flip-flop outputs the respective control signals of the special register; if the selector determines that the write enable signal wr is invalid, the Q port of the D flip-flop in the special register SFRPD enables the write enable signal wr to reach the D port of the D flip-flop through the selector, and the Q port of the D flip-flop outputs the respective control signals of the special register; the control signal output by the special register SFRPD reaches the one-to-one corresponding power request generating circuit in the logic control circuit;

[0016] Step S3: The corresponding power request generating circuit first determines whether the first control signal is updated and configured. If the first control signal is updated and configured, a first power request signal pw_gating_req1 is generated. The first power request signal pw_gating_req1 enters and controls the first power switch PW1. After the first power switch PW1 turns off or turns on the first power VCC1, the first power switch PW1 generates a first power response signal pw_gateing_ack1.

[0017] When the power is turned on, the power is output;

[0018] Step S4: after determining that the first control signal update configuration is completed and the first power response signal pw_gateing_ack1 is generated, the remaining control signals are determined in sequence one by one until the last control signal is the Nth control signal;

[0019] Step S5: Finally, determine whether the Nth control signal has been updated. If the Nth control signal has been updated, the operation method ends; otherwise, repeat from step S3 above.

[0020] The control chip power disconnection device of the present invention adopts the above-mentioned control register, logic control circuit and power switch structure and the operation method of the control chip power disconnection device of the present invention, so the beneficial effect is that during the power switching process, the power of the power domain to be controlled is turned on or off in a serial manner. After the operation of the previous power switch is completed, the next power switch is started, which can control multiple power switches and avoid current shock caused by simultaneous operation; at the same time, the present invention also has a power domain switch selection function, which selects the power domain to be turned off or on through a special register, and under the configuration of the special register, the selected power domains are turned on or off successively, thereby reducing the overall power consumption of the chip and achieving the purpose of reducing instantaneous current shock.

[0021] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural diagram of an existing chip power disconnect device.

[0023] Figure 2 It is a structural diagram of a control chip power disconnection device specifically implemented in the present invention.

[0024] Figure 3 It is a special register structure diagram for the specific implementation of the present invention.

[0025] Figure 4 It is a step diagram of the operation method of the control chip power disconnecting device specifically implemented by the present invention. DETAILED DESCRIPTION

[0026] See also Figure 2 , is a structural diagram of a control chip power disconnection device implemented in the present invention; the control chip power disconnection device includes a control register, a logic control circuit and a power switch, wherein the control register includes N special registers; 2≤N≤6; the special register is connected to the logic control circuit, and the logic control circuit outputs power. Figure 3 , is a structural diagram of a special register specifically implemented in the present invention; the special register includes a write enable generating circuit, a selector and a D flip-flop, the write enable generating circuit is connected to the selector, and the selector is connected to the D flip-flop; the logic control circuit includes N power request generating circuits and N power switches, the N power request generating circuits correspond one-to-one in sequence and are connected to the N power switches, and the N power switches output their own power supplies respectively; the N D flip-flops in the N special registers correspond one-to-one in sequence and are connected to the N power request generating circuits.

[0027] See also Figure 2 and Figure 3As shown, when the power disconnect device is working, the external write signal sfr_wr and the address signal sfr_addr are input into the write enable generation circuit. When the address signal sfr_addr is equal to the address of the special register SFRPD and the write signal sfr_wr is at a high level, the write enable generation circuit outputs the write enable signal wr, and the write enable signal wr enters the selector for judgment; if the write enable signal wr is judged to be valid, the external input write data signal sfr_wdata reaches the D port of the D flip-flop in the special register SFRPD through the selector, and the Q port of the D flip-flop outputs the control signal of the special register; if the write enable signal wr is judged to be invalid, the Q port of the D flip-flop in the special register SFRPD enables the write enable signal wr The control signal of the special register is output through the selector to the D port of the D flip-flop, and the Q port of the D flip-flop outputs the control signal of the special register; the control signal output by the special register SFRPD reaches the corresponding power request generating circuit in the logic control circuit, and the power request generating circuit REG_GEN generates a corresponding power request signal pw_gating_req, and the corresponding power request signal pw_gating_req enters and controls the corresponding power switch PW. After the corresponding power switch PW turns off or turns on the corresponding power supply VCC, the corresponding power switch PW generates a corresponding power response signal pw_gateing_ack signal; if the external input reset signal Reset is enabled, the D flip-flop of the special register SFRPD is reset.

[0028] See also Figure 4 , a step diagram of the operation method of the control chip power disconnection device specifically implemented by the present invention. The operation method of the control chip power disconnection device is divided into the following specific steps:

[0029] Step S1: After the power disconnection device is started, the external write signal sfr_wr and the address signal sfr_addr are input into the special register in the control register, and the write enable generation circuit in the special register judges the write signal sfr_wr and the address signal sfr_addr. When the address signal sfr_addr is equal to the address of the special register SFRPD and the write signal sfr_wr is at a high level, the write enable generation circuit outputs the write enable signal wr, and the write enable signal wr enters the selection port of the selector for judgment;

[0030] Step S2: If the selector determines that the write enable signal wr is valid, the external input write data signal sfr_wdata reaches the D port of the D flip-flop in the special register SFRPD through the selector, and the Q port of the D flip-flop outputs the respective control signals of the special register; if the selector determines that the write enable signal wr is invalid, the Q port of the D flip-flop in the special register SFRPD enables the write enable signal wr to reach the D port of the D flip-flop through the selector, and the Q port of the D flip-flop outputs the respective control signals of the special register; the control signal output by the special register SFRPD reaches the one-to-one corresponding power request generating circuit in the logic control circuit;

[0031] Step S3: The corresponding power request generating circuit first determines whether the first control signal is updated and configured. If the first control signal is updated and configured, a first power request signal pw_gating_req1 is generated. The first power request signal pw_gating_req1 enters and controls the first power switch PW1. After the first power switch PW1 turns off or turns on the first power VCC1, the first power switch PW1 generates a first power response signal pw_gateing_ack1.

[0032] When the power is turned on, the power is output;

[0033] Step S4: after determining that the first control signal update configuration is completed and the first power response signal pw_gateing_ack1 is generated, the remaining control signals are determined in sequence one by one until the last control signal is the Nth control signal;

[0034] Step S5: Finally, determine whether the Nth control signal has been updated. If the Nth control signal has been updated, the operation method ends; otherwise, repeat from step S3 above.

[0035] In the present invention, the switches of the power domains are selectable, and the operations of the selected power domains can be executed in sequence, thereby achieving the effect of reducing the overall power consumption of the chip and reducing the instantaneous current impact.

[0036] It should be noted that the above embodiments are only schematic illustrations of the basic concept of the present invention, and the component circuits related to the present invention are not drawn according to the number, shape, device arrangement, and connection method of the component circuits in actual implementation. The type, number, connection method, device arrangement, and device parameters of each circuit in actual implementation can be changed at will.

[0037] The above-described embodiments are only preferred embodiments of the present invention and cannot limit the extension of the technical solution of the present invention. Any modification, equivalent change and obvious replacement of the known technology made by those skilled in the art on the basis of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A control chip power disconnection device, characterized in that: The power disconnection device includes a control register, a logic control circuit and a power switch, wherein the control register includes N special registers; 2≤N≤6; the special register is connected to the logic control circuit, and the logic control circuit outputs power; The special register includes a write enable generation circuit, a selector and a D flip-flop, the write enable generation circuit is connected to the selector, and the selector is connected to the D flip-flop; The logic control circuit includes N power request generating circuits and N power switches, the N power request generating circuits correspond to and are connected to the N power switches in sequence, and the N power switches output respective power supplies; The N D flip-flops in the N special registers correspond one by one in sequence and are connected to the N power request generating circuits; When the power disconnect device is working, the external write signal sfr_wr and the address signal sfr_addr are input into the write enable generation circuit. When the address signal sfr_addr is equal to the address of the special register SFRPD and the write signal sfr_wr is at a high level, the write enable generation circuit outputs the write enable signal wr, and the write enable signal wr enters the selector for judgment; if the write enable signal wr is judged to be valid, the external input write data signal sfr_wdata reaches the D port of the D flip-flop in the special register SFRPD through the selector, and the Q port of the D flip-flop outputs the control signal of the special register; if the write enable signal wr is judged to be invalid, the Q port of the D flip-flop in the special register SFRPD enables the write enable signal wr to reach the D port of the D flip-flop through the selector, and the Q port of the D flip-flop outputs the control signal of the special register; The control signal output by the special register SFRPD reaches the one-to-one corresponding power request generating circuit in the logic control circuit, and the power request generating circuit REQ_GEN generates a corresponding power request signal pw_gating_req, and the corresponding power request signal pw_gating_req enters and controls the corresponding power switch PW. After the corresponding power switch PW turns off or turns on the corresponding power supply VCC, the corresponding power switch PW generates a corresponding power response signal pw_gating_ack signal; the N power switches perform the operation of turning off or turning on the corresponding power supply VCC in sequence according to the serial connection order; When the external input reset signal Reset is enabled, the D flip-flop of the special register SFRPD is reset.

2. An operation method of a control chip power disconnection device, based on the power disconnection device of claim 1, characterized in that: The operation method is divided into the following specific steps: Step S1: After the power disconnection device is started, the external write signal sfr_wr and the address signal sfr_addr are input into the special register in the control register, and the write enable generation circuit in the special register judges the write signal sfr_wr and the address signal sfr_addr. When the address signal sfr_addr is equal to the address of the special register SFRPD and the write signal sfr_wr is at a high level, the write enable generation circuit outputs the write enable signal wr, and the write enable signal wr enters the selection port of the selector for judgment; Step S2: If the selector determines that the write enable signal wr is valid, the external input write data signal sfr_wdata reaches the D port of the D flip-flop in the special register SFRPD through the selector, and the Q port of the D flip-flop outputs the respective control signals of the special register; if the selector determines that the write enable signal wr is invalid, the Q port of the D flip-flop in the special register SFRPD enables the write enable signal wr to reach the D port of the D flip-flop through the selector, and the Q port of the D flip-flop outputs the respective control signals of the special register; the control signal output by the special register SFRPD reaches the one-to-one corresponding power request generating circuit in the logic control circuit; Step S3: The corresponding power request generating circuit first determines whether the first control signal is updated and configured. If the first control signal is updated and configured, a first power request signal pw_gating_req1 is generated. The first power request signal pw_gating_req1 enters and controls the first power switch PW1. After the first power switch PW1 turns off or turns on the first power VCC1, the first power switch PW1 generates a first power response signal pw_gating_ack1. When the power is turned on, the power is output; Step S4: after determining that the first control signal update configuration is completed and the first power response signal pw_gating_ack1 is generated, the remaining control signals are determined in sequence until the last control signal is the Nth control signal; Step S5: Finally, determine whether the Nth control signal has been updated. If the Nth control signal has been updated, the operation method ends; otherwise, repeat from step S3 above.

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