Semiconductor devices

Abstract

A semiconductor device with a high operating frequency is provided. One embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a first oxide on the second insulating layer, a second oxide on the first oxide, a third oxide on the second oxide, a third insulating layer on the third oxide, a second conductive layer on the third insulating layer, and a fourth insulating layer, the first conductive layer and the second conductive layer have a region overlapping with the second oxide, the side surfaces of the second conductive layer, the third insulating layer and the third oxide are substantially aligned, the fourth insulating layer is in contact with the side surfaces of the second conductive layer, the third insulating layer and the third oxide and a portion of the top surface of the second oxide, and in the channel width direction of the transistor, the height of the bottom surface of the second oxide when the height of the bottom surface of the second conductive layer in the region not overlapping with the second oxide is taken as a reference is greater than 5 nm and less than 0 nm.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification, etc., semiconductor devices refer to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or storage devices are also a form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] As semiconductor thin films that can be applied to transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, it is known that in addition to unit metal oxides such as indium oxide and zinc oxide, there are also multinary metal oxides. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly hot.

[0005] Through the study of IGZO, CAAC (c-axis aligned crystalline: c-axis oriented crystal) structure and nc (nanocrystalline: nanocrystalline) structure, which are neither single crystal nor amorphous, were discovered in oxide semiconductors (see non-patent documents 1 to 3). Non-patent documents 1 and 2 disclose a technology for manufacturing transistors using an oxide semiconductor having a CAAC structure. Non-patent documents 4 and 5 disclose an oxide semiconductor having a lower crystallinity than a CAAC structure and a nc structure and also having tiny crystals.

[0006] A transistor using IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] [Prior technical literature]

[0008] [Non-patent literature]

[0009] [Non-patent document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186

[0010] [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10

[0011] [Non-patent document 3] S. Ito et al., "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p.151-154

[0012] [Non-patent document 4] S. Yamazaki et al., "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022

[0013] [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p.155-164

[0014] [Non-patent document 6] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7

[0015] [Non-patent document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217

[0016] [Non-patent document 8] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention

[0017] Technical problem to be solved by the invention

[0018] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a high operating frequency. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. Another purpose of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0019] One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a fast data writing speed. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a high degree of design freedom. One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device.

[0020] Note that the recording of these purposes does not prevent the existence of other purposes. Note that one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes can be clearly seen from the description of the specification, drawings, claims, etc., and can be extracted from the description of the specification, drawings, claims, etc.

[0021] Solutions to technical problems

[0022] One embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a first oxide on the second insulating layer, a second oxide on the first oxide, a third oxide on the second oxide, a third insulating layer on the third oxide, a second conductive layer on the third insulating layer, and a fourth insulating layer, the first conductive layer and the second conductive layer have a region overlapping with the second oxide, the side surfaces of the second conductive layer, the third insulating layer and the third oxide are substantially aligned, the fourth insulating layer is in contact with the side surfaces of the second conductive layer, the third insulating layer and the third oxide and a portion of the top surface of the second oxide, in a channel width direction of the transistor, the bottom surface of the second oxide is located below the bottom surface of the second conductive layer in a region where the second oxide and the first oxide do not overlap with the second conductive layer, and the height of the bottom surface of the second oxide when the height of the bottom surface of the second conductive layer in the region where the second oxide and the first oxide do not overlap with the second conductive layer is used as a reference is greater than -5 nm and less than 0 nm.

[0023] In addition, one embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a first oxide on the second insulating layer, a second oxide on the first oxide, a third oxide on the second oxide, a third insulating layer on the third oxide, a second conductive layer on the third insulating layer, a third conductive layer on the second oxide, and a fourth conductive layer, a fifth conductive layer on the third conductive layer, and a sixth conductive layer on the fourth conductive layer, the first conductive layer and the second conductive layer have a region overlapping with the second oxide, the fifth conductive layer has a region in contact with a side surface of the third conductive layer on the second conductive layer side and a top surface of the second oxide, and the sixth conductive layer has a region in contact with a side surface of the fourth conductive layer on the second conductive layer side and a top surface of the second oxide, in a channel width direction of the transistor, a bottom surface of the second oxide is located below a bottom surface of the second conductive layer in a region where the second oxide and the first oxide do not overlap with the second conductive layer, and a height of the bottom surface of the second oxide based on a height of the bottom surface of the second conductive layer in a region where the second oxide and the first oxide do not overlap with the second conductive layer is greater than -5 nm and less than 0 nm.

[0024] In the semiconductor device, the bottom height of the second conductive layer in the region overlapping with the second oxide is preferably lower than the top height of the third conductive layer, based on the bottom height of the first insulating layer in a cross section along the channel length direction of the transistor.

[0025] In the semiconductor device, preferably, the second insulating layer has side surfaces substantially aligned with side surfaces of the first oxide and the second oxide, and the third oxide has a region in contact with a top surface of the first insulating layer and a side surface of the second insulating layer.

[0026] In the semiconductor device, the top surface of the second insulating layer in a region overlapping with the second oxide is preferably higher than the top surface of the second insulating layer in a region not overlapping with the second oxide, based on the bottom surface height of the first insulating layer.

[0027] Effects of the Invention

[0028] According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high operating frequency can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0029] In addition, according to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a fast data writing speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high degree of design freedom can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of suppressing power consumption can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0030] Note that the description of these effects does not prevent the existence of other effects. Note that one mode of the present invention does not need to achieve all of the above effects. Effects other than the above effects can be clearly seen from the description of the specification, drawings, claims, etc., and effects other than the above effects can be extracted from the description of the specification, drawings, claims, etc.

[0031] BRIEF DESCRIPTION OF THE DRAWINGS

[0032] [ Figure 1 ] are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention.

[0033] [ Figure 2 ] is a cross-sectional view of a transistor according to one embodiment of the present invention.

[0034] [ Figure 3 ] is a diagram showing the electrical characteristics of a transistor according to one embodiment of the present invention.

[0035] [ Figure 4 ] is a diagram showing the operating frequency of a semiconductor device according to one embodiment of the present invention.

[0036] [ Figure 5 ] is a diagram showing a transistor according to one embodiment of the present invention. Vsh / Graph of Vbg|.

[0037] [ Figure 6 ] is a diagram showing the operating frequency of a semiconductor device according to one embodiment of the present invention.

[0038] [ Figure 7 ] are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention.

[0039] [ Figure 8 ] is a cross-sectional view of a transistor according to one embodiment of the present invention.

[0040] [ Fig. 9 ] is a diagram showing the electrical characteristics of a transistor according to one embodiment of the present invention.

[0041] [ Fig.10 ] is a diagram illustrating a structural example of a transistor according to one embodiment of the present invention.

[0042] [ Fig.11 ] is a diagram illustrating a structural example of a transistor according to one embodiment of the present invention.

[0043] [ Fig.12 ] is a diagram illustrating a structural example of a transistor according to one embodiment of the present invention.

[0044] [ Fig.13 ] is a diagram illustrating a structural example of a transistor according to one embodiment of the present invention.

[0045] [ Fig.14 ] is a diagram illustrating a structural example of a transistor according to one embodiment of the present invention.

[0046] [ Fig.15 ] is a block diagram showing a structural example of a storage device according to one embodiment of the present invention.

[0047] [ Fig.16 ] is a circuit diagram showing a structural example of a storage device according to one embodiment of the present invention.

[0048] [ Fig.17 ] is a schematic diagram of a semiconductor device according to one embodiment of the present invention.

[0049] [ Fig.18 ] is a schematic diagram of a storage device according to one embodiment of the present invention.

[0050] [ Fig.19 ] is a diagram showing an electronic device according to one embodiment of the present invention.

[0051] [ Fig. 20 ] is a SEM observation image of sample 1D viewed from above.

[0052] [ Fig.21 ] is a cross-sectional STEM image according to an embodiment of the present invention.

[0053] Modes for Carrying Out the Invention

[0054] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0055] In the drawings, the size, thickness of the layer or the area are sometimes exaggerated for obvious reasons. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings. For example, in the actual manufacturing process, layers or resist masks are sometimes unintentionally etched due to etching and other processes, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in the drawings, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a special reference numeral.

[0056] In addition, in particular, in a top view (also called a plan view) or a perspective view, in order to facilitate understanding of the invention, description of some components may be omitted. In addition, description of some hidden lines may be omitted.

[0057] In addition, in this specification, for the sake of convenience, ordinal numbers such as first and second are added, but they do not indicate the order of processes or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for description. In addition, the ordinal numbers recorded in this specification and the like are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0058] In this specification, for convenience, words and phrases such as "upper" and "lower" are used to indicate the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in the specification are not limited, and the words and phrases can be appropriately changed according to the situation.

[0059] For example, in this specification, when it is clearly stated that "X is connected to Y", it means the following: X is electrically connected to Y; X is functionally connected to Y; X is directly connected to Y. Therefore, the connection relationship is not limited to the connection relationship shown in the drawings or the text, and the connection relationship other than the connection relationship shown in the drawings or the text is also disclosed in the drawings or the text.

[0060] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0061] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the region where the channel is formed, and the source. Note that in this specification, etc., the region where the channel is formed refers to the region where the current mainly flows.

[0062] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, the terms source and drain may be interchanged.

[0063] In this specification, etc., depending on the structure of the transistor, the actual channel width in the region where the channel is formed (hereinafter, also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter, also referred to as the "apparent channel width") are sometimes different. For example, when the gate electrode covers the side of the semiconductor, sometimes because the effective channel width is larger than the apparent channel width, its influence cannot be ignored. For example, in a miniature transistor with a gate electrode covering the side of the semiconductor, sometimes the proportion of the channel formation region formed on the side of the semiconductor increases. In this case, the effective channel width is larger than the apparent channel width.

[0064] In the above case, it is sometimes difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width based on the design value, an assumption is required, that is, the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0065] In this specification, when simply describing "channel width", sometimes it refers to the apparent channel width. Alternatively, in this specification, when simply expressing "channel width", sometimes it refers to the effective channel width. Note that the values ​​of channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing cross-sectional TEM images, etc.

[0066] In addition, the "impurities" of a semiconductor are, for example, substances other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, water sometimes also acts as an impurity. In addition, in the case of an oxide semiconductor, oxygen vacancies are sometimes generated, for example, due to the entry of impurities. In addition, when the semiconductor is silicon, impurities that change the properties of the semiconductor include, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0067] Note that in this specification and the like, silicon oxynitride refers to a substance containing more oxygen than nitrogen. Also, silicon nitride oxide refers to a substance containing more nitrogen than oxygen.

[0068] Note that in this specification, etc., “insulator” may be referred to as “insulating film” or “insulating layer”. Also, “conductor” may be referred to as “conductive film” or “conductive layer”. Also, “semiconductor” may be referred to as “semiconductor film” or “semiconductor layer”.

[0069] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state where the angle is greater than -5 degrees and less than 5 degrees is also included. In addition, "approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30 degrees and less than 30 degrees. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state where the angle is greater than 85 degrees and less than 95 degrees is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60 degrees and less than 120 degrees.

[0070] Note that in this specification, a barrier film refers to a film having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, and when the barrier film has conductivity, it may be referred to as a conductive barrier film.

[0071] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing an oxide or an oxide semiconductor.

[0072] (Implementation Method 1)

[0073] Below, refer to Figures 1 to 9 A transistor according to one embodiment of the present invention will be described.

[0074] <Transistor Structure Example 1>

[0075] Figure 1 A top view and a cross-sectional view of a transistor according to one embodiment of the present invention are shown. Figure 1 A is a top view of the transistor. In addition, Figure 1 B is along Figure 1 The cross-sectional view of the portion along the dashed line L1 - L2 in A is also a cross-sectional view of the transistor in the channel length direction. Figure 1 C is along Figure 1 The cross-sectional view of the portion along the dot-dash line W1-W2 in A is also a cross-sectional view along the channel width direction of the transistor. Figure 1 In the top view of A, some components are omitted for clarity.

[0076] Note that although Figure 1 The ends of the conductive layer, semiconductor layer, or insulating layer in the top view and cross-sectional view are right angles, but the semiconductor device shown in this embodiment is not limited to this and may have a shape with rounded ends.

[0077] like Figure 1 As shown, the transistor includes a conductive layer BGE configured on a substrate (not shown), an insulating layer BGI1, an insulating layer BGI2 and an insulating layer BGI3 configured on the conductive layer BGE, a semiconductor layer SEM1 and a semiconductor layer SEM2 configured on the insulating layer BGI3, a conductive layer SE and a conductive layer DE configured on the semiconductor layer SEM2, a semiconductor layer SEM3 configured on the semiconductor layer SEM2, the conductive layer SE and the conductive layer DE, an insulating layer TGI configured on the semiconductor layer SEM3, and a conductive layer TGE configured on the insulating layer TGI.

[0078] The conductive layer TGE is used as a first gate (also called a top gate), the conductive layer BGE is used as a second gate (also called a back gate), the insulating layer TGI is used as a first gate insulating layer (also called a top gate insulating layer), the insulating layers BGI1, BGI2 and BGI3 are used as second gate insulating layers (also called back gate insulating layers), the semiconductor layers SEM1, SEM2 and SEM3 are used as semiconductor layers, the conductive layer SE is used as one of the source and the drain, and the conductive layer DE is used as the other of the source and the drain.

[0079] The transistor includes a top gate and a back gate. The threshold voltage of the transistor including the top gate and the back gate can be controlled by applying different potentials to the top gate and the back gate. For example, by applying a negative potential to the back gate, the threshold voltage of the transistor can be further increased and the off-state current can be reduced. In other words, by applying a negative potential to the back gate, the drain current when the potential applied to the top gate is 0V can be reduced.

[0080] The channel formation region of the transistor preferably uses a metal oxide used as a semiconductor (hereinafter also referred to as an oxide semiconductor). Since the transistor using the oxide semiconductor in the channel formation region has an extremely small leakage current in the non-conducting state, a low-power semiconductor device can be provided. In addition, the oxide semiconductor can be formed by sputtering, etc., so it can be used to form a transistor of a highly integrated semiconductor device.

[0081] When an oxide semiconductor is used in the channel formation region of a transistor, it is preferred to use an i-type (intrinsic) or substantially i-type oxide semiconductor with a low carrier concentration. By using an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor, the off-state current of the transistor can be suppressed to a low level, or the reliability of the transistor can be improved. The details of the oxide semiconductor are described in Embodiment 2.

[0082] In addition, the larger the on-state current of the transistor, the better. In addition, it is preferred to have a high operating frequency characteristic (also called frequency characteristic). In addition, it is preferred to suppress the variation of electrical characteristics to achieve stable electrical characteristics while improving reliability.

[0083] Therefore, it is preferred to improve the controllability of the top gate. Here, in this specification, "the controllability of the top gate is high" means "the electric field of the top gate has a large influence on the channel formation region". In other words, even if the change in the potential applied to the top gate is small, the current flowing through the channel formation region is easy to change. Specifically, "the controllability of the top gate is high" means: the on-state current of the transistor is large, the subthreshold swing value (Svalue) is small, etc. Here, Svalue refers to: the change in gate voltage in the subthreshold region that changes the value of the drain current by one digit with a fixed drain voltage. By improving the controllability of the top gate, the on-state current and Svalue of the transistor can be increased, thereby increasing the operating frequency of the semiconductor device including the transistor.

[0084] For example, it is preferred that the conductive layer TGE covers the top surface and side surfaces of the channel formation region of the semiconductor layer SEM2 in the channel width direction via the semiconductor layer SEM3 and the insulating layer TGI. The larger the area of ​​the channel formation region of the semiconductor layer SEM2 covered by the conductive layer TGE is, the larger the effective channel width is and the larger the capacitance on the top gate side is. Therefore, the controllability of the top gate is improved. In addition, if Figure 1 As shown in C, the conductive layer TGE is opposite to the side surface of the semiconductor layer SEM2, so it can be called a side gate.

[0085] However, when the capacitance on the top gate side increases, the ratio of the capacitance on the back gate side to the capacitance on the top gate side becomes smaller. When the ratio of the capacitance on the back gate side to the capacitance on the top gate side becomes smaller, the controllability of the back gate described below decreases. Therefore, the larger the area where the conductive layer TGE covers the channel formation region of the semiconductor layer SEM2 in the channel width direction, the lower the controllability of the back gate. Here, for example, "low controllability of the back gate" means that the change in the drift value (Vsh) for the change in the potential applied to the back gate is small. In the drain current-gate voltage characteristic (Id-Vg characteristic) of the transistor, the Vg at which the tangent of the point with the largest slope on the curve intersects the straight line of Id=1[pA] is used to define Vsh.

[0086] <Correlation between top gate controllability and back gate controllability>

[0087] Here, the correlation between the controllability of the top gate and the controllability of the back gate is described. As an example of the controllability of the top gate, Svalue is shown, and as an example of the controllability of the back gate, | Vsh / Vbg|.| Vsh / Vbg| is the change in Vsh when the back gate voltage Vbg changes by 1V (the absolute value of the drift of Vsh), and its unit is [V / V]. In other words, | Vsh / The larger the Vbg|, the higher the controllability of the back gate.

[0088] As shown in formula (1), | Vsh / Vbg| has a capacitance C that depends on the top gate side T The back gate capacitor C B C B / C T In other words, the controllability of the back gate depends on the capacitance C on the top gate side. T The capacitance C on the back gate side B The tendency of the ratio.

[0089] [Formula 1]

[0090]

[0091] In addition, as shown in formula (2), Svalue has a B / C T In other words, the controllability of the top gate depends on the capacitance C on the top gate side. T The capacitance C on the back gate side B The tendency of the ratio.

[0092] [Formula 2]

[0093]

[0094] In equation (2), k represents the Boltzmann constant, T represents the absolute temperature, q represents the elementary charge, λ represents the natural length, and L represents the channel length. In addition, λ is a parameter related to the short channel effect.

[0095] As mentioned above, C B / C T The bigger | Vsh / The larger the Vbg|, the better the controllability of the back gate, but the larger the Svalue, the lower the reliability. B / C T The smaller the Svalue, the smaller the reliability, but | Vsh / The smaller Vbg| is, the lower the controllability of the back gate is. In other words, the controllability of the top gate is related to the controllability of the back gate.

[0096] Therefore, the bottom height of the semiconductor layer SEM2 is preferably substantially the same as the bottom height of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE. By adopting this structure, the controllability of the top gate can be improved while maintaining the controllability of the back gate.

[0097] <Evaluation of Transistor Electrical Characteristics by Calculation Using a Device Simulator 1>

[0098] Next, the relationship between the size of the area where the side gate covers the channel formation area and the electrical characteristics of the transistor is evaluated by calculation using a device simulator. Specifically, the Svalue and on-state current of the transistor are calculated. In addition, the transistor assumed in the calculation using the device simulator is Figure 1 The transistor shown.

[0099] In this calculation, structures (Structure 1A to Structure 8A) in which the range of the conductive layer TGE covering the semiconductor layer SEM2 is different from each other are prepared. Table 1 shows the values ​​of parameters that are different between Structure 1A to Structure 8A among the values ​​of the parameters assumed in the calculation using the device simulator.

[0100] [Table 1]

[0101]

[0102] H shown in Table 1 represents the height of the bottom surface of the semiconductor layer SEM2 when the height of the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE is used as a reference. When the bottom surface of the semiconductor layer SEM2 is located above the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE (on the opposite side of the conductive layer BGE), H is a positive value. In addition, when the bottom surface of the semiconductor layer SEM2 is located below the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE (on the conductive layer BGE side), H is a negative value.

[0103] Figure 2 A is a cross-sectional view in the channel width direction of the structure (Structure 6A to Structure 8A) in which H is a positive value. The bottom surface ( Figure 2 The position indicated by the dot-dash line in A) is located at the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE ( Figure 2 A) (on the opposite side to the conductive layer BGE).

[0104] in addition, Figure 2 B is a cross-sectional view in the channel width direction of the structure (Structure 1A to Structure 4A) in which H is a negative value. Figure 2 The position indicated by the dot-dash line in B) is located at the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE ( Figure 2B) (on the conductive layer BGE side).

[0105] The electrical characteristics of the structures 1A to 8A were calculated by using a device simulator. As the device simulator, Atlas3D manufactured by Silvaco was used. Table 2 shows the values ​​of parameters common to the structures 1A to 8A among the values ​​of the parameters assumed in the calculation using the device simulator.

[0106] [Table 2]

[0107]

[0108] IGZO (134) shown in Table 2 assumes an In-Ga-Zn oxide with a composition of In:Ga:Zn=1:3:4. In addition, IGZO (423) shown in Table 2 assumes an In-Ga-Zn oxide with a composition of In:Ga:Zn=4:2:3. In addition, the parameters recorded in the SEM shown in Table 2 are common among the semiconductor layer SEM1, the semiconductor layer SEM2, and the semiconductor layer SEM3.

[0109] Svalue and on-state current Ion are calculated by calculating the Id-Vg characteristics of structures 1A to 8A when drain voltage Vd=1.2V and back gate Vbg=-6.0V. Here, Ion is set to the current value when gate voltage Vg=Vsh+2.5V.

[0110] Figure 3 A shows the calculated Svalue of each of structures 1A to 8A. Figure 3 In A, the horizontal axis represents the angle H [nm], and the vertical axis represents S value [mV / decade]. Figure 3 A It can be seen that within the negative range of H, the smaller the H value (the closer to zero), the smaller the Svalue. In addition, it can be seen that within the positive range of H, Svalue hardly changes.

[0111] Figure 3 B shows the calculated Ion for each of structures 1A to 8A. Figure 3 In B, the horizontal axis represents H [nm], and the vertical axis represents Ion (Vg = Vsh + 2.5V) [A]. Figure 3 B It can be seen that in the negative range of H value, the smaller the H value (the closer to zero), the larger the Ion. In addition, the change amount of Ion with respect to H in the positive range of H value is smaller than that in the negative range of H value.

[0112] [Estimation of the operating frequency of a semiconductor device by calculation using a device simulator]

[0113] Here, the operating frequency of a semiconductor device including a transistor is evaluated by performing calculations using a device simulator. Specifically, Figure 4 The result of estimating the operating frequency of the semiconductor device according to one embodiment of the present invention will be described.

[0114] Here, the semiconductor device refers to a DRAM using a 1OS transistor 1 capacitor type memory cell. A DRAM using a 1OS transistor 1 capacitor type memory cell is also called a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). The details of DOSRAM will be described in the following embodiments.

[0115] The data retention time of DOSRAM can be said to be the time required for the charge stored in the storage capacitor included in the DOSRAM to decrease from the "size after data is written" to the "prescribed size". In this embodiment, the above-mentioned "prescribed size" is defined as the time required for the potential supplied to the capacitor included in the DOSRAM (the storage capacitor is 3.5fF) to decrease by 0.2V from the state after data is written. For example, in this embodiment, "the data retention time of DOSRAM is 1 hour" means that the time required for the potential supplied to the capacitor included in the DOSRAM to decrease by 0.2V from the state after data is written is 1 hour.

[0116] The data retention time of the DOSRAM depends on the size of the off-state leakage current of the transistor included in the DOSRAM. Here, the off-state leakage current of the transistor can be replaced by (Id) (i.e., Icut) when Vg=0V of the transistor. For example, when the data retention characteristic of the DOSRAM depends only on the size of the Icut of the transistor included in the DOSRAM, the data retention time of the DOSRAM is inversely proportional to the size of the Icut of the transistor included in the DOSRAM.

[0117] Icut is estimated by extrapolating from (Vsh) and (Svalue) using the following equation (3). Note that equation (3) is established assuming that the off-state current of the transistor decreases monotonically until Vg=0V according to Svalue obtained by Vg-Id measurement.

[0118] [Formula 3]

[0119]

[0120] According to the above formula, the data retention time of DOSRAM can be estimated by calculating Vsh and Svalue obtained from the Id-Vg characteristics.

[0121] In addition, the operating frequency of the DOSRAM is defined as the reciprocal of the data write cycle time of the DOSRAM. The data write cycle time of the DOSRAM is a parameter set according to the charging time of the capacitor included in the DOSRAM, etc. In this embodiment, the time equivalent to 40% of the data write cycle time of the DOSRAM (the reciprocal of the operating frequency of the DOSRAM) is set as the charging time of the capacitor included in the DOSRAM.

[0122] As mentioned above, the operating frequency of the DOSRAM depends on the charging time of the capacitor included in the DOSRAM. Therefore, when estimating the operating frequency of the DOSRAM, the charging time of the capacitor included in the DOSRAM must be known in advance. In this embodiment, the state in which the capacitor included in the DOSRAM (the storage capacitor is 3.5fF) is supplied with a potential of 0.55V or more is defined as the capacitor being in a "charged state". Therefore, in this embodiment, the time from the start of the data writing operation of the DOSRAM until the potential supplied to the capacitor reaches 0.55V is equivalent to the charging time of the capacitor included in the DOSRAM.

[0123] In addition, when the charge charged to the capacitor whose storage capacitance is Cs[F] included in the DOSRAM is set to Q[C], the charging time is set to t[sec], the potential supplied to the capacitor by charging is set to Vcs(=Vs)[V], and the drain current of the transistor included in the DOSRAM is set to Id[A], the parameters satisfy the relationship of the following formula (4).

[0124] [Formula 4]

[0125]

[0126] Therefore, by transforming equation (4), the charging time t of the capacitor included in the DOSRAM can be expressed by the following equation (5).

[0127] [Formula 5]

[0128]

[0129] As described above, in this embodiment, the state in which the potential supplied to the capacitor having a storage capacitance of 3.5 fF is 0.55 V or more is defined as the capacitor being in a "charged state". Thus, by substituting 3.5 fF into Cs of formula (5), substituting +0.55 V into Vcs, and substituting the measured value or calculated value of the transistor according to one embodiment of the present invention into Id, the charging time t of the capacitor included in the DOSRAM can be calculated.

[0130] The charging time of the capacitor included in the DOSRAM depends on the size of the Id of the transistor included in the DOSRAM when the DOSRAM data is written. In other words, the operating frequency of the DOSRAM can be estimated by obtaining the Id-Vs characteristic.

[0131] Therefore, here, the potential assumed to be applied to the transistor included in the DOSRAM when writing the DOSRAM data is actually applied to the transistor according to one embodiment of the present invention to reproduce the writing operation of the DOSRAM data, and measure the Id of the transistor at this time. Specifically, the Id of the transistor is measured by fixing the gate potential Vg of the structure 1A to the structure 8A to +2.97V, fixing the drain potential Vd to +1.08V, setting the back gate potential Vbg to an arbitrary potential, and sweeping the source potential Vs from 0V to +0.55V. The measurement temperature is set to 27°C.

[0132] In addition, the data retention time and operating frequency of the DOSRAM are calculated by calculating the Id-Vg characteristics and Id-Vs characteristics of the structures 1A to 8A using the device simulator using the above conditions. The values ​​of the parameters assumed in the calculation using the device simulator are the values ​​shown in Tables 1 and 2. In the calculation of the data retention time, the degradation of the element characteristics due to leakage and long-term retention is not considered.

[0133] Figure 4 Estimation of the DOSRAM operating frequency at a power supply voltage of 3.3 V and a temperature of 27° C. for a DOSRAM having any one of Structure 1A to Structure 8A is shown. Figure 4 The DOSRAM operating frequency shown is normalized in such a way that the DOSRAM operating frequency of the structure 5A becomes 1. Figure 4 In the figure, the horizontal axis represents the angle H [nm], and the vertical axis represents the normalized DOSRAM operating frequency. Figure 4 It can be seen that the larger the value of H is, the higher the operating frequency of the DOSRAM is. In other words, it can be seen that the larger the value of H is, the higher the operating frequency of the semiconductor device including the transistor is.

[0134] 〔Back gate control〕

[0135] Next, the controllability of the back gate is evaluated by calculation using a device simulator. In order to evaluate the controllability of the back gate, the back gate voltage dependency of the Id-Vg characteristic of the transistor is calculated to calculate | Vsh / Vbg|.

[0136] By calculating the Id-Vg characteristics in structures 1A to 8A using a device simulator, | Vsh / Vbg|. The values ​​of the parameters assumed by calculation using a device simulator are the values ​​shown in Tables 1 and 2.

[0137] Figure 5 The calculated | Vsh / Vbg|. Figure 5 In the figure, the horizontal axis represents H [nm] and the vertical axis represents | Vsh / Vbg|[V / V]. Figure 5 It can be seen that the larger the value of H is, the larger the value of | Vsh / Therefore, it can be seen that the larger the value of H, the lower the controllability of the back gate.

[0138] In this way, by adopting a structure in which the conductive layer TGE used as a top gate covers the side and top surfaces of the semiconductor layer SEM2 in the channel formation region via the semiconductor layer SEM3 and the insulating layer TGI, it is easy to make the electric field of the conductive layer TGE act on the entire semiconductor layer SEM2 in the channel formation region. Therefore, the on-state current of the transistor can be increased and the operating frequency of the semiconductor device including the transistor can be improved.

[0139] Therefore, the height of the bottom surface of the semiconductor layer SEM2 is substantially the same as the height of the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE, and the transistor has a small Svalue, a large on-state current, good electrical characteristics, and can maintain the controllability of the back gate. For example, H is preferably greater than -15nm and less than 15nm, more preferably greater than -10nm and less than 10nm, and further preferably greater than -5nm and less than 5nm or greater than -5nm and less than 0nm.

[0140] In addition, the lower the back gate voltage Vbg, the better. When the back gate voltage Vbg is high, the Id-Vg characteristics of the transistor may be reduced. Examples of the reduction in the Id-Vg characteristics of the transistor include an increase in Svalue and a decrease in on-state current.

[0141] In order to reduce the back gate voltage Vbg, for example, it is necessary to improve the controllability of the back gate. When the controllability of the back gate is low, it is necessary to further increase the back gate voltage Vbg in order to maintain data. In order to improve the controllability of the back gate, for example, it is preferable to increase | Vsh / Vbg|.

[0142] The controllability of the back gate depends on the film thickness of the back gate insulating layer (insulating layer BGI1, insulating layer BGI2, and insulating layer BGI3), the film thickness of the semiconductor layer (semiconductor layer SEM1, semiconductor layer SEM2, and semiconductor layer SEM3), etc. Therefore, in order to increase the operating frequency of the transistor while maintaining data, it is important to optimize the film thickness of the back gate insulating layer and the semiconductor layer. By optimizing the film thickness, a structure of a transistor that maintains data and has a high operating frequency can be realized.

[0143] <Optimization of Film Thickness of Back Gate Insulation Layer and Semiconductor Layer>

[0144] Below, use Figure 6 The following describes optimization of the film thickness of a back gate insulating layer and a semiconductor layer in order to realize a transistor that can retain data and has a high operating frequency.

[0145] First, the controllability of the back gate is determined by the back gate voltage Vbg required in actual operation. For example, assuming a transistor with electrical characteristics showing that Vsh is 0V when Vbg=0V, in order to drift Vsh at 27°C to 1.2V with a potential of -5V or less applied to the back gate, | Vsh / Vbg| is preferably 0.24 V / V or more. Alternatively, in order to drift Vsh at 27°C to 0.83 V in a state where a potential of -3 V or less is applied to the back gate, | Vsh / Vbg| is preferably 0.28 V / V or more.

[0146] Next, the most suitable film thicknesses of the back gate insulating layer and the semiconductor layer that satisfy the determined controllability of the back gate are determined. Vsh / When the optimal film thickness of the back gate insulating layer and the semiconductor layer is 0.24V / V or more, a plurality of transistors with different film thicknesses of the back gate insulating layer or the semiconductor layer are first prepared. Then, the Id-Vg characteristics of the transistors are calculated to calculate | Vsh / Vbg|. The calculated | Vsh / The film thickness of the back gate insulating layer and the semiconductor layer is set to the most appropriate film thickness when Vbg| is 0.24 V / V or more. Note that the film thickness of the back gate insulating layer or the semiconductor layer is set separately, so the most appropriate film thickness is sometimes not determined by a single factor but exists in multiple factors.

[0147] Next, the DOSRAM operating frequency is calculated in the transistors formed with the above-mentioned optimal film thickness. By extracting the transistor structure with the highest operating frequency from the calculated DOSRAM operating frequencies, the structure of the transistor that holds data and has a high operating frequency is determined.

[0148] The following is an example of calculating the optimum film thickness of the back gate insulating layer and the semiconductor layer by using a device simulator. Figure 1 In the transistor shown, structures (Structure 1B to Structure 4B) in which the film thicknesses of the insulating layers BGI1, BGI2, BGI3, the semiconductor layers SEM1, and SEM2 are different from each other are prepared. Table 3 shows the values ​​of the parameters that are different between Structure 1B to Structure 4B among the values ​​of the parameters assumed by the calculation of the device simulator.

[0149] [Table 3]

[0150]

[0151] H shown in Table 3 represents the height of the bottom surface of the semiconductor layer SEM2 when the height of the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE is used as a reference. H in structures 1B to 4B is a positive value. Figure 4 It can be considered that DOSRAM operates at a high frequency.

[0152] Calculation using a device simulator was performed on structures 1B to 4B. As the device simulator, Atlas3D manufactured by Silvaco was used. Table 4 shows the values ​​of parameters common to structures 1B to 4B among the values ​​of the parameters assumed in the calculation using the device simulator.

[0153] [Table 4]

[0154]

[0155] According to the calculation results using the device simulator, it can be seen that the structure 1B | Vsh / Vbg| is 0.1V / V, and | Vsh / Vbg| is 0.24 V / V or more. Therefore, it is understood that the back gate controllability of Structures 2B to 4B is higher than that of Structure 1B.

[0156] Next, the data retention time and operating frequency of the DOSRAM are calculated by calculating the Id-Vg characteristics and Id-Vs characteristics of structures 1B to 4B using a device simulator. The values ​​of the parameters assumed in the calculation using the device simulator are the values ​​shown in Tables 3 and 4. In the calculation of the data retention time, the degradation of the element characteristics due to leakage and long-term retention is not considered.

[0157] Figure 6 Estimation of the DOSRAM operating frequency at a power supply voltage of 3.3 V and a temperature of 27° C. for a DOSRAM having any one of Structures 1B to 4B is shown. Figure 6 The DOSRAM operating frequency shown is normalized in such a way that the DOSRAM operating frequency of the structure 1B becomes 1. Figure 6 In the figure, the vertical axis represents the normalized DOSRAM operating frequency. Figure 6 It can be seen that among structures 2B to 4B, the DOSRAM operating frequency of structure 4B is the highest.

[0158] Note that in the above calculation, the most suitable film thickness is obtained after the controllability of the back gate is determined, but the invention is not limited thereto. For example, the structure of a transistor that retains data and has a high operating frequency can be determined by obtaining the most suitable film thickness that satisfies the required DOSRAM operating frequency and extracting the transistor structure with the highest controllability of the back gate in the most suitable film thickness.

[0159] In addition, not limited to Figure 1 The structure of the transistor shown, as long as the transistor has a structure in which the height of the bottom surface of the semiconductor layer SEM2 is approximately the same as the height of the bottom surface of the conductive layer TGE in the area where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE, the Svalue of the transistor is small, the on-state current is large, the electrical characteristics are good, and the controllability of the back gate can be maintained.

[0160] <Transistor Structure Example 2>

[0161] Figure 7 A top view and a cross-sectional view of a transistor according to one embodiment of the present invention are shown. Figure 7 A is a top view of the transistor. In addition, Figure 7 B is along Figure 7 The cross-sectional view of the portion along the dashed line L1 - L2 in A is also a cross-sectional view of the transistor in the channel length direction. Figure 7 C is along Figure 7 The cross-sectional view of the portion along the dot-dash line W1-W2 in A is also a cross-sectional view along the channel width direction of the transistor. Figure 7 In the top view of A, some components are omitted for clarity.

[0162] Figure 7 The transistor shown is Figure 1 Therefore, in order to avoid duplication of explanation, the following mainly describes the transistors of Figure 1 The differences between the transistors shown are explained.

[0163] like Figure 7 As shown, the transistor includes a conductive layer BGE configured on a substrate (not shown), an insulating layer BGI2 and an insulating layer BGI3 configured on the conductive layer BGE, a semiconductor layer SEM1 and a semiconductor layer SEM2 configured on the insulating layer BGI3, a conductive layer SE and a conductive layer DE configured on the semiconductor layer SEM2, a semiconductor layer SEM3 configured on the semiconductor layer SEM2 and in contact with the side surfaces of the conductive layer SE and the conductive layer DE, an insulating layer TGI configured on the semiconductor layer SEM3, and a conductive layer TGE configured on the insulating layer TGI.

[0164] <Evaluation of Transistor Electrical Characteristics by Calculation Using a Device Simulator 2>

[0165] Below, calculate Figure 7 The Svalue and on-state current of the transistor are shown.

[0166] In this calculation, structures (Structure 1C to Structure 10C) in which the range of the conductive layer TGE covering the semiconductor layer SEM2 is different from each other are prepared. Table 5 shows the values ​​of parameters that are different between Structure 1C and Structure 10C among the values ​​of the parameters assumed in the calculation using the device simulator.

[0167] [Table 5]

[0168]

[0169] Figure 8 A is a cross-sectional view of the channel width direction of the structure (Structure 7C to Structure 10C) where H is a positive value. Figure 8 B is a cross-sectional view in the channel width direction of the structure (Structure 1C to Structure 5C) in which H is a negative value.

[0170] The calculation using the device simulator was performed on the structures 1C to 10C. As the device simulator, Atlas3D manufactured by Silvaco was used. Table 6 shows the values ​​of parameters common to the structures 1C to 10C among the values ​​of the parameters assumed in the calculation using the device simulator.

[0171] [Table 6]

[0172]

[0173] Svalue and on-state current Ion are calculated by calculating the Id-Vg characteristics of structures 1C to 10C when drain voltage Vd=1.2V and back gate Vbg=-6.0V. Here, Ion is set to the current value when gate voltage Vg=Vsh+2.5V.

[0174] Fig. 9 A shows the calculated Svalue of each of the structures 1C to 10C. Fig. 9 In A, the horizontal axis represents the angle H [nm], and the vertical axis represents S value [mV / decade]. Fig. 9 A It can be seen that within the negative range of H, the smaller the H value (the closer to zero), the smaller the Svalue. In addition, it can be seen that within the positive range of H, Svalue hardly changes.

[0175] Fig. 9 B shows the calculated Ion of each of structures 1C to 10C. Fig. 9 In B, the horizontal axis represents H [nm], and the vertical axis represents Ion (Vg = Vsh + 2.5V) [A]. Fig. 9 B It can be seen that within the negative range of H value, the smaller the H value (the closer to zero), the larger Ion becomes. On the other hand, within the positive range of H value, Ion hardly changes.

[0176] Therefore, as long as the height of the bottom surface of the semiconductor layer SEM2 is approximately the same as the height of the bottom surface of the conductive layer TGE in the area where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE, the transistor has a small Svalue, a large on-state current, good electrical characteristics, and can maintain the controllability of the back gate.

[0177] Note that details of the transistor according to one embodiment of the present invention will be described in the following embodiment.

[0178] In order to manufacture a transistor in which the height of the bottom surface of the semiconductor layer SEM2 is substantially the same as the height of the bottom surface of the conductive layer TGE in the region where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE, it is necessary to consider the film thicknesses of the semiconductor layer SEM1, the semiconductor layer SEM2, the semiconductor layer SEM3, the insulating layer TGI, and the insulating layer BGI3. Note that the film thicknesses of the semiconductor layer SEM1, the semiconductor layer SEM2, the semiconductor layer SEM3, and the insulating layer TGI are substantially the same as the film thicknesses during film formation.

[0179] Sometimes, in the process of processing the semiconductor layer SEM2 and the semiconductor layer SEM1 by etching, the insulating layer BGI3 is etched and the film thickness is reduced (so-called film reduction occurs). In addition, sometimes, a polymer that becomes an etching protection film is deposited on the insulating layer BGI3 in this process. When the insulating layer BGI3 is processed by etching after this process, the polymer deposited on the insulating layer BGI3 hinders the etching reaction of the insulating layer BGI3. Therefore, it is difficult to control the film thickness of the insulating layer BGI3 by processing using the etching method.

[0180] Therefore, it is preferred to perform oxygen plasma treatment after processing the semiconductor layer SEM2 and the semiconductor layer SEM1 by etching or before processing the insulating layer BGI3 by etching. By performing the oxygen plasma treatment, the polymer deposited on the insulating layer BGI3 can be removed. By removing the polymer by the oxygen plasma treatment and then processing the insulating layer BGI3 by etching, the film thickness of the insulating layer BGI3 can be controlled. Therefore, miniaturization or high integration of transistors can sometimes be achieved. In addition, the productivity of transistors can sometimes be improved.

[0181] By performing the above-mentioned process, for example, the insulating layer BGI3 in the region not overlapping with the semiconductor layer SEM2 and the semiconductor layer SEM1 can be removed, and the semiconductor layer SEM3 can have a region in contact with the top surface of the insulating layer BGI2. Alternatively, a portion of the insulating layer BGI3 in the region not overlapping with the semiconductor layer SEM2 and the semiconductor layer SEM1 can be removed so that the height of the top surface of the insulating layer BGI3 in the region overlapping with the semiconductor layer SEM2 and the semiconductor layer SEM1 is higher than the height of the top surface of the insulating layer BGI3 in the region not overlapping with the semiconductor layer SEM2 and the semiconductor layer SEM1.

[0182] Note that oxygen plasma treatment refers to a treatment in which the irradiated object is exposed to a plasma generated in an atmosphere containing an oxygen gas. The oxygen gas refers to an oxidizing gas containing oxygen, such as oxygen, ozone, and nitrous oxide. In particular, oxygen or ozone is preferably used as the oxygen gas. Note that a rare gas may also be added during the oxygen plasma treatment. By performing oxygen plasma treatment with the addition of a rare gas, impurities such as hydrogen or carbon on the surface and near the surface of the irradiated object can be reduced.

[0183] As described above, by controlling the film thicknesses of semiconductor layer SEM1, semiconductor layer SEM2, semiconductor layer SEM3, insulating layer TGI and insulating layer BGI3, a transistor can be manufactured in which the height of the bottom surface of the semiconductor layer SEM2 is approximately the same as the height of the bottom surface of the conductive layer TGE in the area where the semiconductor layer SEM2 and the semiconductor layer SEM1 do not overlap with the conductive layer TGE.

[0184] According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high operating frequency can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0185] As described above, the structure, method, and the like described in this embodiment mode can be implemented in combination with the structure, method, and the like described in other embodiments and examples as appropriate.

[0186] (Implementation Method 2)

[0187] In this embodiment, a structural example of the transistor described in the above embodiment will be described.

[0188] <Transistor Structure Example 1>

[0189] Reference Fig.10 A to Fig.10 C describes a structural example of the transistor 200A. Fig.10 A is a top view of transistor 200A. Fig.10 B is along Fig.10 A is a cross-sectional view of a portion indicated by a dashed line L1 - L2. Fig.10 C is along Fig.10 A is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.10 In the plan view of A, some components are omitted for clarity.

[0190] Fig.10 A to Fig.10 C shows insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 280, insulating layer 282, and insulating layer 284, which are used as interlayer films of transistor 200A. In addition, conductive layer 246 (conductive layer 246a and conductive layer 246b) which are electrically connected to transistor 200A and used as contact plugs, and conductive layer 203 used as wiring are also shown.

[0191] Transistor 200A includes a conductive layer 260 (conductive layer 260a and conductive layer 260b) used as a first gate (also called a top gate), a conductive layer 205 (conductive layer 205a and conductive layer 205b) used as a second gate (also called a bottom gate), an insulating layer 250 used as a first gate insulating layer, insulating layers 220, 222 and 224 used as second gate insulating layers, an oxide 230 (oxide 230a, oxide 230b and oxide 230c) having a region for forming a channel, a conductive layer 242a used as one of a source and a drain, a conductive layer 242b used as the other of a source and a drain, and an insulating layer 274.

[0192] As the interlayer film, a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide can be added to these insulators. Alternatively, the above-mentioned insulators can also be nitrided. Silicon oxide, silicon oxynitride or silicon nitride can also be stacked on the above-mentioned insulators.

[0193] For example, the insulating layer 210 is preferably used as a barrier film for inhibiting impurities such as water or hydrogen from entering the transistor 200A from the substrate side. Therefore, as the insulating layer 210, it is preferred to use an insulating material having a function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferred to use an insulating material having a function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In addition, for example, it is preferred to use aluminum oxide or silicon nitride as the insulating layer 210. By adopting this structure, it is possible to inhibit impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200A side across the insulating layer 210.

[0194] For example, the dielectric constant of the insulating layer 212 is preferably lower than that of the insulating layer 210. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0195] The conductive layer 203 is formed in a manner embedded in the insulating layer 212. Here, the height of the top surface of the conductive layer 203 and the height of the top surface of the insulating layer 212 may be substantially the same. Note that although the conductive layer 203 is shown as a single-layer structure, the present invention is not limited thereto. For example, the conductive layer 203 may also have a multilayer film structure of two or more layers. As the conductive layer 203, a highly conductive conductive material having tungsten, copper, or aluminum as a main component is preferably used.

[0196] In transistor 200A, conductive layer 260 is sometimes used as a first gate. In addition, conductive layer 205 is sometimes used as a second gate. In this case, by independently changing the potential applied to conductive layer 205 without interlocking it with the potential applied to conductive layer 260, the threshold voltage of transistor 200A can be controlled. In particular, by applying a negative potential to conductive layer 205, the threshold voltage of transistor 200A can be increased and the off-state current can be reduced. Therefore, compared with when a negative potential is not applied to conductive layer 205, when a negative potential is applied to conductive layer 205, the drain current when the potential applied to conductive layer 260 is 0V can be reduced.

[0197] In addition, for example, by overlapping the conductive layer 205 with the conductive layer 260 , when a potential is supplied to the conductive layer 260 and the conductive layer 205 , the electric field generated from the conductive layer 260 and the electric field generated from the conductive layer 205 are connected, so that the channel formation region formed in the oxide 230 can be covered.

[0198] That is, the channel formation region can be electrically surrounded by the electric field of the conductive layer 260 used as the first gate and the electric field of the conductive layer 205 used as the second gate. In this specification, the transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0199] The insulating layer 214 and the insulating layer 216 are used as interlayer films, similarly to the insulating layer 210 or the insulating layer 212. For example, the insulating layer 214 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from entering the transistor 200A from the substrate side. By adopting this structure, it is possible to suppress impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200A side across the insulating layer 214. For example, the dielectric constant of the insulating layer 216 is preferably lower than that of the insulating layer 214. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0200] In the conductive layer 205 used as the second gate, a conductive layer 205a is formed in contact with the inner wall of the opening of the insulating layer 214 and the insulating layer 216, and a conductive layer 205b is formed inside. Here, the height of the top surface of the conductive layer 205a and the conductive layer 205b may be substantially the same as the height of the top surface of the insulating layer 216. Note that the conductive layer 205a and the conductive layer 205b are stacked in the transistor 200A, but the present invention is not limited to this. For example, the conductive layer 205 may also have a single-layer structure or a stacked structure of three or more layers.

[0201] Here, as the conductive layer 205a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In this specification, "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities or oxygen.

[0202] For example, by providing the conductive layer 205a with a function of suppressing diffusion of oxygen, a decrease in conductivity due to oxidation of the conductive layer 205b can be suppressed.

[0203] In addition, when the conductive layer 205 also has a wiring function, it is preferable to use a highly conductive conductive material with tungsten, copper or aluminum as a main component as the conductive layer 205b. In this case, it is not necessary to provide the conductive layer 203. In the drawings, the conductive layer 205b has a single-layer structure, but it may also have a laminated structure, for example, a laminated layer of titanium, titanium nitride and the above conductive materials may be used.

[0204] In addition, in the insulating layer 224 in contact with the oxide 230, oxygen is preferably removed by heating. In this specification, oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulating layer 224. By providing an insulating layer containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced, thereby improving the reliability of the transistor 200A.

[0205] Specifically, an oxide material from which a part of oxygen is released by heating is preferably used as the insulating layer 224. The oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in thermal desorption spectroscopy (TDS) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 The surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0206] Fig.10The structure in which the insulating layer 224 is arranged in the region overlapping with the oxide 230a and the oxide 230b is shown, but the present invention is not limited thereto and the insulating layer 224 may be arranged in the region not overlapping with the oxide 230a and the oxide 230b. In other words, in the region not overlapping with the oxide 230a and the oxide 230b, the insulating layer 224 may be arranged between the insulating layer 222 and the oxide 230c and between the insulating layer 222 and the insulating layer 274.

[0207] The insulating layer 222 preferably has a barrier property. When the insulating layer 222 has a barrier property, the insulating layer 222 serves as a layer for suppressing impurities such as hydrogen from entering the transistor 200A from the surrounding portion of the transistor 200A.

[0208] As the insulating layer 222, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin filming of the gate insulating layer. By using a high-k material as an insulator used as a gate insulator, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0209] For example, the insulating layer 220 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulating layer of a high-k material with silicon oxide or silicon oxynitride, an insulating layer 220 having a stacked structure with thermal stability and a high relative dielectric constant can be formed.

[0210] Note that Fig.10 In the embodiment, the second gate insulating layer has a three-layer stacked structure, but may also have a single-layer structure, a two-layer structure, or a four-layer stacked structure. In this case, the stacked structure is not limited to being made of the same material, but may also be a stacked structure formed of different materials.

[0211] The oxide 230 including the region used as the channel formation region includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. When the oxide 230a is provided below the oxide 230b, it is possible to prevent impurities from being diffused from the structure formed below the oxide 230a to the oxide 230b. When the oxide 230c is provided above the oxide 230b, it is possible to prevent impurities from being diffused from the structure formed above the oxide 230c to the oxide 230b. As the oxide 230, an oxide semiconductor of one of the metal oxides shown below can be used.

[0212] in addition, Fig.10The transistor 200A shown has a region where the conductive layer 242 (the conductive layer 242a and the conductive layer 242b) overlaps with the oxide 230c, the insulating layer 250, and the conductive layer 260. With this structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0213] The conductive layer 242 may be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing these metals as a main component. In particular, a metal nitride film such as tantalum nitride is preferred because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

[0214] In addition, although Fig.10 2 shows that the conductive layer 242 has a single-layer structure, but a stacked structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be stacked. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0215] Alternatively, a titanium film or titanium nitride film, an aluminum film or copper film stacked on the titanium film or titanium nitride film, and a three-layer structure of a titanium film or titanium nitride film formed thereon; a molybdenum film or molybdenum nitride film, an aluminum film or copper film stacked on the molybdenum film or molybdenum nitride film, and a three-layer structure of a molybdenum film or molybdenum nitride film formed thereon, etc. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0216] Alternatively, a barrier layer may be provided on the conductive layer 242. The barrier layer is preferably made of a substance that has a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductive layer 242 can be suppressed when the insulating layer 274 is formed.

[0217] The barrier layer may be made of, for example, a metal oxide. In particular, an insulating film having barrier properties to oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide, is preferably used. Alternatively, silicon nitride formed by CVD may be used.

[0218] By including the barrier layer, the range of choices for the material of the conductive layer 242 can be expanded. For example, a material with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used as the conductive layer 242. In addition, for example, a conductor that is easy to form or process can be used.

[0219] When miniaturization and high integration of transistors are performed, leakage current and other problems may occur due to the thin film of the gate insulating layer. In this case, the insulating layer 250 may also have a laminated structure, similar to the second gate insulating layer. By making the insulator used as the gate insulating layer have a laminated structure of a high-k material and a material with thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a laminated structure with thermal stability and a high relative dielectric constant can be achieved.

[0220] The conductive layer 260 used as the first gate includes a conductive layer 260a and a conductive layer 260b on the conductive layer 260a. As with the conductive layer 205a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used as the conductive layer 260a. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0221] When the conductive layer 260a has a function of suppressing the diffusion of oxygen, the selectivity of the material of the conductive layer 260b can be improved. That is, by including the conductive layer 260a, oxidation of the conductive layer 260b can be suppressed, and a decrease in conductivity can be prevented.

[0222] As a conductive material having a function of inhibiting the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. In addition, as the conductive layer 260a, an oxide semiconductor layer that can be used for the oxide 230 can be used. In this case, by forming the conductive layer 260b by sputtering, the resistivity of the conductive layer 260a can be reduced to make it a conductive layer. The conductive layer 260a formed by the above process can be called an OC (Oxide Conductor) electrode.

[0223] In addition, since the conductive layer 260 is used as wiring, it is preferable to use a conductive layer with high conductivity. For example, as the conductive layer 260b, a conductive material mainly composed of tungsten, copper or aluminum can be used. In addition, the conductive layer 260b can have a stacked structure, for example, it can have a stacked layer of titanium, titanium nitride and the above conductive materials.

[0224] In addition, it is preferable to provide an insulating layer 274 so as to cover the top surface and side surfaces of the conductive layer 260, the side surfaces of the insulating layer 250, and the side surfaces of the oxide 230c. As the insulating layer 274, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide, hafnium oxide, etc. are preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. can also be used.

[0225] The insulating layer 274 can be provided to suppress oxidation of the conductive layer 260. In addition, by including the insulating layer 274, diffusion of impurities such as water and hydrogen included in the insulating layer 280 into the transistor 200A can be suppressed.

[0226] Similar to the insulating layer 214 , the insulating layer 282 is preferably used as a block insulating film for suppressing impurities such as water and hydrogen from entering the transistor 200A from the outside.

[0227] As with the insulating layer 216, the insulating layer 280 and the insulating layer 284 preferably have a lower dielectric constant than the insulating layer 282. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0228] In addition, the transistor 200A may be electrically connected to other structures through plugs or wiring such as the conductive layer 246 embedded in the insulating layer 274 , the insulating layer 280 , the insulating layer 282 , and the insulating layer 284 .

[0229] In addition, as with the conductive layer 205, as the material of the conductive layer 246, a single layer or a stack of conductive materials such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. For example, a high melting point material such as tungsten or molybdenum having heat resistance and conductivity is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0230] For example, by using a stacked-layer structure of tantalum nitride or the like, a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity as the conductive layer 246, diffusion of impurities from the outside can be suppressed while maintaining conductivity as a wiring.

[0231] Alternatively, an insulating layer 276 (insulating layer 276a and insulating layer 276b) having a barrier property may be provided between the conductive layer 246 and the insulating layer 280. Providing the insulating layer 276 can prevent oxidation of the conductive layer 246 due to reaction of oxygen in the insulating layer 280 with the conductive layer 246.

[0232] In addition, by providing the insulating layer 276 having a barrier property, the range of materials for the conductive layer used for the plug or wiring can be expanded. For example, by using a metal material having the property of absorbing oxygen and having high conductivity for the conductive layer 246, a low-power semiconductor device can be provided. Specifically, a material having low oxidation resistance and high conductivity, such as tungsten and aluminum, can be used. In addition, for example, a conductive layer that is easy to form or process can be used.

[0233] By adopting the above structure, a semiconductor device having a transistor with a large on-state current can be provided. In addition, a semiconductor device including a transistor with a low off-state current can be provided. In addition, a semiconductor device having stable electrical characteristics and high reliability can be provided by suppressing changes in electrical characteristics.

[0234] <Constitution Materials>

[0235] 〔Substrate〕

[0236] Although there are no major restrictions on the material used for the substrate, the substrate must have at least a sufficiently high heat resistance to withstand the subsequent heat treatment. For example, as a substrate, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., etc. can be used. In addition, an SOI substrate or a substrate having semiconductor elements such as strained transistors or FIN-type transistors arranged on a semiconductor substrate can also be used. In addition, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, etc. that can be used for high electron mobility transistors (HEMT: High Electron Mobility Transistor) can also be used. In other words, the substrate is not only a supporting substrate, but can also be a substrate on which other devices such as transistors are formed.

[0237] In addition, as a substrate, a glass substrate such as barium borosilicate glass and aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, a flexible substrate can be used as a substrate. When a flexible substrate is used, a transistor or a capacitor can be directly manufactured on the flexible substrate, or a transistor or a capacitor can be manufactured on another manufacturing substrate, and then the transistor is peeled off and transferred to the flexible substrate. In addition, in order to peel off the transistor and the capacitor from the manufacturing substrate and transfer it to the flexible substrate, it is preferable to set a peeling layer between the manufacturing substrate and the transistor and the capacitor.

[0238] As a flexible substrate, for example, metal, alloy, resin, glass or its fiber can be used. The lower the linear expansion coefficient of the flexible substrate used as a substrate, the more deformation caused by the environment is suppressed, so it is preferred. For example, a flexible substrate with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less or 1×10 -5 / K or less. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for use in flexible substrates.

[0239] 〔Insulation layer〕

[0240] The insulating layer is a single layer or a stack of the following materials, and the material is selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In addition, a material obtained by mixing multiple types of oxide materials, nitride materials, oxynitride materials, and oxynitride materials can also be used.

[0241] Note that in this specification, etc., nitrogen oxide refers to a compound in which the nitrogen content is greater than the oxygen content. Also, oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content. In addition, the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS) or the like.

[0242] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, in order to prevent the hydrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the hydrogen concentration in the insulating layer. Specifically, the hydrogen concentration in the insulating layer measured by secondary ion mass spectrometry (SIMS) is 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 the following.

[0243] In order to prevent the nitrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer measured by SIMS is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0244] The insulating layer preferably has fewer defects in at least the region in contact with the semiconductor layer, and typically the signal observed by the electron spin resonance method (ESR) is preferably smaller. For example, as the above signal, the signal of the E' center observed at a g value of 2.001 can be cited. The E' center is caused by a dangling bond of silicon. For example, when a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, a spin density of 3×10 17 spins / cm 3 Below, preferably 5×10 16 spins / cm 3 The following silicon oxide layer or silicon oxynitride layer.

[0245] Sometimes, in addition to the above signals, a signal caused by nitrogen dioxide (NO2) is observed. This signal is split into three signals due to the nuclear spin of nitrogen, and the g values ​​are observed at 2.037 to 2.039 (first signal), 2.001 to 2.003 (second signal), and 1.964 to 1.966 (third signal).

[0246] For example, it is preferable to use a signal derived from nitrogen dioxide (NO2) with a spin density of 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 insulation layer.

[0247] Nitrogen dioxide (NO2) Nitrogen oxides (NO x ) forms an energy level in the insulating layer. This energy level is located in the energy gap of the oxide semiconductor layer. x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, sometimes this energy level captures electrons on the insulating layer side. As a result, the captured electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, by using a film with a low content of oxynitride as the insulating layer, the drift of the threshold voltage of the transistor can be reduced.

[0248] As nitrogen oxides (NO x ) can be used as an insulating layer with a low release amount, for example, a silicon oxynitride layer. The silicon oxynitride layer releases more ammonia than nitrogen oxides (NO x ) release rate, typically 1×10 18 molecules / cm 3 Above and 5×10 19 molecules / cm 3The ammonia release amount is the total amount in the TDS when the temperature of the heat treatment is within the range of 50°C to 650°C or within the range of 50°C to 550°C.

[0249] Since nitrogen oxides (NO x ) reacts with ammonia and oxygen, so by using an insulating layer that releases a lot of ammonia, nitrogen oxides (NO x ).

[0250] At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen by heating. Specifically, it is preferable to use an insulating layer whose oxygen release amount converted to oxygen atoms when TDS analysis is performed (wherein the layer surface temperature is heated to 100° C. to 700° C., preferably 100° C. to 500° C.) is 1.0×10 18 atoms / cm 3 Above, 1.0×10 19 atoms / cm 3 Above, or 1.0×10 20 atoms / cm 3 above.

[0251] The insulating layer containing excess oxygen can be formed by adding oxygen to the insulating layer. As the oxygen addition treatment, heat treatment in an oxidizing atmosphere, plasma treatment, etc. can be used. Alternatively, oxygen addition can be performed by ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of the gas used for the oxygen addition treatment include 16 O2 or 18 Oxygen gas such as O2, oxygen-containing gas such as nitrous oxide gas or ozone gas. Note that in this specification, treatment of adding oxygen may be referred to as "oxygen doping treatment." The oxygen doping treatment may be performed while heating the substrate.

[0252] As the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above-mentioned organic materials, low-k materials, siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, the insulating layer can also be formed by stacking a plurality of insulating layers formed of the above-mentioned materials.

[0253] Siloxane resins are equivalent to resins containing Si-O-Si bonds formed using siloxane materials as starting materials. Siloxane-based resins may include organic groups (e.g., alkyl groups or aryl groups) or fluorine groups as substitutes. In addition, the organic group may also have a fluorine group.

[0254] There is no particular limitation on the method for forming the insulating layer. Note that a baking process may be required depending on the material used for the insulating layer. In this case, the baking process of the insulating layer can be combined with other heat treatment processes to efficiently manufacture the transistor.

[0255] 〔electrode〕

[0256] As the conductive material for forming the electrode, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. can be used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and a silicide such as nickel silicide can also be used.

[0257] In addition, a conductive material containing the above-mentioned metal element and oxygen can also be used. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, indium tin oxide (ITO: Indium Tin Oxide), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium gallium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used.

[0258] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a conductive material containing nitrogen and a conductive material containing oxygen are combined may be used.

[0259] In addition, when an oxide semiconductor is used as the semiconductor layer and a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen is used as the gate electrode, it is preferred to provide a conductive material containing oxygen on one side of the semiconductor layer. By providing a conductive material containing oxygen on one side of the semiconductor layer, oxygen released from the conductive material can be easily supplied to the semiconductor layer.

[0260] In addition, as an electrode, for example, a highly embedded conductive material such as tungsten or polysilicon can be used. In addition, a combination of a highly embedded conductive material and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer can also be used. Sometimes the electrode is called a "contact plug".

[0261] In particular, it is preferable to use a conductive material that does not easily allow impurities to pass through as an electrode in contact with the gate insulating layer. As an example of a conductive material that does not easily allow impurities to pass through, tantalum nitride can be mentioned.

[0262] By using an insulating material that is not easily permeable to impurities as an insulating layer and a conductive material that is not easily permeable to impurities as an electrode, it is possible to further suppress the diffusion of impurities into the transistor. Therefore, the reliability of the transistor can be further improved. In other words, the reliability of the storage device can be further improved.

[0263] 〔Semiconductor layer〕

[0264] As the semiconductor layer, one or more of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, and an amorphous semiconductor can be used. As the semiconductor material, for example, silicon or germanium can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, or organic semiconductors can also be used.

[0265] When an organic semiconductor is used as the semiconductor layer, a low molecular weight organic material having an aromatic ring or a π-electron conjugated conductive polymer can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, etc. can be used.

[0266] The semiconductor layer may also adopt a stacked structure. When the semiconductor layer adopts a stacked structure, semiconductors with different crystal states or different semiconductor materials may be used.

[0267] In addition, since the band gap of an oxide semiconductor, which is a type of metal oxide, is greater than 2 eV, when an oxide semiconductor is used as a semiconductor layer, a transistor with an extremely small off-state current can be realized. Specifically, the off-state current per channel width of 1 μm at a voltage of 3.5 V between the source and the drain can be less than 1×10 -20 A, preferably less than 1×10 -22 A, more preferably less than 1×10 -24 A. That is, the on-off ratio can be more than 20 digits. In addition, in a transistor using an oxide semiconductor as a semiconductor layer (OS transistor), the insulation withstand voltage between the source and the drain is high. Thus, a transistor with good reliability can be provided. In addition, a transistor with a large output voltage and a high withstand voltage can be provided. In addition, a storage device with good reliability can be provided. In addition, a storage device with a large output voltage and a high withstand voltage can be provided.

[0268] In this specification and the like, a transistor using crystalline silicon in a semiconductor layer forming a channel is referred to as a "crystalline Si transistor".

[0269] Compared with OS transistors, crystalline Si transistors can easily obtain higher mobility. On the other hand, it is difficult for crystalline Si transistors to achieve extremely small off-state currents like OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to its purpose and use. For example, a combination of OS transistors and crystalline Si transistors, etc., can be used depending on the purpose or use.

[0270] When an oxide semiconductor layer is used as a semiconductor layer, it is preferred to form the oxide semiconductor layer by sputtering. The density of the oxide semiconductor layer formed by sputtering is higher, so it is preferred. In the case of forming the oxide semiconductor layer by sputtering, as the sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen can be used. In addition, the sputtering gas needs to be highly purified. For example, as an oxygen gas or a rare gas used as a sputtering gas, a high-purity gas with a dew point of less than -60°C, preferably less than -100°C, is used. By using a high-purity sputtering gas for film formation, it is possible to prevent moisture and the like from mixing into the oxide semiconductor layer as much as possible.

[0271] When the oxide semiconductor layer is formed by sputtering, it is preferable to remove as much water as possible from the film forming chamber of the sputtering device. For example, it is preferable to use an adsorption vacuum pump such as a cryopump to evacuate the film forming chamber to a high vacuum (to 5×10 -7 Pa to 1×10 -4 In particular, when the sputtering device is on standby, the partial pressure of the gas molecules corresponding to H2O (the gas molecules corresponding to m / z=18) in the film forming processing chamber is preferably 1×10 -4 Pa or less, more preferably 5×10 -5 Below Pa.

[0272] 〔Metal oxide〕

[0273] The oxide semiconductor as one of the metal oxides preferably contains at least indium or zinc. In particular, it is preferred to contain indium and zinc. In addition, it is preferred to contain aluminum, gallium, yttrium or tin. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0274] Here, the case where the oxide semiconductor includes indium, element M, and zinc is considered. Note that element M represents aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that as element M, a plurality of the above elements may be combined.

[0275] In addition, in this specification and the like, a metal oxide containing nitrogen may be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0276] [Structure of Metal Oxide]

[0277] Oxide semiconductors, which are a type of metal oxide, are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0278] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction, and the crystal structure has distortion. Distortion refers to the part where the lattice arrangement direction changes between the region where multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0279] Nanocrystals are basically hexagonal, but are not limited to regular hexagons, and are sometimes non-regular hexagons. In addition, nanocrystals sometimes have lattice arrangements such as pentagons or heptagons in distortion. In addition, in CAAC-OS, no clear grain boundaries are observed even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms caused by the substitution of metal elements.

[0280] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be represented as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0281] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. In addition, the crystallinity of metal oxides is sometimes reduced due to the mixing of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with few impurities or defects (oxygen vacancies, etc.). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide with CAAC-OS has heat resistance and high reliability.

[0282] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0283] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0284] Oxide semiconductors (metal oxides) have various structures and various characteristics. Oxide semiconductors may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0285] [Transistor with metal oxide]

[0286] Next, a case where the above-mentioned metal oxide is used in a channel formation region of a transistor will be described.

[0287] By using the above-mentioned metal oxide in the channel formation region of the transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0288] In addition, it is preferable to use a metal oxide with a low carrier density for a transistor. When the carrier density of a metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in a metal oxide can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3, more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 above.

[0289] Because a high purity intrinsic or substantially high purity intrinsic metal oxide film has a lower defect state density, it is possible to have a lower trap state density.

[0290] Furthermore, it takes a long time for the charges trapped in the trap states of the metal oxide to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region in a metal oxide with a high trap state density may be unstable.

[0291] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0292] [Impurities]

[0293] Here, the influence of each impurity in the metal oxide is described.

[0294] When the metal oxide contains silicon or carbon belonging to the Group 14 element, defect states are formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon near the interface of the metal oxide (concentration measured by SIMS) are set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0295] In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferred to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0296] When the metal oxide contains nitrogen, electrons as carriers are generated, the carrier density increases, and the metal oxide is easily converted to n-type. As a result, a transistor using a metal oxide containing nitrogen in a channel formation region tends to have a normally-on characteristic. Therefore, in the metal oxide, it is preferable to reduce nitrogen in the channel formation region as much as possible. For example, the nitrogen concentration in the metal oxide measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0297] Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to generate water, thus sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using a metal oxide containing hydrogen as a channel formation region tend to have a normally-on characteristic. Therefore, it is preferred to reduce the hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide measured by SIMS analysis is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0298] By using a metal oxide in which impurities are sufficiently reduced in a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0299] As a metal oxide for a semiconductor of a transistor, a thin film with high crystallinity is preferably used. By using this thin film, the stability or reliability of the transistor can be improved. As the thin film, for example, a single crystal metal oxide thin film or a polycrystalline metal oxide thin film can be cited. However, forming a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate requires a process of high temperature or laser heating. Therefore, the cost of the manufacturing process becomes high and the throughput decreases.

[0300] Non-patent Documents 1 and 2 report that In-Ga-Zn oxide (also called CAAC-IGZO) with a CAAC structure was discovered in 2009. Non-patent Documents 1 and 2 report that CAAC-IGZO has c-axis orientation, unclear grain boundaries, and can be formed on a substrate at low temperatures. In addition, it is also reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

[0301] In addition, In-Ga-Zn oxide (called nc-IGZO) with an nc structure was discovered in 2013 (see Non-Patent Document 3). It was reported that the atomic arrangement of nc-IGZO in a tiny region (e.g., a region greater than 1 nm and less than 3 nm) is periodic, and no regularity in crystal orientation is observed between different regions.

[0302] Non-patent literature 4 and non-patent literature 5 show the change of the average crystal size when the thin films of the above-mentioned CAAC-IGZO, nc-IGZO and IGZO with low crystallinity are irradiated with electron beams, respectively. In the IGZO thin film with low crystallinity, crystalline IGZO of about 1 nm can be observed before it is irradiated with an electron beam. Therefore, it is reported in non-patent literature 4 and non-patent literature 5 that the existence of a completely amorphous structure (completely amorphous structure) has not been confirmed in IGZO. Furthermore, it is disclosed that the stability of CAAC-IGZO thin films and nc-IGZO thin films relative to electron beam irradiation is higher than that of IGZO thin films with low crystallinity. Therefore, it is preferable to use a CAAC-IGZO thin film or a nc-IGZO thin film as a semiconductor of a transistor.

[0303] Non-patent document 6 discloses that the leakage current of a transistor using metal oxide in the non-conducting state is extremely low. Specifically, the off-state current of the transistor per channel width of 1 μm is yA / μm (10 -24 For example, a low-power CPU or the like that utilizes the low leakage current characteristic of a transistor using a metal oxide has been disclosed (see Non-Patent Document 7).

[0304] In addition, there are reports that use transistors using metal oxides to apply the transistor to display devices by taking advantage of the low leakage current characteristic of the transistor (see non-patent document 8). In a display device, the displayed image is switched dozens of times in 1 second. The number of image switches per 1 second is called the "refresh frequency". In addition, the refresh frequency is sometimes called the "drive frequency". Such high-speed screen switching that is difficult for the human eye to recognize is believed to be a cause of eye fatigue. Therefore, a technology has been proposed to reduce the refresh frequency of the display device to reduce the number of image rewrites. The drive with a reduced refresh frequency can reduce the power consumption of the display device. This driving method is called "idle stop (IDS) drive".

[0305] The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of transistors using the CAAC structure or metal oxides having the nc structure, the reduction of the cost of the manufacturing process, and the increase of the throughput. In addition, research has been conducted on the application of the transistors to display devices and LSIs by utilizing the low leakage current characteristic of the transistors.

[0306] <Film Formation Method>

[0307] The insulating material used to form the insulating layer, the conductive material used to form the electrode, or the semiconductor material used to form the semiconductor layer can be formed by sputtering, spin coating, chemical vapor deposition (CVD: Chemical Vapor Deposition) method (including thermal CVD method, MOCVD (Metal Organic Chemical Vapor Deposition, organic metal CVD) method, PECVD (Plasma Enhanced CVD, plasma enhanced CVD) method, high-density plasma CVD (High density plasma CVD) method, LPCVD (low pressure CVD, reduced pressure CVD) method, APCVD (atmospheric pressure CVD, atmospheric pressure CVD) method, etc.), ALD (Atomic Layer Deposition, atomic layer deposition) method, or MBE (Molecular Beam Epitaxy, molecular beam epitaxy) method, PLD (Pulsed Laser Deposition, pulsed laser deposition) method, dip coating, spraying, droplet jetting method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), etc.

[0308] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In the case of using a film forming method that does not use plasma, such as the MOCVD method, the ALD method, or the thermal CVD method, it is not easy to cause damage to the formed surface. For example, the wiring, electrodes, elements (transistors, capacitors, etc.) included in the storage device sometimes generate charge accumulation (charge up) due to receiving charges from plasma. At this time, the wiring, electrodes, elements, etc. included in the storage device are sometimes damaged due to the accumulated charge. On the other hand, in the case of a film forming method that does not use plasma, since such plasma damage does not occur, the yield of the storage device can be improved. In addition, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

[0309] Unlike the film forming method of depositing particles released from a target material, etc., the CVD method and the ALD method are film forming methods that form films due to reactions on the surface of the object to be processed. Therefore, the films formed by the CVD method and the ALD method are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a film covering the surface of an opening with a high aspect ratio. However, the film forming speed of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other film forming methods such as the CVD method with a fast film forming speed.

[0310] The CVD method or the ALD method can control the composition of the obtained film by adjusting the flow ratio of the source gas. For example, when the CVD method or the ALD method is used, a film of any composition can be formed by adjusting the flow ratio of the source gas. In addition, for example, when the CVD method or the ALD method is used, a film whose composition continuously changes can be formed by changing the flow ratio of the source gas while forming the film. When the film is formed while changing the flow ratio of the source gas, the time required for conveying and adjusting the pressure can be omitted, so the time required for film formation can be shortened compared to the case where the film is formed using multiple film forming chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0311] Note that when the film is formed by the ALD method, it is preferable to use a gas that does not contain chlorine as a material gas.

[0312] <Transistor Structure Example 2>

[0313] Reference Fig.11 A to Fig.11 C describes a structural example of the transistor 200B. Fig.11 A is a top view of transistor 200B. Fig.11 B is along Fig.11 A is a cross-sectional view of a portion indicated by a dashed line L1 - L2. Fig.11C is along Fig.11 A is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.11 In the plan view of A, some components are omitted for clarity.

[0314] The transistor 200B is a modified example of the transistor 200A. Therefore, in order to avoid duplication of description, the difference between the transistor 200B and the transistor 200A will be mainly described.

[0315] exist Fig.11 In the transistor 200B shown, the oxide 230c, the insulating layer 250, and the conductive layer 260 are arranged in an opening provided in the insulating layer 280 via the insulating layer 274. In addition, the oxide 230c, the insulating layer 250, and the conductive layer 260 are arranged between the conductive layer 242a and the conductive layer 242b.

[0316] It is preferable that the oxide 230c is formed in an opening provided in the insulating layer 280 via the insulating layer 274. When the insulating layer 274 has a barrier property, diffusion of impurities included in the insulating layer 280 into the oxide 230 can be suppressed.

[0317] The insulating layer 250 is preferably formed in an opening provided in the insulating layer 280 via the oxide 230 c and the insulating layer 274 .

[0318] An insulating layer 274 is disposed between the insulating layer 280 and the transistor 200B. As the insulating layer 274, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide, hafnium oxide, etc. are preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. can also be used.

[0319] By including the insulating layer 274, impurities such as water and hydrogen in the insulating layer 280 can be prevented from diffusing into the oxide 230b through the oxide 230c and the insulating layer 250. In addition, oxidation of the conductive layer 260 by excess oxygen included in the insulating layer 280 can be prevented.

[0320] <Transistor Structure Example 3>

[0321] Reference Fig.12 A to Fig.12 C describes a structural example of the transistor 200C. Fig.12 A is a top view of transistor 200C. Fig.12 B is along Fig.12 A is a cross-sectional view of a portion indicated by a dashed line L1 - L2. Fig.12 C is along Fig.12 A is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.12 In the plan view of A, some components are omitted for clarity.

[0322] The transistor 200C is a modified example of the transistor 200B. Therefore, in order to avoid duplication of description, the difference between the transistor 200C and the transistor 200B will be mainly described.

[0323] Fig.12 The transistor 200C shown has a conductive layer 247a disposed between the conductive layer 242a and the oxide 230b, and a conductive layer 247b disposed between the conductive layer 242b and the oxide 230b. Here, the conductive layer 242a (conductive layer 242b) has a region extending beyond the top surface of the conductive layer 247a (conductive layer 247b) and the side surface on one side of the conductive layer 260 and in contact with the top surface of the oxide 230b. Here, the conductive layer 247 (conductive layer 247a and conductive layer 247b) can use a conductor that can be used for the conductive layer 242 (conductive layer 242a and conductive layer 242b). In addition, it is preferred that the film thickness of the conductive layer 247 is at least thicker than that of the conductive layer 242.

[0324] because Fig.12 The transistor 200C shown has the above structure, and compared with the transistor 200B, the conductive layer 242 can be closer to the conductive layer 260. Alternatively, the end of the conductive layer 242a and the end of the conductive layer 242b can overlap the conductive layer 260. Thus, the substantial channel length of the transistor 200C can be reduced to improve the on-state current and the operating frequency characteristics.

[0325] In addition, the conductive layer 247a (conductive layer 247b) preferably overlaps the conductive layer 242a (conductive layer 242b). With this structure, when etching is performed to form an opening to fill the conductive layer 246a (conductive layer 246b), the conductive layer 247a (conductive layer 247b) is used as an etching stopper to prevent overetching of the oxide 230b.

[0326] In addition, Fig.12 In the transistor 200C shown, an insulating layer 245 may be arranged in contact with the insulating layer 244. The insulating layer 244 is preferably used as a blocking insulating film for suppressing impurities such as water or hydrogen or excess oxygen from entering the transistor 200C from the insulating layer 280 side. As the insulating layer 245, an insulator that can be used for the insulating layer 244 can be used. In addition, as the insulating layer 245, for example, a nitride insulator such as aluminum nitride, aluminum nitride, titanium nitride, silicon nitride, or silicon nitride oxide can be used.

[0327] In addition, Fig.11 The transistor 200B shown is different in that Fig.12The conductive layer 205 of the transistor 200C shown may have a single-layer structure. At this time, an insulating film to become the insulating layer 216 may be formed on the conductive layer 205 that has been formed into a pattern, and the top of the insulating film may be removed by using a chemical mechanical polishing (CMP) method or the like until the top surface of the conductive layer 205 is exposed. Here, it is preferred to make the top surface of the conductive layer 205 have good flatness. For example, the average surface roughness (Ra) of the top surface of the conductive layer 205 is less than 1 nm, preferably less than 0.5 nm, and more preferably less than 0.3 nm. Thus, the flatness of the insulating layer formed on the conductive layer 205 can be improved, and the crystallinity of the oxide 230b and the oxide 230c can be improved.

[0328] <Transistor Structure Example 4>

[0329] Reference Fig.13 A to Fig.13 C describes a structural example of the transistor 200D. Fig.13 A is a top view of transistor 200D. Fig.13 B is along Fig.13 A is a cross-sectional view of a portion indicated by a dashed line L1 - L2. Fig.13 C is along Fig.13 A is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.13 In the plan view of A, some components are omitted for clarity.

[0330] The transistor 200D is a modified example of the above-mentioned transistor, and therefore, in order to avoid duplication of description, the difference between it and the above-mentioned transistor will be mainly described.

[0331] exist Fig.13 A to Fig.13 In FIG. 2C, the conductive layer 205 having the function of the second gate is also used as a wiring without providing the conductive layer 203. In addition, an insulating layer 250 is provided on the oxide 230c, and a metal oxide 252 is provided on the insulating layer 250. In addition, a conductive layer 260 is provided on the metal oxide 252, and an insulating layer 270 is provided on the conductive layer 260. In addition, an insulating layer 271 is provided on the insulating layer 270.

[0332] The metal oxide 252 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 252 that suppresses oxygen diffusion between the insulating layer 250 and the conductive layer 260, oxygen diffusion to the conductive layer 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductive layer 260 due to oxygen can be suppressed.

[0333] In addition, the metal oxide 252 may be used as part of the first gate. For example, an oxide semiconductor layer that can be used as the oxide 230 may be used for the metal oxide 252. In this case, by forming the conductive layer 260 by sputtering, the resistivity of the metal oxide 252 may be reduced to make it a conductive layer.

[0334] In addition, the metal oxide 252 is sometimes used as a part of the first gate insulating layer. Therefore, when silicon oxide or silicon oxynitride is used for the insulating layer 250, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide 252. By adopting this stacked structure, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0335] Although the metal oxide 252 in the transistor 200D is shown as a single-layer structure, a stacked structure of two or more layers may be adopted. For example, a metal oxide used as part of the first gate and a metal oxide used as part of the first gate insulating layer may be stacked.

[0336] When the metal oxide 252 is used as the first gate, the on-state current of the transistor 200D can be increased without weakening the influence of the electric field from the conductive layer 260. In addition, when the metal oxide 252 is used as the first gate insulating layer, the leakage current between the conductive layer 260 and the oxide 230 can be suppressed by maintaining the distance between the conductive layer 260 and the oxide 230 by utilizing the physical thickness of the insulating layer 250 and the metal oxide 252. Thus, by providing a stacked structure of the insulating layer 250 and the metal oxide 252, the physical distance between the conductive layer 260 and the oxide 230 and the electric field strength applied from the conductive layer 260 to the oxide 230 can be easily adjusted.

[0337] Specifically, an oxide semiconductor that can be used for the oxide 230 can be used as the metal oxide 252 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0338] In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used as an insulating layer containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than hafnium oxide. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, the metal oxide 252 does not necessarily need to be provided. It can be appropriately designed according to the required transistor characteristics.

[0339] An insulating material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 270. For example, aluminum oxide, hafnium oxide, etc. are preferably used. Thus, oxidation of the conductive layer 260 due to oxygen from above the insulating layer 270 can be prevented. In addition, impurities such as water or hydrogen from above the insulating layer 270 can be inhibited from entering the oxide 230 through the conductive layer 260 and the insulating layer 250.

[0340] The insulating layer 271 is used as a hard mask. By providing the insulating layer 271, the conductive layer 260 can be processed in a manner such that its side surface is substantially perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductive layer 260 and the substrate surface can be made greater than 75 degrees and less than 100 degrees, preferably greater than 80 degrees and less than 95 degrees.

[0341] Alternatively, the insulating layer 271 may also function as a barrier layer by using an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the insulating layer 271. In this case, the insulating layer 270 may not be provided.

[0342] By using the insulating layer 271 as a hard mask, the insulating layer 270, the conductive layer 260, the metal oxide 252, the insulating layer 250, and a portion of the metal oxide 230c are selectively removed, so that their side surfaces can be roughly aligned and a portion of the surface of the metal oxide 230b can be exposed.

[0343] In addition, the transistor 200D has a region 231a and a region 231b in a portion of the surface of the exposed oxide 230b. One of the region 231a and the region 231b is used as a source region, and the other is used as a drain region.

[0344] For example, the regions 231a and 231b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed oxide 230b by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, etc. Note that in this embodiment mode, "impurity elements" refer to elements other than main component elements.

[0345] Alternatively, after a portion of the surface of the oxide 230 b is exposed, a metal film may be formed, and then heat treatment may be performed to diffuse elements included in the metal film into the oxide 230 b , thereby forming the regions 231 a and 231 b .

[0346] The resistivity of a portion of the metal oxide 230b into which the impurity element is introduced decreases. Therefore, the region 231a and the region 231b are sometimes referred to as an "impurity region" or a "low-resistance region."

[0347] By using the insulating layer 271 or the conductive layer 260 as a mask, the region 231a and the region 231b can be formed in a self-aligned manner. Therefore, the region 231a and / or the region 231b do not overlap with the conductive layer 260, and the parasitic capacitance can be reduced. In addition, the bias region is not formed between the channel formation region and the source region or the drain region (region 231a or region 231b). By forming the region 231a and the region 231b in a self-aligned manner, an increase in the on-state current, a decrease in the threshold voltage, an increase in the operating frequency, etc. can be achieved.

[0348] In addition, in order to further reduce the off-state current, a bias region may be provided between the channel formation region and the source region or the drain region. The bias region is a region with high resistivity and is a region where the above-mentioned impurity elements are not introduced. The bias region can be formed by introducing the above-mentioned impurity elements after forming the insulating layer 275. In this case, the insulating layer 275 is also used as a mask as the insulating layer 271. Therefore, the region of the oxide 230b overlapping the insulating layer 275 is not introduced with impurity elements, thereby maintaining the resistivity of the region high.

[0349] The transistor 200D includes an insulating layer 275 on the side of the insulating layer 270, the conductive layer 260, the metal oxide 252, the insulating layer 250, and the metal oxide 230c. The insulating layer 275 is preferably an insulating layer with a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores is used for the insulating layer 275, it is preferred because an excess oxygen region can be easily formed in the insulating layer 275 in the subsequent process. In addition, silicon oxide and silicon oxynitride are thermally stable, so they are preferred. In addition, the insulating layer 275 preferably has a function of diffusing oxygen.

[0350] The transistor 200D includes an insulating layer 274 over the insulating layer 275 and the oxide 230. The insulating layer 274 is preferably formed by sputtering. By using the sputtering method, an insulator with less impurities such as water and hydrogen can be formed. For example, aluminum oxide is preferably used as the insulating layer 274.

[0351] Oxide films formed by sputtering may extract hydrogen from the structure being formed. Therefore, the insulating layer 274 extracts hydrogen and water from the oxide 230 and the insulating layer 275 to reduce the hydrogen concentration of the oxide 230 and the insulating layer 275.

[0352] <Transistor Structure Example 5>

[0353] Reference Fig.14 A to Fig.14C describes a structural example of the transistor 200E. Fig.14 A is a top view of transistor 200E. Fig.14 B is along Fig.14 A is a cross-sectional view of a portion indicated by a dashed line L1 - L2. Fig.14 C is along Fig.14 A is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.14 In the plan view of A, some components are omitted for clarity.

[0354] The transistor 200E is a modified example of the transistor 200B. Therefore, in order to avoid duplication of description, the difference between the transistor 200E and the transistor 200B will be mainly described.

[0355] exist Fig.14 A to Fig.14 In FIG. 2C, regions 231a and 231b are provided on a portion of the surface of the exposed oxide 230b without providing a conductive layer 242. One of the regions 231a and 231b is used as a source region, and the other is used as a drain region. In addition, an insulating layer 273 is provided between the oxide 230b and the insulating layer 274.

[0356] Fig.14 The region 231 (region 231a and region 231b) shown is a region where an element that reduces the resistance of the oxide 230b is added to the oxide 230b. The region 231 can be formed by using a dummy gate, for example.

[0357] Specifically, a dummy gate is provided on the oxide 230b, and the dummy gate is used as a mask to add an element that makes the oxide 230b low in resistance to the oxide 230b. That is, the element is added to the region of the oxide 230 that does not overlap with the dummy gate, thereby forming the region 231. As a method for adding the element, an ion implantation method in which the ionized source gas is mass-separated and added; an ion doping method in which the ionized source gas is not mass-separated and added; and a plasma immersion ion implantation method, etc. can be used.

[0358] The element that makes the oxide 230 low in resistance is typically boron or phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. may also be used. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. The concentration of the element can be measured using SIMS or the like.

[0359] In particular, boron and phosphorus are preferred because they can be used in the production line of amorphous silicon or low-temperature polysilicon. Existing equipment can be used, thereby reducing equipment investment.

[0360] Next, an insulating film serving as insulating layer 273 and an insulating film serving as insulating layer 274 may be formed on oxide 230b and the dummy gate. By providing a stack of insulating films serving as insulating layer 273 and insulating layer 274, a region where region 231 overlaps with oxide 230c and insulating layer 250 may be provided.

[0361] Specifically, an insulating film serving as insulating layer 280 is provided on an insulating film serving as insulating layer 274, and then a CMP (Chemical Mechanical Polishing) process is performed on the insulating film serving as insulating layer 280 to remove a portion of the insulating film serving as insulating layer 280, thereby exposing the above-mentioned dummy gate. Next, when removing the above-mentioned dummy gate, it is preferred to also remove a portion of the insulating film serving as insulating layer 273 in contact with the above-mentioned dummy gate. As a result, on the side of the opening portion provided in the insulating layer 280, the insulating layer 274 and the insulating layer 273 are exposed, and on the bottom surface of the opening portion, a portion of the region 231 provided in the oxide 230b is exposed. Next, an oxide film serving as oxide 230c, an insulating film serving as insulating layer 250, and a conductive film serving as conductive layer 260 are sequentially formed in the opening portion, and then a portion of the oxide film serving as oxide 230c, the insulating film serving as insulating layer 250, and the conductive film serving as conductive layer 260 are removed by CMP treatment or the like until the insulating layer 280 is exposed, thereby forming Fig.14 Transistor 200E is shown.

[0362] In addition, the insulating layer 273 and the insulating layer 274 are not necessarily provided and may be appropriately designed according to required transistor characteristics.

[0363] Fig.14 The transistor 200E shown can utilize existing devices, and further, since the conductive layer 242 is not provided, the cost can be reduced.

[0364] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes, examples, and the like as appropriate.

[0365] (Implementation method 3)

[0366] In this embodiment, refer to Figure 15 to Figure 16 , a memory device using a transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor using an oxide for a semiconductor according to one embodiment of the present invention (hereinafter sometimes referred to as an OS memory device) is described. The OS memory device is a memory device including at least a capacitor and an OS transistor for controlling the charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can be used as a non-volatile memory.

[0367] <Configuration Example of Storage Device>

[0368] Fig.15 A shows an example of the structure of the OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0369] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read out from the memory cell. Note that the above-mentioned wiring is a wiring connected to the memory cell included in the memory cell array 1470, and its details are described below. The amplified data signal is output as a data signal RDATA to the outside of the memory device 1400 through the output circuit 1440. In addition, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0370] The memory device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0371] The control logic circuit 1460 processes the control signals (CE, WE, RE) from the outside to generate control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals can be input as needed.

[0372] The memory cell array 1470 includes a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in one column, etc. In addition, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in one row, etc.

[0373] In addition, although Fig.15A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited thereto. Fig.15 As shown in FIG. 1B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be adopted.

[0374] Fig.16 An example of a structure of a memory cell that can be applied to the above-described memory cell MC will be described.

[0375] [DOSRAM]

[0376] Fig.16 A to Fig.16 C shows an example of a circuit structure of a memory cell of a DRAM. In this specification, etc., a DRAM using a 1-OS transistor 1-capacitor type memory cell may be referred to as a DOSRAM. Fig.16 The memory cell 1471 shown in A includes a transistor M1 and a capacitor CA. In addition, the transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0377] The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

[0378] The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CA. When writing and reading data, it is preferred to apply a low-level potential to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0379] In addition, the memory cell MC is not limited to the memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also be used as follows Fig.16 The back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. Fig.16 A memory cell such as the memory cell 1473 shown in C is a memory cell composed of a single-gate structure transistor, that is, a transistor M1 that does not include a back gate.

[0380] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor described in the previous embodiment can be used as the transistor M1. By using the OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. In other words, since the written data can be maintained for a long time by the transistor M1, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is extremely small, multi-value data or analog data can be maintained in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0381] In addition, in DOSRAM, when a sense amplifier is provided so as to overlap below the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell.

[0382] [NOSRAM]

[0383] Fig.16 D to Fig.16 G shows a circuit configuration example of a gain unit type memory cell having two transistors and one capacitor. Fig.16 The memory cell 1474 shown in D includes a transistor M2, a transistor M3, and a capacitor CB. In addition, the transistor M2 includes a top gate (sometimes simply referred to as a gate) and a back gate. In this specification, etc., a memory device including a gain unit type memory cell using an OS transistor for the transistor M2 is sometimes referred to as a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0384] The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0385] Wiring WBL is used as a write bit line, wiring RBL is used as a read bit line, and wiring WOL is used as a word line. Wiring CAL is used as a wiring for applying a specified potential to the second terminal of capacitor CB. When writing, holding, and reading data, it is preferred to apply a low-level potential to wiring CAL. Wiring BGL is used as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0386] In addition, the memory cell MC is not limited to the memory cell 1474, and its circuit structure can be changed appropriately. For example, the memory cell MC can also be used as follows. Fig.16 The back gate of the transistor M2 is not connected to the wiring BGL but to the wiring WOL, as in the memory cell 1475 shown in E. In addition, for example, the memory cell MC may also be as follows: Fig.16 F is a memory cell composed of a single-gate transistor, that is, a memory cell M2 that does not include a back gate. In addition, for example, the memory cell MC may also have a structure such as Fig.16 The memory cell 1477 shown in G has a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL.

[0387] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor described in the previous embodiment can be used as the transistor M2. By using the OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely small. Thus, since the written data can be maintained for a long time by the transistor M2, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is extremely small, multi-value data or analog data can be maintained in the memory cell 1474. The same is true for the memory cells 1475 to 1477.

[0388] In addition, the transistor M3 may also be a transistor including silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The field effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, as the transistor M3 used as a readout transistor, a Si transistor may also be used. In addition, by using a Si transistor for the transistor M3, the transistor M2 may be stacked on the transistor M3, thereby reducing the occupied area of ​​the memory cell and realizing high integration of the memory device.

[0389] In addition, the transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M2 and the transistor M3, the circuit can be configured using only n-type transistors in the memory cell array 1470 .

[0390] in addition, Fig.16 H shows an example of a gain unit type memory cell having three transistors and one capacitor. Fig.16The memory cell 1478 shown in FIG. 14 includes transistors M4 to M6 and a capacitor CC. The capacitor CC can be appropriately provided. The memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL. The wiring GNDL is a wiring for supplying a low-level potential. In addition, the memory cell 1478 can also be electrically connected to the wiring RBL and the wiring WBL without being electrically connected to the wiring BIL.

[0391] The transistor M4 is an OS transistor including a back gate, and the back gate is electrically connected to the wiring BGL. In addition, the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include a back gate.

[0392] In addition, transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, transistors M4 to M6 may all be OS transistors. In this case, only n-type transistors may be used to form a circuit in memory cell array 1470.

[0393] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor described in the previous embodiment can be used as the transistor M4. By using an OS transistor as the transistor M4, leakage current of the transistor M4 can be minimized.

[0394] Note that the structure of the peripheral circuit 1411, the memory cell array 1470, and the like described in this embodiment are not limited to the above-described structure. In addition, the arrangement or function of these circuits and wirings connected to the circuits, circuit elements, and the like may be changed, removed, or added as necessary.

[0395] The structure described in this embodiment mode can be implemented in combination with the structure described in other embodiment modes, examples, etc. as appropriate.

[0396] (Implementation 4)

[0397] In this embodiment, refer to Fig.17 An example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described. A plurality of circuits (systems) are mounted on the chip 1200. In this way, a technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0398] like Fig.17As shown in A, the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0399] Bumps (not shown) are provided on the chip 1200. Fig.17 B is connected to the first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the back of the first surface of the PCB 1201, and the bumps 1202 are connected to a motherboard 1203.

[0400] In addition, a storage device such as a DRAM 1221 and a flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM described in the above embodiment mode may be applied to the DRAM 1221. In addition, the NOSRAM described in the above embodiment mode may be applied to the flash memory 1222, for example.

[0401] CPU1211 preferably has multiple CPU cores. In addition, GPU1212 preferably has multiple GPU cores. In addition, CPU1211 and GPU1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by CPU1211 and GPU1212 may be provided on chip 1200. The above-mentioned NOSRAM or DOSRAM may be applied to the memory. In addition, GPU1212 is suitable for parallel calculation of multiple data, which can be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention as GPU1212, image processing and product-sum operations can be performed with low power consumption.

[0402] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0403] The analog operation unit 1213 includes one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. In addition, the above-mentioned product-sum operation circuit may be provided in the analog operation unit 1213.

[0404] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0405] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, an image capture device, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0406] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0407] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at a low cost.

[0408] The motherboard 1203 including the PCB 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0409] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing a product-sum operation circuit using the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recursive neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module can be used as an AI system module.

[0410] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes, examples, etc. as appropriate.

[0411] (Implementation method 5)

[0412] In this embodiment, an application example of a storage device using the semiconductor device shown in the above embodiment is described. The semiconductor device shown in the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smart phone, an e-book reader terminal, a digital camera (including a video camera), a video playback device, a navigation system, etc.). Note that here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). Fig.18 Several structural examples of the removable storage device are schematically shown. For example, the semiconductor device described in the above embodiment mode is processed into a packaged memory chip and used in various storage devices or removable memories.

[0413] Fig.18 A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device described in the above embodiment can be assembled to the memory chip 1105 and the like.

[0414] Fig.18 B is the appearance diagram of SD card. Fig.18 C is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1114, etc.

[0415] Fig.18 D is the appearance diagram of SSD. Fig.18E is a schematic diagram of the internal structure of the SSD. SSD1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD1150 can be increased. The semiconductor device shown in the above embodiment can be assembled to the memory chip 1154, etc.

[0416] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes, examples, and the like as appropriate.

[0417] (Implementation 6)

[0418] A semiconductor device according to one embodiment of the present invention can be applied to a processor or chip such as a CPU or a GPU. Fig.19 Specific examples of electronic devices including a processor or chip such as a CPU or a GPU according to one embodiment of the present invention are shown.

[0419] 〈Electronic equipment and systems>

[0420] A GPU or chip according to one embodiment of the present invention can be installed in a variety of electronic devices. As examples of electronic devices, in addition to electronic devices with larger screens such as television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, and large-scale game machines such as pinball machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices can also be cited. In addition, by setting an integrated circuit or chip according to one embodiment of the present invention in an electronic device, the electronic device can be provided with artificial intelligence.

[0421] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, an image or information can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0422] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0423] An electronic device of one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc. Fig.19 An example of an electronic device is shown.

[0424] [Mobile phone]

[0425] Fig.19 A shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 has a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0426] By applying a chip of one embodiment of the present invention to the information terminal 5500, an application program utilizing artificial intelligence can be executed. Examples of the application program utilizing artificial intelligence include an application program that recognizes a conversation and displays the content of the conversation on the display unit 5511, an application program that recognizes text or graphics input by a user to a touch panel provided on the display unit 5511 and displays the text or graphics on the display unit 5511, and an application program that performs biometric recognition such as fingerprints or voiceprints.

[0427] [Information Terminal]

[0428] Fig.19 B shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal body 5301, a display 5302, and a keyboard 5303.

[0429] As with the above-mentioned information terminal 5500, by applying a chip of one embodiment of the present invention to the desktop information terminal 5300, an application program utilizing artificial intelligence can be executed. Examples of applications utilizing artificial intelligence include design support software, article proofreading software, and menu automatic generation software. In addition, by using the desktop information terminal 5300, novel artificial intelligence can be developed.

[0430] Note that in the above example, Fig.19 A and Fig.19 B shows a smartphone and a desktop information terminal as examples of electronic devices, but information terminals other than smartphones and desktop information terminals may also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0431] [Electrical products]

[0432] Fig.19 C shows an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0433] By applying a chip of one embodiment of the present invention to an electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food, and a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food.

[0434] In the above example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0435] [Game console]

[0436] Fig.19 D shows a portable game machine 5200 which is an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0437] By applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, a low-power portable game console 5200 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0438] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, a portable game console 5200 having artificial intelligence can be realized.

[0439] The performance of the progress of the game, the words and deeds of creatures appearing in the game, and the phenomena occurring in the game are originally specified by the program of the game, but by applying artificial intelligence to the portable game machine 5200, it is possible to realize performance not limited to the game program. For example, it is possible to realize the performance of the content of the questions asked by the game player, the progress of the game, the time, the words and deeds of the characters appearing in the game, etc.

[0440] Furthermore, when using the portable game console 5200 to play a game that requires multiple players, artificial intelligence can be used to construct an anthropomorphic game player, whereby the artificial intelligence game player can be used as an opponent, and one person can play the game that requires multiple players.

[0441] Although Fig.19 D shows a portable game console as an example of a game console, but the game console to which the GPU or chip of one embodiment of the present invention is applied is not limited thereto. Examples of game consoles to which the GPU or chip of one embodiment of the present invention is applied include home-use fixed game consoles, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0442] [Mobile body]

[0443] The GPU or chip according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0444] Fig.19 E1 is a diagram showing a car 5700 which is an example of a moving object. Fig.19 E2 is a diagram showing the periphery of the front windshield in the interior of the vehicle. Fig.19 E2 shows a display panel 5701 installed on the instrument panel, a display panel 5702, a display panel 5703, and a display panel 5704 installed on a pillar.

[0445] Display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a driving distance, a refueling amount, a gear status, and an air conditioning setting. In addition, the user can appropriately change the display content and layout displayed on the display panel according to his or her preferences, thereby improving the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0446] By displaying the image captured by the camera device (not shown) installed in the car 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillar can be supplemented. In other words, by displaying the image captured by the camera device installed outside the car 5700, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the image that supplements the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0447] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of the automobile 5700. The chip can also be used in a system for navigation, danger prediction, etc. In addition, information such as navigation and danger prediction can be displayed on the display panels 5701 to 5704.

[0448] Although a car is described as an example of a mobile body in the above example, the mobile body is not limited to a car. For example, a tram, a monorail, a ship, a flying object (a helicopter, an unmanned aircraft (drone), an airplane, a rocket), etc. can also be cited as a mobile body, and a chip of one embodiment of the present invention can be applied to these mobile bodies to provide a system using artificial intelligence.

[0449] [Broadcasting and Television System]

[0450] A GPU or a chip according to one embodiment of the present invention can be applied to a broadcasting television system.

[0451] Fig.19 F schematically illustrates data transmission in a broadcast television system. Specifically, Fig.19 F shows a path for radio waves (broadcast television signals) transmitted from a broadcasting station 5680 to reach a television receiver (TV) 5600 in each household. The TV 5600 is provided with a receiver (not shown), and the broadcast television signals received by the antenna 5650 are input to the TV 5600 via the receiver.

[0452] Although in Fig.19 Although a UHF (Ultra High Frequency) antenna is shown as the antenna 5650 in F, a BS or 110° C. S antenna, a CS antenna, or the like may be used as the antenna 5650 .

[0453] Radio waves 5675A and 5675B are terrestrial broadcast television signals. Radio tower 5670 amplifies received radio waves 5675A and transmits radio waves 5675B. Each household can watch terrestrial TV broadcasts with TV 5600 by receiving radio waves 5675B with antenna 5650. In addition, the broadcast television system may be satellite broadcast television using artificial satellites, data broadcast television using optical lines, etc., and is not limited to Fig.19 Terrestrial broadcast television shown in F.

[0454] In addition, a chip of one embodiment of the present invention can also be applied to the above-mentioned broadcasting and television system to form a broadcasting and television system using artificial intelligence. When broadcasting and television data is sent from a broadcasting and television station 5680 to TV5600 in each household, an encoder is used to compress the broadcasting and television data; when the antenna 5650 receives the broadcasting and television data, a decoder of a receiver included in TV5600 is used to restore the broadcasting and television data. By utilizing artificial intelligence, for example, a display model contained in a displayed image can be identified by a variation compensation prediction of one of the compression methods of the encoder. In addition, intra-frame prediction using artificial intelligence can also be performed. For example, when TV5600 receives low-resolution broadcasting and television data and displays it at a high resolution, supplementary image processing such as up-conversion can be performed in the recovery of the broadcasting and television data performed by the decoder.

[0455] The above-mentioned broadcasting and television system using artificial intelligence is suitable for ultra-high-definition television (UHDTV: 4K, 8K) playback with increased broadcasting and television data volume.

[0456] In addition, as an application of artificial intelligence on the TV 5600 side, for example, a recording device with artificial intelligence can be provided in the TV 5600. By adopting this structure, the recording device with artificial intelligence can learn the user's preferences and automatically record television programs that match the user's preferences.

[0457] The electronic device, the functions of the electronic device, the application examples of artificial intelligence and the effects thereof, and the like described in this embodiment mode can be implemented in combination with the description of other electronic devices as appropriate.

[0458] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0459] [Example 1]

[0460] In this embodiment, an example of processing the insulating layer BGI3 using etching described in Embodiment 1 is described. Specifically, an SEM (Scanning Electron Microscope) observation image of a sample after etching is obtained by plan view.

[0461] The manufactured sample 1D is described below.

[0462] A hafnium oxide film with a film thickness of 10 nm is formed on the first oxynitride silicon film formed on the substrate as an insulating layer BGI2 by an ALD method, a second oxynitride silicon film with a film thickness of 15 nm is formed on the hafnium oxide film as an insulating layer BGI3 by a CVD method, a first In-Ga-Zn oxide with a film thickness of 5 nm is formed on the second oxynitride silicon film as a semiconductor layer to become a semiconductor layer SEM1 by a sputtering method, and a second In-Ga-Zn oxide with a film thickness of 15 nm is formed on the first In-Ga-Zn oxide as a semiconductor layer to become a semiconductor layer SEM2 by a sputtering method.

[0463] Next, a first tantalum nitride film with a thickness of 20 nm is formed on the second In-Ga-Zn oxide as a conductive layer to become the conductive layer SE or the conductive layer DE by a sputtering method, an aluminum oxide film with a thickness of 5 nm is formed on the first tantalum nitride film by an ALD method, and a second tantalum nitride film with a thickness of 15 nm is formed on the aluminum oxide film by a sputtering method.

[0464] Next, the second tantalum nitride film is processed by photolithography to form a hard mask. Then, the second tantalum nitride film, the aluminum oxide film, the first tantalum nitride film, the second In-Ga-Zn oxide, and the first In-Ga-Zn oxide are processed using the hard mask. By performing this processing, the conductive layer SE, the conductive layer DE, the semiconductor layer SEM2, and the semiconductor layer SEM1 are formed.

[0465] Next, oxygen plasma treatment was performed. The oxygen plasma treatment was performed by using a CVD device and the following method: exposure to plasma generated by using 200 sccm of oxygen as a reaction gas, an ICP power of 2000 W, a bias power of 50 W, and a pressure of 0.67 Pa for 10 seconds. Next, etching was performed to process the second silicon oxynitride film and the first tantalum nitride film.

[0466] Through the above-mentioned steps, sample 1D was manufactured.

[0467] Next, a SEM observation image of the sample 1D viewed from above was obtained to confirm the shape of the sample 1D. The SEM observation image was obtained using a scanning transmission electron microscope SU8030 manufactured by Hitachi High-Technologies Corporation, with an acceleration voltage of 5.0 kV.

[0468] Fig. 20 An SEM observation image of sample 1D viewed from above is shown. Fig. 20 This is a SEM image with a magnification of 200,000 times. Fig. 20 As shown, since the surface of the hafnium oxide film as the insulating layer BGI2 is exposed, it can be seen that the second silicon oxynitride film as the insulating layer BGI3 on ​​the hafnium oxide film can be removed.

[0469] At least a part of this embodiment can be implemented in combination with other embodiment modes or examples described in this specification as appropriate.

[0470] [Example 2]

[0471] In this example, a transistor 200A (sample 1E) according to one embodiment of the present invention was manufactured and the shape of the sample 1E was evaluated. A scanning transmission electron microscope (STEM: Scanning Transmission Electron Microscope) was used to evaluate the shape of the sample 1E.

[0472] The following describes sample 1E.

[0473] An aluminum oxide film is used as the insulating layer 214. A silicon oxynitride film is used as the insulating layer 216. A stacked-layer structure of tantalum nitride, titanium nitride, and tungsten is used as the conductive layer 205.

[0474] A 10-nm-thick silicon oxynitride film was used as the insulating layer 220. A 20-nm-thick hafnium oxide film was used as the insulating layer 222. A 30-nm-thick silicon oxynitride film was used as the insulating layer 224.

[0475] As the oxide 230a, a metal oxide having a film thickness of 5 nm formed by a sputtering method using an In-Ga-Zn oxide target material having an In:Ga:Zn=1:3:4 [atomic ratio] was used. Also, as the oxide 230b, a metal oxide having a film thickness of 15 nm formed by a sputtering method using an In-Ga-Zn oxide target material having an In:Ga:Zn=4:2:4.1 [atomic ratio] was used.

[0476] Tantalum nitride is used as the conductive layer 242a and the conductive layer 242b. In addition, an aluminum oxide film is used as a barrier layer on the conductive layer 242.

[0477] As the oxide 230 c , a metal oxide having a film thickness of 5 nm was used which was formed by a sputtering method using an In—Ga—Zn oxide target having an In:Ga:Zn ratio of 4:2:4.1 (atomic number ratio).

[0478] Silicon oxynitride with a thickness of 10 nm was used as the insulating layer 250. Titanium nitride with a thickness of 10 nm was used as the conductive layer 260a. Tungsten with a thickness of 30 nm was used as the conductive layer 260b.

[0479] As the insulating layer 274, an aluminum oxide film is used.

[0480] This is the description of Sample 1E.

[0481] Next, the result of cross-sectional observation of sample 1E is described. As an apparatus for cross-sectional observation, HD-2300 manufactured by Hitachi High-Technologies Corporation was used.

[0482] Fig.21 This is a cross-sectional STEM image of sample 1E in the channel width direction. Fig.21 The dashed line shown indicates the height of the bottom surface of the conductive layer 260a in the region where the oxide 230b does not overlap with the conductive layer 260a. Fig.21 The dashed-dotted line shown indicates the height of the bottom surface of the oxide 230 b .

[0483] from Fig.21 It can be seen that the bottom surface of oxide 230b is located above the bottom surface of conductive layer 260a in the region where oxide 230b does not overlap conductive layer 260a. In addition, when the height of the bottom surface of conductive layer 260a in the region where oxide 230b does not overlap conductive layer 260a is used as a reference, the height of the bottom surface of oxide 230b is 4.0 nm.

[0484] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0485] [Explanation of symbols]

[0486] BGE: conductive layer, BGI1: insulating layer, BGI2: insulating layer, BGI3: insulating layer, DE: conductive layer, SE: conductive layer, SEM1: semiconductor layer, SEM2: semiconductor layer, SEM3: semiconductor layer, TGE: conductive layer, TGI: insulating layer, 200A: transistor, 200B: transistor, 200C: transistor, 200D: transistor, 200E: transistor, 203: conductive layer, 205: conductive layer, 205a: conductive layer, 205b: conductive layer, 210: insulating layer, 212: insulating layer, 214: insulating layer, 216: insulating layer, 220: insulating layer, 222: insulating layer, 224: insulating layer, 230: oxide, 230a: oxide, 230 b: oxide, 230c: oxide, 231: region, 231a: region, 231b: region, 242: conductive layer, 242a: conductive layer, 242b: conductive layer, 244: insulating layer, 245: insulating layer, 246: conductive layer, 246a: conductive layer, 246b: conductive layer, 247: conductive layer, 247a: conductive layer, 247b: conductive layer, 250: insulating layer, 252: metal oxide, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 270: insulating layer, 271: insulating layer, 273: insulating layer, 274: insulating layer, 275: insulating layer, 276: insulating layer, 276a: insulating layer, 276b: insulating layer, 280: insulating layer, 282: insulation layer, 284: insulation layer, 1100: USB memory, 1101: housing, 1102: cover, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: PCB, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: simulation operation unit, 1214: storage controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: storage cell array, 1471: storage cell, 1472: storage cell, 1473: storage cell, 1474: storage cell, 1475: storage cell, 1476: storage cell, 1477: storage cell, 1478: storage cell, 5200: portable game console, 5201: casing,5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display, 5303: keyboard, 5500: information terminal, 5510: casing, 5511: display unit, 5600: TV, 5650: antenna, 5670: radio tower, 5675A: radio wave, 5675B: radio wave, 5680: radio station, 5700: automobile, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: casing, 5802: refrigerator door, 5803: freezer door.

Claims

1. A semiconductor device comprising a transistor, the transistor comprising: a first conductive layer; a first insulating layer on the first conductive layer; a second insulating layer on the first insulating layer; a first oxide on the second insulating layer; a second oxide on the first oxide; a third oxide on the second oxide; a third insulating layer on the third oxide; a second conductive layer on the third insulating layer; as well as The fourth insulating layer, The first conductive layer and the second conductive layer have a region overlapping with the second oxide, The side surface of the second conductive layer, the side surface of the third insulating layer and the side surface of the third oxide are substantially aligned, The fourth insulating layer is in contact with a side surface of the second conductive layer, a side surface of the third insulating layer, and a side surface of the third oxide. Furthermore, in the channel width direction of the transistor, the bottom surface of the second oxide is located below a region of the bottom surface of the second conductive layer that does not overlap with the second oxide and the first oxide, and the height of the bottom surface of the second oxide based on the height of the region of the bottom surface of the second conductive layer that does not overlap with the second oxide and the first oxide is greater than -5nm and less than 0nm.

2. The semiconductor device according to claim 1, wherein a side surface of the second insulating layer is substantially aligned with a side surface of the first oxide and a side surface of the second oxide, and The third oxide contacts a top surface of the second insulating layer.

3. A semiconductor device comprising a transistor, the transistor comprising: a first conductive layer; a first insulating layer on the first conductive layer; a second insulating layer on the first insulating layer; a first oxide on the second insulating layer; a second oxide on the first oxide; a third oxide on the second oxide; a third insulating layer on the third oxide; a second conductive layer on the third insulating layer; a third conductive layer and a fourth conductive layer on the second oxide; a fifth conductive layer on the third conductive layer; and a sixth conductive layer on the fourth conductive layer, The first conductive layer and the second conductive layer have a region overlapping with the second oxide, The fifth conductive layer is in contact with a side surface of the third conductive layer on the side of the second conductive layer and is in contact with a top surface of the second oxide. The sixth conductive layer is in contact with a side surface of the fourth conductive layer on the second conductive layer side and is in contact with a top surface of the second oxide. Furthermore, in the channel width direction of the transistor, the bottom surface of the second oxide is located below a first region of the bottom surface of the second conductive layer that does not overlap with the second oxide and the first oxide, and the height of the bottom surface of the second oxide when based on the height of the first region of the bottom surface of the second conductive layer that does not overlap with the second oxide and the first oxide is greater than -5nm and less than 0nm.

4. The semiconductor device according to claim 3, In the cross section of the transistor in the channel length direction, when the height of the bottom surface of the first insulating layer is taken as a reference, the height of the bottom surface of the second conductive layer in the second region overlapping with the second oxide is less than or equal to the height of the top surface of the third conductive layer.

5. The semiconductor device according to claim 3, wherein a side surface of the second insulating layer is substantially aligned with a side surface of the first oxide and a side surface of the second oxide, and The third oxide contacts a top surface of the first insulating layer.

6. The semiconductor device according to claim 1 or 3, When the height of the bottom surface of the first insulating layer is used as a reference, the height of the top surface of the second insulating layer in the first region overlapping with the second oxide is higher than the height of the top surface of the second insulating layer in the second region not overlapping with the second oxide.

7. A semiconductor device comprising a transistor, the transistor comprising: a first gate electrode; a first insulating layer on the first gate electrode; a second insulating layer on the first insulating layer; a first oxide semiconductor layer on the second insulating layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a third insulating layer on the third oxide semiconductor layer; as well as a second gate electrode on the third insulating layer, In the channel width direction of the transistor, the bottom surface of the second oxide semiconductor layer is located below the area of ​​the bottom surface of the second gate electrode that does not overlap with the second oxide semiconductor layer and the first oxide semiconductor layer, and the height of the bottom surface of the second oxide semiconductor layer when based on the height of the area of ​​the bottom surface of the second gate electrode that does not overlap with the second oxide semiconductor layer and the first oxide semiconductor layer is greater than -5nm and less than 0nm.

8. The semiconductor device according to claim 7, wherein a side surface of the second insulating layer is substantially aligned with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer, and The third oxide semiconductor layer is in contact with a top surface of the second insulating layer.

9. The semiconductor device according to claim 7, When the height of the bottom surface of the first insulating layer is taken as a reference, the height of the first region of the top surface of the second insulating layer is higher than the height of the second region of the top surface of the second insulating layer, and A first region of a top surface of the second insulating layer overlaps with the second oxide semiconductor layer, and a second region of a top surface of the second insulating layer does not overlap with the second oxide semiconductor layer.

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