Electrostatic protection structure

Abstract

An electrostatic protection structure comprises: a plurality of voltage domain circuits, each of the voltage domain circuits at least comprising a ground level bus; a conduction circuit connecting the ground level buses of adjacent voltage domain circuits, the conduction circuit at least comprising a control end, the control end being used to control the conduction circuit to establish a path between the adjacent ground level buses when a potential difference between the adjacent ground level buses is detected, thereby being able to timely reduce the potential difference on the ground level buses, avoiding failure of the clamping circuit or excessive reaction time caused by excessive potential of the floating ground level bus, thereby improving the protection performance of the electrostatic protection structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to an electrostatic protection structure. Background Art

[0002] In integrated circuits (ICs), the impact of electrostatic discharge (ESD) on chip reliability cannot be ignored, especially in today's era of widespread application of deep submicron and nanotechnology. The destructive impact of electrostatic discharge from the external environment, human body, machinery, radiation field, etc. on ICs is more significant. The industry has done a lot of research and practice on ESD protection during the design and manufacturing process of ICs.

[0003] In the production and application of integrated circuit chips, with the continuous improvement of ultra-large-scale integrated circuit process technology, the current CMOS integrated circuit production technology has entered the deep submicron and nanometer stages, the size of MOS devices has been continuously reduced, the thickness of the gate oxide layer has become thinner and thinner, the voltage resistance of MOS devices has been continuously reduced, and the harm of electrostatic discharge to integrated circuits has become more and more significant. Therefore, ESD protection of integrated circuits has become particularly important.

[0004] When designing a large SOC chip with multiple voltage domains and multi-function modules, global ESD protection is required for the chip. The most common approach is to isolate the power lines of each different voltage domain, and connect adjacent ground lines with one or more back-to-back diodes to discharge ESD current. This structure is usually designed together with the I / O library and is called a power cut cell.

[0005] However, the protection performance of the global ESD protection of the chip using the power cut cell method still needs to be improved. Summary of the invention

[0006] The problem solved by the invention is to provide an electrostatic protection structure to improve the electrostatic protection performance of a device.

[0007] To solve the above problems, the present invention provides an electrostatic protection structure, comprising: a plurality of voltage domain circuits, each of the voltage domain circuits comprising at least a ground level bus; a conduction circuit connecting the ground level buses of adjacent voltage domain circuits, the conduction circuit comprising at least a control end, and the control end controls the conduction circuit to establish a path between the adjacent ground level buses when detecting the potential difference between the adjacent ground level buses.

[0008] Preferably, the adjacent ground level buses include a first ground level bus and a second ground level bus;

[0009] The conduction circuit includes a first conduction unit and a second conduction unit, wherein the first conduction unit is used to establish a path from the first ground level bus to the second ground level bus, and the second conduction unit is used to establish a path from the second ground level bus to the first ground level bus.

[0010] Preferably, both the first conduction unit and the second conduction unit are MOS devices.

[0011] Preferably, the control end includes a first control end located at the first conduction unit and a second control end located at the second conduction unit;

[0012] The first conduction unit is a first PMOS transistor, the gate and source of the first PMOS transistor are connected to the second ground level bus, and the drain is connected to the first ground level bus, wherein the gate of the first PMOS transistor serves as the first control terminal;

[0013] The second conduction unit is a second PMOS transistor, a gate and a source of the second PMOS transistor are connected to the first ground level bus, and a drain is connected to the second ground level bus, wherein the gate of the second PMOS transistor serves as the second control terminal.

[0014] Preferably, the first PMOS transistor is located on a semiconductor substrate and comprises:

[0015] a first n-well region located in the semiconductor substrate;

[0016] a first PMOS device unit and a first n-type doping region located in the first n-well region;

[0017] The first PMOS device unit includes a gate located on the first n-type well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region;

[0018] The first n-type doping region is located at one side of the source region of the first PMOS device unit, the first n-type doping region and the drain region of the first PMOS device form a parasitic diode, and the first n-type doping region is connected to the source of the first PMOS device.

[0019] Preferably, the second PMOS transistor and the first PMOS transistor are located on the same semiconductor substrate, comprising:

[0020] a second n-well region located in the semiconductor substrate;

[0021] a second PMOS device unit and a second n-type doping region located in the second n-well region;

[0022] The second PMOS device unit includes a gate located on the second n-type well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region;

[0023] The second n-type doped region is located at one side of the source region of the second PMOS device unit, the second n-type doped region and the drain region of the second PMOS device form a parasitic diode, and the second n-type doped region is connected to the source of the second PMOS device.

[0024] Preferably, the number of the first PMOS device units in the first PMOS transistor is multiple, and the multiple first PMOS device unit arrays are arranged in the first n-well region; the number of the second PMOS device units in the second PMOS transistor is multiple, and the multiple second PMOS device unit arrays are arranged in the second n-well region.

[0025] Preferably, the ground level bus includes a plurality of ground level branch lines, and one ground level branch line is connected to a row of the first PMOS device units and / or the second PMOS device units.

[0026] Preferably, the first conduction unit is a first NMOS transistor, the gate and source of the first NMOS transistor are connected to the first ground level bus, and the drain is connected to the second ground level bus, wherein the gate of the first NMOS transistor serves as the first control terminal;

[0027] The second conduction unit is a second NMOS transistor, the gate and source of the second NMOS transistor are connected to the second ground level bus, and the drain is connected to the first ground level bus, wherein the gate of the second NMOS transistor serves as a second control terminal.

[0028] Preferably, the first NMOS transistor is located on a semiconductor substrate and comprises:

[0029] a first p-well region located in the semiconductor substrate, wherein a first isolation layer is provided between the first p-well region and the semiconductor substrate;

[0030] a first NMOS device unit and a first p-type doped region located in the first p-well region;

[0031] The first NMOS device unit includes a gate located on the first p-type well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region;

[0032] The first p-type doped region is located at one side of the source region of the first NMOS device unit, the first p-type doped region and the drain region of the first NMOS device form a parasitic diode, and the first p-type doped region is connected to the source of the first NMOS device.

[0033] Preferably, the second NMOS transistor and the first NMOS transistor are located on the same semiconductor substrate, comprising:

[0034] a second p-well region located in the semiconductor substrate, wherein a second isolation layer is provided between the second p-well region and the semiconductor substrate;

[0035] a second NMOS device unit and a second p-type doped region located in the second p-well region;

[0036] The second NMOS device unit includes a gate located on the second p-type well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region;

[0037] The second p-type doped region is located at one side of the source region of the second NMOS device unit, the second p-type doped region and the drain region of the second NMOS device form a parasitic diode, and the second p-type doped region is connected to the source of the second NMOS device.

[0038] Preferably, the number of the first NMOS device units in the first NMOS transistor is multiple, and the multiple first NMOS device units are arrayed in the first p-well region; the number of the second NMOS device units in the second NMOS transistor is multiple, and the multiple second NMOS device units are arrayed in the second p-well region.

[0039] Preferably, the ground level bus includes a plurality of ground level branch lines, and one ground level branch line is connected to a row of the first NMOS device units and / or the second NMOS device units.

[0040] Preferably, the voltage domain circuit includes a power bus and a clamping circuit connecting the power bus and the ground level bus.

[0041] Preferably, the voltage domain circuit further includes a voltage domain working circuit, and the voltage domain working circuit is powered by the power bus.

[0042] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0043] In an embodiment of the present invention, a conduction circuit is arranged between adjacent voltage domain circuits, and the conduction circuit includes at least a control end, and the control end is used to establish a path between the adjacent ground level buses when the potential difference of the adjacent ground level buses is detected, so that the potential difference on the ground level buses can be reduced in time, and the failure of the clamping circuit or the long reaction time caused by the excessive potential of the floating ground level bus can be avoided, thereby improving the protection performance of the electrostatic protection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a chip global ESD protection for a power cut cell;

[0045] Figure 2 A schematic diagram of the structure of an electrostatic protection structure according to an embodiment of the present invention;

[0046] Figure 3 It is a schematic diagram of the structure of a voltage domain circuit according to an embodiment of the present invention;

[0047] Figure 4 It is a schematic diagram of the structure of the conducting circuit according to an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the circuit structure of a conducting circuit according to an embodiment of the present invention;

[0049] Figure 6 A structural diagram of a first PMOS transistor and a second PMOS transistor according to an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the connection between the ground level splitter and the PMOS device unit according to an embodiment of the present invention;

[0051] Figure 8 for Figure 1 The performance parameter diagram of the ESD protection structure shown in FIG. 1 when discharging ESD current;

[0052] Fig. 9 is a performance parameter diagram of an embodiment of the present invention when discharging ESD current;

[0053] Fig.10 A schematic diagram of the circuit structure of a conducting circuit according to another embodiment of the present invention;

[0054] Fig.11 A structural diagram of a first NMOS transistor and a second NMOS transistor according to another embodiment of the present invention;

[0055] Fig.12 A schematic diagram of the connection between a ground level splitter and an NMOS device unit according to another embodiment of the present invention;

[0056] Fig.13Schematic diagram of the structure of a clamping circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] As can be seen from the background technology, the existing electrostatic protection structure has poor protection performance. Now, in combination with an electrostatic protection structure, the reasons why the protection performance of the electrostatic protection structure needs to be improved are analyzed.

[0058] refer to Figure 1 , is a chip global ESD protection for a power cut cell, comprising a voltage domain circuit (Domain) 11 and a voltage domain circuit 12, wherein the voltage domain circuit 11 comprises a power bus VDD1, a ground level bus VSS1, and a first clamp circuit (Clamp) 13 and a first inner working circuit (Inner Circuits) 14 connected between the power bus VDD1 and the ground level bus VSS1; the voltage domain circuit 12 comprises a power bus VDD2, a ground level bus VSS2, a second clamp circuit 15 and a second inner working circuit 16 connected between the power bus VDD2 and the ground level bus VSS2. The ground level bus VSS2 is connected to a ground voltage power supply, and between the voltage domain circuit 11 and the voltage domain circuit 12, a conduction circuit 17 with a multi-stage back-to-back diode connection is provided.

[0059] It can be seen that in this structure of ESD protection, not all ground level buses are grounded. The floating ground level bus VSS1 needs to use the ground level bus VSS2 of the ground voltage power supply to discharge the ESD current, that is, Figure 1 The discharge path A is shown by the dotted arrow in the figure. However, since the diode has a certain on-resistance, the floating ground level bus VSS1 has a large potential difference during ESD transients. If the potential difference reaches a certain level, it is easy to cause the clamping circuit connecting these ground level buses to fail or react too long, causing the ESD current to be released through the internal working circuit between the voltage domains, that is, Figure 1 The discharge path B is shown by the dotted arrow, which causes damage to the internal working circuit.

[0060] In large SOC chips with multiple voltage domains and multi-function modules, there are more voltage domains and corresponding cascade diodes, which can more easily cause the potential of the floating ground level bus to be too large, causing the clamping circuits connecting these ground level buses to fail or take too long to react, ultimately causing the ESD current to be released through the internal working circuits between the voltage domains, causing damage to the internal working circuits.

[0061] In order to solve the technical problem, an embodiment of the present invention provides an electrostatic protection structure, including: multiple voltage domain circuits, each of the voltage domain circuits includes at least a ground level bus; a conduction circuit connecting the ground level buses of adjacent voltage domain circuits, the conduction circuit includes at least a control end, and the control end is used to establish a path between the adjacent ground level buses when the potential difference between the adjacent ground level buses is detected.

[0062] In an embodiment of the present invention, a conduction circuit is arranged between adjacent voltage domain circuits, and the conduction circuit includes at least a control end, and the control end is used to establish a path between the adjacent ground level buses when the potential difference of the adjacent ground level buses is detected, so that the potential difference on the ground level buses can be reduced in time, and the failure of the clamping circuit or the long reaction time caused by the excessive potential of the floating ground level bus can be avoided, thereby improving the protection performance of the electrostatic protection structure.

[0063] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0064] refer to Figure 2 , is a schematic structural diagram of an electrostatic protection structure according to an embodiment of the present invention, the electrostatic protection structure comprising: a plurality of voltage domain circuits 1 (only two are shown in the figure), each of the voltage domain circuits comprising at least a ground level bus 2; a conduction circuit 3 connecting the ground level buses of adjacent voltage domain circuits, the conduction circuit comprising at least a control end, and the control end controls the conduction circuit 2 to establish a path between the adjacent ground level buses when detecting a potential difference between adjacent ground level buses.

[0065] The voltage domain circuit 1 is a circuit for realizing a specific function, wherein the multiple voltage domain circuits may be multiple circuits for realizing the same function or multiple circuits for realizing different functions. Figure 3 , is a schematic diagram of the structure of the voltage domain circuit of an embodiment of the present invention, each voltage domain circuit 1 is provided with a ground level bus 2, a power bus 5, a clamping circuit 6 connecting the power bus 5 and the ground level bus 2, and a voltage domain working circuit 7 powered by the power bus 5.

[0066] The clamp circuit 6 is used to discharge the ESD current of the voltage domain circuit 1 to the ground level bus 2, and the voltage domain working circuit 7 is used to implement the corresponding function. Among the multiple voltage domain circuits, the ground level bus in at least one voltage domain circuit is grounded to discharge the ESD current in the corresponding voltage domain circuit.

[0067] Combined with reference Figure 2, the ground level buses 2 of the adjacent voltage domain circuits are connected through the conduction circuit 3. In this embodiment, the conduction circuit 3 at least includes a control end, and when the control end detects the potential difference of the adjacent ground level buses, the conduction circuit 3 is controlled to establish a path between the adjacent ground level buses, thereby timely and effectively reducing the potential difference on the ground level buses, avoiding the failure of the clamping circuit or the long reaction time caused by the excessive potential of the floating ground level bus, and improving the protection performance of the electrostatic protection structure.

[0068] Specifically, refer to Figure 4 , is a schematic diagram of the structure of the conduction circuit according to an embodiment of the present invention, wherein the adjacent ground level buses include a first ground level bus and a second ground level bus, specifically, one of the adjacent ground level buses is the first ground level bus VSS1, and the other of the adjacent ground level buses is the second ground level bus VSS2; the conduction circuit 3 includes a first conduction unit 31 and a second conduction unit 32, the control end includes a first control end 41 located at the first conduction unit 31 and a second control end 42 located at the second conduction unit 32, the first control end 41 is used to control the first conduction unit 31 to establish a path from the first ground level bus VSS1 to the second ground level bus VSS2, and the second control end 42 is used to control the second conduction unit 32 to establish a path from the second ground level bus VSS2 to the first ground level bus VSS1.

[0069] Among them, in the ground level bus, the direction of the potential difference between adjacent ground level buses is uncertain. Taking the potential difference that makes the current flow from the first ground level bus VSS1 to the second ground level bus VSS2 as a positive potential difference and the potential difference that makes the current flow from the second ground level bus VSS2 to the first ground level bus VSS1 as a negative potential difference as an example, the potential difference between adjacent ground level buses may be a positive potential difference or a negative potential difference. Therefore, the conduction circuit in this embodiment includes a first conduction unit 31 that establishes a path from the first ground level bus VSS1 to the second ground level bus VSS2 and a second conduction unit 32 that establishes a path from the second ground level bus VSS2 to the first ground level bus VSS1. According to different directions of the potential difference, the control of the first conduction unit 31 and the second conduction unit 32 is realized.

[0070] Specifically, when the first control terminal 41 detects a positive potential difference, the first conduction unit 31 is controlled to establish a path from the first ground level bus VSS1 to the second ground level bus VSS2. When the second control terminal 42 detects a negative potential difference, the second conduction unit 32 is controlled to establish a path from the second ground level bus VSS2 to the first ground level bus VSS1.

[0071] In an optional example, the first conduction unit 31 and the second conduction unit 32 are MOS devices. Since MOS devices can be turned on quickly during ESD transients and have very small on-resistance (close to 0), the potential on the ground level bus can be reduced in time.

[0072] refer to Figure 5 , is a schematic diagram of the circuit structure of the conduction circuit according to an embodiment of the present invention, wherein the first conduction unit 31 is a first PMOS transistor P1, the gate of the first PMOS transistor P1 serves as the first control terminal 41, the source of which is connected to the second ground level bus VSS2, and the drain of which is connected to the first ground level bus VSS1; the second conduction unit 32 is a second PMOS transistor P2, the gate of the second PMOS transistor P2 serves as the second control terminal 42, the source of which is connected to the first ground level bus VSS1, and the drain of which is connected to the second ground level bus VSS2.

[0073] Among them, the gate of the first PMOS transistor P1 serves as the first control terminal 41. When a positive potential difference is detected, the first PMOS transistor P1 is turned on, thereby establishing a path from the first ground level bus VSS1 to the second ground level bus VSS2, so that the potential on the first ground level bus VSS1 is rapidly reduced, thereby avoiding failure of the clamping circuit in the voltage domain circuit where the first ground level bus VSS1 is located or a long reaction time due to the excessive potential of the first ground level bus VSS1, thereby improving the protection performance of the electrostatic protection structure.

[0074] Correspondingly, the gate of the second PMOS transistor P2 serves as the second control terminal 42. When a negative potential difference is detected, the second PMOS transistor P2 is turned on, thereby establishing a path from the second ground level bus VSS2 to the first ground level bus VSS1, so that the potential on the second ground level bus VSS2 is rapidly reduced, thereby avoiding failure of the clamping circuit in the voltage domain circuit where the second ground level bus VSS2 is located or a long reaction time due to the excessive potential of the second ground level bus VSS2, thereby improving the protection performance of the electrostatic protection structure.

[0075] refer to Figure 6 , is a structural diagram of a first PMOS transistor and a second PMOS transistor in an embodiment of the present invention, wherein the first PMOS transistor is located on a semiconductor substrate 100 .

[0076] Specifically, the first PMOS transistor includes: a first n-well region 110 located in the semiconductor substrate; a first PMOS device unit 120 and a first n-type doping region 130 located in the first n-well region 110; the first PMOS device unit 120 includes a gate 121 located on the first n-well region 110, a source region 122 and a drain region 123 located on both sides of the gate, and a source electrode 124 connected to the source region 122 and a drain electrode 125 connected to the drain region 123; the first n-type doping region 130 is located on one side of the source region 122 of the first PMOS device unit 120, the first n-type doping region 130 and the drain region 123 of the first PMOS device form a parasitic diode, and the first n-type doping region 130 is connected to the source electrode 124 of the first PMOS device.

[0077] Among them, the parasitic diode formed by the first n-type doped region 130 and the drain region 123 of the first PMOS device can utilize the MOS channel and the parasitic diode to work simultaneously, quickly reduce the potential difference between different ground lines, and thus reduce the risk of cross-region ESD protection.

[0078] In this embodiment, the second PMOS transistor and the first PMOS transistor are located on the same semiconductor substrate.

[0079] Specifically, the second PMOS transistor includes: a second n-well region 210 located in the semiconductor substrate; a second PMOS device unit 220 and a second n-type doping region 230 located in the second n-well region 210; the second PMOS device unit 220 includes a gate 221 located on the second n-well region 210, a source region 222 and a drain region 223 located on both sides of the gate, and a source 224 connected to the source region 222 and a drain 225 connected to the drain region 223; the second n-type doping region 230 is located on one side of the source region 222 of the second PMOS device unit 220, the second n-type doping region 230 and the drain region 223 of the second PMOS device form a parasitic diode, and the second n-type doping region 230 is connected to the source 224 of the second PMOS device.

[0080] Similarly, the parasitic diode formed by the second n-type doped region 230 and the drain region 223 of the second PMOS device can utilize the MOS channel and the parasitic diode to work simultaneously to quickly reduce the potential difference between different ground lines, thereby reducing the risk of cross-region ESD protection.

[0081] In this embodiment, the number of the first PMOS device units in the first PMOS transistor is multiple, and the multiple first PMOS device unit arrays are arranged in the first n-well region; the number of the second PMOS device units in the second PMOS transistor is multiple, and the multiple second PMOS device unit arrays are arranged in the second n-well region.

[0082] The first PMOS device unit and the second PMOS device unit arranged in an array increase the perimeter of the parasitic diode of the MOS tube per unit area, which can further increase the effective perimeter of the ESD path and improve the discharge capacity of the device ESD current. In addition, since the perimeter of the MOS tube active area is increased, the drain control capability of the MOS tube is improved.

[0083] In this embodiment, the ground level bus includes a plurality of ground level branch lines, and one ground level branch line is connected to a row of the first PMOS device units and / or the second PMOS device units.

[0084] refer to Figure 7 , is a schematic diagram of the connection between the ground level branch line and the PMOS device unit in an embodiment of the present invention. The figure takes the first PMOS transistor including 6 first PMOS device units 120 as an example to schematically illustrate the connection relationship between the ground level branch line and the first PMOS device unit 120 in the first PMOS transistor. Specifically, the first ground level bus includes a plurality of first ground level branch lines VSS11, the second ground level bus includes a plurality of first ground level branch lines VSS21, one first ground level branch line VSS11 is connected to the drain of a row of first PMOS device units 120 (not shown in the figure), and one second ground level branch line VSS21 is connected to the source and gate of a row of first PMOS device units 120 (not shown in the figure) and the first n-type doping region 130.

[0085] Wherein, the first PMOS transistor and the second PMOS transistor can be made on one chip, and the first PMOS transistor and the second PMOS transistor can be arranged horizontally or vertically on the chip. When the first PMOS transistor and the second PMOS transistor are arranged horizontally, the contact points corresponding to the transistors can be arranged in a coordinated manner so that a row of ground level branch lines can simultaneously connect the first PMOS transistor and the second PMOS transistor. When the first PMOS transistor and the second PMOS transistor are arranged vertically, a ground level branch line can only connect a row of first PMOS device units or only connect a row of second PMOS device units, thereby simplifying the device structure and reducing the process cost of the device.

[0086] refer to Figure 8 and Fig. 9 , Figure 8 for Figure 1The performance parameter diagram of the ESD protection structure when discharging ESD current is shown. Fig. 9 : is a performance parameter diagram of this embodiment when discharging ESD current. Wherein, Vesd is the ESD voltage, Vss1 is the potential on the first ground level bus, Icmp is the ESD current discharged by the clamping circuit, and Ic is the total ESD current discharged by the clamping circuit.

[0087] It can be seen that, when the electrostatic protection structure in this embodiment discharges the ESD current, the potential on the floating ground level bus Vss1 is 1.1V, which is much smaller than Figure 1 The 2.0V in the structure, the ESD current Icmp discharged by the clamp circuit is 1.6A, which is much larger than Figure 1 54.7mA in the structure. Obviously, the electrostatic protection structure in this embodiment can effectively reduce the potential of the floating ground level bus, avoid the failure of the clamping circuit or the long reaction time caused by the excessive potential of the floating ground level bus, thereby improving the protection performance of the electrostatic protection structure.

[0088] Optional, reference Fig.10 , is a schematic diagram of the circuit structure of a conduction circuit according to another embodiment of the present invention; the first conduction unit 31 is a first NMOS transistor N1, the gate of the first NMOS transistor N1 serves as the first control terminal 41, the source is connected to the first ground level bus VSS1, and the drain is connected to the second ground level bus VSS2;

[0089] The second conduction unit 32 is a second NMOS transistor N2 , the gate of the second NMOS transistor N2 serves as the second control terminal 42 , the source is connected to the second ground level bus VSS2 , and the drain is connected to the first ground level bus VSS1 .

[0090] Among them, the gate of the first NMOS transistor N1 serves as the first control terminal 41. When a positive potential difference is detected, the first NMOS transistor N1 is turned on, thereby establishing a path from the first ground level bus VSS1 to the second ground level bus VSS2, so that the potential on the first ground level bus VSS1 is rapidly reduced, thereby avoiding failure of the clamping circuit in the voltage domain circuit where the first ground level bus VSS1 is located or a long reaction time due to the excessive potential of the first ground level bus VSS1, thereby improving the protection performance of the electrostatic protection structure.

[0091] Correspondingly, the gate of the second NMOS transistor N2 serves as the second control terminal 42. When a negative potential difference is detected, the second NMOS transistor N2 is turned on, thereby establishing a path from the second ground level bus VSS2 to the first ground level bus VSS1, so that the potential on the second ground level bus VSS2 is rapidly reduced, thereby avoiding failure of the clamping circuit in the voltage domain circuit where the second ground level bus VSS2 is located or a long reaction time due to the excessive potential of the second ground level bus VSS2, thereby improving the protection performance of the electrostatic protection structure.

[0092] refer to Fig.11 , shows a structural diagram of a first NMOS transistor and a second NMOS transistor in this embodiment, where the first NMOS transistor is located on a semiconductor substrate 200 .

[0093] Specifically, the first NMOS transistor includes: a first p-well region 310 located in the semiconductor substrate, with a first isolation layer 340 between the first p-well region and the semiconductor substrate; a first NMOS device unit 320 and a first p-type doping region 330 located in the first p-well region 310; the first NMOS device unit 320 includes a gate 321 located on the first p-well region 310, a source region 322 and a drain region 323 located on both sides of the gate, and a source 324 connected to the source region 322 and a drain 325 connected to the drain region 323; the first p-type doping region 330 is located on one side of the source region 322 of the first NMOS device unit 320, the first p-type doping region 330 and the drain region 323 of the first NMOS device form a parasitic diode, and the first p-type doping region 330 is connected to the source 324 of the first NMOS device.

[0094] Among them, the parasitic diode formed by the first p-type doped region 330 and the drain region 323 of the first NMOS device can utilize the MOS channel and the parasitic diode to work simultaneously, quickly reduce the potential difference between different ground lines, and thus reduce the risk of cross-region ESD protection.

[0095] In this embodiment, the second NMOS transistor and the first NMOS transistor are located on the same semiconductor substrate.

[0096] Specifically, the second NMOS transistor includes: a second p-well region 410 located in the semiconductor substrate, with a second isolation layer 440 between the second p-well region and the semiconductor substrate; a second NMOS device unit 420 and a second p-type doped region 430 located in the second p-well region 410; the second NMOS device unit 420 includes a gate 421 located on the second p-well region 410 and a source region 422 and a drain region 423 located on both sides of the gate, as well as a source 424 connected to the source region 422 and a drain 425 connected to the drain region 423; the second p-type doped region 430 is located on one side of the source region 422 of the second NMOS device unit 420, the second p-type doped region 430 and the drain region 423 of the second NMOS device form a parasitic diode, and the second p-type doped region 430 is connected to the source 424 of the second NMOS device.

[0097] Similarly, the parasitic diode formed by the second p-type doped region 430 and the drain region 423 of the second NMOS device can utilize the MOS channel and the parasitic diode to work simultaneously to quickly reduce the potential difference between different ground lines, thereby reducing the risk of cross-region ESD protection.

[0098] In this embodiment, the number of the first NMOS device units in the first NMOS transistor is multiple, and the multiple first NMOS device units are arrayed in the first p-well region; the number of the second NMOS device units in the second NMOS transistor is multiple, and the multiple second NMOS device units are arrayed in the second p-well region.

[0099] Among them, the first NMOS device unit and the second NMOS device unit arranged in an array increase the perimeter of the parasitic diode of the MOS tube per unit area, which can further effectively pass the ESD current and improve ESD protection. In addition, since the perimeter of the active area of ​​the MOS tube is increased, the effective perimeter of the ESD current discharge is effectively increased, and the discharge capacity of the device ESD current is improved.

[0100] In this embodiment, the ground level bus includes a plurality of ground level branch lines, and one ground level branch line is connected to a row of the first NMOS device units and / or the second NMOS device units.

[0101] refer to Fig.12, is a schematic diagram of the connection between the ground level branch line and the NMOS device unit in an embodiment of the present invention. The first ground level bus includes a plurality of first ground level branch lines VSS11, the second ground level bus includes a plurality of first ground level branch lines VSS21, one first ground level branch line VSS11 is connected to the drain of a row of first PMOS device units 120 (not shown in the figure), and one second ground level branch line VSS21 is connected to the source and gate of a row of first PMOS device units 120 (not shown in the figure).

[0102] The first NMOS transistor and the second NMOS transistor can be arranged horizontally or vertically. When the first NMOS transistor and the second NMOS transistor are arranged horizontally, the contact points corresponding to the transistors can be arranged in a coordinated manner so that a row of ground level branch lines simultaneously connects the first NMOS transistor and the second NMOS transistor. When the first NMOS transistor and the second NMOS transistor are arranged vertically, one ground level branch line connects a row of first NMOS device units or second NMOS device units, thereby simplifying the device structure and reducing the process cost of the device.

[0103] In an alternative example, refer to Fig.13 , is a schematic diagram of a structure of a clamping circuit in an embodiment of the present invention, and the clamping circuit structure can be set in any voltage domain circuit among multiple voltage domain circuits. Specifically, the clamping circuit includes: a first resistor R1, a first capacitor C1, a third PMOS transistor P3, a third NMOS transistor N3 and a fourth NMOS transistor N4;

[0104] Among them, one end of the first resistor R1 is connected to the power bus VDD, and the other end is connected to the first capacitor C1, and the first capacitor C1 is connected to the ground level bus VSS; the source of the third PMOS transistor P3 is connected to the power bus VDD, the drain is connected to the drain of the third NMOS transistor N3, and the gate is connected to the gate of the third NMOS transistor N3 and the other end of the first resistor R1; the source of the third NMOS transistor N3 is connected to the first ground level bus VSS; the source of the fourth NMOS transistor N4 is connected to the power bus VDD, the drain is connected to the first ground level bus VSS, and the gate is connected to the other end of the first resistor R1.

[0105] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An electrostatic protection structure, characterized in that: include: a plurality of voltage domain circuits, each of the voltage domain circuits comprising at least a ground level bus; A conduction circuit connecting adjacent ground level buses, the conduction circuit at least comprising a control end, and the control end controls the conduction circuit to establish a path between the adjacent ground level buses when detecting a potential difference between the adjacent ground level buses; The adjacent ground level buses include a first ground level bus and a second ground level bus, the conduction circuit includes a first conduction unit and a second conduction unit, the first conduction unit is used to establish a path from the first ground level bus to the second ground level bus, and the second conduction unit is used to establish a path from the second ground level bus to the first ground level bus; The first conduction unit and the second conduction unit are both MOS devices; The MOS devices of the first conduction unit and the second conduction unit both include parasitic diodes, and the channels of the MOS devices and the parasitic diodes work simultaneously to reduce the potential difference of buses with different ground levels.

2. The electrostatic protection structure according to claim 1, characterized in that: The control end includes a first control end located at the first conduction unit and a second control end located at the second conduction unit; The first conduction unit is a first PMOS transistor, the gate and source of the first PMOS transistor are connected to the second ground level bus, and the drain is connected to the first ground level bus, wherein the gate of the first PMOS transistor serves as the first control terminal; The second conduction unit is a second PMOS transistor, a gate and a source of the second PMOS transistor are connected to the first ground level bus, and a drain is connected to the second ground level bus, wherein the gate of the second PMOS transistor serves as the second control terminal.

3. The electrostatic protection structure according to claim 2, characterized in that: The first PMOS transistor is located on a semiconductor substrate and includes: a first n-well region located in the semiconductor substrate; a first PMOS device unit and a first n-type doping region located in the first n-well region; The first PMOS device unit includes a gate located on the first n-well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region; The first n-type doping region is located at one side of the source region of the first PMOS device unit, the first n-type doping region and the drain region of the first PMOS device form a parasitic diode, and the first n-type doping region is connected to the source of the first PMOS device.

4. The electrostatic protection structure according to claim 3, characterized in that: The second PMOS transistor and the first PMOS transistor are located on the same semiconductor substrate, comprising: a second n-well region located in the semiconductor substrate; a second PMOS device unit and a second n-type doping region located in the second n-well region; The second PMOS device unit includes a gate located on the second n-well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region; The second n-type doped region is located at one side of the source region of the second PMOS device unit, the second n-type doped region and the drain region of the second PMOS device form a parasitic diode, and the second n-type doped region is connected to the source of the second PMOS device.

5. The electrostatic protection structure according to claim 4, characterized in that: The number of the first PMOS device units in the first PMOS transistor is multiple, and the multiple first PMOS device unit arrays are arranged in the first n-well region; the number of the second PMOS device units in the second PMOS transistor is multiple, and the multiple second PMOS device unit arrays are arranged in the second n-well region.

6. The electrostatic protection structure according to claim 5, characterized in that: The ground level bus includes a plurality of ground level branch lines, and one ground level branch line is connected to a row of the first PMOS device units and / or the second PMOS device units.

7. The electrostatic protection structure according to claim 1, wherein: The first conduction unit is a first NMOS transistor, the gate and source of the first NMOS transistor are connected to the first ground level bus, and the drain is connected to the second ground level bus, wherein the gate of the first NMOS transistor serves as a first control terminal; The second conduction unit is a second NMOS transistor, the gate and source of the second NMOS transistor are connected to the second ground level bus, and the drain is connected to the first ground level bus, wherein the gate of the second NMOS transistor serves as a second control terminal.

8. The electrostatic protection structure according to claim 7, characterized in that: The first NMOS transistor is located on a semiconductor substrate and includes: a first p-well region located in the semiconductor substrate, wherein a first isolation layer is provided between the first p-well region and the semiconductor substrate; a first NMOS device unit and a first p-type doped region located in the first p-well region; The first NMOS device unit includes a gate located on the first p-well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region; The first p-type doped region is located at one side of the source region of the first NMOS device unit, the first p-type doped region and the drain region of the first NMOS device form a parasitic diode, and the first p-type doped region is connected to the source of the first NMOS device.

9. The electrostatic protection structure according to claim 8, characterized in that: The second NMOS transistor and the first NMOS transistor are located on the same semiconductor substrate, comprising: a second p-well region located in the semiconductor substrate, wherein a second isolation layer is provided between the second p-well region and the semiconductor substrate; a second NMOS device unit and a second p-type doped region located in the second p-well region; The second NMOS device unit includes a gate located on the second p-well region, a source region and a drain region located on both sides of the gate, and a source electrode connected to the source region and a drain electrode connected to the drain region; The second p-type doped region is located at one side of the source region of the second NMOS device unit, the second p-type doped region and the drain region of the second NMOS device form a parasitic diode, and the second p-type doped region is connected to the source of the second NMOS device.

10. The electrostatic protection structure according to claim 9, characterized in that: The number of the first NMOS device units in the first NMOS transistor is multiple, and the multiple first NMOS device units are arrayed in the first p-well region; the number of the second NMOS device units in the second NMOS transistor is multiple, and the multiple second NMOS device units are arrayed in the second p-well region.

11. The electrostatic protection structure according to claim 10, characterized in that: The ground level bus includes a plurality of ground level branch lines, and one ground level branch line connects a row of the first NMOS device units and / or the second NMOS device units.

12. The electrostatic protection structure according to claim 1, characterized in that: The voltage domain circuit includes a power bus and a clamping circuit connecting the power bus and the ground level bus.

13. The electrostatic protection structure according to claim 12, characterized in that: The voltage domain circuit further includes a voltage domain working circuit, and the voltage domain working circuit is powered by the power bus.

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