Heterogeneous many-core data reuse method

A data and heterogeneous technology, applied in the direction of program code conversion, code compilation, etc., can solve the problems of repeated data transmission and task scheduling method unfavorable data reuse, and achieve the effect of reducing the amount of data transmission and improving program performance.

Active Publication Date: 2021-03-30
JIANGNAN INST OF COMPUTING TECH
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  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to provide a heterogeneous many-core data reuse method, the heterogeneous many-core data reuse compilation optimization method solves the problem of repeated data transmission and task scheduling that is not conducive to data reuse, thereby reducing the gap between the main memory and the cache Data transfer volume, improve program performance

Method used

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  • Heterogeneous many-core data reuse method

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Embodiment

[0025] Embodiment: a method for reusing heterogeneous many-core data, based on a Stencil calculation identification module, a block segmentation task scheduling module and a data redirection module, the Stencil calculation identification module is used to complete the identification work of Stencil calculation, and the block segmentation The segment task scheduling module is used to complete the work of changing task division and scheduling when the dimension optimized for Stencil calculation is the outermost layer of the cycle, and the data redirection module is used to complete the work of data reuse;

[0026] The data reuse method includes the following steps:

[0027] S1. Assuming that i is a layer in a multi-layer loop iteration, use the Stencil calculation identification module to scan all the array subscripts involved in the calculation, and identify whether the i-dimension subscripts of the same array are all in [i-a, i +a], and the subscript contains all i-b and i+b i...

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Abstract

The invention discloses a heterogeneous many-core data reuse method. The method comprises a Stencil calculation identification module, a block segmentation task scheduling module and a data redirection module, the Stencil calculation identification module completes the identification work of Stencil calculation, the block segmentation task scheduling module completes the task division scheduling work when the dimension for performing the Stencil optimization is the outermost layer of a loop, and the data redirection module completes the work of data reuse. The method comprises the following steps: S1, assuming that the same dimension of the same array is i, identifying whether subscripts such as i-a / i+a exist in the same dimension of the same array or not and the subscripts are within therange of [i-a, i+a] through all array subscripts involved in scanning calculation by a Stencil calculation and identification module, and if so, considering that Stencil calculation exists in the dimension, taking the dimension as an alternative dimension of the start optimization, and executing the next step. According to the invention, the data transmission amount between the main memory and thecache is reduced, and the program performance is improved.

Description

technical field [0001] The invention belongs to the technical field of parallel compilation and optimization, in particular to a method for reusing heterogeneous many-core data. Background technique [0002] A processor with a heterogeneous fusion architecture is usually composed of a control core unit and a computing core array. The control core is responsible for program initialization, I / O, communication, and task assignment of the computing core array. Work faster. Each computing core is usually equipped with an on-chip cache SPM, which has fast access speed and low latency. The key data of the accelerated core segment can only be laid out to the on-chip cache through DMA to achieve the best acceleration effect. [0003] Stencil calculation is a commonly used calculation mode in scientific computing, and its characteristic is that there are accesses like [i-1], [i], [i+1]. In this calculation, some data of the current i iteration When performing i+1 iteration (denoted ...

Claims

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Application Information

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IPC IPC(8): G06F8/41
CPCG06F8/41G06F8/45
Inventor 尤洪涛顾龙姜小成毛兴权张立博孙俊
Owner JIANGNAN INST OF COMPUTING TECH
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