A digitally controlled dual-frequency low-noise amplifier circuit with differential output

Abstract

The present invention discloses a digitally controlled dual-frequency low-noise amplifier circuit with differential output, which includes an input impedance matching network, an amplifier stage, a differential output stage and a load stage. Compared with the traditional dual-frequency low-noise amplifier with independent channels, the present invention shares a common-gate amplifier with source negative feedback, which improves the power gain of the circuit, and also significantly improves the chip area, cost and circuit utilization. Compared with the traditional dual-frequency low-noise amplifier with independent channels, the present invention uses a switch to control the shutdown of the bias voltage, which reduces the design difficulty and increases the design flexibility, so that the circuit can obtain good noise performance and impedance matching effects in various frequency bands. The present invention effectively reduces the power consumption of the system by controlling the selection of the frequency band path through the switch.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuit design, and in particular to a digitally controlled dual-frequency low-noise amplifier circuit with differential output. Background Art

[0002] The low noise amplifier is the first amplifier circuit of the RF receiver. This type of amplifier can process very weak signals close to the noise level. Therefore, the low noise amplifier circuit is particularly important for the overall performance of the receiver. In addition, with the rapid development of 5G wireless communication systems, there are higher requirements for integrating more standard and multi-frequency RF receiver chips on a single chip to save chip area and reduce chip costs.

[0003] In the low noise amplifier circuit, there are many ways to achieve dual frequency bands. Among them, the low noise amplifier using two independent channels has the advantages of simple design and good performance. However, the need to use an independent low noise amplifier in each frequency band will not only increase the chip area, but also increase the overall power consumption of the system. At the same time, there are several technical problems in the realization of dual-frequency low noise amplifiers. First, a switching circuit is needed to switch the frequency, but MOS transistors as switching devices will introduce large parasitic capacitance and noise, resulting in unsatisfactory switching characteristics; second, there is feedthrough between the ports of the transistor itself, which can easily cause interference with the input signal and affect the performance of the circuit; third, because the mixer directly connected to the last stage of the low noise amplifier needs to have a differential output, and the commonly used solution is to add a balun output, but this will increase the chip area, which is not conducive to the chip integration, thereby increasing the chip cost. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a digitally controlled dual-frequency low-noise amplifier circuit with differential output.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] A digitally controlled dual-frequency low-noise amplifier circuit with differential output comprises an input impedance matching network, an amplifying stage, a differential output stage and a load stage.

[0007] The input impedance matching network is composed of a DC blocking capacitor C1-C2, a gate inductor L1-L2 and a resistor R1-R2; one end of the DC blocking capacitor C1 forms a first frequency band input end RFin1 of the digitally controlled dual-frequency low-noise amplifier circuit with a differential output, one end of the resistor R1 is connected to a first bias voltage Vbias1, one end of the gate inductor L1 is connected to the DC blocking capacitor C1 and the other end of the resistor R1, and the other end of the gate inductor L1 is connected to a gate of an NMOS tube N1 of an amplifier stage; one end of the DC blocking capacitor C2 forms a second frequency band input end RFin2 of the digitally controlled dual-frequency low-noise amplifier circuit with a differential output, one end of the resistor R2 is connected to a second bias voltage Vbias2, one end of the gate inductor L2 is connected to the DC blocking capacitor C2 and the other end of the resistor R2, and the other end of the gate inductor L2 is connected to a gate of an NMOS tube N2 of an amplifier stage.

[0008] The amplifier stage is composed of NMOS tubes N1-N4 and DC blocking capacitors C3 and C4; the drain of NMOS tube N1 is connected to one end of inductor L3 and one end of DC blocking capacitor C3 and C4, and the source of NMOS tube N1 is grounded; the gate of NMOS tube N3 is connected to one end of resistor R3 and the other end of DC blocking capacitor C3, the other end of resistor R3 is connected to the first bias voltage Vbias1, and the drain of NMOS tube N3 and the drain of NMOS tube N4 are connected to the inductor L4 of the differential output stage. One end of the NMOS tube N3 source is connected to the ground wire; the drain of the NMOS tube N2 is connected to one end of the inductor L3 and one end of the DC blocking capacitor C3 and the DC blocking capacitor C4, and the source of the NMOS tube N2 is connected to the ground wire; the gate of the NMOS tube N4 is connected to one end of the resistor R4 and the other end of the DC blocking capacitor C4, the other end of the resistor R4 is connected to the second bias voltage Vbias2, the drain of the NMOS tube N4 and the drain of the NMOS tube N3 are connected to one end of the inductor L4 of the differential output stage, and the source of the NMOS tube N4 is connected to the ground wire.

[0009] The differential output stage consists of NMOS tubes N5-N6, inductors L3-L4, resistors R5-R6 and DC-blocking capacitors C5-C6; the source of the NMOS tube N5 is connected to the other end of the inductor L3, and the drain of the NMOS tube N5 is connected to the DC-blocking capacitor C5 and one end of the load-level resistor R7; the gate of the NMOS tube N5 is connected to one end of the resistor R5; the source of the NMOS tube N6 is connected to the other end of the inductor L4, and the drain of the NMOS tube N6 is connected to the DC-blocking capacitor C6 and one end of the load-level resistor R8; the gate of the NMOS tube N6 is connected to one end of the resistor R6; the other end of the DC-blocking capacitor C5 forms the output port RFout- of the differential output digitally controlled dual-frequency low-noise amplifier circuit, and the other end of the DC-blocking capacitor C6 forms the output port RFout+ of the differential output digitally controlled dual-frequency low-noise amplifier circuit; one end of the resistor R5 is connected to the third bias voltage Vbias3, and the other end of the resistor R6 is connected to the third bias voltage Vbias3.

[0010] The load stage is composed of a resistor R7 and a resistor R8; the other end of the resistor R7 is connected to the power supply VDD; the other end of the resistor R8 is connected to the power supply VDD.

[0011] In the above scheme, the switch control module is composed of NMOS tubes N12-N13, PMOS tube P1 and PMOS tube P2; the gate of NMOS tube N12 is connected to the gate of PMOS tube P1, and forms the switch control terminal K0 of the switch control module; the drain of NMOS tube N12 is connected to the drain of PMOS tube P1 and the gate of NMOS tube N13 is connected to the gate of PMOS tube P2, forming the switch control terminal K1 of the switch control module; the drain of NMOS tube N13 is connected to the drain of PMOS tube P2, forming the switch control terminal K2 of the switch control module; the source of NMOS tube N12 and the source of NMOS tube N13 are grounded, and the source of PMOS tube P1 and the source of PMOS tube P2 are connected to the power supply VDD.

[0012] In the above scheme, the first current mirror is composed of an NMOS tube N8, an NMOS tube N10 and a resistor R10; the gate and drain of the NMOS tube N8 and the source of the NMOS tube N10 are connected, and output a first bias voltage Vbias1; the drain of the NMOS tube N10 is connected to one end of the resistor R10, and the gate of the NMOS tube N10 is connected to the control switch terminal K1 of the switch control module; the source of the NMOS tube N8 is grounded; and the other end of the resistor R10 is connected to the power supply VDD.

[0013] In the above scheme, the second current mirror is composed of an NMOS tube N9, an NMOS tube N11 and a resistor R11; the gate and drain of the NMOS tube N9 and the source of the NMOS tube N11 are connected, and output a second bias voltage Vbias2; the drain of the NMOS tube N11 is connected to one end of the resistor R11, and the gate of the NMOS tube N11 is connected to the control switch terminal K2 of the switch control module; the source of the NMOS tube N9 is grounded; and the other end of the resistor R11 is connected to the power supply VDD.

[0014] In the above scheme, the third current mirror is composed of an NMOS tube N7 and a resistor R9; the gate and drain of the NMOS tube N7 and one end of the resistor R9 are connected, and outputs a third bias voltage Vbias3; the source of the NMOS tube N7 is grounded; the other end of the resistor R9 is connected to the power supply VDD.

[0015] Compared with the prior art, the present invention has the following characteristics:

[0016] 1. Compared with the traditional independent-channel dual-band low-noise amplifier, it shares a common-gate amplifier with source negative feedback, which improves the power gain of the circuit, and also significantly improves the chip area, cost and circuit utilization;

[0017] 2. Compared with the traditional independent channel dual-band low noise amplifier, the use of switch to control the shutdown of the bias voltage reduces the design difficulty and increases the design flexibility, so that the circuit can obtain good noise performance and impedance matching effect in each frequency band;

[0018] 3. By controlling the selection of frequency band paths through switches, the power consumption of the system is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The schematic diagram is a differential output digitally controlled dual-frequency low-noise amplifier circuit of the present invention.

[0020] Figure 2 This is the schematic diagram of the switch control module circuit.

[0021] Figure 3 is a schematic diagram of the first current mirror, wherein (a) is the first current mirror, (b) is the second current mirror, and (c) is the third current mirror.

[0022] Figure 4 It is a simulation result diagram of the input matching curve (S11) of the present invention.

[0023] Figure 5 It is a simulation result diagram of the power gain curve (S21) of the present invention.

[0024] Figure 6 It is a noise factor curve (NF) simulation result diagram of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0026] A digitally controlled dual-frequency low-noise amplifier circuit with differential output, such as Figure 1 As shown, it includes an input impedance matching network, an amplification stage, a differential output stage, a load stage, three current mirror biases and a switch control module.

[0027] The input impedance matching network is composed of a DC blocking capacitor C1-C2, a gate inductor L1-L2 and a resistor R1-R2; one end of the DC blocking capacitor C1 forms the first frequency band input terminal RFin1 of the differential output digital control dual-frequency low noise amplifier circuit, one end of the resistor R1 is connected to the first bias voltage Vbias1, one end of the gate inductor L1 is connected to the DC blocking capacitor C1 and the other end of the resistor R1, and the other end of the gate inductor L1 is connected to the gate of the NMOS tube N1 of the amplifier stage; one end of the DC blocking capacitor C2 forms the second frequency band input terminal RFin2 of the differential output digital control dual-frequency low noise amplifier circuit, one end of the resistor R2 is connected to the second bias voltage Vbias2, one end of the gate inductor L2 is connected to the DC blocking capacitor C2 and the other end of the resistor R2, and the other end of the gate inductor L2 is connected to the gate of the NMOS tube N2 of the amplifier stage. The inductor L1 provides impedance matching for the first frequency band RFin1, and the inductor L2 provides impedance matching for the second frequency band RFin2.

[0028] The amplifier stage is composed of NMOS tubes N1-N4 and DC blocking capacitors C3 and C4; the drain of NMOS tube N1 is connected to one end of inductor L3 and one end of DC blocking capacitor C3 and C4, and the source of NMOS tube N1 is grounded; the gate of NMOS tube N3 is connected to one end of resistor R3 and the other end of DC blocking capacitor C3, the other end of resistor R3 is connected to the first bias voltage Vbias1, and the drain of NMOS tube N3 and the drain of NMOS tube N4 are connected to the inductor L4 of the differential output stage. One end of the NMOS tube N3 source is connected to the ground wire; the drain of the NMOS tube N2 is connected to one end of the inductor L3 and one end of the DC blocking capacitor C3 and the DC blocking capacitor C4, and the source of the NMOS tube N2 is connected to the ground wire; the gate of the NMOS tube N4 is connected to one end of the resistor R4 and the other end of the DC blocking capacitor C4, the other end of the resistor R4 is connected to the second bias voltage Vbias2, the drain of the NMOS tube N4 and the drain of the NMOS tube N3 are connected to one end of the inductor L4 of the differential output stage, and the source of the NMOS tube N4 is connected to the ground wire.

[0029] The differential output stage consists of NMOS tubes N5-N6, inductors L3-L4, resistors R5-R6 and DC-blocking capacitors C5-C6; the source of the NMOS tube N5 is connected to the other end of the inductor L3, and the drain of the NMOS tube N5 is connected to the DC-blocking capacitor C5 and one end of the load-level resistor R7; the gate of the NMOS tube N5 is connected to one end of the resistor R5; the source of the NMOS tube N6 is connected to the other end of the inductor L4, and the drain of the NMOS tube N6 is connected to the DC-blocking capacitor C6 and one end of the load-level resistor R8; the gate of the NMOS tube N6 is connected to one end of the resistor R6; the other end of the DC-blocking capacitor C5 forms the output port RFout- of the differential output digitally controlled dual-frequency low-noise amplifier circuit, and the other end of the DC-blocking capacitor C6 forms the output port RFout+ of the differential output digitally controlled dual-frequency low-noise amplifier circuit; one end of the resistor R5 is connected to the third bias voltage Vbias3, and the other end of the resistor R6 is connected to the third bias voltage Vbias3. The inductor L3 and the inductor L4 can improve the gain of the low noise amplifier.

[0030] The load stage is composed of a resistor R7 and a resistor R8; the other end of the resistor R7 is connected to the power supply VDD; the other end of the resistor R8 is connected to the power supply VDD.

[0031] The switch control module can control the selection of the frequency band. The switch control module is composed of NMOS tubes N12-N13, PMOS tubes P1 and PMOS tubes P2; Figure 2 As shown. The gate of the NMOS tube N12 is connected to the gate of the PMOS tube P1, and forms the switch control terminal K0 of the switch control module; the drain of the NMOS tube N12 is connected to the drain of the PMOS tube P1, and the gate of the NMOS tube N13 is connected to the gate of the PMOS tube P2, forming the switch control terminal K1 of the switch control module; the drain of the NMOS tube N13 is connected to the drain of the PMOS tube P2, forming the switch control terminal K2 of the switch control module; the source of the NMOS tube N12 and the source of the NMOS tube N13 are grounded, and the source of the PMOS tube P1 and the source of the PMOS tube P2 are connected to the power supply VDD.

[0032] The first current mirror is composed of NMOS tube N8, NMOS tube N10 and resistor R10. Figure 3 As shown in (a); the gate and drain of the NMOS tube N8 and the source of the NMOS tube N10 are connected, and a first bias voltage Vbias1 is output; the drain of the NMOS tube N10 is connected to one end of the resistor R10, and the gate of the NMOS tube N10 is connected to the control switch terminal K1 of the switch control module; the source of the NMOS tube N8 is grounded; the other end of the resistor R10 is connected to the power supply VDD.

[0033] The second current mirror is composed of NMOS tube N9, NMOS tube N11 and resistor R11. Figure 3(b) as shown; the gate and drain of the NMOS tube N9 and the source of the NMOS tube N11 are connected, and a second bias voltage Vbias2 is output; the drain of the NMOS tube N11 is connected to one end of the resistor R11, and the gate of the NMOS tube N11 is connected to the control switch terminal K2 of the switch control module; the source of the NMOS tube N9 is grounded; the other end of the resistor R11 is connected to the power supply VDD.

[0034] The third current mirror is composed of NMOS tube N7 and resistor R9. Figure 3 (c) As shown; the gate and drain of the NMOS tube N7 and one end of the resistor R9 are connected, and output a third bias voltage Vbias3; the source of the NMOS tube N7 is grounded; the other end of the resistor R9 is connected to the power supply VDD.

[0035] The working process of the present invention is as follows:

[0036] 1) When the switch control signal K0 is at a low level, the switch control K1 is at a high level and the switch control K2 is at a low level, the bias circuit connected to Vbias1 is in an open state, and the bias circuit connected to Vbias2 is in a closed state. This makes the NMOS tubes N1 and NMOS tubes N3 in the saturation region, and the NMOS tubes N2 and NMOS tubes N4 in the cut-off region. At this time, the RF signal selects the first frequency band RFin1. The RF signal RFin1 is differentially divided into two paths after being amplified by the common source stage of the NMOS tube N1. One path is amplified by the common gate of the inductor L3 and the NMOS tube N5 and output to RFout-. The other path is amplified by the common source stage of the inductor L4 and the NMOS tube N3, and then amplified by the common gate stage of the NMOS tube N6 and output to RFout+. In addition, the bias voltage Vbias3 provides a voltage bias for the NMOS tubes N5 and NMOS tubes N6, so that they all work in the saturation region. The gate inductor L1 provides good impedance matching for the circuit in the first frequency band, so that the circuit has a good noise coefficient and voltage gain.

[0037] 2) When the switch control signal K0 is at a high level, the switch control K1 is at a low level and the switch control K2 is at a high level, the bias circuit connected to Vbias1 is in a closed state, and the bias circuit connected to Vbias2 is in an open state. This makes the NMOS tubes N1 and NMOS tubes N3 in the cut-off region, and the NMOS tubes N2 and NMOS tubes N4 in the saturation region. At this time, the RF signal selects the second frequency band RFin2. The RF signal RFin2 is differentially divided into two paths after being amplified by the common source stage of the NMOS tube N2. One path is amplified by the common gate of the inductor L3 and the NMOS tube N5 and output to RFout-. The other path is amplified by the common source stage of the inductor L4 and the NMOS tube N4, and then amplified by the common gate stage of the NMOS tube N6 and output to RFout+. In addition, the bias voltage Vbias3 provides a voltage bias for the NMOS tubes N5 and NMOS tubes N6, so that they all work in the saturation region. The gate inductor L2 provides good impedance matching for the circuit in the second frequency band, so that the circuit has a good noise coefficient and voltage gain.

[0038] for Figure 1 The dual-band low-noise amplifier shown in the figure is designed using CMOS 0.18μm process and is obtained through simulation. Figure 4-6 The simulation results are as follows. Figure 4 It is shown that the input matching (S11) of the dual-band low noise amplifier designed in this embodiment at the operating frequencies of 3.5 GHz and 5 GHz is -11.38 dB and -18.84 dB respectively. Figure 5 It is shown that the power gain (S21) of the dual-band low noise amplifier designed in this embodiment at the operating frequencies of 3.5 GHz and 5 GHz is 18.06 dB and 12.43 dB respectively. Figure 6 It is shown that the power gains (NF) of the dual-band low noise amplifier designed in this embodiment at the operating frequencies of 3.5 GHz and 5 GHz are 3.4 dB and 3.9 dB respectively.

[0039] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A digitally controlled dual-frequency low-noise amplifier circuit with differential output, characterized in that: It includes an input impedance matching network, an amplifier stage, a differential output stage, and a load stage; The input impedance matching network is composed of a DC blocking capacitor C1-C2, a gate inductor L1-L2 and a resistor R1-R2; one end of the DC blocking capacitor C1 forms a first frequency band input end RFin1 of the digitally controlled dual-frequency low-noise amplifier circuit with a differential output, one end of the resistor R1 is connected to a first bias voltage Vbias1, one end of the gate inductor L1 is connected to the DC blocking capacitor C1 and the other end of the resistor R1, and the other end of the gate inductor L1 is connected to the gate of the NMOS tube N1 of the amplifier stage; one end of the DC blocking capacitor C2 forms a second frequency band input end RFin2 of the digitally controlled dual-frequency low-noise amplifier circuit with a differential output, one end of the resistor R2 is connected to a second bias voltage Vbias2, one end of the gate inductor L2 is connected to the DC blocking capacitor C2 and the other end of the resistor R2, and the other end of the gate inductor L2 is connected to the gate of the NMOS tube N2 of the amplifier stage; The amplifier stage is composed of NMOS tubes N1-N4 and DC blocking capacitors C3 and C4; the drain of NMOS tube N1 is connected to one end of inductor L3 and one end of DC blocking capacitor C3 and C4, and the source of NMOS tube N1 is grounded; the gate of NMOS tube N3 is connected to one end of resistor R3 and the other end of DC blocking capacitor C3, the other end of resistor R3 is connected to the first bias voltage Vbias1, and the drain of NMOS tube N3 and the drain of NMOS tube N4 are connected to the inductor L4 of the differential output stage. One end of the NMOS tube N3 source is connected to the ground wire; the drain of the NMOS tube N2 is connected to one end of the inductor L3 and one end of the DC blocking capacitor C3 and the DC blocking capacitor C4, and the source of the NMOS tube N2 is connected to the ground wire; the gate of the NMOS tube N4 is connected to one end of the resistor R4 and the other end of the DC blocking capacitor C4, the other end of the resistor R4 is connected to the second bias voltage Vbias2, the drain of the NMOS tube N4 and the drain of the NMOS tube N3 are connected to one end of the inductor L4 of the differential output stage, and the source of the NMOS tube N4 is connected to the ground wire; The differential output stage is composed of NMOS tubes N5-N6, inductors L3-L4, resistors R5-R6 and DC-blocking capacitors C5-C6; the source of the NMOS tube N5 is connected to the other end of the inductor L3, and the drain of the NMOS tube N5 is connected to the DC-blocking capacitor C5 and one end of the load-level resistor R7; the gate of the NMOS tube N5 is connected to one end of the resistor R5; the source of the NMOS tube N6 is connected to the other end of the inductor L4, and the drain of the NMOS tube N6 is connected to the DC-blocking capacitor C6 and one end of the load-level resistor R8; the gate of the NMOS tube N6 is connected to one end of the resistor R6; the other end of the DC-blocking capacitor C5 forms the output port RFout- of the differential output digitally controlled dual-frequency low-noise amplifier circuit, and the other end of the DC-blocking capacitor C6 forms the output port RFout+ of the differential output digitally controlled dual-frequency low-noise amplifier circuit; one end of the resistor R5 is connected to the third bias voltage Vbias3, and the other end of the resistor R6 is connected to the third bias voltage Vbias3; The load stage is composed of a resistor R7 and a resistor R8; the other end of the resistor R7 is connected to the power supply VDD; the other end of the resistor R8 is connected to the power supply VDD.

2. The digitally controlled dual-frequency low noise amplifier circuit with differential output according to claim 1, characterized in that: The switch control module is composed of NMOS tubes N12-N13, PMOS tube P1 and PMOS tube P2; The gate of the NMOS tube N12 is connected to the gate of the PMOS tube P1 and forms a switch control terminal K0 of the switch control module; The drain of the NMOS tube N12 is connected to the drain of the PMOS tube P1 and the gate of the NMOS tube N13 is connected to the gate of the PMOS tube P2 to form a switch control terminal K1 of the switch control module; The drain of the NMOS tube N13 is connected to the drain of the PMOS tube P2 to form a switch control terminal K2 of the switch control module; The source of the NMOS tube N12 and the source of the NMOS tube N13 are connected to the ground line, and the source of the PMOS tube P1 and the source of the PMOS tube P2 are connected to the power supply VDD.

3. The digitally controlled dual-frequency low noise amplifier circuit with differential output according to claim 2, characterized in that: The first current mirror is composed of NMOS tube N8, NMOS tube N10 and resistor R10; The gate and drain of the NMOS tube N8 and the source of the NMOS tube N10 are connected, and output a first bias voltage Vbias1; the drain of the NMOS tube N10 is connected to one end of the resistor R10, and the gate of the NMOS tube N10 is connected to the control switch terminal K1 of the switch control module; the source of the NMOS tube N8 is grounded; the other end of the resistor R10 is connected to the power supply VDD.

4. The digitally controlled dual-frequency low noise amplifier circuit with differential output according to claim 2, characterized in that: The second current mirror is composed of NMOS tube N9, NMOS tube N11 and resistor R11; The gate and drain of the NMOS tube N9 and the source of the NMOS tube N11 are connected, and output a second bias voltage Vbias2; the drain of the NMOS tube N11 is connected to one end of the resistor R11, and the gate of the NMOS tube N11 is connected to the control switch terminal K2 of the switch control module; the source of the NMOS tube N9 is grounded; the other end of the resistor R11 is connected to the power supply VDD.

5. The digitally controlled dual-frequency low noise amplifier circuit with differential output according to claim 2, characterized in that: The third current mirror is composed of NMOS tube N7 and resistor R9; The gate and drain of the NMOS tube N7 are connected to one end of the resistor R9, and outputs a third bias voltage Vbias3; the source of the NMOS tube N7 is connected to the ground line; The other end of the resistor R9 is connected to the power supply VDD.

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