Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched; forming a plurality of core layers on the layer to be etched, with a first groove between adjacent core layers; forming a sidewall material layer and a first sacrificial layer, wherein the sidewall material layer is located on the sidewall of the core layer and the top surface of the layer to be etched, and the first sacrificial layer is located on the sidewall and top surface of the sidewall material layer; removing the core layer, and forming a first opening in the sidewall material layer and the first sacrificial layer. Since the sidewall material layer is formed before the first opening, the end distance between the adjacent first conductive layers formed subsequently, i.e., the end distance between the adjacent core layers, is consistent with the expected target. In addition, since the end distance between the adjacent first conductive layers is consistent with the expected target, the length of the corresponding first conductive layer is increased, and when performing the connection process between metal wires, the position of the conductive plug connecting the first conductive layer has a better degree of freedom.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the improvement of circuit integration and the increase of scale, the size of unit devices in the circuit continues to shrink, and the requirements for integrated circuit manufacturing processes continue to increase. For example, the key size continues to decrease, and the chip manufacturing has higher and higher requirements for lithography resolution. As the design size continues to shrink, the minimum resolution of the design graphics has exceeded the limit of the existing optical lithography platform. The industry has adopted a variety of technical solutions to solve this technical problem. According to the international semiconductor technology blueprint, the industry has placed high hopes on technical solutions such as double patterning technology (DPT), extreme ultraviolet technology (EUV), and electron beam direct writing (EBL).

[0003] There are many existing double patterning processes, among which the double patterning process method using the LELE (Litho-Etch-Litho-Etch, lithography-etching-lithography-etching) process is a more common one among the existing multiple double patterning process methods. The LELE process method requires splitting the layout into two parts, and then generating a part of the pattern through two separate lithography and etching steps. However, the lithography, etching and deposition processes will produce EPE (Edge Placement Error), which will lead to vertical alignment deviation between layers. The appearance of EPE will eventually affect the performance of the formed semiconductor device. In order to reduce EPE, a patterning technology based on a sidewall process is proposed, such as a self-aligned LELE technology based on a sidewall process.

[0004] At present, when a metal line is formed by a sidewall-based self-aligned LELE process, a first groove is usually formed first, and then a sidewall is formed on the inner wall of the first groove. The sidewall is used as an alignment reference during the second photolithography, thereby achieving self-alignment of the second groove formed by the second photolithography and reducing EPE. The substrate is then patterned by relying on the sidewalls of the first groove and the inner wall of the first groove, as well as the second groove.

[0005] However, there are still problems with the metal lines formed in the prior art. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can reduce the device size, form a smaller HTH size, and make the HTH size consistent with the expected target.

[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, the layer to be etched comprising a first area and a second area arranged along a first direction; forming a plurality of core layers arranged along a second direction on the first area, the first direction and the second direction being perpendicular to each other, and a first groove being provided between adjacent core layers; forming a sidewall material layer and a first sacrificial layer, the sidewall material layer being located on the sidewall surface of the core layer and the top surface of the layer to be etched, and the first sacrificial layer being located on the sidewall and top surface of the sidewall material layer; removing the core layer, and forming a first opening in the sidewall material layer and the first sacrificial layer; after forming the first opening, forming a second opening in the sidewall material layer and the first sacrificial layer on the second area, and the sidewall of the second opening exposes the sidewall of the sidewall material layer.

[0008] Optionally, a width of the first groove is 12 nm to 200 nm, and the width direction is along the second direction.

[0009] Optionally, the method for forming the core layer includes: forming a core material layer on the layer to be etched; forming an initial first patterned layer on the core material layer; forming a photoresist layer on the initial first patterned layer; exposing the photoresist layer using an extreme ultraviolet light source to form a photoresist opening on the photoresist layer to expose a portion of the initial first patterned layer; after forming the photoresist opening, etching the initial first patterned layer using the photoresist layer as a mask until the top surface of the core material layer is exposed to form a first patterned layer; etching the core material layer using the first patterned layer as a mask to form the core layer.

[0010] Optionally, the layer to be etched includes: a substrate and a first mask layer located on the substrate, and the spacer material layer is located on the first mask layer.

[0011] Optionally, after forming the first opening and the second opening, the method further includes: etching the first mask layer using the first sacrificial layer and the spacer material layer as masks to form a first groove and a second groove in the first mask layer.

[0012] Optionally, after forming the first groove and the second groove, the method further includes: etching the substrate using the first mask layer as a mask to form a first target groove and a second target groove in the substrate; forming a first conductive layer in the first target groove; and forming a second conductive layer in the second target groove.

[0013] Optionally, the method for forming the spacer material layer and the first sacrificial layer includes: forming an initial spacer material layer on the side wall and top surface of the core layer and the top surface of the layer to be etched; forming an initial first sacrificial layer on the initial spacer material layer, the initial first sacrificial layer covering the initial spacer material layer; performing back etching on the initial first sacrificial layer until the top surface of the initial spacer material layer or the top surface and part of the side wall of the initial spacer material layer are exposed to form the first sacrificial layer; after forming the first sacrificial layer, removing the exposed initial spacer material layer until part of the surface of the core layer is exposed to form the spacer material layer.

[0014] Optionally, the process of etching back the initial first sacrificial layer includes one or more combinations of a chemical mechanical polishing process, a wet etching process and a dry etching process.

[0015] Optionally, the material of the first sacrificial layer includes: one or more combinations of spin-coated carbon, spin-coated glass, spin-coated organic matter, spin-coated silicon oxide, spin-coated metal oxide, oxides or nitrides formed by chemical vapor deposition or atomic layer deposition processes, amorphous carbon and amorphous silicon.

[0016] Optionally, the method for forming the second opening includes: forming a second sacrificial layer in the first opening and on the first sacrificial layer; forming a second patterned layer on the top of the second sacrificial layer, the second patterned layer exposing the top surface of the portion of the second sacrificial layer; etching the second sacrificial layer, the first sacrificial layer and the sidewall material layer using the second patterned layer as a mask until the top surface of the layer to be etched is exposed to form the second opening; after forming the second opening, removing the patterned layer and the second sacrificial layer.

[0017] Optionally, the material of the second sacrificial layer includes: one or more combinations of spin-coated carbon, spin-coated glass, spin-coated organic matter, spin-coated metal oxide, silicon oxide, silicon oxynitride, amorphous carbon, a silicon-containing organic anti-reflective layer and a bottom anti-radiation layer.

[0018] Optionally, the process of etching the second sacrificial layer, the first sacrificial layer and the spacer material layer includes one or more combinations of a wet etching process and a dry etching process.

[0019] Optionally, the material of the core layer includes one or more combinations of amorphous silicon, polycrystalline silicon, silicon nitride, silicon oxide, amorphous carbon and nitrogen-containing silicon oxide.

[0020] Optionally, the material of the spacer material layer includes: one or more combinations of silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride and aluminum oxide.

[0021] Optionally, the material of the first mask layer includes: one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0022] Optionally, the layer to be etched further includes an underlying hard mask layer, the underlying hard mask layer is located on the substrate, and the first mask layer is located on the underlying hard mask layer.

[0023] Optionally, the material of the bottom hard mask layer includes one or more combinations of silicon oxide, titanium nitride, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0024] Optionally, the first region and the second region are adjacent or not adjacent.

[0025] Optionally, the spacer material layer completely fills the first trench.

[0026] Optionally, the spacer material layer does not completely fill the first trench.

[0027] Optionally, the material of the first conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

[0028] Optionally, the material of the second conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the technical solution of the present invention, before forming the first opening and the second opening, a core layer is first formed on the layer to be etched, and the position and size of the first opening to be formed subsequently are defined by the core layer; then a sidewall material layer is formed on the sidewall of the core layer and the top surface of the layer to be etched, and the sidewall material layer is used as an alignment reference when forming the second opening, thereby reducing the alignment deviation between the second opening and the first opening.

[0031] Since the sidewall material layer is formed before the first opening, after the first opening is formed, it is not necessary to form a sidewall material layer in the first opening for self-alignment, so that the morphology of the formed first opening can be consistent with the core layer. In the subsequent process, when the morphology of the first opening is transferred to the layer to be etched, the morphology of the formed first target groove is also consistent with the core layer. Then, when metal is filled in the first target groove to form the first conductive layer, the end distance between adjacent first conductive layers, that is, the end distance between adjacent core layers, is consistent with the expected target. In addition, the end distance between adjacent first conductive layers is consistent with the expected target, which increases the length of the corresponding first conductive layer, and when the connection process between metal wires is performed, the position of the conductive plug connecting the first conductive layer has better freedom.

[0032] Furthermore, the width of the first trench is 12nm-200nm, and the width direction is along the second direction. The first trench with a width of 12nm-200nm makes the spacing between adjacent core layers smaller, and further makes the spacing between the first conductive layers formed subsequently smaller, thereby improving the integration of the components of the semiconductor structure finally formed.

[0033] Furthermore, an extreme ultraviolet light source is used to expose the photoresist layer, so that the width of the first channel between the adjacent core layers is 12nm to 200nm. In the prior art, since the spacing less than 70nm is small, if the spacing between the adjacent core layers is less than 70nm, two photomasks need to be formed separately. In the technical solution of the present invention, an extreme ultraviolet light source or an ultraviolet light source is used for exposure, and a photomask corresponding to the adjacent core layers is formed simultaneously using a single photomask, thereby effectively saving photomasks, simplifying the process steps, and also reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figures 1 to 5 It is a schematic diagram of the structure of a semiconductor structure;

[0035] Figures 6 to 21 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

[0036] Figure 22 to Figure 25 It is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, there are still problems with the metal lines formed in the prior art, which will be described in detail below with reference to the accompanying drawings.

[0038] Figures 1 to 5It is a structural schematic diagram of the formation process of a semiconductor structure.

[0039] Please refer to Figure 1 , providing a layer to be etched 100, wherein the layer to be etched 100 includes a plurality of first regions I and a plurality of second regions II, wherein the first regions I and the second regions II are alternately arranged along a first direction X, and adjacent first regions I and second regions II are adjacent to each other.

[0040] Please refer to Figure 2 , a first mask layer 101 is formed on the first region I and the second region II; a plurality of mutually discrete first grooves 102 are formed in the first mask layer 101 of the first region I, and the end distance between adjacent first grooves 102 in a second direction Y is d1, and the second direction Y is perpendicular to the first direction X; and sidewalls 103 are formed on the sidewalls of the first grooves 102.

[0041] Please refer to Figure 3 A first graphic layer 104 is formed on the first mask layer 101, and the first graphic layer 104 has a plurality of openings 105, and the openings 105 expose a portion of the top surface of the first mask layer 101 on the second region II and a portion of the top surface of the sidewall 103 of the first groove 102.

[0042] Please refer to Figure 4 , using the first graphic layer 104 as a mask, etching the first mask layer 101 exposed by the opening 105, forming a plurality of mutually discrete second grooves 106 in the first mask layer 101 on the second region II, and the sidewalls of the second grooves 106 expose the sidewalls 103; after forming the second grooves 106, removing the first graphic layer 104.

[0043] Please refer to Figure 5 , etching the layer to be etched 100 at the bottom of the first groove 102, forming a first target groove (not shown) in the layer to be etched 100; etching the layer to be etched 100 at the bottom of the second groove 106, forming a second target groove (not shown) in the layer to be etched 100; forming a first conductive layer 107 in the first target groove, and the end distance between adjacent first conductive layers 107 in the second direction Y is d2; forming a second conductive layer 108 in the second target groove.

[0044] In this embodiment, the sidewall 103 is formed on the sidewall of the first groove 102 , and the sidewall 103 is used as an alignment reference when the second groove 106 is formed by the subsequent second photolithography-etching, thereby reducing the edge placement error of the second groove 106 .

[0045] In this embodiment, the end distance d1 (Head to Head, HTH) between adjacent first grooves 102 is the expected target end distance between adjacent first conductive layers 107 to be formed subsequently. However, since the formed sidewall 103 is located inside the first groove 102, when metal is subsequently filled in the first groove 102 to form the first conductive layer 107, the end distance d2 between adjacent first conductive layers 107 is the sum of the end distance d1 of the adjacent first grooves 102 and the thickness of the two sidewalls 103, resulting in the HTH size d2 of the formed first conductive layer 107 failing to meet the minimum size requirement and not meeting the expected target.

[0046] If a smaller HTH size of the first conductive layer 107 is desired, an additional mask cutting process is required to remove the sidewall 103 located adjacent to the end sidewall of the first groove 102 (eg, Figure 4 As shown in part A in the figure, after removing the sidewall spacer 103, the first conductive layer 107 is formed, which will increase the number of steps and cost of the process.

[0047] In addition, since the HTH size d2 between adjacent first conductive layers 107 is larger than the expected target HTH size d1, this causes the length of the corresponding first conductive layer 107 to be reduced. When the subsequent connection process between metal wires is performed, the positional freedom of the conductive plug connecting the first conductive layer 107 is limited, which in turn causes difficulties in the connection process between metal wires, which is not conducive to the performance of the semiconductor device.

[0048] On this basis, the present invention provides a method for forming a semiconductor structure, by forming the sidewall material layer before forming the first opening, so that after forming the first opening, it is not necessary to form a sidewall material layer in the first opening for self-alignment, so that the morphology of the formed first opening can be consistent with the core layer, and in the subsequent process, when the morphology of the first opening is transferred to the layer to be etched, the morphology of the formed first target groove is also consistent with the core layer, and then when metal is filled in the first target groove to form the first conductive layer, the end distance between adjacent first conductive layers, that is, the end distance between adjacent core layers, is consistent with the expected target. In addition, the end distance between adjacent first conductive layers is consistent with the expected target, which increases the length of the corresponding first conductive layer, and when performing the connection process between metal wires, the position of the conductive plug connecting the first conductive layer has better freedom.

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] Figures 6 to 21 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0051] Please refer to Figure 6 and Figure 7 , Figure 7 yes Figure 6 In the cross-sectional schematic diagram along line AA, a layer to be etched is provided, and the layer to be etched includes a first region I and a second region II arranged along a first direction X.

[0052] In this embodiment, a first region I and a second region II are taken as examples, and the first region I and the second region II are adjacent to each other. Regions not marked with the first region I or the second region II are considered to be other regions where the first conductive layer or the second conductive layer is not formed.

[0053] In other embodiments, there may be multiple first areas and multiple second areas. If there are multiple first areas and multiple second areas, the first areas and the second areas are arranged alternately, and adjacent first areas and second areas are adjacent. The alternate arrangement here means that there is only one second area between adjacent first areas, and there is only one first area between adjacent second areas.

[0054] In other embodiments, the first region and the second region may not be adjacent to each other.

[0055] In this embodiment, the layer to be etched includes: a substrate 200 and a first mask layer 202 located on the substrate 200 .

[0056] In this embodiment, the material of the substrate 200 is a low-K dielectric layer (K ​​is less than or equal to 3.9); in other embodiments, the material of the substrate includes silicon oxide.

[0057] The material of the first mask layer 202 includes one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride. In this embodiment, the material of the first mask layer 202 is silicon oxide.

[0058] In this embodiment, the layer to be etched further includes an underlying hard mask layer 201 . The underlying hard mask layer 201 is located on the substrate 200 , and the first mask layer 202 is located on the underlying hard mask layer 201 .

[0059] The function of the bottom hard mask layer 201 is that the bottom hard mask layer 201 can be used as a stop layer for the subsequent planarization of the conductive film; the material of the bottom hard mask layer 201 is a hard mask material, so when the first target groove and the second target groove are subsequently etched, the etching loss of the bottom hard mask layer 201 is small, so in the process of transferring the pattern in the bottom hard mask layer 201 to the substrate 200, the stability of the pattern transfer is relatively high.

[0060] The bottom hard mask layer 201 may be a single-layer structure or a multi-layer structure, and the material of the bottom hard mask layer 201 includes one or more combinations of silicon oxide, titanium nitride, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide or aluminum nitride. In this embodiment, the material of the bottom hard mask layer 201 is titanium nitride.

[0061] Please refer to Figure 8 , Figure 8 and Figure 6 In accordance with the viewing direction, a plurality of core layers 203 arranged along a second direction Y are formed on the first region I, the first direction X and the second direction Y are perpendicular to each other, and first grooves 204 are provided between adjacent core layers 203 .

[0062] In this embodiment, a width D1 of the first trench 204 is in a range of 12 nm to 200 nm, and a direction of the width D1 is along the second direction.

[0063] The first trench 204 with a width of 12 nm to 200 nm makes the distance between adjacent core layers 203 smaller, and further makes the distance between the first conductive layers formed subsequently smaller, thereby improving the integration of components of the finally formed semiconductor structure.

[0064] In this embodiment, the method for forming the core layer 203 includes: forming a core material layer (not shown) on the layer to be etched 203; forming an initial first patterned layer (not shown) on the core material layer; forming a photoresist layer (not shown) on the initial first patterned layer; exposing the photoresist layer using an extreme ultraviolet light source to form a photoresist opening on the photoresist layer to expose a portion of the initial first patterned layer; after forming the photoresist opening, etching the initial first patterned layer using the photoresist layer as a mask until the top surface of the core material layer is exposed to form a first patterned layer; etching the core material layer using the first patterned layer as a mask to form the core layer 203.

[0065] In the prior art, since the spacing less than 70nm is small, if one wants to obtain a spacing of less than 70nm between adjacent core layers 203, two photomask formations are required. In the technical solution of the present invention, exposure treatment is performed by an ultraviolet light source or an extreme ultraviolet light source, and a photoresist layer corresponding to the adjacent core layer 203 is formed simultaneously using a single photomask, thereby effectively saving photomasks, simplifying the process steps, and also reducing the production cost.

[0066] The material of the core layer 203 includes amorphous silicon, polysilicon, silicon nitride, silicon oxide, amorphous carbon or one or more combinations thereof. In this embodiment, the material of the core layer 203 is amorphous carbon.

[0067] In this example, the size and position of the core layer 203 correspond to the position and size of the first target groove subsequently formed in the substrate 200 .

[0068] In this embodiment, the width of the core layer 203 in the first direction X is consistent with the width of the first region I in the first direction X; in other embodiments, the width of the core layer in the first direction X may be inconsistent with the width of the first region in the first direction X.

[0069] In this embodiment, the number of the core layers 203 formed is two, the two core layers 203 are arranged along the second direction Y and located on the same straight line, and the width D1 of the first channel 204 is the end distance between the two core layers 203; in other embodiments, the number of the core layers formed can also be other values, and the present invention is not limited to this.

[0070] After forming the core layer 203, the method further includes: forming a spacer material layer and a first sacrificial layer, wherein the spacer material layer is located on the sidewall surface of the core layer 203 and the top surface of the layer to be etched, and the first sacrificial layer is located on the sidewall and top surface of the spacer material layer. For the specific formation process of the spacer material layer and the first sacrificial layer, please refer to Figures 9 to 12 .

[0071] Please refer to Fig. 9 and Fig.10 , Fig.10 yes Fig. 9In the cross-sectional schematic diagram along line BB, an initial sidewall material layer 205 is formed on the sidewall and top surface of the core layer 203, and the top surface of the layer to be etched; an initial first sacrificial layer (not shown) is formed on the initial sidewall material layer 205, and the initial first sacrificial layer covers the initial sidewall material layer 205; the initial first sacrificial layer is etched back until the top surface of the initial sidewall material layer 205 is exposed, so as to form the first sacrificial layer 206.

[0072] The initial spacer material layer 205 is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this embodiment, the initial spacer material layer 205 is formed by atomic layer deposition, so that the initial spacer material layer 205 has good step coverage.

[0073] The material of the first sacrificial layer 206 includes one or more combinations of spin-coated silicon oxide, spin-coated carbon, spin-coated glass, spin-coated organic matter, spin-coated metal oxide, oxides or nitrides formed by chemical vapor deposition or atomic layer deposition, amorphous carbon and amorphous silicon. In this embodiment, the material of the first sacrificial layer 206 is spin-coated silicon oxide.

[0074] In this embodiment, the method of forming the initial first sacrificial layer is spin coating.

[0075] In this embodiment, the process of etching back the initial first sacrificial layer adopts a dry etching process; in other embodiments, the process of etching back the initial first sacrificial layer can also adopt one or more combinations of chemical mechanical polishing (CMP), wet etching and dry etching processes.

[0076] Please refer to Fig.11 and Fig.12 , Fig.12 yes Fig.11 In the cross-sectional diagram along line CC, after forming the first sacrificial layer 206 , the exposed initial spacer material layer 205 is removed until a portion of the surface of the core layer 203 is exposed, thereby forming the spacer material layer 207 .

[0077] In this embodiment, the spacer material layer 207 completely fills the first trench 204 .

[0078] In this embodiment, the material of the spacer material layer 207 is different from that of the core layer 203, so that the subsequent process of removing the spacer material layer 207 or the core layer 203 has a larger etching selectivity ratio for the core layer 203 and the spacer material layer 207. In addition, the material of the spacer material layer 207 is different from that of the first mask layer 202, so that the spacer material layer 207 and the first mask layer 202 also have a larger etching selectivity ratio.

[0079] The material of the spacer material layer 207 includes: one or more combinations of silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride and aluminum oxide. In this embodiment, the material of the spacer material layer 207 is titanium oxide.

[0080] In this embodiment, the process of removing the exposed initial spacer material layer 205 adopts a wet etching process; in other embodiments, the process of removing the exposed initial spacer material layer may also adopt a dry etching process or a combination of a dry etching process and a wet etching process.

[0081] Please refer to Fig.13 , Fig.12 and Fig.12 The core layer 203 is removed and a first opening 208 is formed in the sidewall material layer 207 in the same viewing direction.

[0082] In this embodiment, the first opening 208 is also located in the first sacrificial layer 206. In other embodiments, if the initial first sacrificial layer is etched back more, when the top surface of the formed first sacrificial layer is lower than the top surface of the initial spacer material layer located on the top of the core layer, the first opening finally formed is only located in the spacer material layer.

[0083] In this embodiment, the process of etching and removing the core layer 203 adopts a dry etching process; in other embodiments, a wet etching process or a combination of a dry etching process and a wet etching process may also be adopted to etch and remove the core layer.

[0084] After forming the first opening 208, the method further includes: forming a second opening in the spacer material layer 207 and the first sacrificial layer 206 on the second region II, wherein the sidewall of the second opening exposes the sidewall of the spacer material layer 207. For the specific formation process of the second opening, please refer to Figures 14 to 17 .

[0085] Please refer to Fig.14, forming a second sacrificial layer 209 in the first opening 208 and on the first sacrificial layer 206 ; forming a second patterned layer 210 on the top of the second sacrificial layer 209 , wherein the second patterned layer 210 exposes a portion of the top surface of the second sacrificial layer 209 .

[0086] The material of the second sacrificial layer includes: one or more combinations of spin-on carbon, spin-on glass, spin-on organic matter, spin-on metal oxide, silicon oxide, silicon oxynitride, amorphous carbon, a silicon-containing organic anti-reflective layer (Si-ARC) and a bottom anti-radiation layer (BARC). In this embodiment, the material of the second sacrificial layer 209 is spin-on organic matter.

[0087] In this embodiment, the second sacrificial layer 209 is formed by spin coating.

[0088] Please refer to Fig.15 The second sacrificial layer 209 , the first sacrificial layer 206 and the spacer material layer 207 are etched using the second patterned layer 210 as a mask until the top surface of the layer to be etched is exposed, thereby forming the second opening 211 .

[0089] In this embodiment, the process of etching the second sacrificial layer 209, the first sacrificial layer 206 and the sidewall material layer 207 adopts a wet etching process; in other embodiments, the process of etching the second sacrificial layer, the first sacrificial layer and the sidewall material layer may also adopt a dry etching process.

[0090] Please refer to Fig.16 and Fig.17 , Fig.17 yes Fig.16 In the cross-sectional diagram along line DD, after the first opening 208 and the second opening 211 are formed, the second patterned layer 210 and the second sacrificial layer 209 are removed.

[0091] In this embodiment, the sidewall material layer 207 serves as an alignment reference when forming the second opening 211, thereby reducing the alignment deviation between the first opening 208 and the second opening 211. Since the first opening 208 defines the position and size of the first groove to be formed subsequently, and the second opening 211 defines the position and size of the second groove to be formed subsequently, the position deviation between the first groove and the second groove is reduced.

[0092] Please refer to Fig.18 , Fig.18 and Fig.17The viewing direction is consistent with that of the embodiment of the present invention, after removing the second patterned layer 210 and the second sacrificial layer 209 , the first mask layer 202 is etched using the first sacrificial layer 206 and the sidewall material layer 207 as masks to form a first groove 212 and a second groove 213 in the first mask layer 202 .

[0093] In this embodiment, after forming the first groove 212 and the second groove 213, the first sacrificial layer 206 and the spacer material layer 207 are removed. In other embodiments, after forming the first groove and the second groove, the first sacrificial layer and the spacer material layer may not be removed, and in subsequent processes, the substrate is continuously etched using the first sacrificial layer, the spacer material layer and the first mask layer as masks.

[0094] In this embodiment, the first mask layer 202 is etched by a dry etching process; in other embodiments, the first mask layer may be removed by a wet etching process or a combination of dry etching and wet etching.

[0095] In this embodiment, the retained sidewall material layer 207 is used to form the spacing between the first groove 212 and the second groove 213 in the first direction X. Through two photolithography-etching processes based on the sidewall material layer 207 process, the spacing between devices is further reduced, and the device size is reduced. At the same time, the sidewall material layer 207 also provides an alignment reference, reducing the alignment deviation between the first groove 212 and the second groove 213.

[0096] Please refer to Fig.19 , using the first mask layer 202 as a mask, etching the bottom hard mask layer 201 and the substrate 200 to form a first target groove 214 and a second target groove 215 in the substrate 200 .

[0097] The process of etching the bottom hard mask layer 201 and the substrate 200 using the first mask layer 202 as a mask includes one of a dry etching process and a wet etching process or a combination of the two.

[0098] In this embodiment, after the first target groove 214 and the second target groove 215 are formed, the first mask layer 202 and the bottom hard mask layer 201 are not removed first; in other embodiments, after the first target groove and the second target groove are formed, part of the mask layer can be removed first, for example, the first mask layer can be removed first.

[0099] Please refer to Fig. 20 and Fig.21 , Fig.21 yes Fig. 20In the cross-sectional schematic diagram along line EE, after the first target groove 214 and the second target groove 215 are formed, a first conductive layer 216 is formed in the first target groove 214, and a second conductive layer 217 is formed in the second target groove 215; after the first conductive layer 216 and the second conductive layer 217 are formed, the first mask layer 202 and the underlying hard mask layer 201 are removed.

[0100] Since the sidewall material layer 207 is formed before the first opening 208, after the first opening 208 is formed, it is not necessary to form the sidewall material layer 207 in the first opening 208 for self-alignment, so that the morphology of the formed first opening 208 can be consistent with the core layer 203. After the first opening 208 is formed, when the morphology of the first opening 208 is transferred to the layer to be etched, the morphology of the formed first target groove 214 is also consistent with the core layer 203. Then, when metal is filled in the first target groove 214 to form the first conductive layer 216, the end distance D2 between adjacent first conductive layers 216, that is, the end distance D1 between adjacent core layers 203, is consistent with the expected target. In addition, the end distance between adjacent first conductive layers 216 is consistent with the expected target, which increases the length of the corresponding first conductive layer 216, and when the metal wire connection process is performed, the position of the conductive plug connecting the first conductive layer 216 has better freedom.

[0101] In this embodiment, the method for forming the first conductive layer 216 and the second conductive layer 217 includes: forming a conductive film (not shown) in the first target groove 214 and the second target groove 215, wherein the conductive film covers the first mask layer 202; planarizing the conductive film, the first mask layer 202 and the bottom hard mask layer 201 until the substrate 200 is exposed, forming the first conductive layer 216 in the first target groove 214, and forming the second conductive layer 217 in the second target groove 215.

[0102] The material of the first conductive layer 216 includes one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene. In this embodiment, the material of the first conductive layer 216 is copper and tantalum nitride, and tantalum nitride is used as a barrier layer for copper diffusion.

[0103] The material of the first conductive layer 217 includes one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene. In this embodiment, the material of the second conductive layer 217 is copper and tantalum nitride, and tantalum nitride is used as a barrier layer for copper diffusion.

[0104] Figure 22 to Figure 25It is a structural schematic diagram of a formation process of a semiconductor structure according to another embodiment of the present invention.

[0105] This embodiment further describes the method for forming a semiconductor structure based on the above embodiment, and the difference between this embodiment and the above embodiment is that the spacer material layer 207 does not completely fill the first trench 204. The following will be described in detail with reference to the accompanying drawings.

[0106] Please refer to Fig. 22 and Fig.23 , Fig.23 yes Fig. 22 In the cross-sectional schematic diagram along the FF line, an initial sidewall material layer 205 is formed on the sidewall and top surface of the core layer 203, and the top surface of the layer to be etched; an initial first sacrificial layer (not shown) is formed on the initial sidewall material layer 205, and the initial first sacrificial layer covers the initial sidewall material layer 205; the initial first sacrificial layer is etched back until the top surface of the initial sidewall material layer 205 is exposed, so as to form the first sacrificial layer 206.

[0107] Please refer to Fig.24 and Fig.25 , Fig.25 yes Fig.24 In the cross-sectional diagram along line GG, after forming the first sacrificial layer 206, the exposed initial spacer material layer 205 is removed until the top surface of the core layer 203 is exposed, thereby forming the spacer material layer 207.

[0108] In this embodiment, the spacer material layer 207 does not completely fill the first trench 204 .

[0109] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein the layer to be etched includes a first area and a second area arranged along a first direction; forming a plurality of core layers arranged along a second direction on the first region, wherein the first direction is perpendicular to the second direction, and first grooves are provided between adjacent core layers; Forming a spacer material layer and a first sacrificial layer, wherein the spacer material layer is located on the sidewall surface of the core layer and the top surface of the layer to be etched, and the first sacrificial layer is located on the sidewall and top surface of the spacer material layer; removing the core layer and forming a first opening in the sidewall material layer; After the first opening is formed, a second opening is formed in the spacer material layer and the first sacrificial layer on the second region, and the sidewall of the second opening exposes the sidewall of the spacer material layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The width of the first groove is 12 nm to 200 nm, and the width direction is along the second direction.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the core layer includes: forming a core material layer on the layer to be etched; forming an initial first patterned layer on the core material layer; forming a photoresist layer on the initial first patterned layer; exposing the photoresist layer using an ultraviolet light source or an extreme ultraviolet light source to form a photoresist opening on the photoresist layer to expose a portion of the initial first patterned layer; after forming the photoresist opening, etching the initial first patterned layer using the photoresist layer as a mask until the top surface of the core material layer is exposed to form a first patterned layer; etching the core material layer using the first patterned layer as a mask to form the core layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate and a first mask layer located on the substrate, and the spacer material layer is located on the first mask layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: After forming the first opening and the second opening, the method further includes: etching the first mask layer using the first sacrificial layer and the spacer material layer as masks to form a first groove and a second groove in the first mask layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: After forming the first groove and the second groove, the method further includes: etching the substrate using the first mask layer as a mask to form a first target groove and a second target groove in the substrate; forming a first conductive layer in the first target groove; and forming a second conductive layer in the second target groove.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the spacer material layer and the first sacrificial layer includes: forming an initial spacer material layer on the side wall and top surface of the core layer and the top surface of the layer to be etched; forming an initial first sacrificial layer on the initial spacer material layer, the initial first sacrificial layer covering the initial spacer material layer; etching back the initial first sacrificial layer until the top surface of the initial spacer material layer or the top surface and part of the side wall of the initial spacer material layer are exposed to form the first sacrificial layer; after forming the first sacrificial layer, removing the exposed initial spacer material layer until part of the surface of the core layer is exposed to form the spacer material layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process of etching back the initial first sacrificial layer includes one or more combinations of a chemical mechanical polishing process, a wet etching process and a dry etching process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sacrificial layer includes: one or more combinations of spin-coated carbon, spin-coated glass, spin-coated organic matter, spin-coated silicon oxide, spin-coated metal oxide, oxide or nitride formed by chemical vapor deposition or atomic layer deposition process, amorphous carbon and amorphous silicon.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second opening includes: forming a second sacrificial layer in the first opening and on the first sacrificial layer; forming a second patterned layer on the top of the second sacrificial layer, the second patterned layer exposing a portion of the top surface of the second sacrificial layer; etching the second sacrificial layer, the first sacrificial layer and the sidewall material layer using the second patterned layer as a mask until the top surface of the layer to be etched is exposed to form the second opening; after forming the second opening, removing the patterned layer and the second sacrificial layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The material of the second sacrificial layer includes: one or more combinations of spin-coated carbon, spin-coated glass, spin-coated organic matter, spin-coated metal oxide, silicon oxide, silicon oxynitride, amorphous carbon, a silicon-containing organic anti-reflective layer and a bottom anti-radiation layer.

12. The method for forming a semiconductor structure according to claim 10, wherein: The process of etching the second sacrificial layer, the first sacrificial layer and the spacer material layer includes one or more combinations of a wet etching process and a dry etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the core layer includes one or more combinations of amorphous silicon, polycrystalline silicon, silicon nitride, silicon oxide, amorphous carbon and silicon oxide containing nitrogen.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the spacer material layer includes: one or more combinations of silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride and aluminum oxide.

15. The method for forming a semiconductor structure according to claim 4, wherein: The material of the first mask layer includes: one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

16. The method for forming a semiconductor structure according to claim 4, wherein: The layer to be etched further includes an underlying hard mask layer, the underlying hard mask layer is located on the substrate, and the first mask layer is located on the underlying hard mask layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The material of the bottom hard mask layer includes one or more combinations of silicon oxide, titanium nitride, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

18. The method for forming a semiconductor structure according to claim 16, wherein: The first region and the second region are contiguous or non-contiguous.

19. The method for forming a semiconductor structure according to claim 1, wherein: The spacer material layer fully fills the first trench.

20. The method for forming a semiconductor structure according to claim 1, wherein: The spacer material layer does not completely fill the first trench.

21. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

22. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

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