Electronic system and method of using an electronic system

Abstract

An electronic system and a method of using the electronic system are disclosed. The system includes a differential signal generator configured to generate a first single-ended signal and a second single-ended signal having opposite polarities. The input signal and the first and second single-ended signals transition between a first power supply voltage and a first ground voltage. The system also includes a glitch management circuit configured to generate an output signal based on the first and second single-ended signals. The output signal transitions between a second power supply voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals. The first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The system also includes a second latch configured to generate an output signal based on the first and second intermediate signals.

Description

Technical Field

[0001] The subject matter described in this article relates to deglitch circuits, and more specifically to deglitch circuits that can be used for signals that cross power domains. Background Technology

[0002] Certain systems, such as mobile phones and other electronic systems, are particularly sensitive to signals with glitches caused by events such as ESD, noise, or other glitches. For example, glitches in certain reset, clock, and mode control signals that cross from a first power domain to a second power domain can cause system malfunctions. Such malfunctions can lead to automatic system resets or crashes, requiring the user to reset or restart the system. Summary of the Invention

[0003] One aspect of the invention is an electronic system. The system includes a differential signal generator comprising one or more differential signal generator components collectively configured to receive an input signal and generate first and second single-ended signals based on the input signal, wherein the first and second single-ended signals have opposite polarities, wherein the input signal transitions between a first power supply voltage and a first ground voltage, and wherein each of the first and second single-ended signals transitions between the first power supply voltage and the first ground voltage. The system also includes a glitch management circuit comprising one or more glitch management components collectively configured to receive the first and second single-ended signals and generate an output signal based on the first and second single-ended signals, wherein the output signal transitions between a second power supply voltage and a second ground voltage, wherein the glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals based on the first and second single-ended signals. The first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The system also includes a second latch configured to receive the first and second intermediate signals and generate the output signal based on the first and second intermediate signals.

[0004] In some embodiments, at least one of the following: A) as a result of a change in one or both of the first power supply voltage and the first ground voltage relative to one or both of the second power supply voltage and the second ground voltage, the first single-ended signal has a first signal glitch, and wherein the glitch management circuit is configured to suppress the first signal glitch; and B) as a result of a change in one or both of the first power supply voltage and the first ground voltage relative to one or both of the second power supply voltage and the second ground voltage, the second single-ended signal has a second signal glitch, and wherein the glitch management circuit is configured to suppress the second signal glitch.

[0005] In some embodiments, at least one of the following: A) as a result of a change in one or both of the first power supply voltage and the first ground voltage relative to one or both of the second power supply voltage and the second ground voltage, the first single-ended signal has first and second signal glitches, wherein the first and second signal glitches have opposite polarities, and wherein the glitch management circuit is configured to suppress the first and second signal glitches; and B) as a result of a change in one or both of the first power supply voltage and the first ground voltage relative to one or both of the second power supply voltage and the second ground voltage, the second single-ended signal has third and fourth signal glitches, wherein the third and fourth signal glitches have opposite polarities, and wherein the glitch management circuit is configured to suppress the third and fourth signal glitches.

[0006] In some embodiments, the first latch is configured to: receive first, second, third, and fourth signal glitches, propagate the first signal glitches to the second intermediate signal, propagate the third signal glitches to the first intermediate signal, and suppress the second and fourth signal glitches such that the second and fourth signal glitches do not propagate to the first and second intermediate signals, wherein the first and third signal glitches have the same first polarity, and wherein the second and fourth signal glitches have the same second polarity.

[0007] In some embodiments, the second latch is configured to receive propagating first and third signal glitches from the first latch and suppress propagating first and third signal glitches such that the propagating first and third signal glitches do not propagate further to the output signal.

[0008] In some embodiments, the differential signal generator includes: an inverting signal path configured to receive an input signal and generate a first single-ended signal based on the input signal, wherein the first single-ended signal and the input signal have opposite polarities; and a non-inverting signal path configured to receive an input signal and generate a second single-ended signal based on the input signal, wherein the second single-ended signal and the input signal have the same polarity.

[0009] In some embodiments, the first latch includes a first SR (set / reset) latch, and the second latch includes a second SR latch.

[0010] In some embodiments, the first and second power supply voltages are different.

[0011] In some embodiments, the first and second power supply voltages are substantially equal.

[0012] In some embodiments, the first and second ground voltages are different.

[0013] In some embodiments, the first and second ground voltages are substantially equal.

[0014] Another aspect of the invention is a method using an electronic system including a differential signal generator and a glitch management circuit. The method includes receiving an input signal using one or more differential signal generator components of the differential signal generator, and generating first and second single-ended signals based on the input signal using the differential signal generator components, wherein the first and second single-ended signals have opposite polarities, wherein the input signal transitions between a first power supply voltage and a first ground voltage, and wherein each of the first and second single-ended signals transitions between the first power supply voltage and the first ground voltage. The method also includes receiving the first and second single-ended signals using one or more glitch management components, and generating an output signal based on the first and second single-ended signals using the glitch management components, wherein the output signal transitions between a second power supply voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals based on the first and second single-ended signals, wherein the first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The glitch management circuit also includes a second latch configured to receive the first and second intermediate signals and generate the output signal based on the first and second intermediate signals.

[0015] In some embodiments, at least one of the following is performed: A) As a result of a change in one or both of a first power supply voltage and a first ground voltage relative to one or both of a second power supply voltage and a second ground voltage, the first single-ended signal has a first signal glitch, and the method further includes using a glitch management circuit to suppress the first signal glitch; B) As a result of a change in one or both of a first power supply voltage and a first ground voltage relative to one or both of a second power supply voltage and a second ground voltage, the second single-ended signal has a second signal glitch, and the method further includes using a glitch management circuit to suppress the second signal glitch.

[0016] In some embodiments, at least one of the following: A) as a result of a change in one or both of a first power supply voltage and a first ground voltage relative to one or both of a second power supply voltage and a second ground voltage, the first single-ended signal has first and second signal glitches, wherein the first and second signal glitches have opposite polarities, and wherein the method further includes using a glitch management circuit to suppress the first and second signal glitches; and B) as a result of a change in one or both of a first power supply voltage and a first ground voltage relative to one or both of a second power supply voltage and a second ground voltage, the second single-ended signal has third and fourth signal glitches, wherein the third and fourth signal glitches have opposite polarities, and wherein the method further includes using a glitch management circuit to suppress the third and fourth signal glitches.

[0017] In some embodiments, the first latch is configured to: receive first, second, third, and fourth signal glitches, propagate the first signal glitches to the second intermediate signal, propagate the third signal glitches to the first intermediate signal, and suppress the second and fourth signal glitches such that the second and fourth signal glitches do not propagate to the first and second intermediate signals, wherein the first and third signal glitches have the same first polarity, and wherein the second and fourth signal glitches have the same second polarity.

[0018] In some embodiments, the second latch is configured to receive propagating first and third signal glitches from the first latch and suppress propagating first and third signal glitches such that the propagating first and third signal glitches do not propagate further to the output signal.

[0019] In some embodiments, the differential signal generator includes: an inverting signal path configured to receive an input signal and generate a first single-ended signal based on the input signal, wherein the first single-ended signal and the input signal have opposite polarities; and a non-inverting signal path configured to receive an input signal and generate a second single-ended signal based on the input signal, wherein the second single-ended signal and the input signal have the same polarity.

[0020] In some embodiments, the first latch includes a first SR (set / reset) latch, and the second latch includes a second SR latch.

[0021] In some embodiments, the first and second power supply voltages are different.

[0022] In some embodiments, the first and second power supply voltages are substantially equal. Attached Figure Description

[0023] The accompanying drawings, which are included in and form a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the specification, help to illustrate some principles associated with the disclosed embodiments.

[0024] Figure 1 A schematic diagram of a signal transmission system according to an embodiment is shown.

[0025] Figure 2 The illustration shows an embodiment. Figure 1 A schematic diagram of a set of waveforms representing the operation of a signal transmission system.

[0026] Figure 3 A schematic diagram of a differential signal generator according to an embodiment is shown.

[0027] Figure 4 A schematic diagram of a burr management system according to an embodiment is shown.

[0028] Figure 5A schematic diagram of a set of waveforms is shown, illustrating an embodiment. Figure 4 Operation of the burr management system.

[0029] Figure 6 A schematic diagram of a signal transmission system according to an embodiment is shown.

[0030] Figure 7 The illustration shows an embodiment. Figure 6 A schematic diagram of a set of waveforms representing the operation of a signal transmission system.

[0031] Figure 8 A schematic diagram of a burr management system according to an embodiment is shown.

[0032] Figure 9 The illustration shows an embodiment. Figure 8 A schematic diagram of a set of waveforms representing the operation of the glitch management system.

[0033] Figure 10 A schematic diagram of a latch according to an embodiment is shown.

[0034] In practical applications, similar reference numerals indicate similar structures, features, or elements. Detailed Implementation

[0035] As discussed in further detail below, a system can employ a glitch management circuitry to reduce or eliminate glitches in the signal. Systems such as mobile phones and other electronic systems may be particularly sensitive to glitches, for example, those caused by ESD, noise, or other glitch-inducing events. For instance, glitches in certain reset, clock, and mode control signals crossing from a first power domain to a second power domain may have glitches caused by independent changes in the power supply and / or ground voltages of the first and second power domains. These and other glitches in the signals can cause system malfunctions. For example, a system malfunction may cause an automatic system reset or crash, requiring the user to, for example, reset or restart the system.

[0036] Some glitches are based on time-delay digital circuits. For example, transitions between digital states in a signal may not occur until the new state has persisted for a certain period. Therefore, glitches lasting less than the delay time will not occur. Time-delay solutions are ineffective in systems where the glitch duration is considerably larger than the system's time scale. For example, a system with a 100MHz clock has a clock period of 10ns and a clock pulse of 5ns. Glitches of 1–3ns cannot be managed with conventional time-delay-based glitches. The circuits and aspects discussed in this paper take into account appropriate glitches with durations considerably larger than the system's time scale.

[0037] In some embodiments, due to the glitch management circuitry, glitches in certain signals are suppressed or prevented from propagating to sensitive system circuitry. Examples of systems using glitch management systems and techniques are discussed below.

[0038] Several illustrative embodiments are described with reference to the accompanying drawings, which form part of this disclosure. The following description provides only one or more embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of one or more embodiments will provide those skilled in the art with a feasible description for implementing one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain embodiments of the invention. However, it will be apparent that various embodiments can be practiced without these specific details. The drawings and description are not intended to be limiting. The terms “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or superior to other embodiments or designs.

[0039] Figure 1 A schematic diagram of a signal transmission system 10 according to an embodiment is shown. As discussed in further detail below, the signal transmission system 10 transmits a signal from a first power domain to a second power domain. The first power domain includes a power supply voltage VDD1 and a ground voltage GND1. The second power domain includes a power supply voltage VDD2 and a ground voltage GND2. Due to glitches as understood by those skilled in the art, the voltage of one or both of the power supply voltage VDD1 and the ground voltage GND1 may temporarily change or exhibit glitches relative to one or both of the power supply voltage VDD2 and the ground voltage GND2.

[0040] Glitches can be caused by events that directly affect the supply voltage VDD1. For example, ESD events, noise, or power bounce may occur at the supply voltage VDD1 node. Similarly, glitches can be caused by events that directly affect the ground voltage GND1. For example, ESD events, noise, or ground bounce may occur at the ground voltage GND1 node.

[0041] Glitches can be caused, for example, by glitch-induced events that directly affect the supply voltage VDD2. For instance, ESD events, noise, or power bounce may occur at the supply voltage VDD2 node. Similarly, glitches can be caused by glitch-induced events that directly affect the ground voltage GND2. For instance, ESD events, noise, or ground bounce may occur at the ground voltage GND2 node.

[0042] In some embodiments, one or more coupling capacitors (not shown) may be placed across the power supply voltage VDD1 and the ground voltage GND1. The function of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between the power supply voltage VDD1 and the ground voltage GND1.

[0043] In some embodiments, one or more coupling capacitors (not shown) may be placed across the power supply voltage VDD2 and the ground voltage GND2. The function of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between the power supply voltage VDD2 and the ground voltage GND2.

[0044] In some embodiments, one or more coupling capacitors (not shown) may be placed across power supply voltages VDD1 and VDD2. The purpose of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between power supply voltages VDD1 and VDD2.

[0045] In some embodiments, one or more coupling capacitors (not shown) may be placed across ground voltage GND1 and ground voltage GND2. The function of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between ground voltage GND1 and ground voltage GND2.

[0046] In some embodiments, one or more coupling capacitors (not shown) may be placed across the ground voltage GND1 and the power supply voltage VDD2. The purpose of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between the power supply voltage VDD2 and the ground voltage VDD1.

[0047] In some embodiments, one or more coupling capacitors (not shown) may be placed across the power supply voltage VDD1 and the ground voltage GND2. The function of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between the ground voltage GND2 and the power supply voltage GND2.

[0048] In some embodiments with one or more coupling capacitors, the coupling capacitors reduce but do not eliminate glitches, thus enabling the circuit techniques discussed herein to advantageously prevent glitches from affecting sensitive circuit systems.

[0049] The signal transmission system 10 is configured to receive an input signal at input terminal IN and transmit a digital representation of the input signal as an output signal to output terminal OUT. In some embodiments, output terminal OUT is connected to one or more circuits that are sensitive to glitches that may occur in the output signal.

[0050] In some embodiments, the output signal represents a reset signal. For example, the input signal can be generated as a reset signal by a power management circuit, where the output signal can reset a microcontroller connected to the output terminal OUT. Therefore, unexpected glitches in the output signal may cause the microcontroller to reset unintentionally.

[0051] In some embodiments, the output signal represents an asynchronous signal, such as a mode control signal. For example, the input signal may be generated as a mode control signal by control circuitry, wherein the output signal can cause processing circuitry connected to the output terminal OUT to operate according to different modes. Therefore, unexpected glitches in the output signal may cause the processing circuitry to unintentionally change the mode.

[0052] In some embodiments, the output signal represents a clock signal. For example, the input signal can be generated into a clock signal by a clock generation circuit, wherein the output signal can cause the processing circuit connected to the output terminal OUT to operate according to the clock signal. Therefore, unexpected glitches in the output signal may cause the processing circuit to malfunction.

[0053] In some embodiments, the output signal represents another signal, wherein unexpected glitches in the output signal may cause the circuit connected to the output terminal OUT to malfunction.

[0054] The signal transmission system 10 includes a differential signal generator 100 and a glitch management circuit 200.

[0055] The differential signal generator 100 is configured to receive an input signal at its input terminal IN. Furthermore, the differential signal generator 100 is configured to generate differential signals representing the input signal at differential nodes D and DN. For example, the input signal can be switched between a power supply voltage VDD1 and a ground voltage GND1. Additionally, the single-ended signal at each of the differential nodes D and DN can be switched between the power supply voltage VDD1 and the ground voltage GND1, such that an input signal equal to the power supply voltage VDD1 makes the signal at differential node D equal to the power supply voltage VDD1 and the signal at differential node DN equal to the ground voltage GND1, and an input signal equal to the ground voltage GND1 makes the signal at differential node D equal to the ground voltage GND1 and the signal at differential node DN equal to the power supply voltage VDD1.

[0056] In addition, glitches can cause glitches in the signals at differential nodes D and DN.

[0057] The glitch management circuit 200 is configured to receive signals at differential nodes D and DN, and generate an output signal at output terminal OUT based on the received signals, wherein the output signal can switch between power supply voltage VDD2 and ground voltage GND2. For example, in response to the signal at differential node D being equal to power supply voltage VDD1 and the signal at differential node DN being equal to ground voltage GND1, the glitch management circuit 200 can be configured to make the output signal at output terminal OUT equal to power supply voltage VDD2. Furthermore, in response to the signal at differential node D being equal to ground voltage GND1 and the signal at differential node DN being equal to power supply voltage VDD1, the glitch management circuit 200 can be configured to make the output signal at output terminal OUT equal to ground voltage GND2.

[0058] Furthermore, the glitch management circuit 200 is configured to ensure that the output signal at the output terminal OUT is continuous or unaffected by glitches generated in the signals at the differential nodes D and DN.

[0059] Figure 2 A schematic diagram of a set of waveforms is shown, illustrating an embodiment. Figure 1 The operation of the signal transmission system 10.

[0060] During time T1, the input signal has a value equal to the power supply voltage VDD1. Furthermore, during time T1, the ground voltage GND1 experiences negative glitches relative to one or both of the power supply voltage VDD2 and the ground voltage GND2. Also, during time T1, the power supply voltage VDD1 experiences negative glitches relative to one or both of the power supply voltage VDD2 and the ground voltage GND2.

[0061] During time T1, since the input signal has a voltage equal to the power supply voltage VDD1, the differential node DN has a signal equal to the ground voltage GND1. Furthermore, due to the negative glitches of the ground voltage GND1, the signal at the differential node DN also has negative glitches corresponding to the negative glitches of the ground voltage GND1 during time T1.

[0062] During time T1, since the input signal has a voltage equal to the supply voltage VDD1, the differential node D has a signal equal to the supply voltage VDD1. Furthermore, due to the negative glitches of the supply voltage VDD1, the signal at the differential node D also has negative glitches corresponding to the negative glitches of the supply voltage VDD1 during time T1.

[0063] Furthermore, during time T1, since the differential signal D has a voltage equal to the power supply voltage VDD1 and the differential signal DN has a voltage equal to the ground voltage GND1, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2. Additionally, as shown in the figure, negative glitches at differential nodes D and DN are suppressed and do not affect the output signal.

[0064] Therefore, during time T1, since the input signal has a voltage equal to the power supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2, and the negative glitches of the differential nodes D and DN are suppressed without affecting the output signal.

[0065] During time T2, the input signal has a value equal to the ground voltage GND1. Furthermore, during time T2, the ground voltage GND1 experiences a positive spike relative to one or both of the power supply voltage VDD2 and the ground voltage GND2. Additionally, during time T2, the power supply voltage VDD1 experiences a positive spike relative to one or both of the power supply voltage VDD2 and the ground voltage GND2.

[0066] During time T2, since the input signal has a voltage equal to the ground voltage GND1, the differential node DN has a signal equal to the power supply voltage VDD1. Furthermore, due to the positive glitches of the power supply voltage VDD1, the signal at the differential node DN also has positive glitches corresponding to the positive glitches of the power supply voltage VDD1 during time T2.

[0067] During time T2, since the input signal has a voltage equal to the ground voltage GND1, the differential node D has a signal equal to the ground voltage GND1. Furthermore, due to the positive glitches of the ground voltage GND1, the signal at the differential node D also has positive glitches corresponding to the positive glitches of the ground voltage GND1 during time T2.

[0068] Furthermore, during time T2, since the input signal has a voltage equal to the ground voltage GND1, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND2. Additionally, as shown in the figure, positive glitches at differential nodes D and DN are suppressed and do not affect the output signal.

[0069] During time T3, the input signal has a value equal to the power supply voltage VDD1. Furthermore, during time T3, the ground voltage GND1 experiences a positive spike relative to one or both of the power supply voltage VDD2 and the ground voltage GND2. Also, during time T3, the power supply voltage VDD1 experiences a positive spike relative to one or both of the power supply voltage VDD2 and the ground voltage GND2.

[0070] During time T3, since the input signal has a voltage equal to the power supply voltage VDD1, the differential node DN has a signal equal to the ground voltage GND1. Furthermore, due to the positive glitches of the ground voltage GND1, the signal at the differential node DN also has positive glitches corresponding to the positive glitches of the ground voltage GND1 during time T3.

[0071] During time T3, since the input signal has a voltage equal to the supply voltage VDD1, the differential node D has a signal equal to the supply voltage VDD1. Furthermore, due to the positive glitches of the supply voltage VDD1, the signal at the differential node D also has positive glitches corresponding to the positive glitches of the supply voltage VDD1 during time T3.

[0072] Furthermore, during time T3, since the input signal has a voltage equal to the power supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2. Additionally, as shown in the figure, positive glitches at differential nodes D and DN are suppressed and do not affect the output signal.

[0073] During time T4, the input signal has a value equal to the ground voltage GND1. Furthermore, during time T4, the ground voltage GND1 experiences negative glitches relative to one or both of the power supply voltage VDD2 and the ground voltage GND2. Additionally, during time T4, the power supply voltage VDD1 experiences negative glitches relative to one or both of the power supply voltage VDD2 and the ground voltage GND2.

[0074] During time T4, since the input signal has a voltage equal to the ground voltage GND1, the differential node DN has a signal equal to the power supply voltage VDD1. Furthermore, due to the negative glitches of the power supply voltage VDD1, the signal at the differential node DN also has negative glitches corresponding to the negative glitches of the power supply voltage VDD1 during time T4.

[0075] During time T4, since the input signal has a voltage equal to the ground voltage GND1, the differential node D has a signal equal to the ground voltage GND1. Furthermore, due to the negative glitches of the ground voltage GND1, the signal at the differential node D also has negative glitches corresponding to the negative glitches of the ground voltage GND1 during time T4.

[0076] Furthermore, during time T4, since the input signal has a voltage equal to the ground voltage GND1, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND2. Additionally, as shown in the figure, negative glitches at differential nodes D and DN are suppressed and do not affect the output signal.

[0077] Figure 3A schematic diagram of a differential signal generator 100 according to an embodiment is shown. The differential signal generator 100 can be used as a differential signal generator 100 in a signal transmission system 10. In some embodiments, the signal transmission system 10 uses another embodiment of the differential signal generator.

[0078] The differential signal generator 100 includes an inverting circuit 110 and a non-inverting circuit 120. The differential signal generator 100 is configured to receive an input signal at its input terminal IN. Furthermore, the differential signal generator 100 is configured to generate differential signals representing the input signal at differential nodes D and DN. For example, the input signal can be switched between a power supply voltage VDD1 and a ground voltage GND1. Furthermore, in response to the input signal being equal to the power supply voltage VDD1, the non-inverting circuit 120 makes the signal at differential node D equal to the power supply voltage VDD1, and the inverting circuit 110 makes the signal at differential node DN equal to the ground voltage GND1. Similarly, in response to the input signal being equal to the ground voltage GND1, the non-inverting circuit 120 makes the signal at differential node D equal to the ground voltage GND1, and the inverting circuit 110 makes the signal at differential node DN equal to the power supply voltage VDD1.

[0079] Figure 4 A schematic diagram of a glitch management circuit 200 according to an embodiment is shown. The glitch management circuit 200 can be used as a glitch management circuit 200 of a signal transmission system 10. In some embodiments, the signal transmission system 10 uses another embodiment of the glitch management circuit.

[0080] The glitch management circuit 200 includes a first SR (set / reset) latch 210 and a second SR latch 220.

[0081] The first SR latch 210 is configured to receive signals at differential nodes D and DN. Furthermore, the first SR latch 210 is configured to generate intermediate signals at intermediate nodes I and IB based on the received signals. In this embodiment, if the signal at differential node DN is equal to the ground voltage GND1, then the signal at differential node D is equal to the power supply voltage VDD1, making the voltage at intermediate node I equal to the ground voltage GND2 and the voltage at intermediate node IB equal to the power supply voltage VDD2. Furthermore, in this embodiment, if the signal at differential node D is equal to the ground voltage GND1, then the signal at differential node DN is equal to the power supply voltage VDD1, making the voltage at intermediate node IB equal to the ground voltage GND2 and the voltage at intermediate node I equal to the power supply voltage VDD2.

[0082] The second SR latch 220 is configured to receive signals at intermediate nodes I and IB. Furthermore, the second SR latch 220 is configured to generate an output signal at the output terminal OUT based on the received signals. In this embodiment, the signal at intermediate node I is equal to the power supply voltage VDD2, making the voltage of the output signal equal to the ground voltage GND2. Furthermore, in this embodiment, if the signal at intermediate node I is equal to the ground voltage GND2, then the signal at intermediate node IB is equal to the power supply voltage VDD2, making the voltage of the output signal equal to the power supply voltage VDD2. Additionally, glitches in differential nodes D and DN are suppressed and do not affect the output signal.

[0083] Figure 5 The illustration shows an embodiment. Figure 4 A schematic diagram of a set of waveforms representing the operation of the burr management system 200.

[0084] During time T1, the differential node DN has a signal equal to the ground voltage GND1. Furthermore, during time T1, the signal at the differential node DN also exhibits negative glitches.

[0085] During time T1, differential node D has a signal equal to the supply voltage VDD1. Furthermore, during time T1, the signal at differential node D also exhibits negative glitches.

[0086] During time T1, since differential node D has a voltage equal to the supply voltage VDD1, intermediate node IB has a voltage equal to the supply voltage VDD2. Negative glitches at differential node DN do not interfere with the voltage of intermediate node IB because the voltage of intermediate node IB does not change in response to the voltage of differential node DN falling below a threshold. Similarly, negative glitches at differential node D do not interfere with the voltage of intermediate node IB because the voltage of intermediate node IB does not change in response to the voltage of differential node D falling below a threshold. Conversely, the voltage of intermediate node IB will change in response to the voltage of differential node DN becoming greater than a threshold.

[0087] During time T1, since differential node D has a voltage equal to the supply voltage VDD1, intermediate node I has a voltage equal to the ground voltage GND2. Negative glitches at differential node DN do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to the voltage of differential node DN falling below a threshold. Similarly, negative glitches at differential node D do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to the voltage of differential node D falling below a threshold. Conversely, the voltage of intermediate node I will change in response to the voltage of differential node DN becoming greater than a threshold while the voltage of differential node D falls below a threshold.

[0088] Furthermore, during time T1, since the intermediate node IB has a voltage equal to the power supply voltage VDD2, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2.

[0089] During time T2, the differential node DN has a signal equal to the supply voltage VDD1. Furthermore, during time T2, the signal at the differential node DN also exhibits positive glitches.

[0090] During time T2, differential node D has a signal equal to the ground voltage GND1. Furthermore, during time T2, the signal at differential node D also exhibits positive glitches.

[0091] During time T2, since differential node DN has a voltage equal to the supply voltage VDD1, intermediate node IB has a voltage equal to the ground voltage GND2. A positive glitch at differential node DN will not interfere with the voltage of intermediate node IB because the voltage of intermediate node IB will not change in response to the voltage of differential node DN being greater than the supply voltage VDD2. A positive glitch at differential node D will not interfere with the voltage of intermediate node IB because the voltage of intermediate node IB will not change in response to the voltage of differential node D being greater than a threshold voltage while the voltage of differential node DN is also greater than a threshold voltage. Conversely, the voltage of intermediate node IB will change in response to the voltage of differential node D becoming greater than a threshold voltage while the voltage of differential node DN is less than a threshold voltage.

[0092] During time T2, since differential node DN has a voltage equal to the supply voltage VDD1, intermediate node I has a voltage equal to the supply voltage VDD2. Positive glitches at differential node DN do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to the voltage of differential node DN being greater than the supply voltage VDD2. Positive glitches at differential node D do interfere with the voltage of intermediate node I because the voltage of intermediate node I changes in response to the voltage of differential node D being greater than a threshold voltage while the voltage of differential node DN is also greater than a threshold voltage.

[0093] Furthermore, during time T2, since intermediate node I has a voltage equal to the power supply voltage VDD2, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND2.

[0094] During time T3, the differential node DN has a signal equal to the ground voltage GND1. Furthermore, during time T3, the signal at the differential node DN also exhibits positive glitches.

[0095] During time T3, differential node D has a signal equal to the supply voltage VDD1. Furthermore, during time T3, the signal at differential node D also exhibits positive glitches.

[0096] During time T3, since differential node D has a voltage equal to the supply voltage VDD1, intermediate node IB has a voltage equal to the supply voltage VDD2. Positive glitches at differential node DN interfere with the voltage of intermediate node IB because the voltage of intermediate node IB changes in response to the voltage of differential node DN exceeding a threshold. Positive glitches at differential node D do not interfere with the voltage of intermediate node IB because the voltage of intermediate node IB does not change in response to the voltage of differential node D exceeding the supply voltage VDD2.

[0097] During time T3, since differential node D has a voltage equal to the supply voltage VDD1, intermediate node I has a voltage equal to the ground voltage GND2. Positive glitches at differential node DN do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to both the voltage of differential node DN and the voltage of differential node D exceeding a threshold. Positive glitches at differential node D do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to both the voltage of differential node DN and the voltage of differential node D exceeding a threshold.

[0098] Furthermore, during time T3, since the intermediate node IB has a voltage equal to the power supply voltage VDD2, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2.

[0099] During time T4, the differential node DN has a signal equal to the supply voltage VDD1. Furthermore, during time T4, the signal at the differential node DN also exhibits negative glitches.

[0100] During time T4, differential node D has a signal equal to the ground voltage GND1. Furthermore, during time T4, the signal at differential node D also exhibits negative glitches.

[0101] During time T4, since the differential node DN has a voltage equal to the supply voltage VDD1, the intermediate node IB has a voltage equal to the ground voltage GND2. Negative glitches at the differential node DN do not interfere with the voltage of the intermediate node IB because the voltage of the intermediate node IB does not change in response to the voltage of the differential node DN falling below a threshold. Similarly, negative glitches at the differential node D do not interfere with the voltage of the intermediate node IB because the voltage of the intermediate node IB does not change in response to the voltage of the differential node D falling below a threshold.

[0102] During time T4, since differential node DN has a voltage equal to the supply voltage VDD1, intermediate node I has a voltage equal to the supply voltage VDD2. Negative glitches at differential node DN do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to the voltage of differential node DN falling below a threshold. Negative glitches at differential node D do not interfere with the voltage of intermediate node I because the voltage of intermediate node I does not change in response to the voltage of differential node D falling below a threshold. Conversely, the voltage of intermediate node I will change in response to the voltage of differential node DN becoming greater than a threshold while the voltage of differential node D falls below a threshold.

[0103] Furthermore, during time T4, since intermediate node I has a voltage equal to the power supply voltage VDD2, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND2.

[0104] Figure 6 A schematic diagram of a signal transmission system 20 according to an embodiment is shown. As discussed in further detail below, the signal transmission system 20 transmits a signal from a first power domain to a second power domain. The first power domain includes a power supply voltage VDD1 and a ground voltage GND. The second power domain includes a power supply voltage VDD2 and a ground voltage GND. Due to glitches as understood by those skilled in the art, the voltage of the power supply voltage VDD1 may temporarily change or have glitches relative to one or both of the voltages of the power supply voltage VDD2 and the ground voltage GND.

[0105] Glitches can be caused by events that directly affect the supply voltage VDD1. For example, ESD events, noise, or power bounce may occur at the supply voltage VDD1 node. Similarly, glitches can be caused by events that directly affect the supply voltage VDD2. For example, ESD events, noise, or power bounce may occur at the supply voltage VDD2 node.

[0106] In some embodiments, one or more coupling capacitors (not shown) may be placed across the power supply voltage VDD1 and the ground voltage GND. The purpose of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between the power supply voltage VDD1 and the ground voltage GND.

[0107] In some embodiments, one or more coupling capacitors (not shown) may be placed across the power supply voltage VDD2 and the ground voltage GND. The function of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between the power supply voltage VDD2 and the ground voltage GND2.

[0108] In some embodiments, one or more coupling capacitors (not shown) may be placed across power supply voltages VDD1 and VDD2. The purpose of the coupling capacitors is to reduce glitches caused by changes in the voltage difference between power supply voltages VDD1 and VDD2.

[0109] In some embodiments with one or more coupling capacitors, the coupling capacitors reduce but do not eliminate glitches, thus enabling the circuit techniques discussed herein to advantageously prevent glitches from affecting sensitive circuit systems.

[0110] The signal transmission system 20 is configured to receive an input signal at input terminal IN and transmit a digital representation of the input signal as an output signal to output terminal OUT. In some embodiments, output terminal OUT is connected to one or more circuits that are sensitive to glitches that may occur in the output signal.

[0111] In some embodiments, the output signal represents a reset signal. For example, the input signal may be generated as a reset signal by a power management circuit, where the output signal can reset a microcontroller connected to the output terminal OUT. Therefore, unexpected glitches in the output signal may cause the microcontroller to reset unintentionally.

[0112] In some embodiments, the output signal represents an asynchronous signal, such as a mode control signal. For example, the input signal may be generated as a mode control signal by control circuitry, wherein the output signal can cause processing circuitry connected to the output terminal OUT to operate according to different modes. Therefore, unexpected glitches in the output signal may cause the processing circuitry to unintentionally change the mode.

[0113] In some embodiments, the output signal represents a clock signal. For example, the input signal can be generated into a clock signal by a clock generation circuit, wherein the output signal can cause processing circuitry connected to the output terminal OUT to operate according to the clock signal. Therefore, unexpected glitches in the output signal may cause the processing circuitry to malfunction.

[0114] In some embodiments, the output signal represents another signal, wherein an unexpected glitch in the output signal may cause the circuit connected to the output terminal OUT to malfunction.

[0115] The signal transmission system 20 includes a differential signal generator 100 and a glitch management circuit 300.

[0116] Differential signal generator 100 and Figure 1The differential signal generator 100 is similar to or identical to the differential signal generator 100. Therefore, the differential signal generator 100 is configured to receive the input signal at the input terminal IN. Furthermore, the differential signal generator 100 is configured to generate differential signals representing the input signal at differential nodes D and DN. Additionally, glitches may cause glitches in the signals at differential nodes D and DN.

[0117] The glitch management circuit 300 is configured to receive signals at differential nodes D and DN, and generate an output signal at the output terminal OUT based on the received signals, wherein the output signal can transition between the power supply voltage VDD2 and the ground voltage GND2. For example, in response to the signal at differential node D being equal to the power supply voltage VDD1 and the signal at differential node DN being equal to the ground voltage GND1, the glitch management circuit 300 can be configured to make the output signal at the output terminal OUT equal to the power supply voltage VDD2. Furthermore, in response to the signal at differential node D being equal to the ground voltage GND1 and the signal at differential node DN being equal to the power supply voltage VDD1, the glitch management circuit 300 can be configured to make the output signal at the output terminal OUT equal to the ground voltage GND2.

[0118] Furthermore, the glitch management circuit 300 is configured to ensure that the output signal at the output terminal OUT is continuous or unaffected by glitches generated in the signals at the differential nodes D and DN.

[0119] Figure 7 The illustration shows an embodiment. Figure 6 A schematic diagram of a set of waveforms representing the operation of the signal transmission system 20.

[0120] During time T1, the input signal has a value equal to the supply voltage VDD1. Furthermore, during time T1, the supply voltage VDD1 experiences negative glitches relative to one or both of the supply voltage VDD2 and the ground voltage GND.

[0121] During time T1, since the input signal has a voltage equal to the supply voltage VDD1, the differential node DN has a signal equal to the ground voltage GND. Furthermore, since the input signal has a voltage equal to the supply voltage VDD1, the differential node D also has a signal equal to the supply voltage VDD1. Additionally, due to the negative glitches of the supply voltage VDD1, during time T1, the signal at the differential node D also has negative glitches corresponding to the negative glitches of the supply voltage VDD1.

[0122] Furthermore, during time T1, since the differential signal D has a voltage equal to the power supply voltage VDD1 and the differential signal DN has a voltage equal to the ground voltage GND, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2. Additionally, as shown in the figure, negative glitches at the differential node D are suppressed and do not affect the output signal.

[0123] Therefore, during time T1, since the input signal has a voltage equal to the power supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2, and the negative glitches at the differential node D are suppressed and do not affect the output signal.

[0124] During time T2, the input signal has a value equal to the ground voltage GND. Furthermore, during time T2, the power supply voltage VDD1 experiences a positive spike relative to one or both of the power supply voltage VDD2 and the ground voltage GND.

[0125] During time T2, since the input signal has a voltage equal to the ground voltage GND, the differential node DN has a signal equal to the supply voltage VDD1. Furthermore, due to the positive glitches of the supply voltage VDD1, the signal at the differential node DN also has positive glitches corresponding to the positive glitches of the supply voltage VDD1 during time T2.

[0126] During time T2, since the input signal has a voltage equal to the ground voltage GND, the differential node D has a signal equal to the ground voltage GND. Furthermore, positive glitches in the power supply voltage VDD1 do not affect the signal at the differential node D.

[0127] Furthermore, during time T2, since the differential signal D has a voltage equal to the ground voltage GND and the differential signal DN has a voltage equal to the power supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND2. Additionally, as shown in the figure, positive glitches at the differential node DN are suppressed and do not affect the output signal.

[0128] Therefore, during time T2, since the input signal has a voltage equal to the ground voltage GND, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND, and the positive glitches of the differential node DN are suppressed and do not affect the output signal.

[0129] During time T3, the input signal has a value equal to the supply voltage VDD1. Furthermore, during time T3, the supply voltage VDD1 experiences a positive spike relative to one or both of the supply voltage VDD2 and the ground voltage GND.

[0130] During time T3, since the input signal has a voltage equal to the supply voltage VDD1, the differential node DN has a signal equal to the ground voltage GND. Furthermore, since the input signal has a voltage equal to the supply voltage VDD1, the differential node D also has a signal equal to the supply voltage VDD1. Additionally, due to the positive glitches of the supply voltage VDD1, during time T3, the signal at the differential node D also has positive glitches corresponding to the positive glitches of the supply voltage VDD1.

[0131] Furthermore, during time T3, since the differential signal D has a voltage equal to the power supply voltage VDD1 and the differential signal DN has a voltage equal to the ground voltage GND, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2. Additionally, as shown in the figure, positive glitches at the differential node D are suppressed and do not affect the output signal.

[0132] Therefore, during time T3, since the input signal has a voltage equal to the power supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the power supply voltage VDD2, and the positive glitches at the differential node D are suppressed and do not affect the output signal.

[0133] During time T4, the input signal has a value equal to the ground voltage GND. Furthermore, during time T4, the power supply voltage VDD1 experiences a negative spike relative to one or both of the power supply voltage VDD2 and the ground voltage GND.

[0134] During time T4, the input signal has a voltage equal to the ground voltage GND, and the differential node DN has a signal equal to the power supply voltage VDD1. Furthermore, due to the negative glitches of the power supply voltage VDD1, the signal at the differential node DN also has negative glitches corresponding to the negative glitches of the power supply voltage VDD1 during time T4.

[0135] During time T4, since the input signal has a voltage equal to the ground voltage GND, the differential node D has a signal equal to the ground voltage GND. Furthermore, negative glitches in the power supply voltage VDD1 do not affect the signal at the differential node D.

[0136] Furthermore, during time T4, since the differential signal D has a voltage equal to the ground voltage GND and the differential signal DN has a voltage equal to the power supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND2. Additionally, as shown in the figure, negative glitches at the differential node DN are suppressed and do not affect the output signal.

[0137] Therefore, during time T4, since the input signal has a voltage equal to the ground voltage GND, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND, and the negative glitches of the differential node DN are suppressed and do not affect the output signal.

[0138] Figure 8 A schematic diagram of a glitch management circuit 300 according to an embodiment is shown. The glitch management circuit 300 can be used as a glitch management circuit 300 of a signal transmission system 20. In some embodiments, the signal transmission system 20 uses another embodiment of the glitch management circuit.

[0139] The glitch management circuit 300 includes an SR latch 310.

[0140] SR latch 310 is configured to receive signals at differential nodes D and DN. Furthermore, SR latch 310 is configured to generate an output signal at output terminal OUT based on the received signals. In this embodiment, the signal at differential node D is equal to the power supply voltage VDD1, causing the voltage at the output signal at output terminal OUT to be equal to the ground voltage GND2. Additionally, in this embodiment, if the signal at differential node D is equal to the ground voltage GND1, then the signal at differential node DN is equal to the power supply voltage VDD1, causing the voltage at the output signal at output terminal OUT to be equal to the power supply voltage VDD2.

[0141] Figure 9 A schematic diagram of a set of waveforms is shown, illustrating an embodiment. Figure 8 Operation of the burr management system 300.

[0142] During time T1, the differential node DN has a signal equal to the ground voltage GND.

[0143] During time T1, differential node D has a signal equal to the supply voltage VDD1. Furthermore, during time T1, the signal at differential node D also exhibits negative glitches.

[0144] During time T1, since differential node D has a voltage equal to the supply voltage VDD1, the output signal at output terminal OUT has a voltage equal to the supply voltage VDD2. Negative glitches at differential node D will not interfere with the output signal voltage at output terminal OUT because the output signal voltage at output terminal OUT will not change in response to the voltage of differential node D falling below a threshold. Conversely, the output signal voltage at output terminal OUT will change in response to the voltage of differential node DN becoming greater than the threshold.

[0145] During time T2, the differential node DN has a signal equal to the supply voltage VDD1. Furthermore, during time T2, the signal at the differential node DN also exhibits positive glitches.

[0146] During time T2, differential node D has a signal equal to the ground voltage GND.

[0147] During time T2, since the differential node DN has a voltage equal to the supply voltage VDD1, the output signal at output terminal OUT has a voltage equal to the ground voltage GND. Positive glitches in the differential node DN will not interfere with the output signal voltage at output terminal OUT because the output signal voltage at output terminal OUT will not change in response to the voltage of the differential node DN being greater than the supply voltage VDD2. Conversely, the output signal voltage at output terminal OUT will change in response to the voltage of the differential node D becoming greater than a threshold and the voltage of the differential node DN becoming less than a threshold.

[0148] During time T3, the differential node DN has a signal equal to the ground voltage GND.

[0149] During time T3, differential node D has a signal equal to the supply voltage VDD1. Furthermore, during time T3, the signal at differential node D also exhibits positive glitches.

[0150] During time T3, since differential node D has a voltage equal to the supply voltage VDD1, the output signal at output terminal OUT has a voltage equal to the supply voltage VDD2. Positive glitches at differential node D will not interfere with the voltage of the output signal at output terminal OUT because the voltage of the output signal at output terminal OUT will not change in response to the voltage of differential node D being greater than the supply voltage VDD2.

[0151] During time T4, the differential node DN has a signal equal to the supply voltage VDD1. Furthermore, during time T4, the signal at the differential node DN also exhibits negative glitches.

[0152] During time T4, differential node D has a signal equal to the ground voltage GND.

[0153] During time T4, since the differential node DN has a voltage equal to the supply voltage VDD1, the output signal at the output terminal OUT has a voltage equal to the ground voltage GND. Negative glitches in the differential node DN will not interfere with the voltage of the output signal at the output terminal OUT because the voltage of the output signal at the output terminal OUT will not change in response to the voltage of the differential node DN falling below a threshold.

[0154] Figure 10A schematic diagram of an SR latch 400 according to an embodiment is shown. The SR latch 400 can be used as each of the first and second SR latches 210 and 220 of the glitch management circuit 200. In some embodiments, the glitch management circuit 200 uses another embodiment of the SR latch. The SR latch 400 can be used as an SR latch of the glitch management circuit 300. In some embodiments, the glitch management circuit 300 uses another embodiment of the SR latch.

[0155] The SR latch 400 includes first and second NOR gates 410 and 420. As understood by those skilled in the art, the SR latch 400 operates according to standard digital logic principles. Therefore, a high voltage input node S causes output node QB to go low, and a high voltage input node R causes output node Q to go low. Furthermore, a high voltage at input node S and a low voltage at input node R causes output node Q to go high and output node QB to go low. Conversely, a low voltage at input node S and a high voltage at input node R causes output node Q to go low and output node QB to go high. Moreover, a low voltage at input node S and a low voltage at input node R maintains the output states of output nodes Q and QB.

[0156] The embodiments and implementations discussed herein are not intended to be an exhaustive explanation of the principles and aspects of this disclosure. Therefore, alternative embodiments can be implemented using principles known to those skilled in the art. For example, alternative circuit embodiments may be implemented using one or more inverters or buffers to regulate various signals. In some embodiments, different latch architectures are used in conjunction with corresponding signal polarity management using one or more inverters. For example, a cross-coupled NAND SR latch may be used instead of the illustrated NOR SR latch.

[0157] In some embodiments, the power supply voltage VDD1 may be equal to, approximately equal to, or substantially equal to the power supply voltage VDD2. In some embodiments, the power supply voltage VDD1 is not equal to the power supply voltage VDD2. In some embodiments, the power supply voltage VDD1 is greater than the power supply voltage VDD2. In some embodiments, the power supply voltage VDD2 is greater than the power supply voltage VDD1.

[0158] In some embodiments, the ground voltage GND1 may be equal to, approximately equal to, or substantially equal to the ground voltage GND2. In some embodiments, the ground voltage GND1 is not equal to the ground voltage GND2. In some embodiments, the ground voltage GND1 is greater than the ground voltage GND2. In some embodiments, the ground voltage GND2 is greater than the ground voltage GND1.

[0159] In some embodiments, the voltage difference between the power supply voltage VDD1 and the ground voltage GND1 may be equal to, approximately equal to, or substantially equal to the voltage difference between the power supply voltage VDD2 and the ground voltage GND2. In some embodiments, the voltage difference between the power supply voltage VDD1 and the ground voltage GND1 is not equal to the voltage difference between the power supply voltage VDD2 and the ground voltage GND2. In some embodiments, the voltage difference between the power supply voltage VDD1 and the ground voltage GND1 is greater than the voltage difference between the power supply voltage VDD2 and the ground voltage GND2. In some embodiments, the voltage difference between the power supply voltage VDD1 and the ground voltage GND1 is less than the voltage difference between the power supply voltage VDD2 and the ground voltage GND2.

[0160] In the foregoing description and claims, phrases such as “at least one” or “one or more” may appear after a list of combinations of elements or features. The term “and / or” may also appear in a list of two or more elements or features. Unless implied or explicitly contradicted by the context in which it is used, such phrases are intended to mean any element or feature listed individually or in combination with any other listed element or feature. For example, the phrases “at least one of A and B”; “one or more of A and B”; and “A and / or B” are intended to mean “A alone, B alone, or A and B together”, respectively. Similar interpretations are also intended for lists comprising three or more items. For example, the phrases “at least one of A, B, and C”; “one or more of A, B, and C”; and “A, B, and / or C” are intended to mean “A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together”, respectively. The term “based on” as used in the foregoing and claims is intended to mean “at least partially based on”, such that features or elements not listed are also permitted.

[0161] The subject matter described herein can be implemented in systems, apparatus, methods, and / or articles according to desired configurations. The embodiments set forth in the foregoing description do not represent all embodiments consistent with the subject matter described herein. Rather, they are merely some examples consistent with aspects related to the described subject matter. Although some variations have been described in detail above, other modifications or additions are possible. In particular, further features and / or variations may be provided in addition to those set forth herein. For example, the above embodiments may involve various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of several additional features disclosed above. Furthermore, the logical flows depicted in the drawings and / or described herein do not necessarily require the specific order or sequential order shown to achieve the desired results. Other embodiments are within the scope of the following claims.

Claims

1. An electronic system comprising: a differential signal generator comprising one or more differential signal generator components collectively configured to receive an input signal and generate a first single-ended signal and a second single-ended signal based on the input signal, wherein the first single-ended signal and the second single-ended signal have opposite polarities, wherein the input signal transitions between a first supply voltage and a first ground voltage, and wherein each of the first single-ended signal and the second single-ended signal transitions between the first supply voltage and the first ground voltage; and a glitch management circuit comprising one or more glitch management components collectively configured to receive the first single-ended signal and the second single-ended signal and generate an output signal based on the first single-ended signal and the second single-ended signal, wherein the output signal transitions between a second supply voltage and a second ground voltage, wherein the glitch management circuit comprises: a first latch configured to receive the first single-ended signal and the second single-ended signal and generate a first intermediate signal and a second intermediate signal based on the first single-ended signal and the second single-ended signal, wherein the first intermediate signal and the second intermediate signal each transition between the second supply voltage and the second ground voltage, and a second latch configured to receive the first intermediate signal and the second intermediate signal and generate the output signal based on the first intermediate signal and the second intermediate signal.

2. The electronic system of claim 1, wherein, At least one of: A) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the first single-ended signal has a first signal glitch, and wherein the glitch management circuit is configured to suppress the first signal glitch; and B) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the second single-ended signal has a second signal glitch, and wherein the glitch management circuit is configured to suppress the second signal glitch.

3. The electronic system of claim 1, wherein, At least one of: A) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the first single-ended signal has a first signal glitch and a second signal glitch, wherein the first signal glitch and the second signal glitch have opposite polarities, and wherein the glitch management circuit is configured to suppress the first signal glitch and the second signal glitch; and B) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the second single-ended signal has a first signal glitch and a second signal glitch, wherein the first signal glitch and the second signal glitch have opposite polarities, and wherein the glitch management circuit is configured to suppress the first signal glitch and the second signal glitch. B) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the second single-ended signal has a third signal glitch and a fourth signal glitch, wherein the third signal glitch and the fourth signal glitch have opposite polarities, and wherein the glitch management circuit is configured to suppress the third signal glitch and the fourth signal glitch.

4. The electronic system of claim 3, wherein, the first latch is configured to receive the first signal glitch, the second signal glitch, the third signal glitch, and the fourth signal glitch, propagate the first signal glitch to the second intermediate signal, propagate the third signal glitch to the first intermediate signal, and suppress the second signal glitch and the fourth signal glitch such that the second signal glitch and the fourth signal glitch do not propagate to the first intermediate signal and the second intermediate signal, wherein the first signal glitch and the third signal glitch have a same first polarity, and wherein the second signal glitch and the fourth signal glitch have a same second polarity.

5. The electronic system of claim 4, wherein, the second latch is configured to receive the propagated first signal glitch and the propagated third signal glitch from the first latch, and to suppress the propagated first signal glitch and the propagated third signal glitch such that the propagated first signal glitch and the propagated third signal glitch do not further propagate to the output signal.

6. The electronic system of claim 1, wherein, the differential signal generator includes: an inverting signal path configured to receive the input signal and generate the first single-ended signal based on the input signal, wherein the first single-ended signal and the input signal have opposite polarities; and a non-inverting signal path configured to receive the input signal and generate the second single-ended signal based on the input signal, wherein the second single-ended signal and the input signal have a same polarity.

7. The electronic system of claim 1, wherein, the first latch includes a first SR set / reset SR latch, and wherein the second latch includes a second SR latch.

8. The electronic system of claim 1, wherein, the first supply voltage and the second supply voltage are different.

9. The electronic system of claim 1, wherein, the first supply voltage and the second supply voltage are substantially equal.

10. The electronic system of claim 1, wherein the first ground voltage and the second ground voltage are different.

11. The electronic system of claim 1, wherein the first ground voltage and the second ground voltage are substantially equal.

12. A method of using an electronic system, the electronic system including a differential signal generator and a glitch management circuit, the method comprising: receiving, with one or more differential signal generator components of the differential signal generator, an input signal; generating, with the differential signal generator component, first and second single-ended signals based on the input signal, wherein the first and second single-ended signals have opposite polarities, wherein the input signal transitions between a first supply voltage and a first ground voltage, and wherein each of the first and second single-ended signals transitions between the first supply voltage and the first ground voltage; receiving, with one or more glitch management components, the first and second single-ended signals; and generating, with the glitch management components, an output signal based on the first and second single-ended signals, wherein the output signal transitions between a second supply voltage and a second ground voltage, wherein the glitch management circuit comprises: a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals based on the first and second single-ended signals, wherein the first and second intermediate signals each transition between the second supply voltage and the second ground voltage; and a second latch configured to receive the first and second intermediate signals and generate the output signal based on the first and second intermediate signals.

13. The method of claim 12, wherein, At least one of the following: A) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the first single-ended signal has a first signal glitch, and wherein the method further comprises suppressing the first signal glitch with the glitch management circuit; B) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the second single-ended signal has a second signal glitch, and wherein the method further comprises suppressing the second signal glitch with the glitch management circuit.

14. The method of claim 12, wherein, At least one of the following: A) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the first single-ended signal has a first signal glitch and a second signal glitch, wherein the first and second signal glitches have opposite polarities, and wherein the method further comprises suppressing the first and second signal glitches with the glitch management circuit; and B) as a result of one or both of the first supply voltage and the first ground voltage changing relative to one or both of the second supply voltage and the second ground voltage, the second single-ended signal has a third signal glitch and a fourth signal glitch, wherein the third and fourth signal glitches have opposite polarities, and wherein the method further comprises suppressing the third and fourth signal glitches with the glitch management circuit.

15. The method of claim 14, wherein, The first latch is configured to receive the first signal glitch, the second signal glitch, the third signal glitch, and the fourth signal glitch, propagate the first signal glitch to the second intermediate signal, propagate the third signal glitch to the first intermediate signal, and suppress the second signal glitch and the fourth signal glitch such that the second signal glitch and the fourth signal glitch do not propagate to the first intermediate signal and the second intermediate signal, wherein the first signal glitch and the third signal glitch have a same first polarity, and wherein the second signal glitch and the fourth signal glitch have a same second polarity.

16. The method of claim 15, wherein, The second latch is configured to receive the propagated first signal glitch and the third signal glitch from the first latch, and to suppress the propagated first signal glitch and the third signal glitch such that the propagated first signal glitch and the third signal glitch do not further propagate to the output signal.

17. The method of claim 12, wherein, The differential signal generator comprises: a non-inverting signal path configured to receive the input signal and generate the first single-ended signal based on the input signal, wherein the first single-ended signal and the input signal have a same polarity; and an inverting signal path configured to receive the input signal and generate the second single-ended signal based on the input signal, wherein the second single-ended signal and the input signal have opposite polarities.

18. The method of claim 12, wherein, The first latch comprises a first set / reset (SR) latch, and wherein the second latch comprises a second SR latch.

19. The method of claim 12, wherein, The first supply voltage and the second supply voltage are different.

20. The method of claim 12, wherein, The first supply voltage and the second supply voltage are substantially equal.

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