A data allocation method for multi-core embedded system based on variable scratch pad memory

Abstract

The present invention relates to a data allocation method for a multi-core embedded system based on a variable scratch pad memory, and belongs to the field of computers. The method is as follows: S1: an embedded application is divided into a plurality of program areas, a data flow diagram between program areas is generated at the same time, and program areas with the same depth in the data flow diagram are combined into a parallel area set; S2: before each parallel area set is executed, the number of single-layer units and multi-layer units of the variable scratch pad storage in the multi-core embedded system is dynamically adjusted to explore the optimal ratio of SLC / MLC; S3: based on the above given optimal ratio, the memory access information of the program area data variables in the parallel area set is considered, and a corresponding data allocation optimization method is designed to allocate the best storage medium to each program area variable, so that the data memory access overhead in the multi-core embedded system is minimized. The present invention can be implemented at the software compilation layer, with low time and energy overhead and good scalability.

Description

Technical Field

[0001] The invention belongs to the field of computers and relates to a data distribution method based on a variable scratchpad memory multi-core embedded system. Background Art

[0002] Embedded multi-core systems are essential to meet the growing performance requirements of high-performance applications such as edge computing, smart cities, and smart manufacturing. Traditional scratch pad memory (SPM) is a software-controlled on-chip memory based on static random access memory (SRAM). With its outstanding advantages of low latency, low power consumption, and small size, it has gradually replaced the hardware-controlled cache in embedded systems and become the mainstream embedded on-chip memory. However, traditional SRAM-based SPM has low power consumption and limited capacity, which may accelerate the consumption of limited resources and reduce the performance of embedded multi-core systems. Therefore, in order to reduce storage overhead and improve the performance of embedded systems, a new generation of non-volatile memory (NVM) is needed to replace SRAM in SPM.

[0003] NVM has significant advantages such as fast memory processing speed, large external memory capacity, storage persistence, low static power consumption, and no data loss after power failure. It has attracted strong attention from researchers and has entered the productization stage. Among them, the storage modes of typical NVMs such as spin transfer torque memory (STT-RAM) and phase change memory (PCM) that uses electrical differences to store data can be dynamically switched between single-layer cell mode (SLC) and multi-layer cell mode (MLC). NVM cells in MLC mode enable high-density memory chips to store multiple bits of data in limited resource embedded systems, but compared with NVM cells in SLC mode, it has higher latency and greater access energy overhead. Therefore, it is necessary to combine the advantages of the two storage modes in NVM and construct a scratch pad memory based on "variable NVM" for use in multi-core embedded systems to optimize the performance and overhead of multi-core embedded systems.

[0004] At present, there have been many studies that use the high access performance of SLC in NVM and the high storage density of MLC to complement each other, so as to achieve a balance between storage capacity and access delay, in order to deal with the "memory" problem. However, these works are all proposed at the level of system memory to replace traditional dynamic random access memory, and cannot be effectively applied to scratch pad memory. There are also works that propose the use of variable SPM in single-core systems, but the performance of single-core systems is far inferior to that of multi-core embedded systems. Therefore, the present invention proposes a data allocation optimization scheme under multi-core embedded systems based on variable SPM, so as to make full use of the advantages of NVM in different storage mode states to improve the performance of multi-core embedded systems and reduce their overhead. Summary of the invention

[0005] In view of this, the object of the present invention is to provide a data allocation method for a multi-core embedded system based on a variable scratch pad memory. The ratio of the number of SLC / MLC units in the SPM is dynamically changed according to different workloads in the program, the optimal ratio is found, and the optimal data allocation is generated for all data in the program area, so as to improve the performance of the multi-core embedded system and reduce its time and energy overhead.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A data allocation method for a multi-core embedded system based on a variable scratchpad memory, the method comprising the following steps:

[0008] S1: Divide the embedded application into multiple program regions, generate data flow graphs between program regions simultaneously, and combine program regions with the same depth in the data flow graph into parallel region sets;

[0009] S2: Before each parallel region set is executed, the number of single-level cells (SLC) and multi-level cells (MLC) of the variable scratch pad storage (SPM) in the multi-core embedded system is dynamically adjusted to find the optimal ratio of SLC / MLC;

[0010] S3: Based on the given optimal ratio, the memory access information of the program area data variables in the parallel area is comprehensively considered, and the corresponding data allocation optimization method is designed to allocate the best storage medium to each program area variable, so as to minimize the data memory access overhead in the multi-core embedded system.

[0011] Optionally, in S2, for each parallel region set, searching for the optimal ratio of SLC / MLC sizes in the variable scratch pad memory specifically comprises the following steps:

[0012] S21: Assume that in a multi-core embedded system, the number of SPM units corresponding to the cth core is SSPM c ; The space size of the kth storage medium is S k , the number of units is M k , if k = 0, it means the storage medium is DRAM, if k = 2c-1, it means the storage medium is SLCSPM corresponding to the c-th core, if k = 2c, it means the storage medium is MLCSPM corresponding to the c-th core; the initial state of all SPM units is single-layer unit SLC, initialize the area to store all its data variables and the minimum overhead value tc of SLC / MLC mode conversion p is infinite;

[0013] S22: Explore the SLC / MLC ratio of each SPM one by one, and call the data allocation optimization algorithm described in step S3. If the obtained memory access overhead plus the SLC / MLC mode conversion overhead is less than tc p , then update tc p and record its data allocation scheme;

[0014] S23: Selecting the SLC / MLC ratio with the minimum memory access overhead as the optimal SLC / MLC ratio of the parallel region.

[0015] Optionally, in S3, the local data allocation optimal optimization algorithm specifically includes the following steps:

[0016] S31: Use c i,k Record the cost of storing the i-th variable in storage medium k,

[0017]

[0018] Assume that the rth region block in the pth parallel region set is executed on the rth core, where cw k is the overhead of reading data in storage medium k, cr k is the overhead of writing data in storage medium k; cwl is the reduction of local access write overhead compared with remote access; crl is the reduction of local access read overhead compared with remote access; w p,r,i is the cost of reading the i-th variable in the r-th region block in the parallel region set p; r p,r,d is the cost of writing the i-th variable in the r-th region block in the parallel region set p;

[0019] S32: Establish a recursive function c[i,s1,s2,…,s K ], find the minimum memory access cost after the i-th variable is stored, where s k is the remaining space size of the kth SPM after the i-th variable is stored in the parallel region;

[0020] S33: Assuming that all variables in the parallel region set are first stored in DRAM, then:

[0021] S34: Establish a recursive relationship for data allocation, where size i is the size of the i-th variable;

[0022]

[0023] S34: Obtain the best data allocation solution and the minimum data access memory overhead through program recursion.

[0024] The beneficial effects of the present invention are as follows: based on a variable scratch pad memory in a multi-core embedded system, the present invention proposes a corresponding data allocation method, which can be implemented at the software compilation layer, can simultaneously reduce the data access energy consumption and access delay of the memory, and has good scalability.

[0025] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0027] Figure 1 The hardware architecture of the variable scratch pad memory in the multi-core embedded system of the present invention;

[0028] Figure 2 This is an example of dividing a program into multiple parallel regions according to the present invention;

[0029] Figure 3 A flow chart of an algorithm for allocating a variable scratch pad memory SLC / MLC size ratio and global optimal data allocation in a multi-core embedded system according to the present invention;

[0030] Figure 4 This is a flow chart of data allocation optimization in the program area under the specific SLC / MLC size ratio described in the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0032] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0033] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0034] The data allocation optimization method of a multi-core embedded system based on a variable scratch pad memory described in the present invention specifically comprises the following steps:

[0035] S1: Divide the embedded application into multiple program regions, generate data flow graphs between program regions simultaneously, and combine program regions with the same depth in the data flow graph into parallel region sets;

[0036] S2: Before each parallel region set is executed, the number of single-level cells (SLC) and multi-level cells (MLC) of the Variable Pad Memory (SPM) in the multi-core embedded system is dynamically adjusted to find the optimal ratio of SLC / MLC;

[0037] S3: Based on the optimal ratio given above, the memory access information of the program area data variables in the parallel area is comprehensively considered, and a corresponding data allocation optimization method is designed to allocate the best storage medium to each program area variable, so as to minimize the data memory access overhead in the multi-core embedded system.

[0038] Figure 1 The hardware model of the variable scratch pad memory in the multi-core embedded system of the present invention is as follows: Figure 1 As shown in the figure, a single chip includes multiple cores, and each core is equipped with an on-chip morphable SPM to replace the traditional hardware-controlled cache. Each core can directly access its local SPM, which is called local access. At the same time, each core can also indirectly access the remote SPM (i.e., the local SPM of other cores) through the interconnecting bus, which is called remote access. In addition, DRAM is used as off-chip main memory, and then a corresponding data allocation optimization method is proposed under this architecture. First, the program is divided into multiple parallel region sets, such as Figure 2As shown. Regions are divided according to program points. The determination method of program points is as follows: 1) the entry and exit of each internal program; 2) the beginning and end of each loop body; 3) the beginning and end of each judgment statement. Then, according to the divided parallel regions, the program static analysis technology is used to count the number, size and number of read and write operations of data variables in each parallel region, and the relationship between data is represented by a data flow graph (DFG). Secondly, according to the variable information in each region of the program, the size of the variable scratch pad memory SLC / MLC is dynamically adjusted. Finally, the optimal address space is dynamically allocated to the variables in each region to minimize the memory access overhead of the entire program.

[0039] like Figure 3 As shown, before each parallel region is executed, the number of cells in the single-layer storage mode and the multi-layer storage mode in the variable scratch pad memory in the multi-core embedded system is dynamically adjusted according to the data variable information of the region, and the process of exploring the optimal ratio of the number of SLC / MLC cells in the SPM is: the process starts at step 201;

[0040] In step 202, given the number of cores C, the number of parallel region sets P, and the size of each variable size i , the number of SPM storage units corresponding to each core SSPM c ;

[0041] In step 203, an array is constructed to record the size S of the SLC SPM corresponding to the cth core in the parallel region set p. p,c ;

[0042] In step 204, it is determined whether there is a next parallel region p+1. If p+1<P is satisfied, step 205 is executed. Otherwise, step 213 is executed.

[0043] In step 205, the next parallel region p=p+1 is switched to, and then all units of all SPMs in the multi-core embedded system are initialized to SLC mode, that is, the initial size of SLC(c) corresponding to the cth core is S p,c =SSPM c Where (1≤c≤C), and initialize the area to store the minimum cost value tc of all its data variables p is a maximum value inf, that is, tc p =inf;

[0044] In step 206, the ratio of SLC / MLC in each SPM is dynamically adjusted, and the size of SLC(c) is S p,c By SSPM c to 0, where c is a positive integer less than C, C is the number of processors, and the total SLC / MLC mode conversion overhead cc is calculated;

[0045] In step 207, the local data allocation optimization algorithm, namely Algorithm 2, is called, and the total number of variables n in the parallel region and the size of each variable i are input. i , and the size S of each storage medium k , returns the variable allocation method X with the lowest overhead for the parallel region p under this SLC / MLC size ratio p,i,k and the minimum memory access overhead value ac, where k=0 represents that the storage medium is DRAM, k=2c-1 represents that the storage medium is SLCSPM corresponding to the c-th core, and k=2c represents that the storage medium is MLCSPM corresponding to the c-th core;

[0046] In step 208, it is determined whether the minimum cost ac obtained by the algorithm 2 under the SLC / MLC size ratio plus the mode switching cost cc is less than the total energy minimum cost tc p , that is, ac+cc<tc p If the judgment result is yes, execute step 209, otherwise, execute step 211;

[0047] In step 209, record the minimum data storage overhead value tc of the parallel region p. p , and SLC / MLC size configuration variable allocation method X p,i,k ;

[0048] In step 210, the next SLC / MLC size ratio is switched to, and the C-layer nested loop is executed. p,c =SSPM c -1, until SSPM c Reduce to 0;

[0049] In step 211, it is determined whether the SLC / MLC size ratio is legal. p,c ≥0, if the judgment result is yes, execute step 204, otherwise, execute step 206;

[0050] In step 212, the minimum energy consumption tc is output. p , the optimal ratio configuration scheme of SLC / MLC size in each parallel area, and the allocation of each variable in each program area p,i,k ;

[0051] In step 213, the process ends.

[0052] like Figure 4As shown, in the above step S3, based on the given SLC / MLC size ratio, the optimal storage address is allocated to all data variables in each parallel region to minimize the data access overhead in the multi-core embedded system. This overhead includes data movement overhead and data storage overhead. This solution is named the local data allocation optimization algorithm, combined with Figure 3 The local data allocation optimization algorithm is further described: the process starts at step 301;

[0053] In step 302, for a given parallel region, the total number of variables n in the parallel region and the size of each variable i are input. i , and the size S of each storage medium k ;

[0054] In step 303, an array is created to record the location x of variable i stored in storage medium k in parallel region set p. p,i,k , and establish a recursive function c[i,s1,s2,…,s K ] Find the minimum memory access cost after the i-th variable is stored, where s k is the remaining space size of the kth SPM after the i-th variable in the parallel region is stored, where k=0 represents the storage medium is DRAM, k=2c-1 represents the storage medium is the SLCSPM corresponding to the c-th core, and k=2c represents the storage medium is the MLCSPM corresponding to the c-th core. i,k Record the cost of storing the i-th variable in storage medium k,

[0055]

[0056] Assume that the rth region block in the pth parallel region set is executed on the rth core, where cw k is the overhead of reading data in storage medium k, cr k is the overhead of writing data in storage medium k; cwl is the reduction of local access write overhead compared with remote access; crl is the reduction of local access read overhead compared with remote access; w p,r,i is the cost of reading the i-th variable in the r-th region block in the parallel region set p; r p,r,d is the cost of writing the i-th variable in the r-th region block in the parallel region set p;

[0057] In step 304, assuming that all variables in the parallel region set are first stored in DRAM, then: Among them, c j,0 represents the overhead of storing data j in DRAM;

[0058] In step 305, all variables in the parallel region set p are traversed, and the following recursive function is called according to the current SLC / MLC ratio in each SPM, and the multi-tuple value is corrected by dynamic programming to find the best storage location for each variable to minimize the memory access overhead;

[0059]

[0060] In step S306, the program recursively obtains the minimum cost value ac of the multi-element array in the current situation, and uses X p,i,k Record the distribution of data i and output it;

[0061] At step 307, the algorithm ends.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A data allocation method for a multi-core embedded system based on a variable scratchpad memory, characterized in that: The method comprises the following steps: S1: Divide the embedded application into multiple program regions, generate data flow graphs between program regions simultaneously, and combine program regions with the same depth in the data flow graph into parallel region sets; S2: Before each parallel region set is executed, the number of single-level cells SLC and multi-level cells MLC of the variable scratch pad storage SPM in the multi-core embedded system is dynamically adjusted to find the optimal ratio of SLC / MLC; specifically, the following steps are included: S21: Assume that in a multi-core embedded system, the number of SPM units corresponding to the cth core is SSPM c ; The space size of the kth storage medium is S k , the number of units is M k , if k = 0, it means the storage medium is DRAM, if k = 2c-1, it means the storage medium is SLC SPM corresponding to the c-th core, if k = 2c, it means the storage medium is MLC SPM corresponding to the c-th core; the initial state of all SPM cells is single-layer cell SLC, initialize all SPM cells to store all their data variables and the minimum overhead value tc of SLC / MLC mode conversion p is infinite; S22: Explore the SLC / MLC ratio of each SPM one by one, and call the data allocation optimization method of step S3. If the obtained memory access overhead plus the SLC / MLC mode conversion overhead is less than tc p , then update tc p and record its data allocation scheme; S23: Selecting the SLC / MLC ratio with the minimum memory access overhead as the optimal SLC / MLC ratio of the parallel region; S3: Based on the given optimal ratio, the memory access information of the program area data variables in the parallel area concentration is comprehensively considered, and a corresponding data allocation optimization method is designed to allocate the best storage medium to each program area variable, so that the data memory access overhead in the multi-core embedded system is minimized; The data allocation optimization method includes the following steps: S31: Use c i,k Record the cost of storing the i-th variable in storage medium k, Assume that the rth region block in the pth parallel region set is executed on the rth core, where cw k is the overhead of reading data in storage medium k, cr k is the overhead of writing data in storage medium k; cwl is the reduction of local access write overhead compared with remote access; crl is the reduction of local access read overhead compared with remote access; w p,r,i is the cost of reading the i-th variable in the r-th region block in the parallel region set p; r p,r,d is the cost of writing the i-th variable in the r-th region block in the parallel region set p; S32: Establish a recursive function c[i,s1,s2,…,s K ], find the minimum memory access cost after the i-th variable is stored, where s k is the remaining space size of the kth SPM after the i-th variable is stored in the parallel region; S33: Assuming that all variables in the parallel region set are first stored in DRAM, then: S34: Establish a recursive relationship for data allocation, where size i is the size of the i-th variable; S34: Obtain the best data allocation solution and the minimum data access memory overhead through program recursion.

Images