Semiconductor package with smart power stage and electronic fuse solution

By integrating an SPS network and an electronic fuse solution network into a semiconductor package, and utilizing the electronic fuse IC to monitor the resistance and current of the high-voltage side MOSFET, the problem of high-voltage side MOSFET failure rate is solved, enabling rapid fault detection and protection, and improving system reliability and safety.

CN114695319BActive Publication Date: 2025-12-23ALPHA & OMEGA SEMICON INT LP
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Patent Information

Application Number
CN202111538930.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-12-28
Filing Date
2021-12-15
Publication Date
2025-12-23
Estimated Expiration
2041-12-15

AI Technical Summary

Technical Problem

In buck converters, the high-side MOSFET has a high failure rate and is prone to overvoltage stress leading to load failure, which is difficult to detect and protect against with existing technologies.

Method used

Integrating the SPS network and electronic fuse solution network into the same semiconductor package, the electronic fuse IC monitors the on-resistance, current, and temperature of the high-voltage side MOSFET, detects faults, and protects the load.

Benefits of technology

It enables rapid detection and protection against high-side MOSFET faults, improving system reliability and safety and reducing the risk of load failures.

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Abstract

A semiconductor package includes a leadframe, a low-side metal-oxide-semiconductor field-effect transistor (MOSFET), an electronic fuse MOSFET, a high-side MOSFET, a metal connection, a gate driver, an electronic fuse IC, and a molded package. A step-down converter includes a smart power stage (SPS) network and an electronic fuse solution network. The SPS network includes a high-side switch, a low-side switch, and a gate driver. A drain of the low-side switch is coupled to a source of the high-side switch via a switch node. The gate driver is coupled to a gate of the high-side switch and a gate of the low-side switch. The electronic fuse solution network includes a sense resistor, an electronic fuse switch, an electronic fuse integrated circuit (IC), and an SD circuit.
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Description

TECHNICAL FIELD

[0001] The present invention relates generally to a power semiconductor package for providing overcurrent protection. More specifically, the present invention relates to a buck converter including a smart power stage (SPS) network and an electronic fuse solution network. BACKGROUND

[0002] For the computing market including data centers and servers, SPS is optimized for highest efficiency at 10-15% duty cycle. The die size of the high side metal oxide semiconductor field effect transistor (MOSFET) is typically one fourth of the low side MOSFET to achieve the best balance between switching loss and conduction loss. The peak current handling capability of the MOSFET is directly proportional to the chip size. Smaller chip size tends to have lower peak current handling capability. In SPS, the high side MOSFET has a higher chance of failure due to lower current rating. If the high side MOSFET in the buck converter configuration fails (typically shorted), it is very likely to cause load failure due to overvoltage electrical stress.

[0003] The present invention integrates the SPS network and the electronic fuse solution network in the same semiconductor package. The electronic fuse solution network detects the high voltage side MOSFET failure. The electronic fuse IC monitors the on resistance (Ron) of the electronic fuse MOSFET to estimate the current through the electronic fuse MOSFET. The electronic fuse IC also detects the average current required for the shoot through event. The electronic fuse IC also monitors the electronic fuse MOSFET temperature and compensates for the Ron variation with temperature. To improve the accuracy of the current measurement, a channel MOSFET with a second mirror effect transistor can also be integrated. DS-on DS-ON The present invention integrates the SPS network and the electronic fuse solution network in the same semiconductor package. The electronic fuse solution network detects the high voltage side MOSFET failure. The electronic fuse IC monitors the on resistance (Ron) of the electronic fuse MOSFET to estimate the current through the electronic fuse MOSFET. The electronic fuse IC also detects the average current required for the shoot through event. The electronic fuse IC also monitors the electronic fuse MOSFET temperature and compensates for the Ron variation with temperature. To improve the accuracy of the current measurement, a channel MOSFET with a second mirror effect transistor can also be integrated. SUMMARY

[0004] A semiconductor package is disclosed. In one example, the semiconductor package is a buck converter. The semiconductor package includes a lead frame, a low side metal oxide semiconductor field effect transistor (MOSFET), an electronic fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an electronic fuse IC, and a molded package. The lead frame includes a first die paddle, a second die paddle, and an end paddle. The low side MOSFET is flipped and connected to the first die pad.

[0005] ​The step-down converter includes a smart power stage (SPS) network and an electronic fuse solution network. The SPS network includes a high-side switch, a low-side switch, and a gate driver. A drain of the low-side switch is coupled to a source of the high-side switch via a switch node. The gate driver is coupled to a gate of the high-side switch and a gate of the low-side switch. The electronic fuse solution network includes a sense resistor, an electronic fuse switch, an electronic fuse integrated circuit (IC), and an SD circuit. BRIEF DESCRIPTION OF DRAWINGS

[0006] In an example of the present invention, Figure 1A represents a top view of a semiconductor package, Figure 1B represents a cross-sectional view thereof, Figure 1C represents another cross-sectional view thereof.

[0007] Figure 2 represents a block diagram of a step-down converter in an example of the present invention.

[0008] Figure 3 represents a shoot-through condition in an example of the present invention.

[0009] Figure 4 represents a waveform diagram in an example of the present invention. DETAILED DESCRIPTION

[0010] In an example of the present invention, Figure 1A represents a top view of a semiconductor package 100, Figure 1B represents a cross-sectional view thereof along AA’, Figure 1B represents a cross-sectional view thereof along BB’. In one example, the semiconductor package 100 is a step-down converter. The semiconductor package 100 includes a lead frame 110, a low-side metal oxide semiconductor field effect transistor (MOSFET) 140, an electronic fuse MOSFET 130, a high-side MOSFET 160, a metal connection 198, a gate driver integrated circuit (IC) 170, an electronic fuse IC 180, and a molded package 190.

[0011] In Figure 1A , the molded package 190 is shown as transparent and represented by dashed lines. For simplicity, in Figure 1B and 1C , the molded package 190 is not represented.

[0012] The lead frame 110 includes a first chip pad 112, a second chip pad 114, and a terminal pad 116.

[0013] Low-side MOSFET 140 is flipped and attached to first die pad 112. Low-side MOSFET 140 includes a source 140S and a gate 140G on a top surface of low-side MOSFET 140, and a drain 140D on a bottom surface of low-side MOSFET 140.

[0014] Electronic fuse MOSFET 130 is connected to second die pad 114. Electronic fuse MOSFET includes a source 130S and a gate 130G on a top surface of electronic fuse MOSFET 130, and a drain 130D on a bottom surface of electronic fuse MOSFET 130.

[0015] High-side MOSFET 160 is connected to electronic fuse MOSFET 130. High-side MOSFET 160 includes a source 160S and a gate 160G on a top surface of high-side MOSFET 160, and a drain 160D on a bottom surface of high-side MOSFET 160. Drain 160D of high-side MOSFET 160 is connected to source 130S of electronic fuse MOSFET 130.

[0016] Metallic connection 198, such as a metallic clip, a metallic strap, or other electrically conductive connection, connects drain 140D of low-side MOSFET 140 and source 160S of high-side MOSFET 160 to end pad 116 of lead frame 110. Gate driver IC 170 is connected to electronic fuse MOSFET 130. Electronic fuse IC 180 is connected to gate driver IC 170. Molded package 190 encloses low-side MOSFET 140, electronic fuse MOSFET 130, high-side MOSFET 160, metallic connection 198, gate driver IC 170, and electronic fuse IC 180. Molded package 190 further encloses a majority of lead frame 110. Majority is greater than 50%. In embodiments of the invention, bottom surface 111 of lead frame 110 is exposed from molded package 190.

[0017] Metallic connection 198 is electrically and mechanically connected to drain 140D of low-side MOSFET 140 by first electrically conductive material 199A. Metallic connection 198 is electrically and mechanically connected to source 160S of high-side MOSFET 160 by second electrically conductive material 199B. Metallic connection 198 is electrically and mechanically connected to end pad 116 of lead frame 110 by third electrically conductive material 199C. In embodiments of the invention, each of first electrically conductive material 199A, second electrically conductive material 199B, and third electrically conductive material 199C includes a solder paste material.

[0018] The source electrode 140S of the low-side MOSFET 140 is electrically and mechanically connected to the first chip pad 112 by a fourth electrically conductive material 129A. The drain electrode 130D of the electronic fuse MOSFET 130 is electrically and mechanically connected to the second chip pad 114 by a fifth electrically conductive material 129B. The drain electrode 160D of the high-side MOSFET 160 is electrically and mechanically connected to the source electrode 130S of the electronic fuse MOSFET 130 by a sixth electrically conductive material 129C. In examples of the present application, each of the fourth electrically conductive material 129A, the fifth electrically conductive material 129B, and the sixth electrically conductive material 129C comprises a solder paste material.

[0019] The gate driver IC 170 is connected to the electronic fuse MOSFET 130 by a first non- electrically conductive material 179A. The electronic fuse IC 180 is connected to the gate driver IC 170 by a second non-electrically conductive material 179B. Each of the first non-electrically conductive material 179A and the second non-electrically conductive material 179B comprises an epoxy material. In an optional example, the electronic fuse IC 180 is integrated on the same IC chip as the gate driver IC 170.

[0020] The gate electrode 140G of the low-side MOSFET is electrically connected to the extension 113 of the leadframe 110. The extension 113 of the leadframe 110 extends to the edge 115 of the leadframe 110. A plurality of bond wires 171 connect the gate driver IC 170 to the extension 113 of the leadframe 110.

[0021] Figure 2 A block diagram of a buck converter 200 is shown in examples of the present application. The buck converter 200 includes a smart power stage (SPS) network 210 and an electronic fuse solution network 250. The SPS network includes a high-side switch 260, a low-side switch 240, and a gate driver 270. The drain of the low-side switch 240 is coupled to the source of the high-side switch 260 via a switch node 241. The gate driver 270 is coupled to the gate of the high-side switch 260 and the gate of the low-side switch 240.

[0022] The electronic fuse solution network 250 includes an optional sense resistor 251, an electronic fuse switch 253, an electronic fuse integrated circuit (IC) 290, and an SD circuit 280. A first node of the optional sense resistor 251 is coupled to the power supply 201. In one example, the power supply 201 is 12 volts. A power supply of the electronic fuse switch 253 is coupled to the drain of the high side switch 260. The electronic fuse IC 290 includes a comparator 292. The comparator 292 includes a reference input 295, a function input 297, and an output 299. The function input 297 is coupled to a short circuit detection (SD) node 291. The SD circuit 280 includes a first circuit resistor 281, a second circuit resistor 283, a circuit capacitor 285, and a circuit diode 287. A first node of the first circuit resistor 281 is coupled to the switch node 241, and a second node of the first circuit resistor 281 is coupled to the short circuit detection (SD) node 291. The second circuit resistor 283 and the circuit capacitor 285 are connected in parallel between the short circuit detection (SD) node 291 and the reference ground. The cathode of the circuit diode 287 is coupled to the switch node 241, and the anode of the circuit diode 287 is coupled to the short circuit detection (SD) node 291.

[0023] Figure 3 A shoot-through condition 301 is represented in the example of the present invention. In the example of the present invention, the low side switch 240 is a first metal oxide semiconductor field effect transistor (MOSFET). The high side switch 260 is a second MOSFET. The peak current handling capability of a MOSFET is directly proportional to the size of the MOSFET. The size of the first MOSFET is larger than the size of the second MOSFET, such that the high side switch 260 has a lower peak current handling capability than the low side switch 240. In the example of the present invention, the size of the second MOSFET is 20-30% of the size of the first MOSFET. The electronic fuse IC 290 also includes an integrated current sense amplifier 390 that measures the current through the high side switch 260. When the current through the high side switch 260 is greater than a predetermined value, the electronic fuse IC 290 turns off the electronic fuse switch 253. When the high side switch 260 shorts and the gate driver 270 continues to drive the low side switch 240, the current through the high side switch 260 increases. In the example of the present invention, the integrated current sense amplifier 390 detects the increase in current through the high side switch 260 and turns off the electronic fuse switch 253. The electronic fuse switch 253 is a MOSFET that is turned on and off by the electronic fuse IC 290. The electronic fuse IC 290 is a comparator that is turned on and off by the SD circuit 280. The SD circuit 280 is a comparator that is turned on and off by the optional sense resistor 251. Figure 3In the illustrated example, current sense amplifier 390 detects the voltage drop across optional sense resistor 251 to measure the current through high-side switch 260. In another example, optional sense resistor 251 is not provided, and the electronic fuse IC monitors the on-resistance (RDS-on) of the electronic fuse MOSFET to estimate the current through the electronic fuse MOSFET. Current sense amplifier 390 detects the voltage drop across electronic fuse switch 253 to measure the current through high-side switch 260. The electronic fuse IC also senses the temperature of the electronic fuse MOSFET to account for the temperature dependence of the R DS-ON of the electronic fuse MOSFET. In another example, the electronic fuse MOSFET is a channel MOSFET with a second mirror FET integrated as a common-drain MOSFET to improve the current measurement accuracy. The second mirror field effect transistor has a source electrode separate from the source electrode of the electronic fuse MOSFET, and a gate and drain electrode connected to the gate and drain electrode of the electronic fuse MOSFET, respectively. The electronic fuse IC measures the current through high-side switch 260 by detecting the current flowing through the second mirror FET, which is only a fraction of the size of the electronic fuse MOSFET and serves as a sense FET to sense the current through the electronic fuse MOSFET. Since the electronic fuse MOSFET and the second mirror FET are integrated on the same chip, and the current through the second mirror FET can be directly detected from the source of the second mirror FET without relying on R DS-on , the current measurement is temperature independent, and by eliminating the temperature sensing function, the electronic fuse integrated circuit can be simplified.

[0024] Reference is now made to Figure 2 SD circuit 280 measures the duration of time that switch node 241 remains high. The value of function input 297 corresponds to the duration of time that switch node 241 remains high. When the value of function input 297 is greater than the value of reference input 295, the output 299 of comparator 292 flags a fault signal. When high-side switch 260 is shorted and low-side switch 240 is not turned on, the duration of time increases.

[0025] Figure 4 A waveform diagram is illustrated in the example of the present invention. Waveform 441 is associated with the voltage at switch node 241. Reference constant 495 is associated with reference input 295. Waveform 491 is associated with SD node 291. Waveform 499 is associated with the output 299 of comparator 292.

[0026] At timing 411, a short is detected on the high side switch 260. The voltage at the switch node 241 remains high for a duration longer than a timing threshold. In the first timing circuit 285, the resistance 283 is constant in the timing circuit 285. In the second timing circuit 285, the resistance 285 is constant in the timing circuit 285, the waveform 499 flags a fault signal, and the electronic fuse IC 290 turns off the electronic fuse switch 253. Thus, the electronic fuse solution protects the load when the high side switch 260 is on or for a duration shorter than a predetermined timing threshold.

[0027] One of ordinary skill in the art can recognize that there are possibilities to modify the embodiments disclosed herein. For example, the number of bonding wires can vary. Other modifications can be made by one of ordinary skill in the art and all such modifications are considered to be within the scope of the application as defined by the claims.

Claims

1. A semiconductor package comprising: a leadframe comprising a first die pad; a second die pad; and a terminal pad; a low side MOSFET flipped such that a front side of the low side MOSFET is electrically and mechanically connected to the first die pad, the low side MOSFET comprising a source electrode and a gate electrode on the front side of the low side MOSFET; and a drain electrode on a bottom side of the low side MOSFET; an electronic fuse MOSFET electrically and mechanically connected to the second die pad, the electronic fuse MOSFET comprising a source and a gate electrode on a front side of the electronic fuse MOSFET; and a drain electrode on a bottom side of the electronic fuse MOSFET; a high side MOSFET electrically and mechanically connected to the electronic fuse MOSFET, the high side MOSFET comprising a source and a gate electrode on a front side of the high side MOSFET; and a drain electrode on a bottom side of the high side MOSFET, the drain electrode of the high side MOSFET electrically and mechanically connected to the source electrode of the electronic fuse MOSFET; a metal link electrically and mechanically connected to the drain electrode of the low side MOSFET and the source electrode of the high side MOSFET; a gate driver IC connected to the electronic fuse MOSFET by a first non-conductive material; and an electronic fuse IC connected to the gate driver IC by a second non-conductive material, the electronic fuse IC further comprising an integrated current sense amplifier that measures current through the high side MOSFET, the electronic fuse IC turning off the electronic fuse MOSFET when the current through the high side MOSFET is greater than a predetermined value, the current through the high side MOSFET increasing when the high side MOSFET is shorted and the gate driver continues to drive the low side MOSFET; a molded package encapsulating the low side MOSFET, the electronic fuse MOSFET, the high side MOSFET, the metal link, the gate driver IC, and the electronic fuse IC.

2. The semiconductor package of claim 1, wherein the bottom side of the leadframe is exposed by the molded package.

3. The semiconductor package of claim 1, wherein the metal link is a metal clip electrically and mechanically connected to the drain of the low side MOSFET by a first conductive material; wherein the metal clip is electrically and mechanically connected to the source of the high side MOSFET by a second conductive material; and wherein the metal clip is electrically and mechanically connected to the terminal pad of the leadframe by a third conductive material.

4. The semiconductor package of claim 3, wherein each of the first conductive material, the second conductive material, and the third conductive material is made of a solder paste material.

5. The semiconductor package of claim 1, wherein each of the first non-conductive material and the second non-conductive material is made of an epoxy material. ​ ​ ​ ​ ​ 6. The semiconductor package of claim 1, wherein the gate electrode of the low-side MOSFET is connected to an extension of the leadframe; and wherein the extension of the leadframe extends to an edge of the leadframe.

7. The semiconductor package of claim 6, wherein one or more bond wires connect the gate driver IC to the extension of the leadframe.

8. A buck converter comprising: a smart power stage (SPS) network comprising a high-side switch; a low-side switch, the drain of the low-side switch coupled to the source of the high-side switch through a switch node; and a gate driver coupled to the gate of the high-side switch and the gate of the low-side switch; and an electronic fuse solution network comprising: an electronic fuse switch, the source of the electronic fuse switch coupled to the drain of the high-side switch; an electronic fuse IC comprising: a comparator comprising: a reference input; a function input coupled to a short detection (SD) node; and an output; and a short detection circuit coupled to the short detection node of the electronic fuse IC, the short detection circuit comprising a first circuit resistor, a first node of the first circuit resistor coupled to the switch node; a second circuit resistor; a circuit capacitor; and a circuit diode; wherein the electronic fuse IC further comprises an integrated current sense amplifier that measures the current flowing through the high-side switch; and wherein the electronic fuse IC opens the electronic fuse when the current flowing through the high-side switch is greater than a predefined value, the current flowing through the high-side switch increasing when the high-side switch is shorted and the gate driver continues to drive the low-side switch.

9. The buck converter of claim 8, wherein the low-side switch is a first MOSFET; wherein the high-side switch is a second MOSFET; and wherein the first MOSFET is sized larger than the second MOSFET, such that the high-side switch has a lower peak current carrying capability than the low-side switch.

10. The buck converter of claim 8, wherein the electronic fuse IC monitors the on-resistance of the electronic fuse switch to predict the current flowing through the high-side switch.

11. The buck converter of claim 8, wherein the electronic fuse solution network further comprises a sense resistor, the current sense amplifier detecting a voltage drop across the sense resistor to measure the current flowing through the high-side switch.

12. The buck converter of claim 8, wherein the electronic fuse switch comprises a trench MOSFET with a second mirror FET integrated as a common drain MOSFET.

13. The buck converter of claim 8, wherein the short detection circuit measures the duration that the switch node remains at a high level; wherein the value of the function input corresponds to the duration that the switch node remains at a high level; wherein the output of the comparator flags a fault signal when the value of the function input is greater than the value of the reference input. ​ ​ 14. The voltage reducer converter of claim 13, wherein the duration increases when the high-side switch is shorted and the low-side switch is not turned on.

Citation Information

Patent Citations

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