Semiconductor structure and method of forming the same

Abstract

The application relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a first transistor comprising a first channel in the substrate and a first end on the surface of the substrate, the first end being used for connecting with a first type of storage unit, and a second transistor comprising a second channel in the substrate and a second end on the surface of the substrate, the second end being used for connecting with a second type of storage unit, and the width of the second channel is greater than that of the first channel. The application can make the manufacturing process of the first transistor compatible with that of the second transistor, and simplify the manufacturing method of the semiconductor structure. Furthermore, the application is helpful to improve the integration density of the storage unit with the first transistor and / or the second transistor in the memory, and reduce the size of the storage unit, and lays a foundation for expanding the application field of the memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] Magnetic Random Access Memory (MARM) is an integration of silicon-based complementary oxide semiconductor (CMOS) and magnetic tunnel junction (MTJ) technology. It is a non-volatile memory that combines the high-speed read / write capabilities of static random access memory (SRAM) with the high integration density of dynamic random access memory (DRAM). The MTJ typically comprises a fixed layer, a tunneling layer, and a free layer. During normal operation, the magnetization direction of the free layer can change, while the magnetization direction of the fixed layer remains constant. The resistance of the MARM is related to the relative magnetization directions of the free and fixed layers. When the magnetization direction of the free layer changes relative to the fixed layer, the resistance of the MARM changes accordingly, corresponding to different stored information.

[0004] To increase memory density and reduce cell size, buried word lines (BWLs) have been widely used in DRAM. However, to avoid leakage current, DRAM with BWLs requires relatively small drive currents for transistor operation. In contrast, DRAM with buried word lines requires relatively large drive currents to ensure the activation of the MTJ switch. Because of this difference in drive current between DRAM and DRAM, it is currently impossible to implement buried word lines in DRAM, thus limiting the increase in DRAM memory density and the reduction in cell size.

[0005] Therefore, how to improve the performance of memory and thus expand its application areas is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] This invention provides a semiconductor structure and a method for forming the same, which addresses the relatively poor performance of existing memory devices and expands the application areas of memory.

[0007] To address the above problems, the present invention provides a semiconductor structure comprising:

[0008] Substrate;

[0009] The first transistor includes a first channel located within the substrate and a first end located on the surface of the substrate, the first end being used to connect to a first type of memory cell;

[0010] The second transistor includes a second channel located within the substrate and a second end located on the surface of the substrate, the second end being used to connect to a second type of memory cell, the width of the second channel being greater than the width of the first channel.

[0011] Optionally, the width of the second channel is 1.5 to 3 times the width of the first channel.

[0012] Optionally, the substrate further includes at least one first active region having two of the first transistors.

[0013] Two first transistors are distributed on opposite sides of the extension direction of the first active region, and the two first transistors located in the first active region have a first common terminal.

[0014] Optionally, the substrate further includes at least one second active region having two second transistors.

[0015] Two second transistors are distributed on opposite sides of the extension direction of the second active region, and the two second transistors located in the second active region have a second common terminal.

[0016] Optionally, the substrate further includes at least one third active region, wherein the third active region has the first transistor and the second transistor;

[0017] The first transistor and the second transistor are distributed on opposite sides of the extension direction of the third active region, and the first transistor and the second transistor located in the third active region have a third common terminal.

[0018] Optionally, multiple letter lines extending along the first direction may also be included;

[0019] The plurality of the third active regions are arranged in an array inside the substrate, the third active regions extend along a second direction, and the second direction is tilted at a predetermined angle relative to the first direction.

[0020] Optionally, along the second direction, the first transistor located in the adjacent third active region is disposed opposite to the second transistor.

[0021] Optionally, along the first direction, the first transistor and the second transistor located in adjacent third active regions correspond to the same word line.

[0022] Optionally, the width of the second channel is 1.5 to 2 times the width of the first channel.

[0023] Optionally, multiple letter lines extending along the first direction may also be included;

[0024] The plurality of the third active regions are arranged in an array inside the substrate, the third active regions extending along a third direction and the third direction being perpendicular to the first direction.

[0025] Optionally, along the third direction, the first transistors in adjacent third active regions are close to each other, or the second transistors are close to each other.

[0026] Optionally, the character lines include first and second sub-character lines arranged alternately along the third direction;

[0027] The first transistors in the plurality of third active regions arranged along the first direction all overlap with the same first sub-word line;

[0028] The second transistors in the plurality of third active regions arranged along the first direction all overlap with the same second sub-word line.

[0029] Optionally, the width of the second channel is 2 to 3 times the width of the first channel.

[0030] Optionally, the projections of two adjacent third active regions arranged along the third direction may overlap, wherein the projection is the projection of the third active region along the third direction.

[0031] Optionally, the first transistors of two adjacent third active regions arranged upwards along the third line correspond to the same word line.

[0032] Optionally, the first type of storage unit includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit;

[0033] The second type of storage unit includes any one of the following: capacitor storage unit, resistor storage unit, magnetic storage unit, phase change storage unit, and ferroelectric storage unit;

[0034] The storage types of the first type of storage unit and the second type of storage unit are different.

[0035] Optionally, the first type of storage unit is a capacitor storage unit;

[0036] The second type of storage unit is a magnetic storage unit.

[0037] To address the above problems, the present invention also provides a method for forming a semiconductor structure, comprising the following steps:

[0038] Provide substrate;

[0039] A first transistor and a second transistor are formed in the substrate. The first transistor includes a first channel located in the substrate and a first end located on the surface of the substrate. The first end is used to connect to a first type of memory cell. The second transistor includes a second channel located in the substrate and a second end located on the surface of the substrate. The second end is used to connect to a second type of memory cell. The width of the second channel is greater than the width of the first channel.

[0040] Optionally, the specific steps of forming the first transistor and the second transistor in the substrate include:

[0041] An active region is formed in the substrate, the active region comprising a first portion and a second portion, wherein the width of the second portion is greater than the width of the first portion;

[0042] A first gate trench and a second gate trench are formed in the first part and the second part of the active region, respectively. The active region is divided by the first gate trench and the second gate trench into a first end, a second end, and a common end between the first end and the second end.

[0043] Gate material is filled in the first gate trench and the second gate trench to form the first gate and the second gate.

[0044] Optionally, the method for forming the semiconductor structure further includes the following steps:

[0045] The active region is etched to form the first gate trench and the second gate trench on opposite sides of the active region extending in the direction of extension.

[0046] The first gate and the second gate are formed by filling the first gate trench and the second gate trench in the active region with gate material.

[0047] Optional, also includes:

[0048] Multiple word lines extending along a first direction are formed within the substrate;

[0049] The active regions are arranged in an array inside the substrate, the active regions extend along a second direction, and the second direction is tilted at a predetermined angle relative to the first direction.

[0050] Optionally, along the second direction, the first transistor in one of two adjacent active regions is positioned opposite to the second transistor in the other active region.

[0051] Optionally, along the first direction, the first transistor in one of two adjacent active regions and the second transistor in the other active region correspond to the same word line.

[0052] Optional, also includes:

[0053] Multiple word lines extending along a first direction are formed within the substrate;

[0054] The active regions are arranged in an array inside the substrate, the active regions extend along a third direction, and the third direction is perpendicular to the first direction.

[0055] Optionally, along the third direction, the first transistors of two adjacent active regions are brought close to each other, or the second transistors are brought close to each other.

[0056] Optionally, the character lines include first and second sub-character lines arranged alternately along the third direction;

[0057] The first transistors in the plurality of active regions arranged along the first direction all overlap with the same first sub-word line;

[0058] The second transistors in the plurality of active regions arranged along the first direction all overlap with the same second sub-word line.

[0059] Optionally, the projections of two adjacent active regions arranged along the third direction overlap, wherein the projection is the projection of the active region along the third direction.

[0060] Optionally, the first type of storage unit includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit;

[0061] The second type of storage unit includes any one of the following: capacitor storage unit, resistor storage unit, magnetic storage unit, phase change storage unit, and ferroelectric storage unit;

[0062] The storage types of the first type of storage unit and the second type of storage unit are different.

[0063] Optionally, the first type of storage unit is a capacitor storage unit;

[0064] The second type of storage unit is a magnetic storage unit.

[0065] The semiconductor structure and its formation method provided by this invention, by simultaneously setting a first transistor for connection to a first type of memory cell and a second transistor for connection to a second type of memory cell in the semiconductor structure, wherein both the first channel and the second channel are located inside the substrate, and the width of the first channel in the first transistor is limited to the width of the second channel in the second transistor, achieves compatibility between the manufacturing processes of the first transistor and the second transistor, thereby simplifying the semiconductor structure manufacturing method. Furthermore, it ensures that the drive current of the second transistor is greater than that of the first transistor, which helps to improve the integration density and device performance of memory cells having the first transistor and / or the second transistor, and reduces the size of the memory cells, laying the foundation for expanding the application areas of memory. Attached Figure Description

[0066] Appendix Figure 1 This is a schematic diagram of the semiconductor structure in a specific embodiment of the present invention;

[0067] Appendix Figure 2 This is a schematic diagram of the arrangement of multiple first active regions in a specific embodiment of the present invention;

[0068] Appendix Figure 3 This is a schematic diagram of the arrangement of multiple second active regions in a specific embodiment of the present invention;

[0069] Appendix Figure 4 This is a schematic diagram of the arrangement of multiple third active regions in a specific embodiment of the present invention;

[0070] Appendix Figure 5 This is a schematic diagram of another arrangement of multiple third active regions in a specific embodiment of the present invention;

[0071] Appendix Figure 6 This is a flowchart of a method for forming a semiconductor structure in a specific embodiment of the present invention. Detailed Implementation

[0072] The specific embodiments of the semiconductor structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0073] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a schematic diagram of a semiconductor structure in a specific embodiment of the present invention. For example... Figure 1 As shown, the semiconductor structure provided in this specific embodiment includes:

[0074] Substrate 10;

[0075] The first transistor includes a first channel located within the substrate 10 and a first end 112 located on the surface of the substrate 10, the first end 112 being used to connect to a first type of memory cell 15.

[0076] The second transistor includes a second channel located within the substrate 10 and a second end 122 located on the surface of the substrate 10. The second end 122 is used to connect to a second type of memory cell 17. The width W2 of the second channel is greater than the width W1 of the first channel.

[0077] Specifically, such as Figure 1 As shown, the substrate 10 can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 10 can be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 10 also has a plurality of active regions arranged in an array, and adjacent active regions are isolated from each other by a shallow trench isolation structure 13. The first transistor and the second transistor can be located in the same active region or in different active regions.

[0078] The first channel of the first transistor and the second channel of the second transistor are both located entirely inside the substrate 10. Therefore, during the formation of the first transistor and the second transistor, the first channel and the second channel can be formed simultaneously by etching the substrate 10, thereby achieving compatibility between the manufacturing processes of the first transistor and the second transistor. This also helps to improve the integration density and device performance of memory cells with the first transistor and / or the second transistor, and to reduce the size of the memory cells.

[0079] The substrate 10 may have a P-well region 101 formed by p-type ion doping; the first terminal 112 of the first transistor and the second terminal 122 of the second transistor are respectively source or drain formed by n-type ion doping. If the first terminal 112 of the first transistor is the drain, then the other terminal of the first transistor is the source, and the region between the source and the drain of the first transistor is the first channel of the first transistor; if the second terminal 122 of the second transistor is the drain, then the other terminal of the second transistor is the source, and the region between the source and the drain of the second transistor is the second channel of the second transistor. Specifically, as shown... Figure 1As shown, the first transistor and the second transistor have a common terminal 16, which can be the common source of the first transistor and the second transistor. The surface region of the substrate 10 located between the common terminal 16 and the first terminal 112 can be the first channel of the first transistor, and the width W1 of the first channel can be the line length where the first channel intersects the first terminal 112. The surface region of the substrate 10 between the common terminal 16 and the second terminal 122 can be the second channel of the second transistor, and the width W2 of the second channel can be the line length where the second channel intersects the second terminal 122. The first channel and the second channel can have a certain thickness, that is, the surface region of the substrate can include an internal region of substrate with a certain thickness, and the thickness can be adjusted by adjusting the ion doping conditions. By setting the width W2 of the second channel to be greater than the width W1 of the first channel, the driving current of the second transistor is greater than the driving current of the first transistor, thereby satisfying the requirement that the driving currents of the first transistor and the second transistor are different. This allows two different transistors to be integrated in the same memory, realizing the complementary advantages of the two types of transistors, thereby improving the performance of the memory and expanding the application field of the memory.

[0080] Optionally, the substrate 10 may have an N-well region 101 formed by N-type ion doping; the first terminal 112 of the first transistor and the second terminal 122 of the second transistor are respectively p-type ion doped.

[0081] Optionally, the width W2 of the second channel is 1.5 to 3 times the width W of the first channel.

[0082] like Figure 1 As shown, the first channel surrounds the first gate 111 of the first transistor, and a first gate dielectric layer 113 is disposed between the first channel and the first gate 111, covering the first channel. The second channel surrounds the second gate 121 of the second transistor, and a second gate dielectric layer 123 is disposed between the second channel and the second gate 121, covering the second channel. The first gate dielectric layer 113 and the second gate dielectric layer 123 can be made of the same or different materials. To simplify the manufacturing process, the first gate dielectric layer 113 and the second gate dielectric layer 123 are made of the same material, for example, both are oxide materials (e.g., silicon dioxide).

[0083] Optionally, the substrate 10 further includes at least one first active region 23, in which two of the first transistors are present;

[0084] Two first transistors are distributed on opposite sides of the extension direction of the first active region 23, and the two first transistors located in the first active region have a first common terminal.

[0085] Appendix Figure 2 This is a schematic diagram illustrating the arrangement of multiple first active regions in a specific embodiment of the present invention. For example, such as... Figure 2 As shown, the substrate 10 has multiple word lines 22 extending along a first direction D1, and these word lines 22 are arranged parallel to a third direction D3 perpendicular to the first direction D1. Multiple first active regions 23 are arranged in an array within the substrate 10, and each first active region 23 extends along a second direction D2. The second direction D2 is tilted at a preset angle relative to the first direction D1. The specific value of the preset angle can be set by those skilled in the art according to actual needs; for example, the preset angle can be greater than or equal to 15 degrees and less than 30 degrees. Two word lines 22 pass through a first active region 23 and respectively control two first transistors on the first active region 23. The first channels of the two first transistors are both located within the substrate 20 and have the same width. The two first transistors are distributed along the second direction D2 on opposite sides of the first active region 23. The width W1 of the first channel can be the length of the first channel along the first direction D1. The first terminals 112 of the two first transistors are both located on the surface of the substrate 20, and the two first transistors share a first common terminal. For example, the first terminal 112 of the first transistor is the drain terminal, and the first common terminal is the first common source terminal. Two first transistors located within the same first active region 23 share the first common source terminal. The first common terminal can be located in the middle of the first active region 23, that is, the portion between the two word lines 22 on the first active region 23. The two first transistors within the same first active region 23 are electrically connected to two memory cells of the first type 15, respectively. It can be understood that the first gate 111 can be the portion of the word line 22 located on the first transistor in the first active region 23. Specifically, as shown... Figure 2 As shown, the substrate 10 includes a plurality of first active regions 23 and shallow trench isolation structures between the first active regions 23. The bit line 22 passes through the plurality of first active regions 23 and shallow trench isolation structures between the first active regions 23. The overlapping portion of the bit line 22 and the first active region 23 can be the first gate 111.

[0086] Optionally, the substrate 10 further includes at least one second active region 24, in which two second transistors are present;

[0087] Two second transistors are distributed on opposite sides of the extension direction of the second active region 24, and the two second transistors located in the second active region 24 have a second common terminal.

[0088] Appendix Figure 3 This is a schematic diagram illustrating the arrangement of multiple second active regions in a specific embodiment of the present invention. For example, such as... Figure 3 As shown, the substrate 10 has multiple word lines 22 extending along a first direction D1, and these word lines 22 are arranged parallel to a third direction D3 perpendicular to the first direction D1. Multiple second active regions 24 are arranged in an array within the substrate 10, and each second active region 24 extends along a second direction D2. The second direction D2 is tilted at a preset angle relative to the first direction D1. The specific value of the preset angle can be set by those skilled in the art according to actual needs; for example, the preset angle can be greater than or equal to 15 degrees and less than 30 degrees. Each second active region 24 has two second transistors, and the second channels of the two second transistors are both located within the substrate 20 and have the same width. The two second transistors are distributed along the second direction D2 on opposite sides of the second active region 24. The width W2 of the second channel can be the length of the second channel along the first direction D1. The second terminals 122 of the two second transistors are both located on the surface of the substrate 20, and the two second transistors share a second common terminal. For example, the second terminal 122 of the second transistor is the drain terminal, and the second common terminal is the second common source terminal. Two second transistors located within the same second active region 24 share the second common source terminal. The second common terminal can be located in the middle of the second active region 24, that is, the portion between the two word lines 22 on the second active region 24. The two second transistors within the same second active region 24 are electrically connected to two memory cells of the second type, respectively. It can be understood that the second gate 121 can be the portion of the word line 22 located on the second transistor in the second active region 24. Specifically, as shown... Figure 2 As shown, the substrate 10 includes a plurality of second active regions 24 and a shallow trench isolation structure between the second active regions 24. The bit line 22 passes through the plurality of second active regions 24 and the shallow trench isolation structure between the second active regions 24. The overlapping portion of the bit line 22 and the second active region 24 can be the second gate 121.

[0089] Optionally, the substrate 10 further includes at least one third active region 25, wherein the third active region 25 has a first transistor and a second transistor;

[0090] The first transistor and the second transistor are distributed on opposite sides of the extension direction of the third active region 25, and the first transistor and the second transistor located in the third active region 25 have a third common terminal.

[0091] Optionally, the semiconductor structure further includes multiple word lines 22 extending along the first direction D1;

[0092] The plurality of the third active regions 25 are arranged in an array inside the substrate 10. The third active regions 25 extend along the second direction D2, and the second direction D2 is tilted at a predetermined angle relative to the first direction D1.

[0093] Appendix Figure 4 This is a schematic diagram illustrating the arrangement of multiple third active regions in a specific embodiment of the present invention. For example, such as... Figure 1 and Figure 4As shown, the substrate 10 has multiple word lines 22 extending along a first direction D1, and these word lines 22 are arranged parallel to a third direction D3 perpendicular to the first direction D1. Multiple third active regions 25 are arranged in an array within the substrate 10, and each third active region 25 extends along a second direction D2. The second direction D2 is tilted at a preset angle relative to the first direction D1. The specific value of the preset angle can be set by those skilled in the art according to actual needs; for example, the preset angle can be greater than or equal to 15 degrees and less than 30 degrees. Each third active region 25 has one first transistor and one second transistor, which are distributed along the second direction D2 on opposite sides of the third active region 25. Two word lines 22 pass through a third active region 25 and respectively control the first transistor and the second transistor on the third active region 25. The width W1 of the first channel is the length of the first channel along the first direction D1, and the width W2 of the second channel is the length of the second channel along the first direction D2. The first terminal 112 of the first transistor and the second terminal 122 of the second transistor are both located on the surface of the substrate 20, and the first transistor and the second transistor, located within the same third active region 25, share the third common terminal. For example, the first terminal 112 of the first transistor is the drain terminal, the second terminal 122 of the second transistor is the drain terminal, and the third common terminal is the third common source terminal. The first transistor and the second transistor, located within the same third active region 25, share the third common source terminal. The third common terminal may be located in the middle of the third active region 25, that is, the portion between the two word lines 22 on the third active region 25. The third common terminal includes a first side facing the first channel and a second side opposite to the first side, the second side facing the second channel. Since the width of the first channel of the first transistor is smaller than the width of the second channel of the second transistor 121, the width of the first side of the third common source terminal (the length of the line intersecting the first channel) is smaller than the width of the second side (the length of the line intersecting the second channel). The first terminal 112 of the first transistor in the same third active region 25 is used to connect to the first type of memory cell 15, and the second terminal 122 of the second transistor is used to connect to the second type of memory cell 17. It can be understood that the first gate 111 can be the portion of the word line 22 located on the first transistor in the third active region 25; the second gate 121 can be the portion of the word line 22 located on the second transistor in the third active region 25; specifically, as... Figure 4As shown, the substrate 10 includes a plurality of third active regions 25 and shallow trench isolation structures between the third active regions 25. The bit line 22 passes through the shallow trench isolation structures between the plurality of third active regions 25. The overlapping portion of the bit line 22 and the third active region 23 can be a first gate 111 or a second gate 121. For example, the overlapping portion of the bit line 22 and the first transistor of the third active region 25 is the first gate 111, and the overlapping portion of the bit line 22 and the second transistor of the third active region 25 is the second gate 121.

[0094] Optionally, along the second direction D2, the first transistor located in the adjacent third active region 25 is disposed opposite to the second transistor.

[0095] Optionally, along the first direction D1, the first transistor and the second transistor located in adjacent third active regions 25 correspond to the same word line 22.

[0096] Specifically, such as Figure 4 As shown, by setting the transistor types of the adjacent ends of the third active regions 25 to be different along the second direction D2, and by having the first transistor and the second transistor in adjacent third active regions 25 correspond to the same word line 22 along the first direction D1, the first transistor and the second transistor can be driven simultaneously through a single word line 22. This improves the driving efficiency of the semiconductor structure and enables high-speed memory reads. Furthermore, by arranging the first transistor and the second transistor in a staggered distribution, the spacing between the first transistor and the second transistor is increased, reducing manufacturing difficulty.

[0097] Optionally, the width of the second channel is 1.5 to 2 times the width of the first channel. Specifically, when the first terminal 112 of the first transistor is electrically connected to the capacitor storage cell and the second terminal 122 of the second transistor is electrically connected to the magnetic storage cell, and the same word line 22 simultaneously controls the first and second transistors, a large difference in width between the first and second channels would increase the difficulty of controlling the word line 22. Within the aforementioned width range, the first and second channels can effectively balance the requirements of drive current and control difficulty.

[0098] Appendix Figure 5 This is a schematic diagram of another arrangement of multiple third active regions in a specific embodiment of the present invention. Optionally, such as... Figure 5 As shown, the semiconductor structure also includes multiple word lines 22 extending along the first direction D1;

[0099] The plurality of the third active regions 25 are arranged in an array inside the substrate 10, the third active regions 25 extend along a third direction D3, and the third direction D3 is perpendicular to the first direction D1.

[0100] Optionally, along the third direction D3, the first transistors in adjacent third active regions 25 are close to each other or the second transistors are close to each other.

[0101] Optionally, the word line 22 includes a first sub-word line and a second sub-word line arranged alternately along the third direction D3;

[0102] The first transistors in the plurality of third active regions 25 arranged along the first direction D1 all overlap with the same first sub-word line 221;

[0103] The second transistors in the plurality of third active regions 25 arranged along the first direction D1 all overlap with the same second sub-word line 222.

[0104] Optionally, the projection portions of two adjacent third active regions 25 arranged along the third direction D3 overlap, wherein the projection is the projection of the third active region 25 onto the third direction D3.

[0105] Optionally, the first transistors of two adjacent third active regions 25 arranged along the third direction D3 correspond to the same word line.

[0106] Specifically, such as Figure 5As shown, the substrate 20 has a plurality of third active regions 25 arranged in an array, and each third active region 25 extends in a direction perpendicular to the extension direction of the word line (i.e., the first direction) (i.e., the third direction). The projections of two adjacent third active regions 25 arranged along the third direction D3 overlap, which can significantly increase the arrangement density of the third active regions 25, increase the density of memory cells in the semiconductor structure, and help reduce the size of memory cells. Each third active region 25 has one first transistor and one second transistor. The first transistor and the second transistor are distributed along the third direction D3 on opposite sides of the third active region 25. Two word lines 22 pass through a third active region 25 and control the first transistor and the second transistor on the third active region 25, respectively. The width W1 of the first channel is the length of the first channel along the first direction D1, and the width W2 of the second channel is the length of the second channel along the first direction D1. The first transistor and the second transistor, located within the same third active region 25, share the third common terminal. The third common terminal may be located in the middle of the third active region 25, specifically between the two word lines 22 on the third active region 25. The third common terminal includes a first side facing the first channel and a second side opposite to the first side, the second side facing the second channel. Since the width of the first channel of the first transistor is smaller than the width of the second channel of the second transistor, the width of the first side of the third common terminal (width along the first direction D1) is smaller than the width of the second side (width along the first direction D1).

[0107] By defining that, along the third direction D3, the first transistors or second transistors in adjacent third active regions 25 are close to each other, and the first transistors in multiple third active regions 25 arranged along the first direction D1 all overlap with the same first sub-word line 221, and the second transistors in multiple third active regions 25 arranged along the first direction D1 all overlap with the same second sub-word line 222, it is possible to simultaneously drive two adjacent first transistors in third active regions 25 through a single first sub-word line 221, and simultaneously drive two adjacent second transistors in third active regions 25 through a single second sub-word line 222. This simplifies the driving method of the semiconductor structure and allows for flexible control of either the first or second transistors. Furthermore, the fact that two adjacent first transistors in two adjacent third active regions 25 arranged along the third direction D3 correspond to the same word line 221 further simplifies the driving method of the semiconductor structure and increases the storage density.

[0108] Optionally, the width of the second channel is 2 to 3 times the width of the first channel. Specifically, when the first terminal 112 of the first transistor is electrically connected to the capacitive storage cell and the second terminal 122 of the second transistor is electrically connected to the magnetic storage cell, the first channel and the second channel can achieve optimized device performance within the aforementioned width range. Specifically, the smaller width of the first channel of the first transistor can minimize leakage current, and the larger width of the second channel of the second transistor can maximize the drive current, thereby improving device performance.

[0109] Optionally, the third active region 25 includes a first portion 251 and a second portion 252, wherein the width of the second portion 252 is greater than the width of the first portion 251. The width of the first portion 251 can be the width of the first portion 251 of the third active region 25 in the direction perpendicular to the extension of the third active region 25; similarly, the width of the second portion 252 can be the width of the second portion 252 of the third active region 25 in the direction perpendicular to the extension of the third active region 25. Specifically, as... Figure 1 , Figure 4 and Figure 5 As shown, two word lines 22 intersect with the first portion 251 and the second portion 252 of a third active region 25, respectively. The single third active region 25 is divided by the two word lines 22 into a first end 112, a second end 122, and a third common end 16. The first end 112 can be the drain of a first transistor, the second end 122 can be the drain of a second transistor, and the third common end 16 can be the common source of the first and second transistors. Specifically, as... Figure 4 As shown, the width of the first channel can be the width of the overlapping area of ​​the word line 22 and the first portion 251 of the third active region 25 in the extending direction of the word line 22; the width of the second channel can be the width of the overlapping area of ​​the word line 22 and the second portion 252 of the third active region 25 in the extending direction of the word line 22. The width of the channel can be changed by adjusting the size of the overlapping area of ​​the word line 22 and the third active region 25 by setting the width of the first and second portions of the third active region 25.

[0110] Optionally, the first type of storage unit 15 includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit.

[0111] The second type of storage unit 17 includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit;

[0112] The storage types of the first type of storage unit 15 and the second type of storage unit 17 are different.

[0113] Optionally, the first type of storage unit 15 is a capacitor storage unit;

[0114] The second type of storage unit 17 is a magnetic storage unit.

[0115] For example, such as Figure 1 As shown, the first type of storage cell 15 is a capacitor storage cell, and the second type of storage cell 17 is a magnetic storage cell (e.g., a magnetic tunnel junction). The capacitor storage cell is electrically connected to the first terminal 112 of the first transistor via a first plug 14. The bottom end of the magnetic storage cell is connected to a bottom electrode 181, and the top end of the magnetic storage cell is connected to a top electrode 182. The bottom electrode 181 is electrically connected to the second terminal 122 of the second transistor via a second plug 20, and the top electrode 182 is electrically connected to the bit line 19 via a third plug 21.

[0116] Furthermore, this specific embodiment also provides a method for forming a semiconductor structure. (See appendix) Figure 6 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of the present invention. A schematic diagram of the semiconductor structure formed in this specific embodiment can be found in [reference needed]. Figure 1 , Figure 4 and Figure 5 .like Figure 1 , Figures 4-6 As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:

[0117] Step S61, provide substrate 10;

[0118] Step S62: A first transistor and a second transistor are formed in the substrate 10. The first transistor includes a first channel located in the substrate 10 and a first end 112 located on the surface of the substrate 10. The first end 112 is used to connect to a first type memory cell 15. The second transistor includes a second channel located in the substrate 10 and a second end 122 located on the surface of the substrate 10. The second end 122 is used to connect to a second type memory cell 17. The width W2 of the second channel is greater than the width W1 of the first channel.

[0119] Optionally, the specific steps for forming the first transistor and the second transistor in the substrate 10 include:

[0120] An active region is formed in the substrate 10, the active region including a first portion 251 and a second portion 252, wherein the width of the second portion 252 is greater than the width of the first portion 251.

[0121] A first gate trench and a second gate trench are formed in the first portion 251 and the second portion 252 of the active region, respectively. The active region is divided by the first gate trench and the second gate trench into a first end, a second end, and a common end between the first end and the second end.

[0122] Gate material is filled in the first gate trench and the second gate trench to form the first gate and the second gate.

[0123] Optionally, the method for forming the semiconductor structure further includes the following steps:

[0124] The active region is etched to form the first gate trench and the second gate trench on opposite sides of the active region extending in the direction of extension.

[0125] The first gate and the second gate are formed by filling the first gate trench and the second gate trench in the active region with gate material.

[0126] Optional, also includes:

[0127] Multiple word lines 22 extending along a first direction are formed within the substrate 10;

[0128] The active regions are arranged in an array within the substrate, and the active regions extend along a second direction, which is tilted at a predetermined angle relative to the first direction.

[0129] Optionally, along the second direction, the first transistor in one of two adjacent active regions is positioned opposite to the second transistor in the other active region.

[0130] Optionally, along the first direction, the first transistor in one of two adjacent active regions and the second transistor in the other active region correspond to the same word line 22.

[0131] Optional, also includes:

[0132] Multiple word lines 22 extending along a first direction are formed within the substrate 10;

[0133] The active regions are arranged in an array inside the substrate 10, and the active regions extend along a third direction, which is perpendicular to the first direction.

[0134] Optionally, along the third direction, the first transistors of two adjacent active regions are brought close to each other, or the second transistors are brought close to each other.

[0135] Optionally, the character line 22 includes a first sub-character line and a second sub-character line arranged alternately along the third direction;

[0136] The first transistors in the plurality of active regions arranged along the first direction all overlap with the same first sub-word line 221;

[0137] The second transistors in the plurality of active regions arranged along the first direction all overlap with the same second sub-word line 222.

[0138] Optionally, the projections of two adjacent active regions arranged along the third direction overlap, wherein the projection is the projection of the active region along the third direction.

[0139] Optionally, the first type of storage unit 15 includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit.

[0140] The second type of storage unit 17 includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit;

[0141] The storage types of the first type of storage unit 15 and the second type of storage unit 17 are different.

[0142] Optionally, the first type of storage unit 15 is a capacitor storage unit;

[0143] The second type of storage unit 17 is a magnetic storage unit.

[0144] The semiconductor structure and its formation method provided in this specific embodiment, by simultaneously setting a first transistor for connection to a first type of memory cell and a second transistor for connection to a second type of memory cell in the semiconductor structure, wherein both the first channel and the second channel are located within the substrate, and the width of the first channel in the first transistor is defined as smaller than the width of the second channel in the second transistor, achieves the effect of making the manufacturing process of the first transistor compatible with that of the second transistor, thus simplifying the manufacturing method of the semiconductor structure. Furthermore, it ensures that the drive current of the first transistor is less than that of the second transistor, which helps to increase the integration density of memory cells having the first transistor and / or the second transistor in the memory, and reduces the size of the memory cells, laying the foundation for expanding the application areas of memory.

[0145] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The first transistor includes a first channel located within the substrate and a first end located on the surface of the substrate, the first end being used to connect to a first type of memory cell; The second transistor includes a second channel located within the substrate and a second end located on the surface of the substrate, the second end being used to connect to a second type of memory cell, and the width of the second channel being greater than the width of the first channel; The substrate further includes at least one third active region, wherein the third active region has the first transistor and the second transistor; The first transistor and the second transistor are distributed on opposite sides of the extension direction of the third active region, and the first transistor and the second transistor located in the third active region have a third common terminal; It also includes multiple letter lines extending along the first direction; The plurality of the third active regions are arranged in an array inside the substrate, the third active regions extend along a second direction, and the second direction is tilted at a predetermined angle relative to the first direction; Along the second direction, the first transistor located in the adjacent third active region is disposed opposite to the second transistor; Along the first direction, the first transistor and the second transistor located in adjacent third active regions correspond to the same word line; The third active region includes a first part and a second part, wherein the width of the second part is greater than the width of the first part.

2. The semiconductor structure according to claim 1, characterized in that, The width of the second channel is 1.5 to 3 times the width of the first channel.

3. The semiconductor structure according to claim 1, characterized in that, The substrate further includes at least one first active region, wherein the first active region has two of the first transistors; Two first transistors are distributed on opposite sides of the extension direction of the first active region, and the two first transistors located in the first active region have a first common terminal.

4. The semiconductor structure according to claim 1, characterized in that, The substrate further includes at least one second active region, wherein the second active region has two second transistors; Two second transistors are distributed on opposite sides of the extension direction of the second active region, and the two second transistors located in the second active region have a second common terminal.

5. The semiconductor structure according to claim 1, characterized in that, The width of the second channel is 1.5 to 2 times the width of the first channel.

6. The semiconductor structure according to claim 1, characterized in that, It also includes multiple letter lines extending along the first direction; The plurality of the third active regions are arranged in an array inside the substrate, the third active regions extending along a third direction and the third direction being perpendicular to the first direction.

7. The semiconductor structure according to claim 6, characterized in that, Along the third direction, the first transistors in adjacent third active regions are close to each other or the second transistors are close to each other.

8. The semiconductor structure according to claim 7, characterized in that, The character lines include first and second sub-character lines arranged alternately along the third direction; The first transistors in the plurality of third active regions arranged along the first direction all overlap with the same first sub-word line; The second transistors in the plurality of third active regions arranged along the first direction all overlap with the same second sub-word line.

9. The semiconductor structure according to claim 8, characterized in that, The width of the second channel is 2 to 3 times the width of the first channel.

10. The semiconductor structure according to claim 8, characterized in that, The projections of two adjacent third active regions arranged along the third direction overlap, and the projection is the projection of the third active region along the third direction.

11. The semiconductor structure according to claim 10, characterized in that, The first transistors of two adjacent third active regions arranged upwards along the third line correspond to the same word line.

12. The semiconductor structure according to any one of claims 1-11, characterized in that, The first type of storage unit includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit; The second type of storage unit includes any one of the following: capacitor storage unit, resistor storage unit, magnetic storage unit, phase change storage unit, and ferroelectric storage unit; The storage types of the first type of storage unit and the second type of storage unit are different.

13. The semiconductor structure according to claim 12, characterized in that, The first type of storage unit is a capacitor storage unit; The second type of storage unit is a magnetic storage unit.

14. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A first transistor and a second transistor are formed in the substrate. The first transistor includes a first channel located in the substrate and a first end located on the surface of the substrate. The first end is used to connect to a first type of memory cell. The second transistor includes a second channel located in the substrate and a second end located on the surface of the substrate. The second end is used to connect to a second type of memory cell. The width of the second channel is greater than the width of the first channel. The specific steps for forming the first transistor and the second transistor in the substrate include: An active region is formed in the substrate, the active region comprising a first portion and a second portion, wherein the width of the second portion is greater than the width of the first portion; A first gate trench and a second gate trench are formed in the first part and the second part of the active region, respectively. The active region is divided by the first gate trench and the second gate trench into a first end, a second end, and a common end between the first end and the second end. Fill the first gate trench and the second gate trench with gate material to form a first gate and a second gate; The method for forming the semiconductor structure further includes the following steps: The active region is etched to form the first gate trench and the second gate trench on opposite sides of the active region extending in the direction of extension. Fill the first gate and the second gate trench in the active region with gate material to form the first gate and the second gate; Also includes: Multiple word lines extending along a first direction are formed within the substrate; The active regions are arranged in an array inside the substrate, the active regions extend along a second direction, and the second direction is tilted at a predetermined angle relative to the first direction; Along the second direction, the first transistor in one of two adjacent active regions is positioned opposite to the second transistor in the other active region; Along the first direction, the first transistor in one of two adjacent active regions and the second transistor in the other active region correspond to the same word line.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, Also includes: Multiple word lines extending along a first direction are formed within the substrate; The active regions are arranged in an array inside the substrate, the active regions extend along a third direction, and the third direction is perpendicular to the first direction.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, Along the third direction, the first transistors of two adjacent active regions are close to each other or the second transistors are close to each other.

17. The method for forming a semiconductor structure according to claim 16, characterized in that, The character lines include first and second sub-character lines arranged alternately along the third direction; The first transistors in the plurality of active regions arranged along the first direction all overlap with the same first sub-word line; The second transistors in the plurality of active regions arranged along the first direction all overlap with the same second sub-word line.

18. The method for forming a semiconductor structure according to claim 16, characterized in that, The projections of two adjacent active regions arranged along the third direction overlap, and the projection is the projection of the active region along the third direction.

19. The method for forming a semiconductor structure according to any one of claims 14-18, characterized in that, The first type of storage unit includes any one of a capacitor storage unit, a resistor storage unit, a magnetic storage unit, a phase change storage unit, and a ferroelectric storage unit; The second type of storage unit includes any one of the following: capacitor storage unit, resistor storage unit, magnetic storage unit, phase change storage unit, and ferroelectric storage unit; The storage types of the first type of storage unit and the second type of storage unit are different.

20. The method for forming a semiconductor structure according to claim 19, characterized in that, The first type of storage unit is a capacitor storage unit; The second type of storage unit is a magnetic storage unit.

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