Single-mode vertical cavity surface emitting laser chip

Abstract

The present application provides a single-mode vertical cavity surface emitting laser chip and a laser containing the same, the chip comprising: a chip substrate, a buffer layer, a chip bottom mirror structure, an optical cavity and a chip top mirror structure arranged in sequence; along the direction from the chip substrate to the chip top mirror structure, the optical cavity is provided with a first cladding layer, an active region layer, a second cladding layer and a current limiting layer in sequence; the insulating material part of the current limiting layer surrounds the semiconductor material part of the current limiting layer; the chip bottom mirror structure is provided with a first reflector layer, and the chip top mirror structure is provided with a fourth reflector layer; the single-mode vertical cavity surface emitting laser chip satisfies at least one of the following conditions: a first cavity layer and a second reflector layer are provided in sequence between the first reflector layer and the first cladding layer; and a third reflector layer and a second cavity layer are provided in sequence between the current limiting layer and the fourth reflector layer. The solution provided in the present application can realize that the vertical cavity surface emitting laser can stably maintain a single-mode working state.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a single-mode vertical cavity surface emitting laser chip. Background Art

[0002] Since its commercialization in 1996, Vertical Cavity Surface Emitting Laser (VCSEL) has been widely used in many fields such as optical communication, information reading, 3D imaging, LiDAR, etc. Various VCSELs have penetrated into the production of various industries due to their advantages such as small size, circular output spot, low threshold current, low power consumption, low cost and easy array integration, playing a huge role in people's life progress and social development.

[0003] In the prior art, the structure adopted by the vertical cavity surface emitting laser chip is two upper and lower distributed Bragg reflectors (Distributed Bragg reflectors). A vertical cavity surface emitting laser (VCSEL) is a laser diode that is used to emit light from a laser beam. The laser diode (DBR) is used to hold an optical cavity containing a quantum well or quantum dot active region to form a vertical resonant cavity. A current injection restriction window is formed in the optical cavity through a wet oxidation process. Since the refractive index of the semiconductor material in the current injection restriction window is greater than that of the surrounding insulating material, in the VCSEL structure, the equivalent refractive index of the longitudinal region corresponding to the current injection restriction window is also greater than that of the longitudinal region corresponding to the surrounding insulating material, which is equivalent to forming an equivalent lateral distributed optical waveguide in the horizontal direction. However, due to the strong light field restriction capability of this equivalent lateral optical waveguide, both the fundamental transverse mode and the high-order transverse mode of the VCSEL chip are effectively matched with the gain region of the VCSEL chip determined by the current injection restriction window. Therefore, both the fundamental transverse mode and the high-order transverse mode obtain considerable optical gain, resulting in multi-mode output of the VCSEL chip when it is working. A large mode dispersion will be introduced during optical signal transmission. At the same time, the optical phase plane of the outgoing light field of the VCSEL changes complexly, which is not conducive to the recognition of three-dimensional imaging.

[0004] Therefore, it is necessary to optimize the VCSEL chip structure so that it can stably maintain a single-mode operating state. Summary of the invention

[0005] The present application provides a single-mode vertical cavity surface emitting laser chip and a laser containing the same, so as to solve the defects in the prior art that the vertical cavity surface emitting laser operates in a multi-mode state, resulting in the introduction of large mode dispersion during optical signal transmission, complex changes in the phase plane of the output light field, and is not conducive to the recognition of three-dimensional imaging, so as to achieve the effect of stably maintaining the single-mode working state of the vertical cavity surface emitting laser.

[0006] The present application provides a single-mode vertical cavity surface emitting laser chip, comprising:

[0007] A chip substrate 1, a buffer layer 2, a chip bottom mirror structure 3, an optical cavity 4 and a chip top mirror structure 5 are arranged in sequence;

[0008] Along the direction from the chip substrate 1 to the chip top mirror structure 5, the optical cavity 4 is provided with a first cladding layer 41, an active region layer 42, a second cladding layer 43 and a current limiting layer 44 in sequence;

[0009] The current limiting layer 44 includes an insulating material portion and a semiconductor material portion, the insulating material portion surrounds the semiconductor material portion, and the diameter of the semiconductor material portion is smaller than a preset diameter threshold;

[0010] The chip bottom mirror structure 3 is provided with a first reflector layer 31, and the chip top mirror structure 5 is provided with a fourth reflector layer 53;

[0011] The single-mode vertical cavity surface emitting laser chip meets at least one of the following conditions:

[0012] In the chip bottom mirror structure 3, along the direction from the chip substrate 1 to the chip top mirror structure 5, a first cavity layer 32 and a second reflector layer 33 are sequentially provided between the first reflector layer 31 and the first cladding layer 41;

[0013] as well as

[0014] In the chip top mirror structure 5 , along the direction from the chip substrate 1 to the chip top mirror structure 5 , a third reflector layer 51 and a second cavity layer 52 are sequentially provided between the current limiting layer 44 and the fourth reflector layer 53 .

[0015] In one embodiment, the chip bottom mirror structure 3 is further provided with a fifth reflector layer 34 and a third cavity layer 35;

[0016] The fifth reflector layer 34 , the third cavity layer 35 and the first reflector layer 31 are sequentially arranged along the direction from the chip substrate 1 to the chip top mirror structure 5 .

[0017] In one embodiment, the chip top mirror structure 5 is further provided with a sixth reflector layer 54 and a fourth cavity layer 55;

[0018] The fourth reflector layer 53 , the fourth cavity layer 55 and the sixth reflector layer 54 are sequentially arranged along the direction from the chip substrate 1 to the chip top mirror structure 5 .

[0019] In one embodiment, the first reflector layer 31 , the second reflector layer 33 , the third reflector layer 51 , the fourth reflector layer 53 , the fifth reflector layer 34 and the sixth reflector layer 54 are made of III-V semiconductor materials.

[0020] In one embodiment, the first reflector layer 31 , the second reflector layer 33 , the third reflector layer 51 , the fourth reflector layer 53 , the fifth reflector layer 34 and the sixth reflector layer 54 are made of dielectric film materials.

[0021] In one embodiment, the number of material film layers of the second reflector layer 33, the third reflector layer 51, the fifth reflector layer 34 and the sixth reflector layer 54 is less than a first layer number threshold, the number of material film layers of the first reflector layer 31 and the fourth reflector layer 53 is greater than a second layer number threshold, the second layer number threshold is greater than the first layer number threshold, and the first layer number threshold is greater than zero.

[0022] In one embodiment, the center wavelength of the reflection spectrum of the first reflector layer 31 and the fourth reflector layer 53 is a first preset wavelength;

[0023] The central wavelength of the reflection spectrum of the second reflector layer 33 and the fifth reflector layer 34 is the second preset wavelength;

[0024] The central wavelength of the reflection spectrum of the third reflector layer 51 and the sixth reflector layer 54 is the third preset wavelength;

[0025] The first preset wavelength, the second preset wavelength and the third preset wavelength are all greater than zero.

[0026] In one embodiment, the insulating material portion of the current limiting layer 44 is an aluminum oxide insulating material obtained by oxidizing a III-V semiconductor material layer with a high Al content through a wet oxidation process;

[0027] The semiconductor material portion of the current limiting layer 44 is the remaining material of the III-V semiconductor material layer that has not been oxidized;

[0028] The III-V semiconductor material layer with a high Al content is a III-V semiconductor material layer with an Al content greater than 90%.

[0029] In one embodiment, the optical cavity 4 is further provided with a third cladding 45;

[0030] The first cladding layer 41, the active region layer 42, the second cladding layer 43, the current limiting layer 44, the third cladding layer 45 and the third reflector layer 51 are sequentially arranged along the direction from the chip substrate 1 to the chip top mirror structure 5;

[0031] The first cladding layer 41, the active region layer 42, the second cladding layer 43, the current confinement layer 44 and the third cladding layer 45 are made of III-V semiconductor materials;

[0032] The active region layer 42 is one of a quantum well active region layer and a quantum dot active region layer.

[0033] In one embodiment, the reflector structure of the first reflector layer 31, the second reflector layer 33, the third reflector layer 51, the fourth reflector layer 53, the fifth reflector layer 34 and the sixth reflector layer 54 is any one of a distributed Bragg reflector structure, a sub-wavelength grating reflector structure and a photonic crystal reflector structure.

[0034] The single-mode vertical cavity surface emitting laser chip provided by the present application is provided with a chip substrate, a buffer layer, a chip bottom mirror structure, an optical cavity and a chip top mirror structure in sequence, and along the direction from the chip substrate to the chip top mirror structure, the optical cavity is provided with a first cladding layer, an active region layer, a second cladding layer and a current limiting layer in sequence, the chip bottom mirror structure is provided with a first reflector layer, and the chip top mirror structure is provided with a fourth reflector layer. The single-mode vertical cavity surface emitting laser chip also needs to meet at least one of the following conditions: in the chip bottom mirror structure, along the direction from the chip substrate to the chip top mirror structure, a first cavity layer and a second reflector layer are provided in sequence between the first reflector layer and the first cladding layer, and in the chip top mirror structure, along the direction from the chip substrate to the chip top mirror structure, a third reflector layer and a second cavity layer are provided in sequence between the current limiting layer and the fourth reflector layer, thereby optimizing the chip top mirror structure and the chip bottom mirror structure of the vertical cavity surface emitting laser, and strengthening the equivalent optical waveguide effect of the longitudinal distribution in the vertical direction of the chip in the chip structure. The longitudinally distributed equivalent optical waveguide effect is The guide can guide the propagation of the lasing light wave of the single-mode vertical cavity surface emitting laser chip in the horizontal direction, thereby expanding the light field distribution of the fundamental transverse mode and the high-order transverse mode of the single-mode vertical cavity surface emitting laser chip in the horizontal direction, and making the light field distribution of its high-order transverse mode much larger than the fundamental transverse mode, and then in the current limiting layer, the semiconductor material part is surrounded by the insulating material part, so as to form a current injection limiting window, and the diameter of the semiconductor material part is less than the preset diameter threshold, so as to achieve the effect of limiting the current injection aperture of the current injection limiting window of the vertical cavity surface emitting laser, and make the light field distribution of the fundamental transverse mode match the optical gain area in the active area layer limited under the current injection limiting window, and at the same time make the light field distribution of the high-order transverse mode much larger than the optical gain area in the active area layer limited under the current injection limiting window, which can effectively suppress the gain of the high-order transverse mode, so that the gain of the high-order transverse mode is much smaller than the gain of the fundamental transverse mode, limit the generation of the high-order transverse mode, and ensure that the vertical cavity surface emitting laser chip stably maintains a single-mode working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 It is a schematic diagram of the structure of a single-mode vertical cavity surface emitting laser chip provided by the present application;

[0037] Figure 2 This is a first single-mode operating characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by the present application;

[0038] Figure 3 This is a second single-mode operating characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by the present application;

[0039] Figure 4 This is a third single-mode operating characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by the present application.

[0040] Reference numerals:

[0041] 1: chip substrate; 2: buffer layer; 3: chip bottom mirror structure; 31: first reflector layer; 32: first cavity layer; 33: second reflector layer; 34: fifth reflector layer; 35: third cavity layer; 4: optical cavity; 41: first cladding layer; 42: active area layer; 43: second cladding layer; 44 current limiting layer; 45: third cladding layer; 5: chip top mirror structure; 51: third reflector layer; 52 second cavity layer; 53: fourth reflector layer; 55: fourth cavity layer; 54: sixth reflector layer; 6: ohmic contact layer. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] Figure 1 Schematic diagram of the structure of the single-mode vertical cavity surface emitting laser chip provided by this application. Figure 1 An embodiment of a single-mode vertical cavity surface emitting laser chip provided by the present application may include:

[0044] A chip substrate 1, a buffer layer 2, a chip bottom mirror structure 3, an optical cavity 4 and a chip top mirror structure 5 are arranged in sequence, the substrate is a clean single crystal thin slice with specific crystal planes and appropriate electrical, optical and mechanical properties for growing epitaxial layers, along the direction from the chip substrate 1 to the chip top mirror structure 5, the optical cavity 4 is provided with a first cladding layer 41, an active region layer 42, a second cladding layer 43 and a current limiting layer 44 in sequence, the chip bottom mirror structure 3 is provided with a first reflector layer 31, and the chip top mirror structure 5 is provided with a fourth reflector layer 53, wherein the first reflector layer 31 and the fourth reflector layer 53 are main reflector layers, and the current limiting layer 44 includes an insulating material part and a semiconductor material part, the insulating material part surrounds the semiconductor material part, thereby forming a current injection limiting window, and the diameter of the semiconductor material part is less than a preset diameter threshold, thereby achieving the effect of limiting the current injection aperture of the current injection limiting window of the vertical cavity surface emitting laser. It can be understood that the semiconductor material portion is the current injection limiting window, which can be regarded as the central point of the current limiting layer 44, and its periphery is surrounded by the insulating material portion, and the diameter range of the semiconductor material portion is limited. In the embodiment of the present application, the preset diameter threshold can be set to any value less than or equal to 10 microns. Preferably, the preset diameter threshold can be set to 10 microns. In actual applications, the setting method of the preset diameter threshold is diverse and needs to be set according to the actual application situation. It is not the only limitation here.

[0045] The single-mode vertical cavity surface emitting laser chip satisfies at least one of the following conditions: in the chip bottom mirror structure, along the direction from the chip substrate 1 to the chip top mirror structure 5, a first cavity layer 32 and a second reflector layer 33 are sequentially arranged between the first reflector layer 31 and the first cladding layer 41; and in the chip top mirror structure, along the direction from the chip substrate 1 to the chip top mirror structure 5, a third reflector layer 51 and a second cavity layer 52 are sequentially arranged between the current limiting layer 44 and the fourth reflector layer 53. The chip bottom mirror structure 3 and the chip top mirror structure 5 of the multi-layer reflector layer and the multi-layer cavity layer are adopted. The equivalent optical waveguide with longitudinal distribution in the vertical direction is strengthened in the chip structure. The longitudinally distributed equivalent optical waveguide can guide the laser light of the single-mode vertical cavity surface emitting laser chip to propagate in the horizontal direction, thereby expanding the light field distribution of the fundamental transverse mode and the high-order transverse mode of the single-mode vertical cavity surface emitting laser chip in the horizontal direction, and making the light field distribution of its high-order transverse mode much larger than the fundamental transverse mode. Combined with the current injection limiting window of the current limiting layer to limit the optical gain zone in the active region layer, the gain of the high-order transverse mode of the vertical cavity surface emitting laser chip can be effectively limited, thereby suppressing the generation of high-order transverse modes.

[0046] From the above embodiments, the following beneficial effects can be seen:

[0047] By sequentially arranging a chip substrate, a buffer layer, a chip bottom mirror structure, an optical cavity and a chip top mirror structure, and along the direction from the chip substrate to the chip top mirror structure, the optical cavity is sequentially provided with a first cladding layer, an active region layer, a second cladding layer and a current limiting layer, the chip bottom mirror structure is provided with a first reflector layer, and the chip top mirror structure is provided with a fourth reflector layer, the single-mode vertical cavity surface emitting laser chip must also meet at least one of the following conditions: in the chip bottom mirror structure, along the direction from the chip substrate to the chip top mirror structure, a first cavity layer and a second reflector layer are sequentially provided between the first reflector layer and the first cladding layer, and in the chip top mirror structure, along the direction from the chip substrate to the chip top mirror structure, a third reflector layer and a second cavity layer are sequentially provided between the current limiting layer and the fourth reflector layer, thereby optimizing the chip top mirror structure and the chip bottom mirror structure of the vertical cavity surface emitting laser, and strengthening the equivalent optical waveguide effect of the longitudinal distribution in the vertical direction of the chip in the chip structure, and the longitudinally distributed equivalent optical waveguide can guide the single-mode vertical cavity The lasing light waves of the surface emitting laser chip propagate in the horizontal direction, thereby expanding the light field distribution of the fundamental transverse mode and the high-order transverse mode of the single-mode vertical cavity surface emitting laser chip in the horizontal direction, and making the light field distribution of its high-order transverse mode much larger than the fundamental transverse mode, and then in the current limiting layer, the semiconductor material part is surrounded by the insulating material part, so as to form a current injection limiting window, and the diameter of the semiconductor material part is less than the preset diameter threshold, so as to achieve the effect of limiting the current injection aperture of the current injection limiting window of the vertical cavity surface emitting laser, and make the light field distribution of the fundamental transverse mode match the optical gain area in the active area layer limited under the current injection limiting window, and at the same time make the light field distribution of the high-order transverse mode much larger than the optical gain area in the active area layer limited under the current injection limiting window, which can effectively suppress the gain of the high-order transverse mode, so that the gain of the high-order transverse mode is less than the gain of the fundamental transverse mode, limit the generation of the high-order transverse mode, and ensure that the vertical cavity surface emitting laser chip stably maintains a single-mode working state.

[0048] For ease of understanding, an embodiment of a single-mode vertical cavity surface emitting laser chip is provided below for illustration. In practical applications, the single-mode vertical cavity surface emitting laser chip will be further designed. Figure 1 An embodiment of a single-mode vertical cavity surface emitting laser chip provided by the present application may include:

[0049] The chip bottom mirror structure 3 is also provided with a fifth reflector layer 34 and a third cavity layer 35, and the fifth reflector layer 34, the third cavity layer 35 and the first reflector layer 31 are sequentially arranged along the direction from the chip substrate 1 to the chip top mirror structure 5. The chip top mirror structure 5 is also provided with a sixth reflector layer 54 and a fourth cavity layer 55, and the fourth reflector layer 53, the fourth cavity layer 55 and the sixth reflector layer 54 are sequentially arranged along the direction from the chip substrate 1 to the chip top mirror structure 5. That is, the fifth reflector layer 34 and the third cavity layer 35 are further arranged on the buffer layer 2, and the fourth cavity layer 55 and the sixth reflector layer 54 are further arranged on the fourth reflector layer 53, so as to further optimize the composition structure of the chip bottom mirror structure 3 and the chip top mirror structure 5, and improve the quality of the longitudinally distributed equivalent optical waveguide in the vertical direction.

[0050] In the embodiment of the present application, the constituent materials of the first reflector layer 31, the second reflector layer 33, the third reflector layer 51, the fourth reflector layer 53, the fifth reflector layer 34 and the sixth reflector layer 54 are III-V semiconductor materials, wherein the III-V semiconductor materials include but are not limited to AlGaAs, GaAs, GaN, InGaN, InGaAs, GaP, InGaP, AlGaP, InGaAlP, InGaAsP, InGaAsN or InGaAlAs and other materials. In actual applications, it is necessary to select appropriate III-V semiconductor materials according to the actual application situation, and no sole limitation is made here.

[0051] In addition, the constituent materials of the first reflector layer 31, the second reflector layer 33, the third reflector layer 51, the fourth reflector layer 53, the fifth reflector layer 34 and the sixth reflector layer 54 may also be dielectric film materials, wherein the dielectric film materials include but are not limited to SiO2, SiN4, SiNOx, MgF, Al2O3 and other materials. In practical applications, it is necessary to select a suitable dielectric film material according to the actual application situation, and no sole limitation is made here.

[0052] It is understandable that, in practical applications, an ohmic contact layer 6 will be provided on the sixth reflector layer 54. If all the reflector layers of the chip bottom mirror structure 3 and all the reflector layers of the chip top mirror structure 5 are composed of III-V semiconductor materials, the electrodes of the single-mode vertical cavity surface emitting laser chip can be respectively provided on the topmost ohmic contact layer 6 and the bottom surface of the chip substrate 1 or the buffer layer 2. When the electrode needs to be provided on the buffer layer 2, the buffer layer 2 needs to be corroded and exposed by a wet or dry etching process to facilitate the production of the electrode. If all the reflector layers of the chip bottom mirror structure 3 and all the reflector layers of the chip top mirror structure 5 are composed of dielectric film materials, the electrodes of the single-mode vertical cavity surface emitting laser chip can be respectively provided on the first cladding layer 41 and the second cladding layer 43.

[0053] In the embodiment of the present application, the thickness of each reflector layer is also optimized. Specifically, the number of material film layers of the second reflector layer 33, the third reflector layer 51, the fifth reflector layer 34 and the sixth reflector layer 54 is less than the first layer number threshold, the number of material film layers of the first reflector layer 31 and the fourth reflector layer 53 is greater than the second layer number threshold, the second layer number threshold is greater than the first layer number threshold, and the first layer number threshold is greater than zero, wherein the first layer number threshold can be set to 4 layers, and the second layer number threshold can be set to 20 layers. In actual applications, there are various ways to set the first layer number threshold and the second layer number threshold, which need to be set according to the actual application situation and are not uniquely limited here.

[0054] In the embodiment of the present application, the central wavelength of the reflection spectrum of each reflector layer is also optimized, wherein the central wavelength of the reflection spectrum of the first reflector layer 31 and the fourth reflector layer 53 is the first preset wavelength, the central wavelength of the reflection spectrum of the second reflector layer 33 and the fifth reflector layer 34 is the second preset wavelength, and the central wavelength of the reflection spectrum of the third reflector layer 51 and the sixth reflector layer 54 is the third preset wavelength. In particular, at least one of the second preset wavelength and the third preset wavelength may be equal to the first preset wavelength, that is, the second preset wavelength is equal to the first preset wavelength, or the third preset wavelength is equal to the first preset wavelength, or the second preset wavelength is equal to the third preset wavelength and the first preset wavelength. It may also be that the first preset wavelength, the second preset wavelength and the third preset wavelength are not equal, which needs to be determined according to the actual application situation and is not limited here. However, if the optical thickness of the first cavity layer is equal to one-quarter of the first preset wavelength, the second preset wavelength must not be equal to the first preset wavelength; if the optical thickness of the second cavity layer is equal to one-quarter of the first preset wavelength, the third preset wavelength must not be equal to the first preset wavelength.

[0055] In addition, in the current limiting layer 44, the insulating material part is an aluminum oxide insulating material obtained by oxidizing a III-V semiconductor material layer with a high Al component through a wet oxidation process, wherein the III-V semiconductor material layer with a high Al component is a III-V semiconductor material layer with an Al component greater than 90%. It can be understood that the semiconductor material part is the remaining material of the III-V semiconductor material layer that has not been oxidized, and the semiconductor material part can be regarded as a current injection limiting window of the current limiting layer. Since the refractive index of the aluminum oxide insulating material is smaller than that of the III-V semiconductor material such as AlGaAs, in the vertical cavity surface emitting laser structure, the equivalent refractive index of the longitudinal region corresponding to the current injection limiting window is greater than the equivalent refractive index of the longitudinal region corresponding to the surrounding insulating material, which is equivalent to forming an equivalent transverse distributed optical waveguide in the horizontal direction, limiting the transverse mode light field distribution of the vertical cavity surface emitting laser chip, and making it effectively match the optical gain region of the vertical cavity surface emitting laser chip, and the optical gain region is the quantum well or quantum dot active region layer limited by its aperture under this current injection limiting window, thereby achieving an optical gain effect.

[0056] In the embodiment of the present application, the optical cavity 4 is further provided with a third cladding 45, and the first cladding 41, the active region layer 42, the second cladding 43, the current limiting layer 44, the third cladding 45 and the third reflector layer 51 are arranged in sequence from the chip substrate 1 to the chip top mirror structure 5, and the constituent materials of the first cladding 41, the active region layer 42, the second cladding 43, the current limiting layer 44 and the third cladding 45 are III-V group semiconductor materials, wherein the active region layer 42 is one of a quantum well active region layer and a quantum dot active region layer.

[0057] In the embodiment of the present application, the reflector structure of the first reflector layer 31, the second reflector layer 33, the third reflector layer 51, the fourth reflector layer 53, the fifth reflector layer 34 and the sixth reflector layer 54 is any one of a distributed Bragg reflector structure, a sub-wavelength grating reflector structure and a photonic crystal reflector structure.

[0058] From the above embodiments, the following beneficial effects can be seen:

[0059] By further optimizing the composition structure of the chip bottom mirror structure 3 and the chip top mirror structure 5, optimizing the setting of the thickness of each reflector layer, and optimizing the setting of the reflection spectrum center wavelength of each reflector layer, the current injection aperture of the current injection limiting window of the current limiting layer can effectively limit the gain of the high-order transverse mode of the vertical cavity surface emitting laser chip, thereby suppressing the generation of high-order transverse modes, so that the vertical cavity surface emitting laser chip can stably maintain a single-mode working state, thereby improving the performance of the optical communication link and three-dimensional imaging system of the device using the relevant vertical cavity surface emitting laser chip.

[0060] For ease of understanding, an embodiment of a single-mode vertical cavity surface emitting laser chip is provided below for illustration. In practical applications, the single-mode vertical cavity surface emitting laser chip can achieve single-mode operating characteristics with a peak wavelength of 853.8nm and a 20dB line width of approximately 0.2nm.

[0061] Figure 2 This is the first single-mode working characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by this application, please refer to Figure 1 and Figure 2 An embodiment of a single-mode vertical cavity surface emitting laser chip provided by the present application may include:

[0062] Since the first cavity layer 32 and the second cavity layer 33 are sequentially arranged between the first reflector layer 31 and the first cladding layer 41 along the direction from the chip substrate 1 to the chip top mirror structure 5, and the third reflector layer 51 and the second cavity layer 52 are sequentially arranged between the current limiting layer 44 and the fourth reflector layer 53 along the direction from the chip substrate 1 to the chip top mirror structure 5, at least one of the two conditions is satisfied, and the following is an example of the third reflector layer 51 and the second cavity layer 52 being sequentially arranged between the current limiting layer 44 and the fourth reflector layer 53 along the direction from the chip substrate 1 to the chip top mirror structure 5:

[0063] The chip substrate 1 is n-type doped GaAs, the buffer layer 2 is n-type doped GaAs, the first reflector layer 31 is forty pairs of distributed Bragg reflectors composed of Al0.9Ga0.1As / Al0.15G0.85As materials, with a central wavelength of 850nm; the first cladding layer 41 is composed of AlGaAs with a thickness of 90nm; the active region layer 42 is three pairs of GaAs / AlGaAs quantum wells; the second cladding layer 43 is composed of AlGaAs with a thickness of 60nm; the current limiting layer 44 is a 30nm thick Al0.96Ga0.04As material layer, in which the current injection aperture is 6 microns; the third cladding layer 45 is composed of AlGaAs with a thickness of 30nm; the third reflector layer 51 is a distributed Bragg reflector composed of three pairs of Al0.9Ga0.1As / Al0.15G0.85As materials, with a central wavelength of 805nm; the second cavity layer 52 is 112nm thick AlGaAs The fourth reflector layer 53 is composed of 25 pairs of distributed Bragg reflectors made of Al0.9Ga0.1As / Al0.15G0.85As materials, with a central wavelength of 850nm; the ohmic contact layer 6 is a 50nm thick GaAs material. In this embodiment, the chip electrodes are an annular electrode located on the ohmic contact layer 6 and a bottom electrode located on the bottom surface of the chip substrate 1.

[0064] When the first cavity layer 32 and the second cavity layer 33 are sequentially arranged between the first reflector layer 31 and the first cladding layer 41 along the direction from the chip substrate 1 to the chip top mirror structure 5, the third reflector layer 51 and the second cavity layer 52 can be removed or retained. Specifically, the first cavity layer 32 is made of Al0.15Ga0.85 with a thickness of 69nm; the second reflector layer 33 is three pairs of distributed Bragg reflectors made of Al0.9Ga0.1As / Al0.15G0.85As materials, with a central wavelength of 805nm. It can be understood that it needs to be set according to the actual application situation, and it is not limited here.

[0065] In this embodiment, the fifth reflector layer 34, the third cavity layer 35, the sixth reflector layer 54 and the fourth cavity layer 55 can also be added to improve the working performance of the vertical cavity surface emitting laser chip, wherein the fifth reflector layer 34 is four pairs of distributed Bragg reflectors composed of Al0.9Ga0.1As / Al0.15G0.85As materials, with a central wavelength of 805nm; the third cavity layer 35 is composed of Al0.15G0.85As with a thickness of 185nm; the fourth cavity layer 55 is a 125nm thick AlGaAs material; the sixth reflector layer 54 is two pairs of distributed Bragg reflectors composed of Al0.9Ga0.1As / Al0.15G0.85As materials, with a central wavelength of 805nm. It can be understood that whether to add the fifth reflector layer 34, the third cavity layer 35, the sixth reflector layer 54 and the fourth cavity layer 55 needs to be determined according to the actual application situation, and it is not limited here.

[0066] like Figure 2 As shown, the single-mode vertical cavity surface emitting laser chip can achieve a single-mode working characteristic with a peak wavelength of 853.8nm and a 20dB line width of about 0.2nm under the above-mentioned configuration. However, the above-mentioned configuration is only exemplary. In practical applications, it is necessary to determine a suitable configuration according to the actual application situation. No sole limitation is made here to improve the performance of optical communication links and three-dimensional imaging systems of devices using relevant vertical cavity surface emitting laser chips.

[0067] For ease of understanding, an embodiment of a single-mode vertical cavity surface emitting laser chip is provided below for illustration. In practical applications, the single-mode vertical cavity surface emitting laser chip can achieve single-mode operating characteristics with a peak wavelength of 939nm and a 20dB line width of approximately 0.2nm.

[0068] Figure 3 This is a second single-mode operating characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by this application. Please refer to Figure 1 and Figure 3 An embodiment of a single-mode vertical cavity surface emitting laser chip provided by the present application may include:

[0069] The chip substrate 1 is n-type doped GaAs; the buffer layer 2 is n-type doped GaAs; the fifth reflector layer 34 is four pairs of distributed Bragg reflectors composed of Al0.9Ga0.1As / Al0.1G0.9As materials, with a central wavelength of 940nm; the third cavity layer 35 is composed of Al0.1G0.9As with a thickness of 99nm; the first reflector layer 31 is a distributed Bragg reflector composed of thirty-five pairs of Al0.9Ga0.1As / Al0.1G0.9As materials, with a central wavelength of 940nm; the first cavity layer 32 is composed of Al0.1Ga0.9 material with a thickness of 210nm; the second reflector layer 33 is composed of four pairs of Al0.9Ga0.1As / Al0.1G0.9As materials The distributed Bragg reflector has a central wavelength of 940nm; the first cladding 41 is made of AlGaAs with a thickness of 99nm; the active region layer 42 is five pairs of InGaAs / GaAs quantum wells; the second cladding 43 is made of AlGaAs material with a thickness of 67nm; the current limiting layer 44 is a 30nm thick Al0.96Ga0.04As material layer, in which the current injection aperture is 6 microns; the third cladding 45 is made of AlGaAs with a thickness of 35nm; the third reflector layer 51 is a distributed Bragg reflector composed of two pairs of Al0.9Ga0.1As / Al0.1G0.9As materials with a central wavelength of 940nm; the second cavity layer 52 is 175nm thick AlGaAs Materials; the fourth reflector layer 53 is 25 pairs of distributed Bragg reflectors made of Al0.9Ga0.1As / Al0.1G0.9As materials, with a central wavelength of 940nm; the fourth cavity layer 55 is 185nm thick AlGaAs material; the sixth reflector layer 54 is two pairs of distributed Bragg reflectors made of Al0.9Ga0.1As / Al0.1G0.9As materials, with a central wavelength of 940nm; the ohmic contact layer 6 is 50nm thick GaAs material. The chip electrodes are the annular electrodes located on the top of the chip and the bottom electrodes located on the bottom surface of the substrate. In this embodiment, the chip electrodes are the annular electrodes located on the ohmic contact layer 6 and the bottom electrodes located on the bottom surface of the chip substrate 1.

[0070] like Figure 3 As shown, the single-mode vertical cavity surface emitting laser chip can achieve a single-mode working characteristic with a peak wavelength of 939nm and a 20dB line width of about 0.2nm under the above-mentioned configuration. However, the above-mentioned configuration is only exemplary. In practical applications, it is necessary to determine a suitable configuration according to the actual application situation. No sole limitation is made here to improve the performance of optical communication links and three-dimensional imaging systems of devices using relevant vertical cavity surface emitting laser chips.

[0071] For ease of understanding, an embodiment of a single-mode vertical cavity surface emitting laser chip is provided below for illustration. In practical applications, the single-mode vertical cavity surface emitting laser chip can achieve single-mode operating characteristics with a peak wavelength of 1549nm and a 20dB line width of approximately 0.2nm.

[0072] Figure 4 This is the third single-mode working characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by this application, please refer to Figure 1 and Figure 4 An embodiment of a single-mode vertical cavity surface emitting laser chip provided by the present application may include:

[0073] The chip substrate 1 is n-type doped InP; the buffer layer 2 is n-type doped InP; the fifth reflector layer 34 is seven pairs of distributed Bragg reflectors composed of InAlGaAs material, with a central wavelength of 1500nm; the third cavity layer 35 is composed of InAlGaAs; the first reflector layer 31 is composed of fifty-five pairs of distributed Bragg reflectors composed of InAlGaAs material, with a central wavelength of 1550nm; the first cavity layer 32 is composed of InAlGaAs material; the second reflector layer 33 is composed of eight pairs of distributed Bragg reflectors composed of InAlGaAs material, with a central wavelength of 1500nm; the first cladding layer 41 is composed of graded InAlGaAs; the active region layer 42 is fifteen pairs of InAlGaAs / InAlGaAs quantum wells; the second cladding layer 43 is composed of graded InAlGaAs material; the current limiting layer 44 is an InAlGaAs material with a thickness of 30nm and an Al component of 95%, wherein the current injection aperture is 9 microns; the third cladding layer 45 The composition material is InAlGaAs; the third reflector layer 51 is a distributed Bragg reflector composed of a pair of SiO2 / MgF materials, with a central wavelength of 1500nm; the second cavity layer 52 is SiO2 material; the fourth reflector layer 53 is ten pairs of distributed Bragg reflectors composed of SiO2 / MgF materials, with a central wavelength of 1550nm; the fourth cavity layer 55 is SiO2 material; the sixth reflector layer 54 is two pairs of distributed Bragg reflectors composed of SiO2 / MgF materials, with a central wavelength of 1500nm. In this embodiment, the ohmic contact layer 6 may not be provided, and the chip electrodes are located at the ring electrode on the third cladding layer 45 exposed by etching and the bottom electrode located at the bottom surface of the chip substrate 1.

[0074] like Figure 4As shown, the single-mode vertical cavity surface emitting laser chip can achieve a single-mode working characteristic with a peak wavelength of 1549nm and a 20dB line width of about 0.2nm under the above-mentioned configuration. However, the above-mentioned configuration is only exemplary. In practical applications, it is necessary to determine a suitable configuration according to the actual application situation. No sole limitation is made here to improve the performance of optical communication links and three-dimensional imaging systems of devices using relevant vertical cavity surface emitting laser chips.

[0075] For ease of understanding, an embodiment of a single-mode vertical cavity surface emitting laser chip is provided below for illustration. In practical applications, when the fourth reflector layer is a sub-wavelength grating reflector structure, the single-mode vertical cavity surface emitting laser chip can also achieve a single-mode operating characteristic with a peak wavelength of 1549nm and a 20dB line width of approximately 0.2nm.

[0076] Figure 4 This is the first single-mode working characteristic effect diagram of the single-mode vertical cavity surface emitting laser chip provided by this application, please refer to Figure 1 and Figure 4 An embodiment of a single-mode vertical cavity surface emitting laser chip provided by the present application may include:

[0077] The chip substrate 1 is n-type doped InP; the buffer layer 2 is n-type doped InP, the first reflector layer 31 is a distributed Bragg reflector composed of 55 pairs of InAlGaAs materials, with a central wavelength of 1550nm; the first cavity layer 32 is composed of InAlGaAs materials; the second reflector layer 33 is a distributed Bragg reflector composed of eight pairs of InAlGaAs materials, with a central wavelength of 1500nm; the first cladding layer 41 is composed of graded InAlGaAs; the active region layer 42 is 15 pairs of InAlGaAs / InAlGaAs quantum wells; the second cladding layer 43 is composed of graded InAlGaAs materials; the current limiting layer 44 is 30nm thick, Al The component is 95% InAlGaAs material, and the current injection aperture is 9 microns; the component material of the third cladding 45 is InAlGaAs; the fourth reflector layer 53 is a sub-wavelength grating reflector made of SiNx material, and the central wavelength is 1550nm; in this embodiment, the ohmic contact layer 6 can be not set, and the chip electrodes are located at the annular electrode on the third cladding 45 exposed by etching and the bottom electrode located on the bottom surface of the chip substrate 1.

[0078] like Figure 4As shown, the single-mode vertical cavity surface emitting laser chip can achieve a single-mode working characteristic with a peak wavelength of 1549nm and a 20dB line width of about 0.2nm under the above-mentioned configuration. However, the above-mentioned configuration is only exemplary. In practical applications, it is necessary to determine a suitable configuration according to the actual application situation. No sole limitation is made here to improve the performance of optical communication links and three-dimensional imaging systems of devices using relevant vertical cavity surface emitting laser chips.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A single-mode vertical cavity surface emitting laser chip, characterized in that: include: A chip substrate (1), a buffer layer (2), a chip bottom mirror structure (3), an optical cavity (4) and a chip top mirror structure (5) are arranged in sequence; Along the direction from the chip substrate (1) to the chip top mirror structure (5), the optical cavity (4) is provided with a first cladding layer (41), an active region layer (42), a second cladding layer (43) and a current limiting layer (44) in sequence; The current limiting layer (44) comprises an insulating material portion and a semiconductor material portion, the insulating material portion surrounds the semiconductor material portion, and the diameter of the semiconductor material portion is smaller than a preset diameter threshold; The chip bottom mirror structure (3) is provided with a first reflector layer (31), and the chip top mirror structure (5) is provided with a fourth reflector layer (53); The single-mode vertical cavity surface emitting laser chip meets at least one of the following conditions: In the chip bottom mirror structure (3), along the direction from the chip substrate (1) to the chip top mirror structure (5), a first cavity layer (32) and a second reflector layer (33) are sequentially provided between the first reflector layer (31) and the first cladding layer (41); as well as In the chip top mirror structure (5), along the direction from the chip substrate (1) to the chip top mirror structure (5), a third reflector layer (51) and a second cavity layer (52) are sequentially provided between the current limiting layer (44) and the fourth reflector layer (53).

2. The single-mode vertical cavity surface emitting laser chip according to claim 1, characterized in that: The chip bottom mirror structure (3) is also provided with a fifth reflector layer (34) and a third cavity layer (35); The fifth reflector layer (34), the third cavity layer (35) and the first reflector layer (31) are arranged in sequence along a direction from the chip substrate (1) to the chip top mirror structure (5).

3. The single-mode vertical cavity surface emitting laser chip according to claim 2, characterized in that: The chip top mirror structure (5) is further provided with a sixth reflector layer (54) and a fourth cavity layer (55); The fourth reflector layer (53), the fourth cavity layer (55), and the sixth reflector layer (54) are arranged in sequence along the direction from the chip substrate (1) to the chip top mirror structure (5).

4. The single-mode vertical cavity surface emitting laser chip according to claim 3, characterized in that: The constituent materials of the first reflector layer (31), the second reflector layer (33), the third reflector layer (51), the fourth reflector layer (53), the fifth reflector layer (34) and the sixth reflector layer (54) are III-V semiconductor materials.

5. The single-mode vertical cavity surface emitting laser chip according to claim 3, characterized in that: The constituent materials of the first reflector layer (31), the second reflector layer (33), the third reflector layer (51), the fourth reflector layer (53), the fifth reflector layer (34) and the sixth reflector layer (54) are dielectric film materials.

6. The single-mode vertical cavity surface emitting laser chip according to claim 3, characterized in that: The number of material film layers of the second reflector layer (33), the third reflector layer (51), the fifth reflector layer (34) and the sixth reflector layer (54) is less than a first layer number threshold, the number of material film layers of the first reflector layer (31) and the fourth reflector layer (53) is greater than a second layer number threshold, the second layer number threshold is greater than the first layer number threshold, and the first layer number threshold is greater than zero.

7. The single-mode vertical cavity surface emitting laser chip according to claim 3, characterized in that: The central wavelength of the reflection spectrum of the first reflector layer (31) and the fourth reflector layer (53) is a first preset wavelength; The central wavelength of the reflection spectrum of the second reflector layer (33) and the fifth reflector layer (34) is a second preset wavelength; The reflection spectrum center wavelengths of the third reflector layer (51) and the sixth reflector layer (54) are third preset wavelengths; The first preset wavelength, the second preset wavelength, and the third preset wavelength are all greater than zero.

8. The single-mode vertical cavity surface emitting laser chip according to claim 1, characterized in that: The insulating material part of the current limiting layer (44) is an aluminum oxide insulating material obtained by oxidizing a III-V semiconductor material layer with a high Al content through a wet oxidation process; The semiconductor material portion of the current limiting layer (44) is the remaining material of the III-V semiconductor material layer that has not been oxidized; The III-V semiconductor material layer with a high Al content is a III-V semiconductor material layer with an Al content greater than 90%.

9. The single-mode vertical cavity surface emitting laser chip according to claim 4, characterized in that: The optical cavity (4) is further provided with a third cladding (45); The first cladding layer (41), the active region layer (42), the second cladding layer (43), the current limiting layer (44), the third cladding layer (45) and the third reflector layer (51) are arranged in sequence along the direction from the chip substrate (1) to the chip top mirror structure (5); The constituent materials of the first cladding layer (41), the active region layer (42), the second cladding layer (43), the current limiting layer (44) and the third cladding layer (45) are the III-V group semiconductor materials; The active region layer (42) is one of a quantum well active region layer and a quantum dot active region layer.

10. The single-mode vertical cavity surface emitting laser chip according to claim 3, characterized in that: The reflector structure of the first reflector layer (31), the second reflector layer (33), the third reflector layer (51), the fourth reflector layer (53), the fifth reflector layer (34) and the sixth reflector layer (54) is any one of a distributed Bragg reflector structure, a sub-wavelength grating reflector structure and a photonic crystal reflector structure.

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