An enhanced high robustness thyristor electrostatic protection device and a manufacturing method thereof

Abstract

The invention discloses an enhanced high-robustness thyristor electrostatic protection device and a manufacturing method thereof, comprising a P-type substrate, an N-type buried layer, an N-well, and a P-type shallow well; since the concentrations on both sides of the P-type shallow well and N+ injection are relatively high, avalanche breakdown is likely to occur in the region, and the avalanche current is guided by the design to optimize the discharge path of the device; the N-type buried layer has a P-type substrate and a P-type shallow well, and the P-type shallow well has five injection regions and a polysilicon gate, two injection regions are respectively connected across the N-well and the surface of the P-type shallow well and the surface of the P-type shallow well and the P-type substrate, and the five electrodes are connected together as the device cathode; two injected electrodes in the N-well are connected together as the device anode; two injection electrodes connected across the N-well and the P-type shallow well and in the P-type shallow well are connected together to guide the current; the device improves the holding voltage and the failure current while significantly reducing the on-resistance, effectively protects the core circuit, stays away from the latch-up risk, and improves the ESD protection level of the chip.

Description

Technical Field

[0001] The invention relates to the field of electrostatic protection, and in particular to an enhanced high-robustness thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the advancement of semiconductor manufacturing technology, the failure of integrated circuit chips and electronic products caused by ESD has become more serious. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers. The ESD design window is an issue that product engineers need to focus on when designing ESD protection, including the trigger voltage V t1 , trigger current I t1 , Maintain voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 , on-resistance R on The trigger voltage of the ESD protection device must be lower than the maximum withstand voltage of the protected port of the core circuit, i.e., the drain-source breakdown voltage. Usually, the trigger voltage is 10% to 20% lower than the maximum withstand voltage. The maintenance voltage of the ESD protection device must be 1.1 to 1.2 times higher than the normal working voltage of the core circuit to protect the core circuit from latching up due to the ESD protection device always being turned on. The failure current I t2 It is one of the important parameters to measure the robustness of ESD protection devices. It indicates the maximum current that the ESD protection device can withstand. If the core circuit is to be effectively protected, the failure current I t2 When the ESD protection device is on, the clamping voltage must be less than the maximum withstand voltage of the protected port; the on-resistance R on It is the resistance characteristic of the device after entering the holding point, which is related to the holding voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 According to Ohm's law, the on-resistance R on Expressed as failure voltage V t2 , Maintain voltage V h Difference and failure current I t2 , Maintaining current I h The ratio of the difference; the human body model HBM regards the equivalent resistance of the human body as 1.5kΩ, and the HBM protection level is 1500 times I t2 .

[0003] The failure modes caused by ESD include hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the current of several amperes to tens of amperes generated locally on the chip when the ESD pulse comes. It lasts for a short time but generates a lot of heat, causing the local metal connection to melt or causing hot spots on the chip, resulting in secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes more and more serious, research on its physical mechanism is receiving more and more attention.

[0004] Compared with other ESD devices, traditional unidirectional thyristor devices have a dual conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness.

[0005] The cross-section diagram of the traditional unidirectional low trigger voltage thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of a unidirectional low trigger voltage thyristor, the N+ injection forms a reverse biased PN junction with the P-type shallow well. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the P-type shallow well / P-type substrate and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the P-type shallow well is equivalent to the base voltage drop of the transistor NPN1. When this voltage is higher than the forward conduction voltage of the lateral NPN1 transistor, the transistor is turned on. After the transistor is turned on, it provides base current for the PNP transistor. After the PNP transistor is turned on, a positive feedback mechanism is formed to fully open the SCR path. Therefore, even if there is no avalanche current afterwards, the large current can be discharged because the SCR path is open. The unidirectional low trigger voltage thyristor can provide electrostatic protection for circuits with positive voltage of the working signal. However, due to its high trigger voltage and low maintenance voltage, it is easy to cause latch-up, which needs to be considered during design. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides an enhanced high-robustness thyristor electrostatic protection device and a manufacturing method thereof, and is applied to the ESD protection design of an analog switch chip with an operating voltage of 0 to 5V.

[0007] The technical solution of the present invention to solve the above problem is as follows: comprising a P-type substrate; an N-type buried layer is arranged in the substrate; a P-type substrate region and two N-well regions are arranged above the N-type buried layer; a P-type shallow well is arranged on the P-type substrate, namely, a first P-type shallow well; the N-well comprises a first N-well and a second N-well; the first N-well is on the left side of the first P-type shallow well, and the second N-well is on the right side of the first P-type shallow well; the P-type substrate has a first, an eighth and a ninth P+ injection; the first N-well has a second, a fourth N+ injection and a third P+ injection; the fifth N+ injection is connected across the first N-well The first P-type shallow well and the surface of the first P-type shallow well; there is a sixth N+ injection on the first P-type shallow well; the seventh N+ injection is connected across the first P-type shallow well and the surface of the P-type substrate; the first gate is above the first P-type shallow well; the first gate, two electrodes on the first P-type shallow well and two electrodes on the P-type substrate, a total of five electrodes are connected together and used as the cathode of the device, the two electrodes on the first N-well are connected together as the anode of the device, and the electrode of the fifth N+ injection connected across the first N-well and the surface of the first P-type shallow well is connected to the electrode of the sixth N+ injection on the first P-type shallow well through metal;

[0008] The enhanced high-robustness thyristor electrostatic protection device is characterized by having seven field oxygen isolation regions; the first field oxygen isolation region is on the right side of the first P+ injection region, the second field oxygen isolation region is between the second N+ injection region and the third P+ injection region, the third field oxygen isolation region is between the third P+ injection region and the fourth N+ injection region, the fourth field oxygen isolation region is between the fourth and fifth N+ injection regions, the fifth field oxygen isolation region is between the fifth and sixth N+ injection regions, the sixth field oxygen isolation region is between the seventh N+ injection region and the eighth P+ injection region, and the seventh field oxygen isolation region is between the eighth P+ injection region and the ninth P+ injection region;

[0009] The enhanced high-robustness thyristor electrostatic protection device is characterized in that: the first field oxygen isolation region is located on the surface of the P-type substrate and the first N-well; the second field oxygen isolation region is on the surface of the first N-well; the third field oxygen isolation region is on the surface of the first N-well; the fourth field oxygen isolation region is on the surface of the first N-well; the fifth field oxygen isolation region is on the surface of the first P-type shallow well; the sixth field oxygen isolation region is on the surface of the P-type substrate; the seventh field oxygen isolation region is on the surface of the P-type substrate and the second N-well;

[0010] The enhanced high-robustness thyristor electrostatic protection device is characterized in that: when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the GGNMOS structure located in the first P-type shallow well is triggered first, and the third P+ injection, the first N-well and the P-type substrate / the first P-type shallow well constitute a parasitic transistor PNP, the first N-well, the P-type substrate / the first P-type shallow well and the seventh N+ injection constitute a lateral parasitic transistor NPN1, the first N-well / N-type buried layer, the P-type substrate / the first P-type shallow well and the seventh N+ injection constitute a longitudinal parasitic transistor NPN2, when PNP and NPN1 are turned on, a lateral SCR path is formed; when PNP and NPN2 are turned on, a longitudinal SCR path is formed;

[0011] The enhanced high-robustness thyristor electrostatic protection device is characterized in that: the sizes of the fifth N+ injection across the first N well and the first P-type shallow well are S1 and S2 respectively, and the sum of S1 and S2 is a fixed value, when the distance S1 decreases and the distance S2 increases, the device trigger voltage increases and the failure current decreases;

[0012] A method for manufacturing an enhanced high-robustness thyristor electrostatic protection device comprises the following steps:

[0013] Step 1: forming an N-type buried layer in a P-type substrate;

[0014] Step 2: Generate two N-wells above the N-type buried layer;

[0015] Step 3: forming a P-type shallow well region on the P substrate, wherein the first P-type shallow well is on the right side of the first N-well;

[0016] Step 4: forming a first P+ injection region and a ninth P+ injection region on the P-type substrate, generating a second N+ injection region, a third P+ injection region and a fourth N+ injection region on the first N-well; generating a fifth N+ injection region on the surface of the first N-well and the first P-type shallow well; generating a sixth N+ injection region and a polysilicon gate on the first P-type shallow well; generating a seventh N+ injection region on the first P-type shallow well and the surface of the P-type substrate; generating an eighth P+ injection region on the surface of the P-type substrate;

[0017] Step 5: forming a first field oxygen isolation region between the first P+ implantation region and the second N+ implantation region, forming a second field oxygen isolation region between the second N+ implantation region and the third P+ implantation region, forming a third field oxygen isolation region and a fourth field oxygen isolation region on the first N well, forming a fifth field oxygen isolation region on the surface of the first P-type shallow well, forming a sixth field oxygen isolation region on the P-type substrate, and generating a seventh field oxygen isolation region between the eighth P+ implantation region and the ninth P+ implantation region;

[0018] Step 6: Annealing all the implanted regions to eliminate the migration of impurities in the implanted regions;

[0019] Step 7: Connect the first P+ injection, the polysilicon gate, the seventh N+ injection, the eighth P+ injection and the ninth P+ injection together as the cathode of the device, connect the second N+ injection and the third P+ injection together as the anode of the device, and connect the fifth N+ injection and the sixth N+ electrode together through metal;

[0020] The method for manufacturing the enhanced high-robustness thyristor electrostatic protection device includes the following steps before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin-coating a photoresist layer on a wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is formed, and removing the silicon nitride layer.

[0021] The beneficial effects of the present invention are:

[0022] 1. The dimensions of the fifth N+ implant of the present invention that crosses the first N-well and the first P-type shallow well are S1 and S2 respectively, and the sum of S1 and S2 is a fixed value. When the distance of S1 decreases and the distance of S2 increases, the trigger voltage of the device increases and the failure current decreases. By changing the dimensions of S1 and S2, the trigger voltage of the device changes significantly, and the holding voltage increases with the increase of the trigger voltage. The ESD window moves to the right, but with the increase of the trigger voltage, the failure current gradually decreases.

[0023] 2. The fifth N+ injection region is connected to the sixth N+ injection region through metal. A strong electric field is formed under the fifth N+ injection to inhibit current from flowing through the device surface, which can promote the opening of the longitudinal SCR path. Moreover, since the on-resistance of the longitudinal SCR path is small, the on-resistance of the overall device is reduced. The traditional LVTSCR device has a large on-resistance and a small failure current, and cannot reach an on-chip integrated ESD protection level of more than 10,000 volts. The ELVTSCR_NBL of the embodiment of the present invention has a small on-resistance and a high failure current, and can reach an on-chip integrated ESD protection level of more than 10,000 volts.

[0024] 3. In order to improve the holding voltage of the device, an N-type buried layer is introduced and the width W of the P-type shallow well is adjusted. After the introduction of the N-type buried layer, due to the higher concentration of the N-type buried layer, it has a stronger ability to attract electrons, which promotes the opening of the vertical SCR path; increasing the width W of the P-type shallow well increases the concentration of the P-type shallow well under the NMOS, thereby improving the holding voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A cross-sectional view of a conventional unidirectional LVTSCR device.

[0026] Figure 2It is the equivalent circuit diagram of the traditional unidirectional LVTSCR device.

[0027] Figure 3 It is a cross-sectional view of the ELVTSCR_NBL device according to an embodiment of the present invention.

[0028] Figure 4 FIG. 4 is an equivalent circuit diagram of the ELVTSCR_NBL device according to an embodiment of the present invention.

[0029] Figure 5 This is an electron microscope image of the ELVTSCR_NBL four-finger TVS device according to an embodiment of the present invention.

[0030] Figure 6 This is an electron microscope image of the ELVTSCR_NBL eight-finger TVS device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The ESD protection design of the analog switch chip applied to the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0032] like Figure 3 As shown, an enhanced high-robustness thyristor electrostatic protection device comprises a P-type substrate 101; an N-type buried layer 201 is provided in the substrate; a P-type substrate region 102 and two N-well regions 301 and 302 are located above the N-type buried layer 201; a first P-type shallow well 401 is provided on the P-type substrate 102; the N-well comprises a first N-well 301 and a second N-well 302; the first N-well 301 is on the left side of the first P-type shallow well 401, and the second N-well 302 is on the right side of the first P-type shallow well 401; the first and ninth P+ injections 501 and 509 are provided on the P-type substrate 101; the eighth P+ injection 508 is provided on the P-type substrate 102; the second, fourth N+ injections 502, 504 and the third P+ injection 503 are provided on the first N-well 301; the fifth N+ The injection 505 is connected across the first N-well 301 and the surface of the first P-type shallow well 401; there is a sixth N+ injection 506 on the first P-type shallow well 401; the seventh N+ injection 507 is connected across the first P-type shallow well 401 and the surface of the P-type substrate 102; the first gate 701 is above the first P-type shallow well 401; the first gate 701, two electrodes on the first P-type shallow well 401 and two electrodes on the P-type substrate 101, a total of five electrodes are connected together and serve as the cathode of the device, the two electrodes on the first N-well 301 are connected together as the anode of the device, and the electrode of the fifth N+ injection 505 connected across the surface of the first N-well 301 and the first P-type shallow well 401 is connected to the electrode of the sixth N+ injection 506 on the first P-type shallow well 401 through metal.

[0033] The fifth N+ injection region and the sixth N+ injection region in the present invention are connected by metal. A strong electric field is formed under the fifth N+ injection to inhibit current from flowing through the device surface, which can promote the opening of the vertical SCR path. Moreover, since the on-resistance of the vertical SCR path is small, the on-resistance of the overall device is reduced. The enhanced high-robustness thyristor electrostatic protection device has seven field oxygen isolation regions; the first field oxygen isolation region 601 is on the right side of the first P+ injection region 501, the second field oxygen isolation region 602 is between the second N+ injection region 502 and the third P+ injection region 503, the third field oxygen isolation region 603 is between the third P+ injection region 503 and the fourth N+ injection region 504, the fourth field oxygen isolation region 604 is between the fourth and fifth N+ injection regions 504 and 505, the fifth field oxygen isolation region 605 is between the fifth and sixth N+ injection regions 505 and 506, the sixth field oxygen isolation region 606 is between the seventh N+ injection region 507 and the eighth P+ injection region 509, and the seventh field oxygen isolation region 607 is between the eighth P+ injection region 508 and the ninth P+ injection region 509;

[0034] The first field oxygen isolation region 601 is located on the surface of the P-type substrate 101 and the first N-well 301; the second field oxygen isolation region 602 is located on the surface of the first N-well 301; the third field oxygen isolation region 603 is located on the surface of the first N-well 301; the fourth field oxygen isolation region 604 is located on the surface of the first N-well 301; the fifth field oxygen isolation region 605 is located on the surface of the first P-type shallow well 401; the sixth field oxygen isolation region 606 is located on the surface of the P-type substrate 102; the seventh field oxygen isolation region 607 is located on the surfaces of the P-type substrates 101 and 102 and the second N-well 302;

[0035] like Figure 4 As shown, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the trigger voltage of the device is determined by the MOS structure located in the first P-type shallow well 401, the third P+ injection 503, the first N-well 301 and the P-type substrate 102 / the first P-type shallow well 401 constitute a parasitic transistor PNP, the first N-well 301, the P-type substrate 102 / the first P-type shallow well 401 and the seventh N+ injection 507 constitute a lateral parasitic transistor NPN1, the first N-well 301 / the N-type buried layer 201, the P-type substrate 102 / the first P-type shallow well 401 and the seventh N+ injection 507 constitute a longitudinal parasitic transistor NPN2, when PNP and NPN1 are turned on, a lateral SCR path P1 is formed; when PNP and NPN2 are turned on, a longitudinal SCR path P2 is formed;

[0036] An N-type buried layer is introduced and the width W of the P-type shallow well is adjusted. After the N-type buried layer is introduced, due to the higher concentration of the N-type buried layer, it has a stronger ability to attract electrons, which promotes the opening of the vertical SCR path; increasing the width W of the P-type shallow well increases the concentration of the P-type shallow well under the NMOS, thereby increasing the holding voltage.

[0037] This device can change the distance S1 / S2 between the junction of the first N-well 301 and the first P-type shallow well 403 relative to the fifth N+ injection 505 according to the requirements of the ESD design window in different application scenarios. The sum of S1 and S2 is a fixed value. When the S1 distance decreases and the S2 distance increases, the ESD window of the device shifts to the right, that is, the trigger voltage increases, the sustaining voltage increases but the failure current decreases. The sustaining voltage of the device can be changed by adjusting the width W of the P-type shallow well. As W increases, the sustaining voltage increases.

[0038] like Figure 2 and Figure 4 As shown, they are equivalent circuit diagrams of a conventional LVTSCR and an embodiment of the present invention ELVTSCR_NBL, respectively, which systematically describe the current discharge path of static electricity from the anode to the cathode of the device when the device is working; Figure 5 and Figure 6 The electronic microscope images of the four-finger device and the eight-finger device of the embodiment of the present invention taped out under the 0.25um BCD standard process. Compared with the SOI process, the analog switch chip integrating the TVS device designed by the present invention based on the BCD process has the advantages of small area and low cost.

[0039] A method for manufacturing an enhanced high-robustness thyristor electrostatic protection device comprises the following steps:

[0040] Step 1: forming an N-type buried layer 201 in a P-type substrate 101;

[0041] Step 2: generating two N-wells 301 and 302 above the N-type buried layer 201;

[0042] Step 3: forming a P-type shallow well region 401 on the P-type substrate 102 , wherein the first P-type shallow well 401 is on the right side of the first N-type well 301 ;

[0043] Step 4: forming a first P+ injection region 501 and a ninth P+ injection region 509 on the P-type substrate 101, generating a second N+ injection region 502, a third P+ injection region 503 and a fourth N+ injection region 504 on the first N-well 301; generating a fifth N+ injection region 505 on the surface of the first N-well 301 and the first P-type shallow well 401; generating a sixth N+ injection region 506 and a polysilicon gate 701 on the first P-type shallow well 401; generating a seventh N+ injection region 507 on the surface of the first P-type shallow well 401 and the P-type substrate 102; generating an eighth P+ injection region 508 on the surface of the P-type substrate 102;

[0044] Step 5: forming a first field oxygen isolation region 601 between the first P+ implantation region 501 and the second N+ implantation region 502, forming a second field oxygen isolation region 602 between the second N+ implantation region 502 and the third P+ implantation region 503, forming a third field oxygen isolation region 603 and a fourth field oxygen isolation region 604 on the first N well 301, forming a fifth field oxygen isolation region 605 on the surface of the first P-type shallow well 401, forming a sixth field oxygen isolation region 606 on the P-type substrate 102, and generating a seventh field oxygen isolation region 607 between the eighth P+ implantation region 508 and the ninth P+ implantation region 509;

[0045] Step 6: Annealing all the implanted regions to eliminate the migration of impurities in the implanted regions;

[0046] Step 7: Connect the first P+ injection 501, the polysilicon gate 701, the seventh N+ injection 507, the eighth P+ injection 508 and the ninth P+ injection 509 together as the cathode of the device, connect the second N+ injection 502 and the third P+ injection 503 together as the anode of the device, and connect the fifth N+ injection 505 and the sixth N+ injection 506 electrodes together through metal;

[0047] The manufacturing method of the enhanced high-robustness thyristor electrostatic protection device of the present invention has simple process and convenient operation.

[0048] The present invention introduces two N+ injection regions to connect electrodes together through metal, so that an avalanche breakdown current flows into another N+ injection through an N+ injection to break down an N+ / P-type shallow well reverse biased PN junction and enter a P-type shallow well; by reducing the size of S1 and increasing the size of S2, the current is suppressed from passing through the device surface, so that the breakdown surface can be changed from the reverse biased PN junction formed by the sixth N+ injection / P-type shallow well of the MOS structure to the reverse biased PN junction formed by the fifth N+ injection / P-type shallow well or the reverse biased PN junction formed by the first N well / P-type shallow well to increase the trigger voltage to adapt to different ESD window designs. As shown in the data in Table 1, by changing the sizes of S1 and S2, the trigger voltage of the device changes significantly, the holding voltage increases with the increase of the trigger voltage, and the ESD window moves to the right, but with the increase of the trigger voltage, the failure current gradually decreases.

[0049] Table 1

[0050]

[0051] Under certain S1 and S2 size conditions, when the device is powered on, due to the N+ injection across the N well and the P-type shallow well, a strong electric field will be generated near the junction of the N well and the P-type shallow well, which will inhibit the current from flowing from the device surface to the cathode, weakening the lateral SCR path's ability to discharge current. At the same time, the N-type buried layer has a high doping concentration and a strong ability to attract electrons, so that the current can flow through the depth of the device, and the longitudinal path has a smaller on-resistance. The on-resistance of the overall device is determined by the on-resistance of the longitudinal SCR path; as shown in the data in Table 2, the on-resistance of the traditional LVTSCR device is large and the failure current is small, and it cannot reach the on-chip integrated ESD protection level of more than 10,000 volts; the embodiment of the present invention ELVTSCR_NBL has a small on-resistance and a high failure current, and can be applied to the on-chip integrated ESD protection level of more than 10,000 volts. By adjusting the width W of the P-type shallow well, the holding voltage of the device is changed. As W increases, the holding voltage increases.

[0052] Table 2

[0053]

[0054] The device of the present invention adopts 0.25 μm BCD standard process and is applied to ESD protection design of analog switch chip with working voltage of 0 to 5V.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. An enhanced high robustness thyristor electrostatic protection device, characterized in that: It comprises a P-type substrate; an N-type buried layer is arranged in the P-type substrate; a P-type substrate and two N-wells are arranged above the N-type buried layer; a P-type shallow well is arranged on the P-type substrate, which is a first P-type shallow well; the N-well comprises a first N-well and a second N-well; the first N-well is on the left side of the first P-type shallow well, and the second N-well is on the right side of the first P-type shallow well; The P-type substrate has a first P+ injection, an eighth P+ injection, and a ninth P+ injection; The first N well has a second N+ injection, a third P+ injection, and a fourth N+ injection; A fifth N+ implant is connected across the first N well and the first P-type shallow well surface; and a sixth N+ implant is provided on the first P-type shallow well; A seventh N+ implant is connected across the first P-type shallow well and the P-type substrate surface; A first gate is above the first P-type shallow well; The first gate, two electrodes on the first P-type shallow well and two electrodes on the P-type substrate, a total of five electrodes, are connected together and serve as the cathode of the device, the two electrodes on the first N-well are connected together as the anode of the device, and the fifth N+ injected electrode bridged on the surface of the first N-well and the first P-type shallow well and the sixth N+ injected electrode on the first P-type shallow well are connected together through a metal wire; It also includes seven field oxygen isolation zones; The first field oxygen isolation region is to the right of the first P+ implant, the second field oxygen isolation region is between the second N+ implant and the third P+ implant, the third field oxygen isolation region is between the third P+ implant and the fourth N+ implant, the fourth field oxygen isolation region is between the fourth N+ implant and the fifth N+ implant, the fifth field oxygen isolation region is between the fifth N+ implant and the sixth N+ implant, the sixth field oxygen isolation region is between the seventh N+ implant and the eighth P+ implant, and the seventh field oxygen isolation region is between the eighth P+ implant and the ninth P+ implant; The first field oxygen isolation region is located on the surface of the P-type substrate and the first N-well; The second field oxygen isolation region is on the surface of the first N-well; the third field oxygen isolation region is on the surface of the first N-well; the fourth field oxygen isolation region is on the surface of the first N-well; the fifth field oxygen isolation region is on the surface of the first P-type shallow well; the sixth field oxygen isolation region is on the surface of the P-type substrate; The seventh field oxygen isolation region is located on the surface of the P-type substrate and the second N-well.

2. The enhanced high robustness thyristor electrostatic protection device according to claim 1, characterized in that: When the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the GGNMOS structure located in the first P-type shallow well is triggered first, and the third P+ injection, the first N-well and the P-type substrate / first P-type shallow well constitute a parasitic transistor PNP. The first N-well, the P-type substrate / first P-type shallow well and the seventh N+ injection constitute a lateral parasitic transistor NPN1. The first N-well / N-type buried layer, the P-type substrate / first P-type shallow well and the seventh N+ injection constitute a vertical parasitic transistor NPN2. When PNP and NPN1 are turned on, a horizontal SCR path is formed; when PNP and NPN2 are turned on, a vertical SCR path is formed.

3. The enhanced high robustness thyristor electrostatic protection device according to claim 1, characterized in that: The dimensions of the fifth N+ injection region spanning the first N-well and the first P-type shallow well are S1 and S2 respectively, and the sum of S1 and S2 is a fixed value. When the distance S1 decreases and the distance S2 increases, the device trigger voltage increases and the failure current decreases. The fifth N+ injection region is connected to the sixth N+ injection region by metal.

4. A method for manufacturing an enhanced high-robustness thyristor electrostatic protection device according to any one of claims 1 to 3, comprising the following steps: Step 1: forming an N-type buried layer in a P-type substrate; Step 2: Generate two N-wells above the N-type buried layer; Step 3: forming a P-type shallow well on the P substrate, wherein the first P-type shallow well is on the right side of the first N-type deep well; Step 4: forming a first P+ injection region and a ninth P+ injection region on the P-type substrate, and generating a second N+ injection region, a third P+ injection region and a fourth N+ injection region on the first N well; Generating a fifth N+ implantation region on the surface of the first N well and the first P-type shallow well; A sixth N+ implantation region and a polysilicon gate are formed on the first P-type shallow well; a seventh N+ implantation region is formed on the first P-type shallow well and the surface of the P-type substrate; An eighth P+ injection region is generated on the surface of the P-type substrate; Step 5: forming a first field oxygen isolation region between the first P+ implantation region and the second N+ implantation region, forming a second field oxygen isolation region between the second N+ implantation region and the third P+ implantation region, forming a third field oxygen isolation region and a fourth field oxygen isolation region on the first N well, forming a fifth field oxygen isolation region on the surface of the first P-type shallow well, forming a sixth field oxygen isolation region on the P-type substrate, and generating a seventh field oxygen isolation region between the eighth P+ implantation region and the ninth P+ implantation region; Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas; Step seven: Connect the first P+ injection, polysilicon gate, seventh N+ injection, eighth P+ injection and ninth P+ injection together and use them as the cathode of the device, connect the second N+ injection and the third P+ injection together and use them as the anode of the device, and connect the fifth N+ injection and the sixth N+ electrode together through metal.

5. The method for manufacturing the enhanced high robustness thyristor electrostatic protection device according to claim 4, characterized in that: The step 1 also includes the following steps: A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.

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