A multi-phase sampling type II phase-locked loop
Through the multi-phase sampling type two-phase locking loop, the multi-phase reference clock signal is used to detect the frequency multiplication and loop bandwidth expansion, solving the problems of limited bandwidth of the phase locking loop loop and high reference clock phase accuracy requirements, realizing the Low stray and high bandwidth phase-locked loop design simplifies circuit design and reduces costs.
Patent Information
- Application Number
- CN202211294518.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-21
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2042-10-21
AI Technical Summary
In the prior art, the maximum operating loop bandwidth of the phase-locked loop is limited by the reference clock frequency, resulting in the need of complex calibration loops in the conventional reference clock frequency-multiplied phase-locked loop to suppress oscillator noise and to phase accuracy for the reference clock. High requirements increase system cost and complexity.
Using multiphase sampling type two-type phase lock loop, it is made by using multiphase reference clock signal through n-channel sampling type phase detector, parallel-serial transconductance amplifier, loop filter, voltage-controlled oscillator and multiphase frequency divider. Phase detection frequency multiplication and loop bandwidth expansion reduce timing requirements and power consumption, and avoid sensitivity to reference clock phase errors.
It achieves low reference spurious performance, expands the loop bandwidth of the phase-locked loop, suppresses more oscillator noise, simplifies the multi-phase reference clock circuit design, and reduces system costs.
Smart Images
Figure CN115632654B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of electronic circuits, and in particular to a multi-phase phase-discrimination broadband type II phase-locked loop. Background Art
[0002] The noise of a phase-locked loop is generally divided into two parts, one is in-band noise and the other is out-of-band noise. In-band noise is mainly contributed by phase detectors, charge pumps, etc., and the in-band noise of the two can be suppressed by high-gain sampling phase detectors. Out-of-band noise is mainly contributed by oscillator noise. By expanding the loop bandwidth of the phase-locked loop, more oscillator noise can be suppressed, thereby achieving lower out-of-band noise. However, the maximum working loop bandwidth that the phase-locked loop can achieve is limited by the reference clock frequency. Directly using high-frequency and expensive crystal oscillators can meet the requirements, but it greatly increases the cost of the system, so on-chip reference clock multiplication technology has become increasingly popular. However, in the existing reference clock multiplication technology, the phase of the multiplied reference clock signal often needs to be very accurate, otherwise it will deteriorate the reference clock spurious of the phase-locked loop output signal. Therefore, it is inevitable to calibrate the equivalent multiplied reference clock in the traditional reference clock multiplication phase-locked loop. Summary of the invention
[0003] In view of the shortcomings of the prior art, the present invention realizes a circuit that can use an inaccurate multi-phase clock reference signal to multiply the phase-locked loop's phase-locked loop frequency and expand the loop bandwidth. The phase-locked loop using this structure can achieve low reference spurious performance without a complex calibration loop, and the output reference spurious is insensitive to the phase error of the input reference clock. The present invention can expand the loop bandwidth of the phase-locked loop, thereby suppressing more oscillator noise. The present invention adopts a multi-phase sampling phase-locked loop, so that the timing requirements and power consumption in the multi-phase sampling phase-locked loop are relatively reduced compared to the traditional high-frequency reference clock signal input phase-locked loop.
[0004] The purpose of the present invention is achieved through the following technical solutions:
[0005] A multi-phase sampling type II phase-locked loop, comprising n-channel sampling phase detectors, parallel-to-serial transconductance amplifiers, loop filters, voltage-controlled oscillators and multi-phase frequency dividers; n is a positive integer;
[0006] The parallel-to-serial transconductance amplifier comprises a high-frequency parallel-to-serial high-pass filter, a low-frequency transconductance amplifier and a high-frequency transconductance amplifier; the output end of the high-frequency parallel-to-serial high-pass filter is connected to n phase-detection results; the output end of the high-frequency parallel-to-serial high-pass filter is used as one of the input ends of the high-frequency transconductance amplifier, and the other input end of the high-frequency transconductance amplifier is connected to a bias voltage; one of the input ends of the low-frequency transconductance amplifier is connected to one of the phase-detection results, and the other input end is connected to a bias voltage; the output ends of the low-frequency transconductance amplifier and the high-frequency transconductance amplifier are connected, and are connected to the loop filter to control the voltage-controlled oscillator;
[0007] The high-frequency parallel-to-serial high-pass filter comprises n-channel switching capacitors and a bias resistor, one end of the n-channel switching capacitors is used as the input end of the n-channel phase-discrimination information, and the other end is connected to one end of the bias resistor; the other end of the bias resistor is connected to the bias voltage; wherein the n-channel switching capacitors are respectively turned on by the n-channel holding clocks, so as to realize the parallel-to-serial conversion of the high-frequency information in the n-channel phase-discrimination information into one channel;
[0008] The multi-phase frequency divider divides the frequency of the high-frequency output signal of the voltage-controlled oscillator to generate n sampling clock signals and n holding clock signals, respectively, and respectively serve as the sampling clock and holding clock of the n sampling phase detector. The n sampling phase detector performs sampling phase detection on the n reference clock signals to obtain n phase detection results. The n phase detection results are filtered out by the high-frequency parallel-to-serial high-pass filter to remove the DC mismatch in the n phase detection results, to obtain high-frequency phase detection information with low loop delay, and pass through the high-frequency transconductance amplifier to provide high-frequency loop gain. At the same time, one of the phase detection results passes through the low-frequency transconductance amplifier to provide low-frequency loop gain.
[0009] Furthermore, the low-frequency transconductance amplifier and the high-frequency transconductance amplifier are transconductance amplifiers using gain boost technology.
[0010] Furthermore, the sampling phase detector is a switching current sampling phase detector.
[0011] The beneficial effects of the present invention are as follows:
[0012] (1) In the multi-phase phase-detection broadband type II phase-locked loop circuit of the present invention, the n-way phase-detection results are filtered out by the high-frequency parallel-to-serial high-pass filter in the parallel-to-serial transconductance amplifier to remove the DC mismatch in the n-way phase-detection results, and high-frequency phase-detection information with low loop delay is obtained and passed through the high-frequency transconductance amplifier to provide high-frequency loop gain; at the same time, one of the phase-detection results is passed through the low-frequency transconductance amplifier in the parallel-to-serial transconductance amplifier to provide low-frequency loop gain. The parallel-to-serial transconductance amplifier achieves the effect of the type II phase-locked loop through the loop filter. In this way, the relatively inaccurate multi-phase reference clock input signal can be used to achieve the equivalent frequency multiplication of the phase-locked loop phase-detection frequency, and the loop bandwidth can be expanded, while avoiding the deterioration of the output reference spurious caused by the input reference clock phase error.
[0013] (2) The present invention reduces the requirement for reference clock phase accuracy in traditional reference clock frequency multiplication technology, thereby greatly simplifying the design of multi-phase reference clock circuits.
[0014] (3) The present invention can expand the loop bandwidth of the phase-locked loop, thereby suppressing more oscillator noise.
[0015] (4) The present invention adopts a multi-phase sampling phase-locked loop, so that the timing requirements and power consumption in the multi-phase sampling phase-locked loop are relatively reduced compared to the traditional phase-locked loop with high-frequency reference clock signal input. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a system architecture diagram of the present invention.
[0017] Figure 2 It is a high-frequency parallel-to-series high-pass filter.
[0018] Figure 3 This is a schematic diagram of the waveform of a multi-phase sampling phase-locked loop (taking four phases as an example).
[0019] Figure 4 It is a parallel-to-series transconductance amplifier. DETAILED DESCRIPTION
[0020] The present invention will be described in detail below based on the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more clear. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0021] like Figure 1 As shown, the low-power clock amplifier circuit of the present invention includes n-channel sampling phase detectors, parallel-to-serial transconductance amplifiers, loop filters, voltage-controlled oscillators, and multi-phase frequency dividers. ref <n:1>is the n-way multi-phase reference clock signal, ck samp <n:1>is the n-channel multi-phase sampling clock signal, ck hold <n:1>For n-way multi-phase holding clock signal, V ctrl is the voltage controlled oscillator control signal, ck VCO is the voltage controlled oscillator output clock signal, and n is a positive integer.
[0022] like Figure 2 As shown, the parallel-to-serial transconductance amplifier includes a high-frequency parallel-to-serial high-pass filter, a low-frequency transconductance amplifier and a high-frequency transconductance amplifier. The output end of the high-frequency parallel-to-serial high-pass filter is connected to n phase-detection results; the output end of the high-frequency parallel-to-serial high-pass filter is used as one of the input ends of the high-frequency transconductance amplifier, and the other input end of the high-frequency transconductance amplifier is connected to a bias voltage. One of the input ends of the low-frequency transconductance amplifier is connected to one of the phase-detection results, and the other input end is connected to a bias voltage. Figure 2 In the embodiment given in , the output end of the high-frequency parallel-to-series high-pass filter enters the positive end of the high-frequency transconductance amplifier. Of course, the negative end can also be connected here. Similarly, the two input ends of the low-frequency transconductance amplifier are also interchangeable. The output ends of the low-frequency transconductance amplifier and the high-frequency transconductance amplifier are connected, and are connected to the loop filter to control the voltage-controlled oscillator.
[0023] like Figure 3 As shown, the high-frequency parallel-to-serial high-pass filter includes n-channel switching capacitors and a bias resistor, one end of the n-channel switching capacitors serves as the input end of the n-channel phase-discrimination information, and the other end is connected to one end of the bias resistor; the other end of the bias resistor is connected to the bias voltage; wherein the n-channel switching capacitors are respectively turned on by the n-channel holding clocks, so as to realize the parallel conversion of the high-frequency information in the n-channel phase-discrimination information into one channel.
[0024] like Figure 1 As shown, the multi-phase frequency divider divides the high-frequency output signal of the voltage-controlled oscillator to generate n sampling clock signals ck respectively. samp <n:1>And n channels keep the clock signal ck hold <n:1>, and serve as the sampling clock and holding clock of the n-channel sampling phase detector respectively. The n-channel sampling phase detector is used for the n-channel reference clock signal ck ref <n:1>Perform sampling phase detection to obtain n-channel phase detection results V hold <n:1>The n-way phase-comparison results are filtered out by a high-frequency parallel-to-serial high-pass filter to remove the DC mismatch in the n-way phase-comparison results, and high-frequency phase-comparison information with low loop delay is obtained, and then passed through a high-frequency transconductance amplifier to provide a high-frequency loop gain; at the same time, one of the phase-comparison results V hold <0> After passing through the low-frequency transconductance amplifier, low-frequency loop gain is provided.
[0025] Preferably, the low-frequency transconductance amplifier and the high-frequency transconductance amplifier are transconductance amplifiers using gain boost technology. The sampling phase detector is a switching current sampling phase detector.
[0026] Here we take four-phase clock input as an example, of course, other numbers of multi-phase reference clock inputs are also possible. The waveforms of each node of the four-phase sampling phase-locked loop are as follows Figure 4 As shown in the figure, here we take the falling edge sampling as an example, of course, the rising edge sampling is similar. Figure 4 It can be seen that in one reference clock cycle, the multi-channel sampling phase detectors perform phase detection multiple times, thus achieving an increase in the phase detection frequency. At the same time, after the sampling of each sampling phase detector is completed, the holding clock immediately holds the sampled signal and updates it to the parallel-to-serial transconductance amplifier, thus avoiding loop delay. However, due to the characteristics of zero-order hold sampling, as the hold time increases, the phase shift of the loop will increase. Therefore, it is necessary to use the parallel-to-serial method to reduce the hold time in the multi-phase sampling phase-locked loop accordingly, which is achieved here by the parallel-to-serial transconductance amplifier.
[0027] Ideally, the mismatch between multi-phase reference signals can be considered as an offset from DC to low frequency, and it changes slowly with non-ideal factors such as temperature. Due to this characteristic of mismatch, the low-frequency offset can be filtered out by high-pass filtering, so that only high-frequency useful signals can be obtained. Generally speaking, the output jitter of the phase-locked loop is mainly determined by the phase noise in the range of one-tenth of the loop bandwidth to ten times the loop bandwidth, so the high-frequency phase-locked information is the key. The deviation between the multi-channel phase-locked information of the low-frequency phase-locked results can be ignored, so it can be considered that the low-frequency signals of each phase-locked result are actually the same. And the bias voltage of each high-pass filter is the same, so the resistance of the high-frequency filter can be shared, so that each high-pass filter reuses the same bias resistor, and the high-frequency phase-locked information is converted from parallel to serial through multi-channel selection, which can greatly reduce the area of the bias resistor. At the same time, the phase-locked loop also needs to provide low-frequency loop gain to achieve frequency and phase locking of the phase-locked loop, so one of the multi-phase phase-locked loop results is taken out to provide low-frequency loop gain. In this way, the relatively inaccurate multi-phase reference clock input signal can be used to achieve equivalent frequency multiplication of the phase-locked loop phase-locked loop frequency, and the loop bandwidth can be expanded, while avoiding the deterioration of the output reference spurious caused by the input reference clock phase error.
[0028] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.
Claims
1. A multi-phase sampling type II phase-locked loop, characterized in that: It includes n-channel sampling phase detectors, parallel-to-serial transconductance amplifiers, loop filters, voltage-controlled oscillators, and multi-phase frequency dividers; n is a positive integer; The parallel-to-serial transconductance amplifier comprises a high-frequency parallel-to-serial high-pass filter, a low-frequency transconductance amplifier and a high-frequency transconductance amplifier; the output end of the high-frequency parallel-to-serial high-pass filter is connected to n phase-detection results; the output end of the high-frequency parallel-to-serial high-pass filter is used as one of the input ends of the high-frequency transconductance amplifier, and the other input end of the high-frequency transconductance amplifier is connected to a bias voltage; one of the input ends of the low-frequency transconductance amplifier is connected to one of the phase-detection results, and the other input end is connected to a bias voltage; the output ends of the low-frequency transconductance amplifier and the high-frequency transconductance amplifier are connected, and are connected to the loop filter to control the voltage-controlled oscillator; The high-frequency parallel-to-serial high-pass filter comprises n-channel switching capacitors and a bias resistor, one end of the n-channel switching capacitors is used as the input end of the n-channel phase-discrimination information, and the other end is connected to one end of the bias resistor; the other end of the bias resistor is connected to the bias voltage; wherein the n-channel switching capacitors are respectively turned on by the n-channel holding clocks, so as to realize the parallel-to-serial conversion of the high-frequency information in the n-channel phase-discrimination information into one channel; The multi-phase frequency divider divides the frequency of the high-frequency output signal of the voltage-controlled oscillator to generate n sampling clock signals and n holding clock signals, respectively, and respectively serve as the sampling clock and holding clock of the n sampling phase detector. The n sampling phase detector performs sampling phase detection on the n reference clock signals to obtain n phase detection results. The n phase detection results are filtered out by the high-frequency parallel-to-serial high-pass filter to remove the DC mismatch in the n phase detection results, to obtain high-frequency phase detection information with low loop delay, and pass through the high-frequency transconductance amplifier to provide high-frequency loop gain. At the same time, one of the phase detection results passes through the low-frequency transconductance amplifier to provide low-frequency loop gain.
2. The multi-phase sampling type II phase-locked loop according to claim 1, characterized in that: The low-frequency transconductance amplifier and the high-frequency transconductance amplifier are transconductance amplifiers using gain enhancement technology.
3. The multi-phase sampling type II phase-locked loop according to claim 1, characterized in that: The sampling phase detector is a switching current sampling phase detector.