A method and system for MCU processor core that is easy to expand application

Abstract

The present invention relates to the field of embedded technology, and more specifically, to a method and system for an MCU processor core that is easy to apply and expand. The scheme includes obtaining an instruction stream through a macroinstruction filtering module, sending the instruction stream to an application macroinstruction decoding module; performing macroinstruction splitting, splitting into a number of application instructions; controlling a value taking control module to fetch instructions according to the application instructions; and selecting a register of a general register group as an input of an application macroinstruction operation module through an application macroinstruction control module according to the application instructions, and selecting an output result to an execution read write back module through a data bus, and writing it to an external storage space. The scheme forms an easy-to-apply-expand processor core architecture by adding a macroinstruction filtering module, an application macroinstruction decoding module, an application macroinstruction control module, and an application macroinstruction operation module on the basis of the original processor core architecture, and is suitable for various embedded fields that are sensitive to and limited in memory and require application expansion and acceleration.

Description

Technical Field

[0001] The present invention relates to the field of embedded technology, and more specifically, to an MCU processor core method and system that is easy to apply and expand. Background Art

[0002] The current mainstream MCU processor architecture is based on RISC, which improves performance by overlapping the execution of multiple instructions through a multi-stage pipeline. It uses relatively simple instructions with fixed lengths. To implement complex applications, it is necessary to combine these simple instructions, which requires more program storage space.

[0003] Prior to the technology of the present invention, in the embedded field, there were various applications that required customized acceleration. The traditional approach was to add an accelerator IP to the bus to accelerate and reduce storage space. However, this method was not flexible enough and was only applicable to specific applications. However, it was not convenient for application expansion in various embedded fields that were memory-sensitive and limited and required appropriate application expansion acceleration. Summary of the invention

[0004] In view of the above problems, the present invention proposes an MCU processor core method and system that is easy to apply and expand. By adding a macroinstruction filtering module, an application macroinstruction decoding module, an application macroinstruction control module and an application macroinstruction operation module on the basis of the original processor core architecture, an MCU processor core architecture that is easy to apply and expand is formed, which is suitable for various memory-sensitive and restricted embedded fields that require appropriate application expansion and acceleration.

[0005] According to a first aspect of an embodiment of the present invention, a method for an MCU processor core that is easy to apply and expand is provided.

[0006] In one or more embodiments, preferably, the MCU processor core method that is easy to apply expansion includes:

[0007] Obtain the instruction stream through the macro instruction filtering module and send the instruction stream to the application macro instruction decoding module;

[0008] Splitting the macro instruction into several application instructions by applying the macro instruction decoding module;

[0009] Controlling the value taking control module to fetch instructions according to the application instructions by applying the macro instruction control module;

[0010] Selecting a register of the general register group as an input of the application macroinstruction operation module according to the application instruction control by the application macroinstruction control module;

[0011] A sub-computing unit that completes one or several specific application accelerations through an application macro-instruction operation module, and feeds back the calculation status and results to an application macro-instruction control module and an execution read-write-back module;

[0012] The application macro instruction control module cyclically controls the number of operation times of the application macro instruction operation, and selects the output result to be sent to the execution read write back module through the data bus and written to the external storage space.

[0013] In one or more embodiments, preferably, the acquiring the instruction stream through the macro instruction filtering module and sending the instruction stream to the application macro instruction decoding module specifically includes:

[0014] After the instruction stream is input, the macro instruction filtering module is first entered;

[0015] The macro instruction filtering module is used to determine whether there is a special byte combination value identification header, and if so, it is determined to be an application macro instruction;

[0016] The macro instruction filtering module is used to determine whether there is a special byte combination value identification header, and if not, it is determined to be a non-application macro instruction.

[0017] In one or more embodiments, preferably, the macro instruction splitting is performed by applying a macro instruction decoding module, and the splitting is performed into a plurality of application instructions, specifically including:

[0018] The splitting rules are pre-set, and when the instruction stream is obtained;

[0019] According to a preset rule, the instruction stream is split into a plurality of separate application instructions;

[0020] The application instructions are sent one by one to the application macro instruction control module.

[0021] In one or more embodiments, preferably, the controlling the value fetching control module to fetch instructions according to the application instruction by the application macro instruction control module specifically includes:

[0022] After receiving each application instruction, the application macro instruction control module determines the need to fetch instructions according to the application instruction;

[0023] According to the demand for instruction fetching, the value fetching control module is used to fetch instructions.

[0024] In one or more embodiments, preferably, the step of controlling the selection of a register of a general register group as an input of an application macroinstruction operation module according to the application instruction by the application macroinstruction control module specifically includes:

[0025] After receiving each application instruction, the application macro instruction control module determines the register group that needs to be called;

[0026] The application macroinstruction control module controls the selection of registers of the general register group as inputs of the application macroinstruction operation module.

[0027] In one or more embodiments, preferably, the sub-computing unit that completes one or several specific application accelerations through the application macroinstruction operation module, and the calculation status and results are fed back to the application macroinstruction control module and the execution read write back module, specifically includes:

[0028] The application macro instruction control module sets the number of operations of the application macro instruction operation;

[0029] According to the number of operations of the application macroinstruction operation, the application macroinstruction operation module completes the accelerated operation and outputs the operation result to the application macroinstruction control module.

[0030] In one or more embodiments, preferably, the step of cyclically controlling the number of operation times of the application macroinstruction operation by the application macroinstruction control module, selecting the output result to be sent to the execution read write back module through the data bus, and writing it to the external storage space specifically includes:

[0031] After the application macro instruction control module obtains the operation result, it determines whether the current operation is completed;

[0032] If it is not finished, continue to control the application macro instruction operation module to complete a new acceleration operation until it is finished;

[0033] If finished, the current operation result is output to the execution read write back module.

[0034] According to a second aspect of an embodiment of the present invention, a MCU processor core system that is easy to apply and expand is provided.

[0035] In one or more embodiments, preferably, the MCU processor core system that is easy to apply and expand includes:

[0036] An instruction stream filtering module, used for acquiring the instruction stream through the macro instruction filtering module, and sending the instruction stream to the application macro instruction decoding module;

[0037] An application instruction splitting module is used to split the macro instruction into several application instructions through the application macro instruction decoding module;

[0038] A macro instruction control module, used for controlling the value control module to fetch instructions according to the application instruction by applying the macro instruction control module;

[0039] An application macroinstruction scheduling module, used for controlling the selection of a register of the general register group as an input of the application macroinstruction operation module according to the application instruction through the application macroinstruction control module;

[0040] An application macro-instruction acceleration calculation module is used to complete one or several sub-calculation units of specific application acceleration through the application macro-instruction calculation module, and the calculation status and results are fed back to the application macro-instruction control module and the execution read write-back module;

[0041] The application macro instruction output module is used to cyclically control the number of operation times of the application macro instruction operation operation through the application macro instruction control module, and select the output result to be sent to the execution read write back module through the data bus to write to the external storage space.

[0042] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method as described in any one of the first aspect of the embodiment of the present invention is implemented.

[0043] According to a fourth aspect of an embodiment of the present invention, there is provided an electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement any one of the methods described in the first aspect of the embodiment of the present invention.

[0044] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0045] The present invention is applicable to various embedded fields that are memory-sensitive and limited and require appropriate application expansion and acceleration, and can be widely used in industries such as home appliance control, industrial sensor acquisition and analysis, etc.

[0046] The present invention adds an application instruction decoding module and an application operation unit module, and can customize different instructions according to different application acceleration characteristics. The customized instructions can not only accelerate the processing of the application, but also reduce the number of instructions for executing operations, thereby reducing the code storage space, so as to solve the various application acceleration problems and code storage limitation problems of RISC.

[0047] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0048] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 The present invention is a flowchart of an MCU processor core method that is easy to apply and expand according to an embodiment of the present invention.

[0051] Figure 2 The invention is a flowchart of an MCU processor core method that is easy to apply and expand, which obtains instruction streams through a macro instruction filtering module and sends the instruction streams to an application macro instruction decoding module.

[0052] Figure 3 The invention discloses a flow chart of an MCU processor core method that is easy to apply and expand according to an embodiment of the present invention, in which a macro instruction is split into several application instructions by applying a macro instruction decoding module.

[0053] Figure 4 The present invention is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which a macro instruction control module is used to control a value control module to fetch instructions according to the application instruction.

[0054] Figure 5 The present invention is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which an application macroinstruction control module is used to control the selection of registers of a general register group as inputs of an application macroinstruction operation module according to the application instruction.

[0055] Figure 6 It is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which a sub-computing unit that completes one or several specific application accelerations through an application macroinstruction operation module, and the calculation status and results are fed back to an application macroinstruction control module and an execution read and write back module.

[0056] Figure 7 It is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which the application macroinstruction control module cyclically controls the number of operation operations of the application macroinstruction operation, selects the output result to be given to the execution read and write back module through the data bus, and writes it to the external storage space.

[0057] Figure 8 The present invention is a structural diagram of an MCU processor core system that is easy to apply and expand according to an embodiment of the present invention.

[0058] Fig. 9 It is a structural diagram of an electronic device in one embodiment of the present invention. DETAILED DESCRIPTION

[0059] In some of the processes described in the specification and claims of the present invention and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0061] The current mainstream MCU processor architecture is based on RISC, which improves performance by overlapping the execution of multiple instructions through a multi-stage pipeline. It uses relatively simple instructions with fixed lengths. To implement complex applications, it is necessary to combine these simple instructions, which requires more program storage space.

[0062] Prior to the technology of the present invention, in the embedded field, there were various applications that required customized acceleration. The traditional approach was to add an accelerator IP to the bus to accelerate and reduce storage space. However, this method was not flexible enough and was only applicable to specific applications. However, it was not convenient for application expansion in various embedded fields that were memory-sensitive and limited and required appropriate application expansion acceleration.

[0063] In the embodiment of the present invention, a method and system for an MCU processor core that is easy to apply and expand are provided. The solution forms an MCU processor core architecture that is easy to apply and expand by adding a macro instruction filtering module, an application macro instruction decoding module, an application macro instruction control module, and an application macro instruction operation module on the basis of the original processor core architecture, and is applicable to various embedded fields that are memory-sensitive and limited and require appropriate application expansion and acceleration.

[0064] According to a first aspect of an embodiment of the present invention, a method for an MCU processor core that is easy to apply and expand is provided.

[0065] Figure 1 The present invention is a flowchart of an MCU processor core method that is easy to apply and expand according to an embodiment of the present invention.

[0066] In one or more embodiments, preferably, the MCU processor core method that is easy to apply expansion includes:

[0067] S101, obtaining an instruction stream through a macro instruction filtering module, and sending the instruction stream to an application macro instruction decoding module;

[0068] S102, splitting the macro instruction into several application instructions by applying a macro instruction decoding module;

[0069] S103, controlling the value taking control module to fetch instructions according to the application instructions through the application macro instruction control module;

[0070] S104, selecting a register of the general register group as an input of the application macroinstruction operation module according to the application instruction control by the application macroinstruction control module;

[0071] S105, completing one or several sub-computing units for specific application acceleration through the application macroinstruction operation module, and feeding back the calculation status and results to the application macroinstruction control module and the execution read and write back module;

[0072] S106 , cyclically controlling the number of operation times of the application macroinstruction operation through the application macroinstruction control module, and selecting output results to be sent to the execution read and write back module through the data bus to write to the external storage space.

[0073] In an embodiment of the present invention, an MCU processor core architecture and method that is easy to expand applications are provided. On the basis of the original RISC processor architecture, an application instruction decoding module and an application operation unit module are added, and different instructions can be customized according to different application acceleration characteristics. The customized instructions can not only accelerate the processing of the application, but also reduce the number of instructions for executing operations, thereby reducing the code storage space, so as to solve the various application acceleration problems and code storage limitation problems of RISC.

[0074] Figure 2 The invention is a flowchart of an MCU processor core method that is easy to apply and expand, which obtains instruction streams through a macro instruction filtering module and sends the instruction streams to an application macro instruction decoding module.

[0075] like Figure 2 As shown, in one or more embodiments, preferably, the acquiring the instruction stream through the macro instruction filtering module and sending the instruction stream to the application macro instruction decoding module specifically includes:

[0076] S201, after inputting the instruction stream, first enter the macro instruction filtering module;

[0077] S202, determining whether there is a special byte combination value identification header through the macro instruction filtering module, and if so, determining that it is an application macro instruction;

[0078] S203: Determine whether there is a special byte combination value identification header through the macro instruction filtering module, and if not, determine it as a non-application macro instruction.

[0079] In the embodiment of the present invention, before the technology of the present invention, the existing embedded system has a decoding module, an instruction fetch control module, an operation module, a general register group and an execution read and write back module. For such a traditional structure, the solution proposed by the present invention first performs a primary filtering after obtaining the instruction stream to determine whether to send it directly to the decoding module for decoding.

[0080] Figure 3 The invention discloses a flow chart of an MCU processor core method that is easy to apply and expand according to an embodiment of the present invention, in which a macro instruction is split into several application instructions by applying a macro instruction decoding module.

[0081] like Figure 3 As shown, in one or more embodiments, preferably, the macro instruction is split by applying a macro instruction decoding module, and the splitting is performed into several application instructions, specifically including:

[0082] S301, pre-set the splitting rules, and obtain the instruction stream;

[0083] S302, splitting the instruction stream into multiple separate application instructions according to a preset rule;

[0084] S303: Send the application instructions one by one to the application macro instruction control module.

[0085] In the embodiment of the present invention, in order to be able to independently control each application, it is ensured that all application macro instructions are separated and processed one by one.

[0086] Figure 4 The present invention is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which a macro instruction control module is used to control a value control module to fetch instructions according to the application instruction.

[0087] like Figure 4 As shown, in one or more embodiments, preferably, the application macroinstruction control module controls the value control module to fetch instructions according to the application instruction, specifically including:

[0088] S401, after receiving each application instruction, the application macroinstruction control module determines the need to fetch instructions according to the application instruction;

[0089] S402: According to the instruction fetching requirement, use the value fetching control module to fetch instructions.

[0090] In the embodiment of the present invention, not every application instruction needs to be fetched, and whether an instruction needs to be fetched needs to be determined based on the interpretation of the application macroinstruction control module.

[0091] Figure 5 The present invention is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which an application macroinstruction control module is used to control the selection of registers of a general register group as inputs of an application macroinstruction operation module according to the application instruction.

[0092] like Figure 5 As shown, in one or more embodiments, preferably, the application macroinstruction control module controls the selection of a register of the general register group as an input of the application macroinstruction operation module according to the application instruction, specifically including:

[0093] S501, after receiving each application instruction, the application macro instruction control module determines the register group that needs to be called;

[0094] S502: The application macroinstruction control module controls the selection of registers of the general register group as inputs of the application macroinstruction operation module.

[0095] In the embodiment of the present invention, in order to realize the specific coordinated operation, the register group is used as the operation data input.

[0096] Figure 6 It is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which a sub-computing unit that completes one or several specific application accelerations through an application macroinstruction operation module, and the calculation status and results are fed back to an application macroinstruction control module and an execution read and write back module.

[0097] like Figure 6 As shown, in one or more embodiments, preferably, the sub-computing unit that completes one or several specific application accelerations through the application macroinstruction operation module, and the calculation status and results are fed back to the application macroinstruction control module and the execution read write back module, specifically includes:

[0098] S601, the application macro instruction control module sets the number of operations of the application macro instruction operation;

[0099] S602: According to the number of operations of the application macroinstruction operation, the application macroinstruction operation module completes the accelerated operation and outputs the operation result to the application macroinstruction control module.

[0100] In the embodiment of the present invention, all the operations shown are controlled by the macroinstruction control module. The specific application macroinstruction operation module is a solidified mode and repeats the operation. The possible sub-calculation units of the application macroinstruction operation module include one or more operations such as square, square root, trigonometric function, logarithm, exponent, CRC calculation, dot multiplication, multiplication and accumulation, etc.

[0101] Figure 7 It is a flowchart of an MCU processor core method that is easy to apply and expand in one embodiment of the present invention, in which the application macroinstruction control module cyclically controls the number of operation operations of the application macroinstruction operation, selects the output result to be given to the execution read and write back module through the data bus, and writes it to the external storage space.

[0102] like Figure 7 As shown, in one or more embodiments, preferably, the application macroinstruction control module cyclically controls the number of operations of the application macroinstruction operation, and selects the output result to be written to the external storage space through the data bus by the execution read write back module, specifically including:

[0103] S701, after obtaining the operation result, the application macro instruction control module determines whether the current operation is completed;

[0104] S702, if it is not finished, continue to control the application macro instruction operation module to complete a new acceleration operation until it is finished;

[0105] S703: If finished, output the current operation result to the execution read write back module.

[0106] In the embodiment of the present invention, specifically when data is transmitted, the application macroinstruction control module communicates with the execution read write back module through a data bus.

[0107] According to a second aspect of an embodiment of the present invention, a MCU processor core system that is easy to apply and expand is provided.

[0108] Figure 8 The present invention is a structural diagram of an MCU processor core system that is easy to apply and expand according to an embodiment of the present invention.

[0109] In one or more embodiments, preferably, the MCU processor core system that is easy to apply and expand includes:

[0110] The instruction stream filtering module 801 is used to obtain the instruction stream through the macro instruction filtering module and send the instruction stream to the application macro instruction decoding module;

[0111] The application instruction splitting module 802 is used to split the macro instruction into several application instructions through the application macro instruction decoding module;

[0112] A macro instruction control module 803, configured to control the value fetching control module to fetch instructions according to the application instruction by applying the macro instruction control module;

[0113] An application macroinstruction scheduling module 804, configured to control the selection of a register of the general register group as an input of the application macroinstruction operation module according to the application instruction through the application macroinstruction control module;

[0114] The application macroinstruction acceleration calculation module 805 is used to complete one or several sub-calculation units of specific application acceleration through the application macroinstruction calculation module, and feed back the calculation status and results to the application macroinstruction control module and the execution read write back module;

[0115] The application macro instruction output module 806 is used to control the number of operation times of the application macro instruction operation through the application macro instruction control module, and select the output result to be sent to the execution read write back module through the data bus to write to the external storage space.

[0116] In the embodiment of the present invention, a system suitable for different structures is realized through a series of modular designs. The system can achieve closed-loop, reliable and efficient execution through collection, analysis and control.

[0117] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method as described in any one of the first aspect of the embodiment of the present invention is implemented.

[0118] According to a fourth aspect of an embodiment of the present invention, an electronic device is provided. Fig. 9 It is a structural diagram of an electronic device in one embodiment of the present invention. Fig. 9 The electronic device shown is a device with a universal MCU processor core that is easy to apply and expand. The electronic device can be a smart phone, a tablet computer, and other devices. As shown, the electronic device 900 includes a processor 901 and a memory 902. Among them, the processor 901 is electrically connected to the memory 902. The processor 901 is the control center of the terminal 900, and uses various interfaces and lines to connect various parts of the entire terminal. By running or calling a computer program stored in the memory 902, and calling the data stored in the memory 902, the various functions of the terminal are executed and the data is processed, thereby monitoring the terminal as a whole.

[0119] In this embodiment, the processor 901 in the electronic device 900 will load the instructions corresponding to the processes of one or more computer programs into the memory 902 according to the following steps, and the processor 901 will run the computer program stored in the memory 902 to achieve various functions: obtain the instruction stream through the macroinstruction filtering module, and send the instruction stream to the application macroinstruction decoding module; split the macroinstruction into several application instructions through the application macroinstruction decoding module; control the value control module to fetch instructions according to the application instructions through the application macroinstruction control module; control the selection of registers of the general register group as inputs of the application macroinstruction operation module according to the application instructions through the application macroinstruction control module; complete one or several sub-computing units of specific application acceleration through the application macroinstruction operation module, and feed back the calculation status and results to the application macroinstruction control module and the execution read write back module; cyclically control the number of operation operations of the application macroinstruction operation operation through the application macroinstruction control module, and select the output result to the execution read write back module through the data bus to write to the external storage space.

[0120] The memory 902 may be used to store computer programs and data. The computer programs stored in the memory 902 include instructions that can be executed in the processor. The computer programs may constitute various functional modules. The processor 901 executes various functional applications and data processing by calling the computer programs stored in the memory 902.

[0121] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0122] The present invention is applicable to various embedded fields that are memory-sensitive and limited and require appropriate application expansion and acceleration, and can be widely used in industries such as home appliance control, industrial sensor acquisition and analysis, etc.

[0123] The present invention adds an application instruction decoding module and an application operation unit module, and can customize different instructions according to different application acceleration characteristics. The customized instructions can not only accelerate the processing of the application, but also reduce the number of instructions for executing operations, thereby reducing the code storage space, so as to solve the various application acceleration problems and code storage limitation problems of RISC.

[0124] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0125] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0126] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0127] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0128] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for an MCU processor core that is easy to apply and expand, characterized in that: The method includes: Obtain the instruction stream through the macro instruction filtering module and send the instruction stream to the application macro instruction decoding module; Splitting the macro instruction into several application instructions by applying the macro instruction decoding module; Controlling the value taking control module to fetch instructions according to the application instructions by applying the macro instruction control module; Selecting a register of the general register group as an input of the application macroinstruction operation module according to the application instruction control by the application macroinstruction control module; The sub-computing unit that completes application acceleration through the application macro-instruction operation module feeds back the computing status and results to the application macro-instruction control module and the execution read write-back module; The application macro instruction control module cyclically controls the number of operation times of the application macro instruction operation, and selects the output result to be sent to the execution read write back module through the data bus and written to the external storage space; The method of obtaining the instruction stream through the macro instruction filtering module and sending the instruction stream to the application macro instruction decoding module specifically includes: After the instruction stream is input, the macro instruction filtering module is first entered; The macro instruction filtering module is used to determine whether there is a special byte combination value identification header, and if so, it is determined to be an application macro instruction; Determine whether there is a special byte combination value identification header through the macro instruction filtering module, and if not, determine it as a non-application macro instruction; The macro instruction is split into several application instructions by applying a macro instruction decoding module, specifically including: The splitting rules are pre-set, and when the instruction stream is obtained; According to a preset rule, the instruction stream is split into a plurality of separate application instructions; Sending the application instructions one by one to the application macro instruction control module; The step of controlling the value taking control module to fetch instructions according to the application instruction by using the macro instruction control module specifically includes: After receiving each application instruction, the application macro instruction control module determines the need to fetch instructions according to the application instruction; According to the demand for instruction fetching, using the value fetching control module to fetch instructions; The sub-computing unit that completes application acceleration through the application macro-instruction operation module feeds back the calculation status and results to the application macro-instruction control module and the execution read and write back module, specifically including: The application macro instruction control module sets the number of operations of the application macro instruction operation; According to the number of operations of the application macroinstruction operation, the application macroinstruction operation module completes the accelerated operation and outputs the operation result to the application macroinstruction control module.

2. The MCU processor core method that is easy to apply and expand as claimed in claim 1, characterized in that: The step of controlling the selection of a register of the general register group as an input of the application macroinstruction operation module by the application macroinstruction control module according to the application instruction specifically includes: After receiving each application instruction, the application macro instruction control module determines the register group that needs to be called; The application macroinstruction control module controls the selection of registers of the general register group as inputs of the application macroinstruction operation module.

3. The MCU processor core method that is easy to apply and expand as claimed in claim 2 is characterized in that: The application macro instruction control module cyclically controls the number of operation times of the application macro instruction operation, selects the output result to be sent to the execution read write back module through the data bus, and writes it to the external storage space, specifically including: After the application macro instruction control module obtains the operation result, it determines whether the current operation is completed; If it is not finished, continue to control the application macro instruction operation module to complete a new acceleration operation until it is finished; If finished, the current operation result is output to the execution read write back module.

4. An MCU processor core system that is easy to apply and expand, characterized in that: The system is used to implement the method according to any one of claims 1 to 3, and the system comprises: An instruction stream filtering module, used for acquiring the instruction stream through the macro instruction filtering module, and sending the instruction stream to the application macro instruction decoding module; An application instruction splitting module is used to split the macro instruction into several application instructions through the application macro instruction decoding module; A macro instruction control module, used for controlling the value control module to fetch instructions according to the application instruction by applying the macro instruction control module; An application macroinstruction scheduling module, used for controlling the selection of a register of the general register group as an input of the application macroinstruction operation module according to the application instruction through the application macroinstruction control module; An application macroinstruction acceleration calculation module is used to complete the sub-calculation unit of application acceleration through the application macroinstruction calculation module, and the calculation status and results are fed back to the application macroinstruction control module and the execution read write back module; The application macro instruction output module is used to cyclically control the number of operation times of the application macro instruction operation operation through the application macro instruction control module, and select the output result to be sent to the execution read write back module through the data bus to write to the external storage space.

5. A computer-readable storage medium storing computer program instructions, characterized in that: The computer program instructions implement the method according to any one of claims 1 to 3 when executed by a processor.

6. An electronic device comprising a memory and a processor, characterized in that: The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1-3.

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