A method and system for rapidly improving CPU fault diagnosis based on FPGA

Abstract

The present invention discloses a method and system for rapidly improving CPU fault diagnosis based on FPGA, which relates to the technical field of computer hardware and system diagnosis, including configuring FPGA UART baud rate and monitoring system status; processing CPU fault according to fault log analysis fault type and recording log records; saving fault information and resetting system and log. The method for rapidly improving CPU fault diagnosis based on FPGA provided by the present invention improves the accuracy and efficiency of data communication by configuring FPGA UART baud rate and monitoring system status, making fault analysis and processing more targeted and effective, and improving the fault recovery speed of the system by saving fault information and resetting system and log. The present invention achieves better results in terms of accuracy, diagnostic speed and fault recovery speed.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware and system diagnosis, and in particular to a method and system for rapidly improving CPU fault diagnosis based on FPGA. Background Art

[0002] In modern computer systems, the CPU is the core processing unit, and its stability and fault handling mechanism have a crucial impact on the reliability of the entire system. With the rapid development of computing technology, especially its wide application in the fields of big data, cloud computing, and the Internet of Things, higher requirements are placed on the stability and rapid fault handling capabilities of the CPU. Traditional CPU fault diagnosis methods mostly rely on software-level solutions, such as monitoring programs and logging systems within the operating system. Although these methods can detect and record faults to a certain extent, they often cannot meet the requirements of high-reliability systems in terms of response speed and processing efficiency when faults occur. In addition, the fault handling mechanism at the software level is largely limited by the stability of the operating system. Once the operating system crashes or core services fail, the effectiveness of these mechanisms will be greatly reduced.

[0003] In recent years, the method of using field programmable gate array (FPGA) technology to diagnose and handle CPU faults has gradually attracted attention. FPGA has the characteristics of high configurability, strong parallel processing capabilities and fast response speed. By directly monitoring and analyzing the CPU status at the hardware level, it can greatly improve the speed and accuracy of system fault handling. However, the existing FPGA-based CPU fault diagnosis technology still has some shortcomings. For example, the processing efficiency and automation level in fault log recording, fault information storage and system reset are not high enough, which to some extent limits its application in high-demand systems.

[0004] Single-core CPU: The CPU is directly connected to a watchdog through a port line. When the CPU is stuck, the watchdog feeding operation is stopped and the watchdog action resets the CPU.

[0005] Multi-core CPU: The CPU is directly connected to the watchdog through the port line. The master core CPU is responsible for feeding the watchdog. The master core CPU communicates with the slave core CPU through heartbeat. When it is detected that the slave core has no heartbeat, the slave core is reset. However, there is a situation where the slave core is stuck and the CPU master core is also stuck. This situation will also cause the CPU to reset abnormally.

[0006] In the above two CPU abnormal reset situations, the fault can only be located by monitoring the CPU through an external serial port and reproducing the problem, which seriously affects the positioning efficiency. Summary of the invention

[0007] In view of the above-mentioned problems, the present invention is proposed.

[0008] Therefore, the technical problem solved by the present invention is that the existing fault diagnosis method has the problems of high watchdog malfunction frequency, low accuracy, low recognition speed, and inability to identify which core of a multi-core CPU is running an operating system that is stuck.

[0009] To solve the above technical problems, the present invention provides the following technical solutions: a method for quickly improving CPU fault diagnosis based on FPGA, including configuring FPGA UART baud rate and monitoring system status; processing CPU faults according to fault log analysis fault type and recording log records; saving fault information and resetting the system and log.

[0010] As a preferred solution of the FPGA-based fast CPU fault diagnosis method described in the present invention, wherein: the configuration of the FPGA UART baud rate and monitoring of the system status includes sending a configuration instruction to the FPGA through the C_SPI0 interface after the CPU is powered on, setting the UART baud rate, and ensuring that the FPGA correctly receives the serial data of the CPU;

[0011] The FPGA monitors the dog feeding signal from the CPU in real time. Based on the signal interval, the FPGA evaluates the system status as normal, overloaded, or faulty.

[0012] As a preferred solution of the FPGA-based fast CPU fault diagnosis method of the present invention, wherein: the configuration of the FPGA UART baud rate and monitoring of the system status includes continuing to judge according to the interval time of the dog feeding signal;

[0013] When the dog feeding signal interval is 100ms to 500ms, the system will not trigger a restart by mistake under load, and will restart immediately when a system failure occurs;

[0014] When the interval between dog-feeding signals is 500ms to 1s, the system is processing high load or experiencing minor performance issues. Warnings should be recorded and monitored for any trend of continued deterioration.

[0015] When the interval between dog-feeding signals is longer than 1 second or no dog-feeding signal is received, the system has crashed or failed. The error is recorded immediately, the administrator is notified, and a restart is triggered according to the system.

[0016] If the interval of the dog feeding signal is less than 1s, the dynamic interval of the task priority is adjusted to a low priority task, and the low priority task increases the interval of the dog feeding signal;

[0017] If the interval of the dog feeding signal is longer than 1s, the dynamic interval for determining the task priority is adjusted to a high priority task, and the system reserves CPU and memory resources to ensure that the task runs under load;

[0018] After determining the watchdog signal interval, it is transmitted to the system load adjustment, and the watchdog signal interval is adjusted according to the usage rates of CPU and memory resources;

[0019] Perform dynamic UART baud rate configuration model and status monitoring. The UART baud rate depends on time and the physical location of the transmission medium , environmental noise and signal attenuation , expressed as:

[0020] ;

[0021] Among them, represents the UART baud rate, which depends on time t and the physical location x of the transmission medium, represents the environmental noise function, indicating that the noise changes with time and location, represents the signal attenuation function, describing the attenuation of the signal with time and location, represents the material and environmental parameters, represents the attenuation coefficient, and represents adjusting the influence of signal attenuation and noise, represents the propagation speed of the signal in the medium, represents the local effect at location x, represents the spectrum of the signal passing through a specific point, represents the past time point;

[0022] When the CPU usage rate ≤ 30%, the system load is low, the watchdog signal interval is increased by 100 ms, the UART baud rate is dynamically adjusted, and by monitoring and environmental noise and signal attenuation relationship, automatically adjust the baud rate during data transmission;

[0023] When 30% < CPU usage rate ≤ 70%, the system load is medium, and the watchdog signal interval remains unchanged;

[0024] When the CPU usage rate > 70%, the system load is high, the watchdog signal interval is reduced by 100 ms, and by combining the dynamically adjusted baud rate with the CPU usage rate and temperature status, optimize the communication protocol, reduce the system load, and adjust the watchdog signal interval based on the system stability and the number of faults occurred in the past 24 hours;

[0025] Considering the system status, construct an evaluation model for fault type determination, expressed as:

[0026] ;

[0027] in, represents the system state function, and is the adjustment parameter, represents the nonlinear action function, Indicates the impact of external factors on the system status, including CPU usage, system temperature, represents the system state vector;

[0028] when Indicates that a fault has occurred and is considered stable, and the interval between dog feeding signals is increased by 50ms;

[0029] when The indication fault is judged as a normal state, and the interval time of the dog feeding signal remains unchanged;

[0030] when The indication fault is judged as unstable state, and the interval of feeding dog signal is reduced by 50ms;

[0031] Combined with the load and priority information, the high-priority tasks with a history of failures are further shortened in the high-load state to feed the dog signal interval and enter the system temperature indicator determination;

[0032] When the temperature is ≤60°C, the system determines it as normal temperature and the interval of feeding the dog signal remains unchanged;

[0033] When the temperature is 60°C < ≤ 80°C, the system initiates a temperature warning and the dog feeding signal interval is reduced by 50ms;

[0034] When the temperature is >80°C, the system triggers a temperature danger and the dog feeding signal interval is reduced by 100ms;

[0035] According to the interval of the dog feeding signal, the FPGA records the status indication and takes corresponding measures according to the set screening conditions, recording the system overload log or preparing for system restart.

[0036] As a preferred solution of the FPGA-based fast CPU fault diagnosis method described in the present invention, the processing of CPU faults and recording log records according to the fault log analysis fault type include sending core dump logs to FPGA through the UART port when the CPU encounters a jam or fault, stopping sending dog feeding signals, and after the FPGA receives the log, classifying and storing it according to the log record level. After a fault occurs, the BRAM data is migrated to the SPI FLASH, and measures are taken according to the fault log analysis fault type.

[0037] As a preferred solution of the FPGA-based fast CPU fault diagnosis method described in the present invention, wherein: the processing of CPU faults and recording log records according to the fault log analysis fault type includes monitoring the CPU state, capturing fault signals, and classifying faults;

[0038] If the CPU temperature exceeds 70°C or the CPU utilization exceeds 90% for five minutes, a detailed log is recorded, including the time of occurrence, duration, and scope of impact, and the CPU power consumption is adjusted to reduce the temperature;

[0039] If the CPU temperature does not fall below 70°C after power consumption adjustment, the warning system is triggered;

[0040] Logs are classified and scored according to the severity of the content. The scores are output based on the frequency, type, and scope of impact of the error.

[0041] If the log score is less than 50 points, the log is marked as information and stored;

[0042] If 50 points < log score ≤ 75 points, analysis is performed. If a repeated pattern is found, the processing priority is upgraded and judgment is made based on the interval time of the dog feeding signal;

[0043] If 75 points < log score ≤ 90 points, notify the system administrator and start the automatic diagnosis program;

[0044] If the log score is > 90 points, the emergency response process is automatically triggered, and an attempt is made to restart the affected services and start the backup system;

[0045] When the log score is greater than 50 points, the system is considered to have a fault, and the fault is classified based on the frequency of the fault and the difficulty of fault repair;

[0046] Construct a high-dimensional matrix model for fault log analysis and define the characteristic matrix of fault logs and the corresponding weight matrix , the fault type is expressed as:

[0047] ;

[0048] in, Indicates the changes in fault characteristics at different time points, is the decay constant, represents the fault score vector;

[0049] The fault logs are analyzed by a high-dimensional matrix model, and faults are classified into information, warning, error, and emergency according to their severity, frequency, and impact range.

[0050] If the fault is classified as information, routine recording and subsequent analysis will be performed without immediate notification;

[0051] If the fault is classified as a warning, a fault report is generated, the technical support team is automatically notified, and the fault is highlighted in the system log;

[0052] If the fault is classified as an error or emergency, the automatic fault recovery procedure will be started immediately. If the automatic recovery fails, the manual emergency handling process will be automatically started, and the backup system will be started to maintain the service.

[0053] Perform fault archiving and preventive analysis based on fault frequency and repair time, and output the fault impact range and fault recurrence probability;

[0054] If the number of affected users is less than 100 or the number of affected components is less than 5%, archive and store the logs and analyze them regularly.

[0055] If the number of users affected is 100 to 1,000 or the number of components affected is 5% to 20%, archive and store the information, perform failure mode analysis, extract failure processing information, and share solutions.

[0056] If the number of affected users is >1000 or the number of components is >20%, archive the results and improvement measures, integrate them into the knowledge base, and conduct special training;

[0057] The generated analysis data and measures should be recorded and saved in the external SPI FLASH.

[0058] As a preferred solution of the FPGA-based fast CPU fault diagnosis method described in the present invention, wherein: the processing of CPU faults according to the fault log analysis fault type and recording log records include when the faults are classified based on the frequency of fault occurrence and the difficulty of fault repair, and when the fault impact range and the fault recurrence probability are output, the WDG CTRL and the retrograde system are reset, and before the reset, the CPU state and the log information in the BRAM are saved, and the output results of the fault impact range and the fault recurrence probability are saved;

[0059] When the WDG CTRL module triggers a system reset, it classifies faults based on the frequency of fault occurrence and the difficulty of fault repair, and outputs the fault impact range and fault recurrence probability;

[0060] Before resetting, all CPU states and log information in the BRAM, including fault analysis data generated by outputting the fault impact range and fault recurrence probability, are saved.

[0061] As a preferred solution of the FPGA-based fast CPU fault diagnosis method of the present invention, wherein: the saving of fault information and resetting the system and log includes, after confirming the system fault, the WDG CTRL of the FPGA instructs the SPIFLASH control to save the CPU state and the log information in the BRAM to the external SPI FLASH;

[0062] After saving all information, WDG CTRL stops sending the dog feeding signal, causing the WATCHDOG chip to trigger a system reset and restart the CPU and FPGA;

[0063] After the system restarts, the FPGA reads the fault information from the SPI FLASH and loads it into the CPU abnormal status register;

[0064] The CPU queries through the C_SPI0 interface, takes recovery measures based on the fault type and log information, and restores the coredump information to the file system for analysis.

[0065] Another object of the present invention is to provide a fast CPU fault diagnosis system based on FPGA, which can solve the problem of low accuracy of current fault diagnosis methods and technologies by configuring FPGA UART baud rate and monitoring system status.

[0066] As a preferred solution of the FPGA-based fast CPU fault diagnosis system described in the present invention, it includes: a system status monitoring module, a CPU fault processing module, a log recording module, a fault information storage module, and a log recovery module; the system status monitoring module is used to configure the FPGA UART baud rate and monitor the system status; the CPU fault processing module is used to perform CPU fault detection; the log recording module is used to classify and screen logs; the fault information storage module is used to classify fault information; and the log recovery module is used to take recovery measures according to the fault type and log information.

[0067] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement a step of a method for rapidly improving CPU fault diagnosis based on FPGA.

[0068] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a method for rapidly improving CPU fault diagnosis based on FPGA.

[0069] Beneficial effects of the present invention: The FPGA-based fast CPU fault diagnosis method provided by the present invention improves the accuracy and efficiency of data communication by configuring the FPGA UART baud rate and monitoring the system status, and improves the beneficial effects of improving the CPU fault diagnosis speed and accuracy. The steps of analyzing the fault type according to the fault log, processing the CPU fault and recording the log further enhance the self-diagnosis and recovery capabilities of the system, making the management of fault information more efficient, and making the fault analysis and processing more targeted and effective, thereby ensuring the rapid recovery and continuous operation of the system. By saving the fault information and resetting the system and the log, the fault recovery speed of the system is improved, and important data support is provided for the continuous improvement of the system. The present invention achieves better results in terms of accuracy, diagnosis speed and fault recovery speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0071] Figure 1 An overall flow chart of a method for rapidly improving CPU fault diagnosis based on FPGA provided in the first embodiment of the present invention.

[0072] Figure 2 A main structural block diagram of a method for rapidly improving CPU fault diagnosis based on FPGA provided in the first embodiment of the present invention.

[0073] Figure 3 A schematic diagram of a dog feeding module for a method for rapidly improving CPU fault diagnosis based on FPGA provided in the first embodiment of the present invention.

[0074] Figure 4 The overall framework diagram of a method for rapidly improving CPU fault diagnosis based on FPGA provided in the first embodiment of the present invention.

[0075] Figure 5 An overall flow chart of a FPGA-based rapid CPU fault diagnosis system provided in the third embodiment of the present invention. DETAILED DESCRIPTION

[0076] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0077] Example 1

[0078] Reference Figure 1-Figure 4 , as an embodiment of the present invention, provides a method for quickly improving CPU fault diagnosis based on FPGA, comprising:

[0079] S1: Configure the FPGA UART baud rate and monitor the system status.

[0080] Furthermore, after the CPU is powered on, it sends configuration instructions to the FPGA through the C_SPI0 interface to set the UART baud rate and ensure that the FPGA correctly receives the serial data from the CPU;

[0081] The FPGA monitors the dog feeding signal from the CPU in real time. Based on the signal interval, the FPGA evaluates the system status as normal, overloaded, or faulty.

[0082] It should be noted that the judgment is continued according to the interval time of the dog feeding signal;

[0083] When the dog feeding signal interval is 100ms to 500ms, the system will not trigger a restart by mistake under load, and will restart immediately when a system failure occurs;

[0084] When the interval between dog-feeding signals is 500ms to 1s, the system is processing high load or experiencing minor performance issues. Warnings should be recorded and monitored for any trend of continued deterioration.

[0085] When the interval between dog-feeding signals is longer than 1 second or no dog-feeding signal is received, the system has crashed or failed. The error is recorded immediately, the administrator is notified, and a restart is triggered according to the system.

[0086] If the interval of the dog feeding signal is less than 1s, the dynamic interval of the task priority is adjusted to a low priority task, and the low priority task increases the interval of the dog feeding signal;

[0087] If the interval of the dog feeding signal is longer than 1s, the dynamic interval for determining the task priority is adjusted to a high priority task, and the system reserves CPU and memory resources to ensure that the task runs under load;

[0088] After determining the dog feeding signal interval, it is passed to the system load adjustment, and the dog feeding signal interval is adjusted according to the utilization rate of CPU and memory resources;

[0089] Perform dynamic UART baud rate configuration model and status monitoring. The UART baud rate depends on time and the physical location of the transmission medium , environmental noise and signal attenuation , expressed as:

[0090] ;

[0091] Among them, represents the UART baud rate, which depends on time t and the physical location x of the transmission medium, represents the environmental noise function, indicating that the noise changes with time and location, represents the signal attenuation function, describing the attenuation of the signal with time and location, represents the material and environmental parameters, represents the attenuation coefficient, and represent adjusting the influence of signal attenuation and noise, represents the propagation speed of the signal in the medium, represents the local effect at position x, represents the spectrum of the signal passing through a specific point, represents the past time point;

[0092] When the CPU usage rate ≤ 30%, the system load is low, the watchdog signal interval time increases by 100 ms, dynamically adjust the UART baud rate, by monitoring the relationship with environmental noise and signal attenuation to automatically adjust the baud rate during data transmission;

[0093] When 30% < CPU usage rate ≤ 70%, the system load is medium, the watchdog signal interval time remains unchanged;

[0094] When the CPU usage rate > 70%, the system load is high, the watchdog signal interval time decreases by 100 ms, by combining the dynamically adjusted baud rate with the CPU usage rate and temperature status, optimize the communication protocol, reduce the system load, and adjust the watchdog signal interval based on the system stability and the number of faults in the past 24 hours;

[0095] Considering the system status, construct an evaluation model for fault type determination, expressed as:

[0096] ;

[0097] Among them, represents the system status function, and is the adjustment parameter, represents the nonlinear action function, Indicates the impact of external factors on the system status, including CPU usage, system temperature, represents the system state vector;

[0098] when Indicates that a fault has occurred and is considered stable, and the interval between dog feeding signals is increased by 50ms;

[0099] when The indication fault is judged as a normal state, and the interval time of the dog feeding signal remains unchanged;

[0100] when The indication fault is judged as unstable state, and the interval of feeding dog signal is reduced by 50ms;

[0101] Combined with the load and priority information, the high-priority tasks with a history of failures are further shortened in the high-load state to feed the dog signal interval and enter the system temperature indicator determination;

[0102] When the temperature is ≤60°C, the system determines it as normal temperature and the interval of feeding the dog signal remains unchanged;

[0103] When the temperature is 60°C < ≤ 80°C, the system initiates a temperature warning and the dog feeding signal interval is reduced by 50ms;

[0104] When the temperature is >80°C, the system triggers a temperature danger and the dog feeding signal interval is reduced by 100ms;

[0105] According to the interval of the dog feeding signal, the FPGA records the status indication and takes corresponding measures according to the set screening conditions, recording the system overload log or preparing for system restart.

[0106] It should also be noted that after the CPU is powered on, the UART baud rate of the FPGA is configured through the C_SPI0 interface and stored in the UART baud rate register of the FPGA, so that the UART of the FPGA can correctly receive the serial data sent by the UART in the CPU.

[0107] When the Linux running on core 1 or the RT Thread running on core 2 of the CPU freezes, the CPU will send the core dump log to the UART pin of the FPGA through UART. At this time, the dog feeding module in the CPU cannot perform the dog feeding operation because the system freezes.

[0108] S2: Analyze the fault type according to the fault log, handle the CPU fault and record the log record.

[0109] Furthermore, when the CPU is stuck or fails, it sends a core dump log to the FPGA through the UART port and stops sending the dog-feeding signal. After receiving the log, the FPGA stores it in categories according to the log record level. When a fault occurs, the BRAM data is migrated to the SPI FLASH, and measures are taken based on the fault type analyzed according to the fault log.

[0110] It should be noted that the CPU status is monitored, fault signals are captured, and faults are classified;

[0111] If the CPU temperature exceeds 70°C or the CPU utilization exceeds 90% for five minutes, a detailed log is recorded, including the time of occurrence, duration, and scope of impact, and the CPU power consumption is adjusted to reduce the temperature;

[0112] If the CPU temperature does not fall below 70°C after power consumption adjustment, the warning system is triggered;

[0113] Logs are classified and scored according to the severity of the log content. The scores are output based on the frequency, type, and scope of impact of the error.

[0114] If the log score is less than 50 points, the log is marked as information and stored;

[0115] If 50 points < log score ≤ 75 points, analysis is performed. If a repeated pattern is found, the processing priority is upgraded and judgment is made based on the interval time of the dog feeding signal;

[0116] If 75 points < log score ≤ 90 points, notify the system administrator and start the automatic diagnosis program;

[0117] If the log score is > 90 points, the emergency response process is automatically triggered, and an attempt is made to restart the affected services and start the backup system;

[0118] When the log score is greater than 50 points, the system is considered to have a fault, and the fault is classified based on the frequency of the fault and the difficulty of fault repair;

[0119] Construct a high-dimensional matrix model for fault log analysis and define the characteristic matrix of fault logs and the corresponding weight matrix , the fault type is expressed as:

[0120] ;

[0121] in, Indicates the changes in fault characteristics at different time points, is the decay constant, represents the fault score vector;

[0122] The fault logs are analyzed by a high-dimensional matrix model, and faults are classified into information, warning, error, and emergency according to their severity, frequency, and impact range.

[0123] If the fault is classified as information, routine recording and subsequent analysis will be performed without immediate notification;

[0124] If the fault is classified as a warning, a fault report is generated, the technical support team is automatically notified, and the fault is highlighted in the system log;

[0125] If the fault is classified as an error or emergency, the automatic fault recovery procedure will be started immediately. If the automatic recovery fails, the manual emergency handling process will be automatically started, and the backup system will be started to maintain the service.

[0126] Perform fault archiving and preventive analysis based on fault frequency and repair time, and output the fault impact range and fault recurrence probability;

[0127] If the number of affected users is less than 100 or the number of affected components is less than 5%, archive and store the logs and analyze them regularly.

[0128] If the number of users affected is 100 to 1,000 or the number of components affected is 5% to 20%, archive and store the information, perform failure mode analysis, extract failure processing information, and share solutions.

[0129] If the number of affected users is >1000 or the number of components is >20%, archive the results and improvement measures, integrate them into the knowledge base, and conduct special training;

[0130] The generated analysis data and measures should be recorded and saved in the external SPI FLASH.

[0131] It should also be noted that when entering the classification of faults based on the frequency of fault occurrence and the difficulty of fault repair, and outputting the fault impact range and the fault recurrence probability, the WDG CTRL and the retrograde system are reset, and before the reset, the CPU state and the log information in the BRAM, as well as the output results of the fault impact range and the fault recurrence probability are saved;

[0132] When the WDG CTRL module triggers a system reset, it classifies faults based on the frequency of fault occurrence and the difficulty of fault repair, and outputs the fault impact range and fault recurrence probability;

[0133] Before resetting, all CPU states and log information in the BRAM, including fault analysis data generated by outputting the fault impact range and fault recurrence probability, are saved.

[0134] Furthermore, the FPGA monitors the log information sent by the CPU through the UART port in real time and stores it in the internal 8KBRAM module. The WATCHDOG monitoring module in the FPGA monitors the level flip signal sent by the CPU in real time. When the level flip signal is not received for 3 consecutive seconds, the CPU abnormal signal is sent to the WDG CTRL module in the FPGA.

[0135] When the WDG CTRL module does not receive the CPU abnormal signal sent by the WATCHDOG monitoring module, it will flip the level of the f4 pin at an interval of 100ms to achieve the dog feeding operation of the WATCHDOG chip. When receiving the CPU abnormal signal sent by the WATCHDOG monitoring module, the WDG CTRL module will first notify the SPI FLASH control module. The SPI FLASH control module first stores the content of the CPU4-byte abnormal status register to the external SPI FLASH through the F_SPI bus, and then stores the CPU core dump information stored in the BRAM to the external SPI FLASH chip. After the CPU core dump information is stored, the WDG CTRL module stops the signal flipping control of the f4 pin, which is equivalent to stopping the dog feeding operation.

[0136] S3: Save fault information and reset the system and log.

[0137] Furthermore, after confirming the system failure, the WDG CTRL of the FPGA instructs the SPI FLASH to control the CPU status and the log information in the BRAM to be saved in the external SPI FLASH;

[0138] After saving all information, WDG CTRL stops sending the dog feeding signal, causing the WATCHDOG chip to trigger a system reset and restart the CPU and FPGA;

[0139] After the system restarts, the FPGA reads the fault information from the SPI FLASH and loads the fault information into the CPU abnormal status register;

[0140] The CPU queries this information through the C_SPI0 interface, takes recovery measures based on the fault type and log information, and restores the core dump information to the file system for analysis.

[0141] It should be noted that as the FPGA stops feeding the dog, the external WATCHDOG chip will reset the CPU and FPGA, causing the CPU and FPGA to restart. After the FPGA restarts, the CPU abnormal status in the external SPI FLASH is read to the CPU abnormal status register through the F_SPI1 interface, and the last stored CPU core dump information is stored in the CORE1 LOG or CORE2 LOG module inside the FPGA according to the abnormal status of the corresponding CPU. After the CPU restarts, the CPU abnormal status register is first queried through the FPGA through the C_SPI0 interface, and the CPU core dump information in the CORE1 or CORE2LOG module in the FPGA is read to the memory according to the corresponding bit of the CPU abnormal status register, and the core dump file is stored in the system's file system for subsequent viewing and positioning. After the CPU storage is completed, the contents of the CPU abnormal status register are cleared through the C_SPI0 interface.

[0142] It should also be noted that the storage structure of data in spi flash is represented as follows: 1-4 bytes store status, 5-8 stores length, and 9-len is the log message. core1 represents the first core in the dual-core CPU; core dump means that when the operating system receives certain signals and terminates the process, it dumps the contents of the process address space and other information about the process status at this time, which is often used for debugging; core2 represents the second core in the dual-core CPU; UART stands for universal asynchronous receiver and transmitter. Universal asynchronous receiver and transmitter is a universal serial data bus used for asynchronous communication. The bus communicates bidirectionally and can achieve full-duplex transmission and reception. In embedded design, UART is used to communicate with PC, including monitoring debugger and other devices such as EEPROM; core dump log means that when the process receives certain signals and stops running, the operating system records the contents of the process address space and other information about the process status; BRAM means block random access memory, which is mainly used to construct data cache memory, deep FIFO and buffer, etc.; WATCHDOG means watchdog, which is essentially a timer circuit, generally with one input and one output, where the input is called feeding dog, and the output is generally connected to the reset end of another part, generally connected to the CPU. The function of the watchdog is to regularly check the internal situation of the chip and send a restart signal to the chip once an error occurs. The watchdog command has the highest priority in the interrupt of the program; SPI FLASH means a storage chip with SPI interface, which is used to store data; UART0_TX and C_SPI0 represent pins.

[0143] Example 2

[0144] An embodiment of the present invention provides a method for rapidly improving CPU fault diagnosis based on FPGA. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0145] First, the experimental preparation includes two sets of identical hardware environments, each containing a CPU and an FPGA board. In the experimental group, the FPGA was configured to communicate with a UART baud rate of 115200bps, and a strategy for monitoring system status, fault log analysis, and system reset was implemented. The control group used existing technology, in which fault diagnosis relied on software-level monitoring and logging.

[0146] The experiment simulated a variety of fault conditions, including CPU overheating (temperature exceeding 95°C), high load (CPU usage exceeded 95% for more than 5 minutes), and hardware failures (such as memory errors). For each fault, the time from the occurrence of the fault to the system diagnosing the fault type, and the time from the occurrence of the fault to the system returning to normal operation were recorded. In addition, the stability of the system after recovery was recorded to verify the effectiveness of fault recovery.

[0147] Table 1 Experimental results

[0148]

[0149] From the above experimental data table, we can see that the FPGA-based CPU fault diagnosis method outperforms the prior art in many aspects. First, in the case of CPU overheating, the FPGA-based method can identify the fault within 15 seconds, while the prior art requires 30 seconds, indicating that the present invention has a significant advantage in fault detection speed. Similarly, in the diagnosis of high load and hardware faults, the present invention only takes 10 seconds and 5 seconds, respectively, which is much faster than the 20 seconds and 15 seconds of the prior art. This result proves that the speed of fault diagnosis can be significantly improved through real-time monitoring and rapid response of the system status by FPGA.

[0150] System recovery time is also an important indicator for measuring fault handling capabilities. Experiments show that it takes only 20 seconds for a system using the method of the present invention to recover from a fault, while it takes 45 seconds for a system using the prior art. This shows that the present invention can not only quickly diagnose faults, but also quickly take measures to recover the system, greatly reducing system downtime.

[0151] In addition to the speed advantage, the present invention also excels in the accuracy of fault diagnosis. The FPGA-based method achieves an accuracy of 98%, while the accuracy of the prior art is 90%. This difference illustrates the efficiency and accuracy of the present invention in fault type analysis and processing, and can more accurately identify and respond to various faults.

[0152] In summary, the present invention achieves better results in terms of accuracy, diagnosis speed and fault recovery speed.

[0153] Example 3

[0154] Reference Figure 5 , as an embodiment of the present invention, provides a FPGA-based rapid CPU fault diagnosis system, including a system status monitoring module, a CPU fault processing module, a log recording module, a fault information storage module, and a log recovery module.

[0155] The system status monitoring module is used to configure the FPGA UART baud rate and monitor the system status, the CPU fault handling module is used to detect CPU faults, the log recording module is used to classify and screen logs, the fault information storage module is used to classify fault information, and the log recovery module is used to take recovery measures according to the fault type and log information.

[0156] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk, etc. Various media that can store program codes.

[0157] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0158] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk case (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0159] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logical function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc. It should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and are not limited. Although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

[0160] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for rapidly improving CPU fault diagnosis based on FPGA, characterized in that: Including: Configuring the FPGA UART baud rate and monitoring the system status; After the CPU is powered on, it sends configuration instructions to the FPGA through the C_SPI0 interface to set the UART baud rate, ensuring that the FPGA correctly receives the serial data from the CPU; The FPGA monitors the watchdog signal from the CPU in real time. According to the signal interval, the FPGA evaluates the system status as normal, overloaded or faulty; Continue to judge according to the watchdog signal interval time; When the watchdog signal interval time is from 100 ms to 500 ms, the system will not be accidentally restarted under load, and will be restarted immediately when a system fault occurs; When the watchdog signal interval time is from 500 ms to 1 s, the system is processing high load or has minor performance problems, and warnings should be recorded and monitored for a continuous deterioration trend; When the watchdog signal interval time is more than 1 s or no watchdog signal is received, the system has crashed or failed. Immediately record the error, notify the administrator, and trigger a restart according to the system; If the watchdog signal interval time is less than 1 s, the dynamic interval for determining task priority is adjusted to low-priority tasks, and the low-priority tasks increase the watchdog signal interval; If the watchdog signal interval time is more than 1 s, the dynamic interval for determining task priority is adjusted to high-priority tasks, and the CPU and memory resources reserved by the system are used to ensure that the tasks run under load; After determining the watchdog signal interval time, it is passed to the system load adjustment, and the watchdog signal interval is adjusted according to the usage rates of CPU and memory resources; Perform dynamic UART baud rate configuration model and status monitoring. The UART baud rate B(t,x) depends on the time t and the physical location x of the transmission medium, the environmental noise N(t,x) and the signal attenuation A(t,x), and is expressed as: Where B represents the UART baud rate, which depends on the time t and the physical location x of the transmission medium. N represents the environmental noise function, indicating that the noise changes with time and location. A represents the signal attenuation function, describing the attenuation of the signal with time and location. α, β, γ, c represent material and environmental parameters. α represents the attenuation coefficient, β and γ represent the effects of adjusting signal attenuation and noise, c represents the propagation speed of the signal in the medium, δ(x) represents the local effect at location x, ω represents the spectrum of the signal passing through a specific point, and τ represents the past time point; When the CPU usage rate ≤ 30%, the system load is low, the watchdog signal interval time is increased by 100 ms, and the UART baud rate is dynamically adjusted. By monitoring the relationship between B(t,x) and the environmental noise N(t,x) and the signal attenuation A(t,x), the baud rate is automatically adjusted during data transmission; When 30% < CPU usage rate ≤ 70%, the system load is medium, and the watchdog signal interval time remains unchanged; When the CPU usage rate > 70%, the system load is high, the watchdog signal interval time is reduced by 100 ms. By combining the dynamically adjusted baud rate with the CPU usage rate and temperature status, the communication protocol is optimized through the control logic to reduce the system load. Based on the system stability and the number of faults in the past 24 hours, the watchdog signal interval is adjusted; Considering the system status, construct an evaluation model for fault type determination, which is expressed as: Among them, S represents the system state function, λ i ,ξ i , and η i is the adjustment parameter, Φ(·) represents the nonlinear action function, Θ(t,v) represents the impact of external factors on the system state, including CPU usage and system temperature, and v represents the system state vector When S indicates a fault and is determined to be in a stable state, the interval of the dog feeding signal increases by 50ms; When S indicates a fault and is judged as a general state, the interval of the dog feeding signal remains unchanged; When S indicates a fault and is judged to be unstable, the interval of feeding the dog signal is reduced by 50ms; Combined with the load and priority information, the high-priority tasks with a history of failures are further shortened in the high-load state to feed the dog signal interval and enter the system temperature indicator determination; When the temperature is ≤60℃, the system determines it as normal temperature and the interval of feeding the dog signal remains unchanged; When the temperature is 60℃<≤80℃, the system will issue a temperature warning and the interval of the dog feeding signal will be reduced by 50ms; When the temperature is >80℃, the system triggers a temperature danger and the dog feeding signal interval is reduced by 100ms; According to the interval of the dog feeding signal, the FPGA records the status indication and takes corresponding measures according to the set screening conditions, recording the system overload log or preparing for system restart; Analyze the fault type according to the fault log, handle CPU faults and record the log records; Save fault information and reset the system and logs.

2. The FPGA-based fast CPU fault diagnosis method according to claim 1, characterized in that: The method of analyzing the fault type according to the fault log, processing the CPU fault and recording the log record includes sending a coredump log to the FPGA through the UART port when the CPU encounters a jam or fault, stopping sending the dog feeding signal, and after the FPGA receives the log, classifying and storing it according to the log record level. After a fault occurs, the BRAM data is migrated to the SPIFLASH, and measures are taken according to the fault type analyzed according to the fault log.

3. The FPGA-based fast CPU fault diagnosis method according to claim 2, characterized in that: The processing of CPU faults and recording of log records according to the fault log analyzing the fault type includes monitoring the CPU status, capturing fault signals, and classifying the faults; If the CPU temperature exceeds 70°C or the CPU utilization exceeds 90% for five minutes, a detailed log will be recorded, including the time of occurrence, duration, and scope of impact, and the CPU power consumption will be adjusted to reduce the temperature; If the CPU temperature is not lower than 70°C after power consumption adjustment, the warning system is triggered; Logs are classified and scored according to the severity of the log content. The scores are output based on the frequency, type, and scope of impact of the error. If the log score is less than 50 points, the log is marked as information and stored; If 50 points < log score ≤ 75 points, analysis is performed. If a repeated pattern is found, the processing priority is upgraded and judgment is made based on the interval time of the dog feeding signal; If 75 points < log score ≤ 90 points, notify the system administrator and start the automatic diagnosis program; If the log score is > 90 points, the emergency response process is automatically triggered, and an attempt is made to restart the affected services and start the backup system; When the log score is greater than 50 points, the system is considered to have a fault, and the fault is classified based on the frequency of the fault and the difficulty of fault repair; A high-dimensional matrix model for fault log analysis is constructed, and the feature matrix F and the corresponding weight matrix W of the fault log are defined. The fault type is expressed as: Among them, G(t) represents the change of fault characteristics at different time points, κ is the attenuation constant, and S represents the fault score vector; The fault logs are analyzed by a high-dimensional matrix model, and faults are classified into information, warning, error, and emergency according to their severity, frequency, and impact range. If the fault is classified as information, routine recording and subsequent analysis will be performed without immediate notification; If the fault is classified as a warning, a fault report is generated, the technical support team is automatically notified, and the fault is highlighted in the system log; If the fault is classified as an error or emergency, the automatic fault recovery procedure will be started immediately. If the automatic recovery fails, the manual emergency handling process will be automatically started, and the backup system will be started to maintain the service. Perform fault archiving and preventive analysis based on fault frequency and repair time, and output the fault impact range and fault recurrence probability; If the number of affected users is less than 100 or the number of affected components is less than 5%, archive and store the logs and analyze them regularly. If the number of users affected is 100 to 1,000 or the number of components affected is 5% to 20%, archive and store the information, perform failure mode analysis, extract failure processing, and share solutions; If the number of affected users is >1000 or the number of components is >20%, archive the results and improvement measures, integrate them into the knowledge base, and conduct special training; The generated fault classification data and measures should be recorded and saved in the external SPIFLASH.

4. The FPGA-based fast CPU fault diagnosis method according to claim 3, characterized in that: The processing of CPU faults according to the fault log analysis fault type and recording log records include classifying faults based on the frequency of fault occurrence and the difficulty of fault repair, and outputting the fault impact range and the fault recurrence probability, resetting the WDG CTRL and the retrograde system, and saving the CPU state and log information in the BRAM before resetting, as well as the output results of the fault impact range and the fault recurrence probability; When the WDG CTRL module triggers a system reset, it classifies the faults based on the frequency of fault occurrence and the difficulty of fault repair, and outputs the fault impact range and fault recurrence probability; Before resetting, all CPU states and log information in the BRAM, including fault analysis data generated by outputting the fault impact range and fault recurrence probability, are saved.

5. The FPGA-based fast CPU fault diagnosis method according to claim 4, characterized in that: The storing of fault information and resetting of the system and log includes, after confirming the system fault, the WDG CTRL of the FPGA instructs the SPI FLASH to control the CPU state and the log information in the BRAM to be stored in the external SPI FLASH; After saving all information, WDG CTRL stops sending the dog feeding signal, causing the WATCHDOG chip to trigger a system reset and restart the CPU and FPGA; After the system restarts, the FPGA reads the fault information from the SPIFLASH and loads it into the CPU abnormal status register; The CPU queries the fault information through the C_SPI0 interface, takes recovery measures according to the fault type and log information, and restores the coredump information to the file system for analysis.

6. A system using the FPGA-based fast CPU fault diagnosis method as claimed in any one of claims 1 to 5, characterized in that: It includes system status monitoring module, CPU fault processing module, log recording module, fault information saving module and log recovery module; The system status monitoring module is used to configure the FPGA UART baud rate and monitor the system status; The CPU fault processing module is used to perform CPU fault detection; The log recording module is used to classify and screen logs; The fault information storage module is used to classify the fault information; The log recovery module is used to take recovery measures according to the fault type and log information.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the FPGA-based fast CPU fault diagnosis method described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the FPGA-based fast CPU fault diagnosis method described in any one of claims 1 to 5 are implemented.

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