A synchronous rectification chip circuit

Abstract

The present invention discloses a synchronous rectification chip circuit, which mainly solves the problems of high cost and multiple withstand voltage versions of synchronous rectification chips in the prior art. The circuit includes a synchronous rectification driving chip, a switch tube NH1 whose gate and drain are connected to the synchronous rectification driving chip, and a diode D7 whose positive electrode is connected to the drain of the switch tube NH1 and whose negative electrode is connected to the source of the switch tube; wherein the synchronous rectification driving chip also leads out a VIN pin to the output voltage VOUT end of the synchronous rectification chip circuit; the driving chip of the present invention is simple in design and low in cost, and synchronous rectification chips of different withstand voltage versions are realized by matching high-voltage transistors NH2 and switch tubes NH1 of different specifications, which greatly improves the application scope of the driving chip, reduces the resource allocation cost, and thus greatly reduces the cost of the switching power supply system.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a synchronous rectification chip circuit. Background Art

[0002] To improve efficiency, most existing switching power supplies have changed from Schottky diode rectification to transistor synchronous rectification. Synchronous switching MOS tubes replace rectifier diodes, which significantly reduces the rectification voltage drop and improves the efficiency of switching power supplies. However, switching MOS tubes require voltage drive, so how to properly draw power from the power system becomes a problem for synchronous rectification driver chips. Since the output power supply voltage may be low (3.3V output) and the output is short-circuited, the synchronous rectification driver chip needs to have a supply voltage independent of the output power supply voltage.

[0003] like Figure 1 As shown, most of the prior art draws power from the drain end D of the synchronous rectifier switch tube. The drain end D of the synchronous rectifier switch tube is also the output end of the output winding Ls of the transformer. When the primary main power tube is turned on, under the voltage coupling of the transformer, a high voltage will appear at the source and drain ends of the synchronous rectifier switch tube. Most of the prior art uses this voltage to charge the VCC capacitor C0 of the chip. In this way, the synchronous rectifier chip U2 has only 3 ports, and only one capacitor is required externally, and the application system is extremely simple. And the synchronous rectifier chip is not affected by the output voltage VOUT. However, this power supply solution has the problem of high cost. The reason is that due to the leakage inductance of the transformer, voltage spikes will appear at the source and drain ends of the synchronous rectifier switch tube, resulting in extremely high voltage requirements for the synchronous rectifier switch tube. Usually, when the output voltage VOUT is 20V, the drain-source voltage of the synchronous rectifier switch tube needs to be at least 120V.

[0004] The existing technology takes power from the drain end of the switch tube, which requires the driver chip to have a 120V high-voltage power bias and detection circuit, and requires a corresponding voltage-resistant ESD device. However, with the existing process technology, the higher the voltage, the larger the device area, the area of ​​the ESD device also increases proportionally, and the cost also increases accordingly. Therefore, the cost of existing synchronous rectifier chips is relatively high. In order to reduce the cost of some power supply systems with low voltage requirements, most synchronous rectifier chips adopt a variety of voltage-resistant versions. For example, a synchronous rectifier driver chip designed with a 60V voltage-resistant device is used in a switching power supply system with an output voltage of 12V or 9V, while a synchronous rectifier driver chip designed with a 120V voltage-resistant device is used in a switching power supply system with an output voltage of 20V. This will result in the need to produce multiple voltage-resistant versions of synchronous rectifier chips, and due to the long production time of chip wafers, they often need to be stocked. If the 60V voltage-resistant version is produced too much, but the market demand decreases, the demand for the 120V voltage-resistant version will increase instead. This will cause problems in resource allocation and indirectly increase system costs. Furthermore, if there is a demand for a higher output voltage, the circuit needs to be redesigned, further increasing costs.

[0005] like Figure 2 The figure shows a schematic diagram of a synchronous rectification power supply structure in the prior art. In the prior art, there are various synchronous rectification power supply technologies, but they can be summarized as follows: Figure 2 As shown. The driver chip U1 is usually sealed with the switch tube NH1 to form a synchronous rectifier chip U2. Since the design principle of the driver chip U1 is to take power from the drain end of the switch tube, the HVESD, HV bias detection module and internal high-voltage transistor NH2 of the driver chip U1 are all connected to the drain end of the switch tube NH1, and are uniformly connected to the D pin end of the synchronous rectifier chip. Among them, HVESD is the pin port ESD protection device of the driver chip U1. The HV bias detection module is responsible for obtaining the voltage bias from the D end when power is on, so that the driver chip can start working normally. The D-end voltage of the synchronous rectifier chip is a switching waveform, and power must be taken when the D end is at a high level. Therefore, the HV bias detection module also has a D-end voltage detection function. When the D-end voltage is detected to be high enough, the signal is output to the charge pump module and the processing drive module, and then the gate Vg of NH2 is controlled to output a high level to turn on the high-voltage transistor NH2. The current flows from the D end through the NH2 transistor, flows through the anti-backflow diode D3, and then charges the VCC capacitor. When the processing drive module detects that the VCC voltage is too high, the charge pump circuit is controlled to turn off the transistor NH2. The function of the anti-backflow diode D3 is to prevent the VCC current from backflowing to the D terminal when the voltage at the D terminal becomes low.

[0006] The prior art, as shown in patent CN109412436B, has N1 and N2 high-voltage transistors connected to the VD terminal. The first signal judgment module receives the judgment output of the VD chip and controls the capacitor bias unit to turn on the N1 and N2 high-voltage transistors after processing by the comparison unit. The first signal judgment module is equivalent to Figure 2 The HV bias detection module, the first and second comparison units are equivalent to the processing control module, and the first and second capacitor bias units are equivalent to the charge pump module. The patent describes the lack of a startup power supply. In theory, the bias voltage module needs to be connected to the VD terminal or the HVIN terminal, otherwise the chip cannot be powered on. Or as shown in patent CN117639526A, the high-voltage transistor N1 and the charge pump module 1 are connected to the VD terminal to output the low voltage vdla to the internal circuit for processing. The charge pump module 1 takes power from the VD terminal and is responsible for the switch control of the high-voltage transistor N1, which is equivalent to Figure 2 The HV bias detection and charge pump modules in the circuit. Transistor N1 needs to use a high-voltage device and port VD needs to use a high-voltage ESD protection device. Summary of the invention

[0007] The purpose of the present invention is to provide a synchronous rectifier chip circuit, which mainly solves the problems of high cost and multiple voltage-resistant versions of synchronous rectifier chips in the prior art.

[0008] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0009] A synchronous rectification chip circuit comprises a synchronous rectification driving chip, a switch tube NH1 whose gate and drain are connected to the synchronous rectification driving chip, and a diode D7 whose positive electrode is connected to the drain of the switch tube NH1 and whose negative electrode is connected to the source of the switch tube; wherein the synchronous rectification driving chip also leads a VIN pin to an output voltage VOUT end of the synchronous rectification chip circuit;

[0010] The synchronous rectification driving chip includes a charging management circuit, a power-on power-taking circuit and a detection and processing driving circuit connected to the charging management circuit, a voltage management circuit connected to the detection and processing driving circuit and the power-on power-taking circuit, and a charge pump connected to the voltage management circuit, the detection and processing driving circuit, the power-on power-taking circuit, and the charging management circuit; wherein the synchronous rectification driving chip leads out a VIN pin from the power-on power-taking circuit, leads out a same Vs pin from the power-on power-taking circuit, the charging management circuit, the voltage management circuit, the detection and processing driving circuit, and the charge pump, leads out a Vg pin from the charge pump, leads out a same GND pin from the power-on power-taking circuit, the voltage management circuit, the detection and processing driving circuit, leads out a same VCC pin from the power management circuit, the voltage management circuit, and the detection and processing driving circuit, and leads out a DRV pin from the detection and processing driving circuit; the gate of the switch tube NH1 is connected to the DRV pin, and the drain of the switch tube NH1 is connected to the Vg pin.

[0011] Furthermore, in the present invention, the power-on circuit includes a transistor P2 and a voltage stabilizing circuit; wherein the drain of the transistor P2 is connected to the voltage stabilizing circuit, and the source of the transistor P2 is connected to the charging management circuit and the charge pump; the gate of the transistor P2 is connected to the detection processing drive circuit; the drain of the transistor P2 is led to the VIN pin; and the other end of the voltage stabilizing circuit is led to the GND pin.

[0012] Further, in the present invention, the charging management circuit includes a power switching circuit connected to the source of the transistor P2, an operational amplifier U3 whose positive power supply end is connected to the power switching circuit, a voltage dividing resistor R1 and a voltage dividing resistor R2 connected to the positive input end of the operational amplifier U3, a voltage dividing resistor R3 and a voltage dividing resistor R4 connected to the negative input end of the operational amplifier U3, and a transistor P1 whose gate is connected to the output end of the operational amplifier U3; wherein, the source of the transistor P1 is connected to the other end of the voltage dividing resistor R3 and is led to the VCC pin; the drain of the transistor P1 is connected to the source of the transistor P2; the other end of the voltage dividing resistor R1 is connected to the source of the transistor P2; the other end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R4 and the negative power supply end of the operational amplifier U3 are led to the GND pin; the control end of the operational amplifier U3 is connected to the detection processing drive circuit.

[0013] Furthermore, in the present invention, the power-on power supply circuit includes a transistor N1, a transistor N2, a diode D1, a voltage regulator D2 and a resistor R5; wherein the gate of the transistor N1 is connected to the drain of the transistor N2, the positive electrode of the diode D1 is connected to the source of the transistor N1, and the negative electrode of the diode D1 is connected to the charging management circuit and the charge pump; the negative electrode of the voltage regulator D2 is connected to the gate of the transistor N1, the resistor R5 is connected between the drain and the gate of the transistor N1, the gate of the transistor N2 is connected to the detection processing drive circuit, and the drain of the transistor N1 is led to the VIN pin; the source of the transistor N2 and the positive electrode of the voltage regulator D2 are led to the GND pin.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The driver chip of the present invention is simple in design and low in cost. By matching high-voltage transistors NH2 and switch tubes NH1 of different specifications, synchronous rectification chips of different withstand voltage versions are realized, which greatly improves the application scope of the driver chip, reduces resource allocation costs, and thus greatly reduces the cost of the switching power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is an application diagram of a synchronous rectification system in the prior art.

[0017] Figure 2 This is a schematic diagram of the synchronous rectification power supply structure of the prior art.

[0018] Figure 3 This is an application diagram of the synchronous rectification system of Example 1 of the present invention.

[0019] Figure 4 This is a block diagram of a synchronous rectification driver chip according to Embodiment 1 of the present invention.

[0020] Figure 5 This is an application diagram of the synchronous rectification chip circuit of Example 1 of the present invention.

[0021] Figure 6 This is an application diagram of the synchronous rectification chip circuit of embodiment 2 of the present invention.

[0022] Figure 7 This is a switching cycle waveform diagram of a key signal in Example 1 of the present invention.

[0023] Figure 8 1 is a key signal waveform of the power-on process of Example 1 of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and embodiments. The embodiments of the present invention include but are not limited to the following embodiments.

[0025] Example 1

[0026] A synchronous rectification chip circuit disclosed in the present invention comprises a synchronous rectification driving chip, a switch tube NH1 whose gate and drain are connected to the synchronous rectification driving chip, and a diode D7 whose positive electrode is connected to the drain of the switch tube NH1 and whose negative electrode is connected to the source of the switch tube; wherein the synchronous rectification driving chip also leads out a VIN pin to an output voltage VOUT end of the synchronous rectification chip circuit.

[0027] The synchronous rectification driving chip includes a charging management circuit, a power-on power-taking circuit and a detection and processing driving circuit connected to the charging management circuit, a voltage management circuit connected to the detection and processing driving circuit and the power-on power-taking circuit, and a charge pump connected to the voltage management circuit, the detection and processing driving circuit, the power-on power-taking circuit, and the charging management circuit; wherein the synchronous rectification driving chip leads out a VIN pin from the power-on power-taking circuit, leads out a same Vs pin from the power-on power-taking circuit, the charging management circuit, the voltage management circuit, the detection and processing driving circuit, and the charge pump, leads out a Vg pin from the charge pump, leads out a same GND pin from the power-on power-taking circuit, the voltage management circuit, the detection and processing driving circuit, leads out a same VCC pin from the power management circuit, the voltage management circuit, and the detection and processing driving circuit, and leads out a DRV pin from the detection and processing driving circuit; the gate of the switch tube NH1 is connected to the DRV pin, and the drain of the switch tube NH1 is connected to the Vg pin.

[0028] In this embodiment, the power-on power supply circuit includes a transistor P2 and a voltage stabilizing circuit; wherein the drain of the transistor P2 is connected to the voltage stabilizing circuit, and the source of the transistor P2 is connected to the charging management circuit and the charge pump; the gate of the transistor P2 is connected to the detection processing drive circuit; the drain of the transistor P2 is led to the VIN pin; and the other end of the voltage stabilizing circuit is led to the GND pin.

[0029] In this embodiment, the charging management circuit includes a power switching circuit connected to the source of the transistor P2, an operational amplifier U3 whose positive power supply terminal is connected to the power switching circuit, a voltage-dividing resistor R1 and a voltage-dividing resistor R2 connected to the positive input terminal of the operational amplifier U3, a voltage-dividing resistor R3 and a voltage-dividing resistor R4 connected to the negative input terminal of the operational amplifier U3, and a transistor P1 whose gate is connected to the output terminal of the operational amplifier U3; wherein, the source of the transistor P1 is connected to the other end of the voltage-dividing resistor R3 and is led to the VCC pin; the drain of the transistor P1 is connected to the source of the transistor P2; the other end of the voltage-dividing resistor R1 is connected to the source of the transistor P2; the other end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R4 and the negative power supply terminal of the operational amplifier U3 are led to the GND pin; and the control end of the operational amplifier U3 is connected to the detection processing drive circuit.

[0030] like Figure 3As shown, when this embodiment is used, the VIN pin port is connected to the output voltage VOUT end of the application system through a resistor R9; at the same time, a transistor NH2 is connected to the Vg pin and the Vs pin, the gate of the transistor NH2 is connected to the Vg pin, and the source of the transistor NH2 is connected to the Vs pin. When the system is powered on, the synchronous rectification chip does not work, and the power supply VCC is at a low level. At this time, the switch tube NH1 remains in the off state, and only the parasitic diode D7 realizes the output rectification work. When the system is powered on, the transformer output winding Ls charges the output capacitor C1 through the diode D7, and the VOUT voltage gradually increases. The chip VCC capacitor is charged through the R9 resistor. After the VCC voltage reaches the working threshold of the synchronous rectification drive chip, the internal charging management circuit and the charge pump work, and the VCC voltage is charged high by taking power from the D terminal, and the switch tube NH1 is turned on when the synchronous rectification working threshold is reached.

[0031] like Figure 4 The block diagram of the synchronous rectification drive chip of the present invention is shown. It includes a power-on power-taking circuit, a charging management circuit, a voltage management circuit, a charge pump, and a detection and processing drive circuit. The power-on power-taking circuit is connected to the detection and processing drive circuit, the VIN pin of the chip, and the VHC node in the chip. The power-on power-taking circuit is controlled by the detection and processing drive circuit and is responsible for providing the VIN voltage to the VHC node when the chip is powered on. The VHC node is connected to the Vs pin of the chip, and the Vs pin voltage changes with the source voltage of the high-voltage transistor. The VHC node in the chip is also connected to the charging management circuit, the voltage management circuit, the charge pump, and the detection and processing drive circuit. The charging management circuit receives the VHC voltage and outputs it to the VCC pin, and is connected to the detection and processing drive circuit and controlled by it. The voltage management circuit is connected to the VCC, VHC nodes, the charge pump, and the detection and processing drive circuit, and is responsible for managing the size of the charge pump output voltage. The charge pump is connected to the detection and processing drive circuit and outputs to the Vg pin to drive the high-voltage transistor NH2 switch. The detection and processing drive circuit outputs the switch tube drive signal to the DRV pin. When the system is powered on, the power-on circuit charges the power supply VCC of the synchronous rectifier chip through the VHC node to realize the power-on function of the driver chip. The voltage management circuit, charge pump and high-voltage transistor NH2 are responsible for converting the drain voltage of the switch tube to the internal low voltage VHC. The voltage management circuit controls the internal low voltage VHC to charge the chip power supply voltage VCC. The detection and processing drive circuit and the switch tube NH1 realize the synchronous rectification function, and detect and control the VCC voltage to avoid the VCC voltage being too high. In actual application, the functions can be merged or split into different circuit combinations.

[0032] like Figure 5The figure shows the circuit diagram of the synchronous rectification driving chip of the present invention. The synchronous rectification driving chip has a total of 6 pins, including a startup power input VIN, a switch power supply control output Vg, a voltage input Vs, a chip power supply VCC, a switch tube drive control DRV and a ground GND. A synchronous rectification chip is obtained by sealing it in a package with a high-voltage transistor NH2 and a switch tube NH1. The startup power input VIN is connected to the voltage stabilizing circuit of the power-on power-taking circuit and the drain end of the transistor P2, the source end of the transistor P2 is connected to the VHC voltage end of the charging management circuit, and the gate of the transistor P2 is connected to the detection and processing driving circuit. When the detection and processing driving circuit detects that the system is in a switching waveform state, the P2 transistor is turned off, or the P2 transistor is turned off after the power-on is completed. The voltage stabilizing circuit controls the pull-down current, and limits the voltage at the VIN end through the R9 resistor of the external system to prevent the voltage at the VIN end from being too high.

[0033] When powered on, transistor P2 is turned on, VIN charges VHC, and the VHC voltage rises to charge VCC. The charging management circuit converts the VHC voltage into the chip's VCC voltage and is responsible for charging the VCC capacitor C0. The drain of transistor P1 is connected to the VHC voltage, the source is connected to the VCC voltage, and the gate is connected to the output of the operational amplifier U3. The voltage divider resistors R1 and R2 divide the VHC voltage, and the voltage divider output is connected to the negative input of the operational amplifier U3. The voltage divider resistors R3 and R4 divide the VCC voltage, and the voltage divider output is connected to the positive input of the operational amplifier U3. When the VHC voltage is higher than the VCC voltage by a set value, the output of the operational amplifier U3 controls the transistor P1 to turn on, and the VHC voltage charges the VCC voltage. When the VHC voltage is lower than the set value, the output of the operational amplifier U3 controls the transistor P1 to turn off, and the VHC voltage stops charging the VCC voltage. At the same time, the detection and processing drive circuit will detect the VCC voltage in real time. When the VCC voltage is too high, the output control turns off the operational amplifier U3, thereby turning off the transistor P1, and the VHC voltage stops charging the VCC voltage. The power switching circuit is responsible for outputting the higher voltage of the VHC voltage and the VCC voltage to the power supply terminal of the operational amplifier U3, so that the high level output by the operational amplifier U3 is always the highest of VHC and VCC, ensuring that the transistor P1 is completely turned off.

[0034] The voltage management circuit is connected to the power supply VCC, the VHC voltage terminal, the charge pump circuit and the detection processing drive circuit. The charge pump output voltage Vg is adjusted by detecting the VHC voltage. The Vg voltage controls its source terminal voltage Vs through the high-voltage transistor NH2, thereby controlling the VHC voltage to avoid excessive voltage.

[0035] In addition to detecting the VCC voltage to control the operational amplifier U3, the detection and processing driving circuit also detects the VHC voltage and the voltage at the DRV terminal of the switch tube gate. The detection and processing driving circuit is used to control the switch NH1 and the operation of the charge pump. The charge pump receives signals from the voltage management circuit and the detection and processing driving circuit, and is connected to the gate Vg and source terminal Vs / VHC of the high-voltage transistor NH2. When the voltage at the D terminal increases, the output Vg voltage is higher than the VCC voltage, so that the NH2 transistor is turned on, the VHC voltage is increased, and then the transistor P2 is controlled to turn on through the operational amplifier U3 to charge VCC.

[0036] like Figure 7 The waveform of a switching cycle of the key signal in this embodiment is shown as follows. Drain is the waveform of the primary main switch tube, D is the waveform of the D end of the synchronous rectifier chip, and the VHC waveform in the driver chip is as follows: Figure 7 As shown in the solid line waveform, the VCC waveform is as follows Figure 7 As shown in the dotted waveform, it can be seen that when the main switch is turned on, the Drain voltage is pulled down, and due to the effect of the transformer, the voltage at the D end of the synchronous rectifier chip becomes higher. When the detection and processing drive module of the synchronous rectifier chip detects that the voltage at the D end rises, the charge pump is started to turn on the high-voltage transistor NH2, as shown in Figure 1. Figure 7 At t0. When the VHC voltage rises and is higher than the VCC voltage by a set value, the charging management module of the driver chip works to charge VCC, and the VCC voltage rises. Figure 7 The t0-t1 time period. When the main switch is turned off, the Drain voltage increases. Due to the effect of the transformer, the voltage at the D terminal of the synchronous rectifier chip becomes lower. At this time, the high-voltage transistor NH2 of the synchronous rectifier driver chip is still turned on, and the VHC voltage will follow the D terminal voltage to decrease. At this time, the synchronous rectifier driver chip will turn on the switch NH1 to realize the synchronous rectification function, which will consume VCC, and the VCC voltage will decrease slightly. Figure 7 In this way, when the voltage at the D terminal increases, the VHC voltage increases accordingly. When it is higher than the VCC voltage by a set value, VCC is charged. When it is not higher than the VCC set value, it is not charged. Figure 7 The t2-8 time period.

[0037] like Figure 8The key signal waveforms of the power-on process in this embodiment are shown. The VOUT waveform is the power output waveform of the power system, the D waveform is a simplified waveform diagram of the synchronous rectifier D terminal, and the VCC waveform is the waveform of the synchronous rectifier chip VCC. When the system is powered on, the VOUT voltage gradually increases, the synchronous rectifier chip draws power through the VIN pin or the D terminal pin, and the chip VCC voltage gradually rises following VOUT. When the chip VCC pin voltage rises to a certain threshold, the charging management circuit starts working, the charge pump drives the high-voltage transistor to turn on, and the VCC voltage gradually increases. When the VCC voltage reaches the set value, the charging management module controls to stop charging. Each time the switch VCC is only charged for a short period of time to supplement the voltage dropped when the switch is working, so that the VCC voltage remains balanced.

[0038] Example 2

[0039] like Figure 6 As shown, the difference between this embodiment and Example 1 is that the power-on power-taking circuit includes a transistor N1, a transistor N2, a diode D1, a voltage regulator D2 and a resistor R5; wherein the gate of the transistor N1 is connected to the drain of the transistor N2, the positive electrode of the diode D1 is connected to the source of the transistor N1, and the negative electrode of the diode D1 is connected to the charging management circuit and the charge pump; the negative electrode of the voltage regulator D2 is connected to the gate of the transistor N1, the resistor R5 is connected between the drain and the gate of the transistor N1, the gate of the transistor N2 is connected to the detection and processing drive circuit, and the drain of the transistor N1 is led to the VIN pin; the source of the transistor N2 and the positive electrode of the voltage regulator D2 are led to the GND pin. In this embodiment, the VIN end uses a medium-voltage-resistant transistor N1, which can withstand the output voltage of the power supply system, such as 20V. Therefore, the ESD of the VIN port needs to be adjusted from an ordinary voltage-resistant ESD to a medium-voltage ESD device, such as Figure 6 MV ESD module in. The medium voltage ESD area is relatively large, and it does not have a specific circuit function here. It is listed to illustrate the cost change of this solution. When the power system output voltage is powered on, the VIN voltage rises, and the medium voltage transistor N1 is turned on through the resistor R5. The transistor N1 outputs the VIN voltage to the positive electrode of the diode D1, and outputs it from the negative electrode of the diode D1 to the VHC voltage to charge the VCC voltage. The diode D1 plays a role in preventing backflow. Because there is a short circuit in the system power supply, VIN will appear at a low level. At this time, it is necessary to prevent the chip VCC voltage from backflowing to the VIN end through the transistor N1. The gate of the transistor N2 is connected to the detection and processing drive circuit, and the drain end is connected to the gate of the transistor N1. When the detection and processing drive circuit detects that the system is in a switching waveform state, the N2 transistor is turned on to pull down the gate voltage of the N1 transistor to turn off the N1 transistor, or the N2 transistor is turned on and the N1 transistor is turned off after the power-on is completed.

[0040] The above embodiment is only one of the preferred implementation modes of the present invention and should not be used to limit the protection scope of the present invention. Any changes or modifications that are made to the main design concept and spirit of the present invention and have no substantive significance, and the technical problems they solve are still consistent with the present invention, should be included in the protection scope of the present invention.

Claims

1. A synchronous rectification chip circuit, characterized in that: It includes a synchronous rectification driving chip, a switch tube NH1 whose gate and drain are connected to the synchronous rectification driving chip, a switch tube NH2 whose drain is connected to the drain of the switch tube NH1 and whose source and gate are both connected to the synchronous rectification driving chip, and a diode D7 whose cathode is connected to the drain of the switch tube NH1 and whose anode is connected to the source of the switch tube NH1; wherein the synchronous rectification driving chip also leads an input VIN pin to an output voltage VOUT end of the synchronous rectification chip circuit; The synchronous rectification driving chip includes a charging management circuit, a power-on power-taking circuit and a detection and processing driving circuit connected to the charging management circuit, a voltage management circuit connected to the detection and processing driving circuit and the power-on power-taking circuit, and a charge pump connected to the voltage management circuit, the detection and processing driving circuit, the power-on power-taking circuit, and the charging management circuit; wherein the synchronous rectification driving chip leads out a VIN pin from the power-on power-taking circuit, leads out a same source voltage Vs pin from the power-on power-taking circuit, the charging management circuit, the voltage management circuit, the detection and processing driving circuit, and the charge pump, leads out a gate voltage Vg pin from the charge pump, leads out a same ground GND pin from the power-on power-taking circuit and the voltage management circuit detection and processing driving circuit, leads out a same power supply VCC pin from the charging management circuit, the voltage management circuit, and the detection and processing driving circuit, and leads out a drive DRV pin from the detection and processing driving circuit; the gate of the switch tube NH1 is connected to the drive DRV pin, the gate of the switch tube NH2 is connected to the gate voltage Vg pin, and the source of the switch tube NH2 is connected to the source voltage Vs pin; The power-on circuit includes a transistor P2 and a voltage stabilizing circuit; wherein the drain of the transistor P2 is connected to one end of the voltage stabilizing circuit, and the source of the transistor P2 is connected to the charging management circuit and the charge pump; the gate of the transistor P2 is connected to the detection processing drive circuit; the drain of the transistor P2 is led to the input VIN pin; the other end of the voltage stabilizing circuit is led to the ground GND pin; The charging management circuit includes a power switching circuit connected to the source of the transistor P2, an operational amplifier U3 whose positive power supply terminal is connected to the power switching circuit, a voltage-dividing resistor R1 and a voltage-dividing resistor R2 whose one ends are connected to the positive input terminal of the operational amplifier U3, a voltage-dividing resistor R3 and a voltage-dividing resistor R4 whose one ends are connected to the negative input terminal of the operational amplifier U3, and a transistor P1 whose gate is connected to the output terminal of the operational amplifier U3; wherein the source of the transistor P1 is connected to the other end of the voltage-dividing resistor R3 and is led to the power supply VCC pin; the drain of the transistor P1 is connected to the source of the transistor P2; the other end of the voltage-dividing resistor R1 is connected to the source of the transistor P2; the other end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R4 and the negative power supply terminal of the operational amplifier U3 are led to the ground GND pin; the control end of the operational amplifier U3 is connected to the detection processing drive circuit; the drain of the transistor P1 is led to the source voltage Vs pin; Alternatively, the power-on power supply circuit includes a transistor N1, a transistor N2, a diode D1, a voltage regulator D2 and a resistor R5; wherein the gate of the transistor N1 is connected to the drain of the transistor N2, the positive electrode of the diode D1 is connected to the source of the transistor N1, and the negative electrode of the diode D1 is connected to the charging management circuit and the charge pump; the negative electrode of the voltage regulator D2 is connected to the gate of the transistor N1, the resistor R5 is connected between the drain and the gate of the transistor N1, the gate of the transistor N2 is connected to the detection and processing drive circuit, and the drain of the transistor N1 is led to the VIN pin; the source of the transistor N2 and the positive electrode of the voltage regulator D2 are led to the ground GND pin.

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