Square wave generating circuit and electronic equipment

Abstract

A square wave generating circuit and electronic device, belonging to the technical field of power supply, wherein a square wave inverter circuit inverts a first DC power connected to output an output square wave; a current detection circuit detects the current of the output square wave to output a current sampling signal; a control circuit outputs an adjustment voltage according to the current sampling signal; a pulse width adjustment circuit outputs a driving signal based on a triangular wave pulse and an adjustment voltage; and the square wave inverter circuit is further configured to invert the first DC power based on the driving signal to output an output square wave. The pulse width adjustment circuit outputs a driving signal based on a triangular wave pulse and an adjustment voltage, realizes real-time dynamic adjustment of the output square wave, improves the flexibility of the square wave generating circuit, and at the same time reduces the risk of arc instability after the plasma power supply starts arcing, improves the stability of the arc, and when applied to a plasma knife, reduces the risk of tissue carbonization and improves safety.

Description

Technical Field

[0001] The present application belongs to the technical field of power supply, and in particular, relates to a square wave generating circuit and an electronic device. Background Art

[0002] Plasma is generally generated by plasma power supply and reactor. Due to its advantages such as strong oxidizing property and chemical activity, plasma is increasingly used in the medical field. Plasma power supply often includes microwave, radio frequency and square wave. Square wave plasma power supply is the power supply used in many medical fields because of its richer frequency content.

[0003] The plasma cutter head is a good conductor of electricity and directly contacts human tissue. The existing plasma power supply is unstable after arcing and the power is not adjustable. There is a risk of arc breaking during tissue cutting. The tissue contacted by the plasma cutter head is at risk of carbonization, and the safety is low.

[0004] Therefore, there is an urgent need for a square wave generating circuit with high safety and flexibility. Summary of the invention

[0005] The purpose of the present application is to provide a square wave generating circuit and electronic equipment, aiming to solve the problems of low safety and flexibility of existing plasma power supplies.

[0006] The present application embodiment provides a square wave generating circuit, comprising:

[0007] A square wave inverter circuit is configured to receive a first direct current and invert the first direct current to output an output square wave;

[0008] A current detection circuit, connected to the square wave inverter circuit, configured to detect the current of the output square wave to output a current sampling signal;

[0009] a control circuit connected to the current detection circuit and configured to output a regulating voltage according to the current sampling signal;

[0010] a pulse width adjustment circuit connected to the control circuit and the square wave inverter circuit and configured to output a driving signal based on a triangular wave pulse and the adjustment voltage;

[0011] The square wave inverter circuit is further configured to invert the first direct current based on the driving signal to output the output square wave.

[0012] In one embodiment, the square wave generating circuit further includes:

[0013] The voltage-controlled DC power supply circuit is configured to receive an input voltage and convert the input voltage to output the first DC power.

[0014] In one embodiment, the square wave generating circuit further includes:

[0015] an isolation conversion circuit, connected to the square wave inverter circuit and the current detection circuit, and configured to isolate and convert the output square wave;

[0016] The current detection circuit is specifically configured to detect the current of the output square wave after isolation and conversion to output a current sampling signal.

[0017] In one embodiment, the square wave generating circuit further includes:

[0018] a reference circuit, connected to the pulse width adjustment circuit, and configured to output the triangular wave pulse based on a reference pulse;

[0019] The amplitude of the triangular wave pulse is constant and has the same frequency as the reference pulse.

[0020] In one embodiment, the reference circuit comprises:

[0021] a signal shaping circuit connected to the control circuit and configured to output a frequency signal based on the reference pulse; wherein the amplitude of the frequency signal is constant and has the same frequency as the reference pulse;

[0022] a gain adjustment circuit connected to the signal shaping circuit and configured to convert the frequency signal into a voltage signal; the voltage of the voltage signal is positively correlated with the frequency of the frequency signal;

[0023] The integration circuit is connected to the signal shaping circuit, the gain adjustment circuit and the pulse width adjustment circuit, and is configured to integrate the frequency signal and amplify the integrated frequency signal based on the voltage signal to output the triangular wave pulse; the amplification factor is positively correlated with the voltage of the voltage signal.

[0024] In one embodiment, the signal shaping circuit includes a D flip-flop, a third diode, a first resistor, a second resistor and an eighth capacitor;

[0025] The clock input terminal of the D flip-flop serves as the reference pulse input terminal of the signal shaping circuit to input the reference pulse; the clear terminal of the D flip-flop is connected to the first terminal of the eighth capacitor, the reverse output terminal of the D flip-flop is connected to the positive electrode of the third diode and the first terminal of the first resistor, the negative electrode of the third diode is connected to the first terminal of the second resistor, the output terminal of the D flip-flop serves as the frequency signal output terminal of the signal shaping circuit, and is connected to the gain adjustment circuit to output the frequency signal; the preset terminal of the D flip-flop and the input terminal of the D flip-flop are commonly connected to the first power supply; the second terminal of the eighth capacitor, the second terminal of the first resistor and the second terminal of the second resistor are commonly connected to the power ground.

[0026] In one embodiment, the gain adjustment circuit includes a frequency-to-voltage converter, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, and a second capacitor;

[0027] The first end of the fourth resistor serves as the frequency signal input end of the gain adjustment circuit and is connected to the signal shaping circuit to input the frequency signal; the second end of the fourth resistor is connected to the positive input signal end of the frequency-to-voltage converter, the first capacitor connection end of the voltage converter is connected to the first end of the second capacitor, the second capacitor connection end of the voltage converter is connected to the first end of the third resistor and the first end of the first capacitor, the inverting input end of the voltage converter, the emitter of the voltage converter and the first end of the fifth resistor serve together as the voltage signal output end of the gain adjustment circuit and are connected to the integration circuit to output the voltage signal; the collector of the voltage converter is connected to the first power supply; the second end of the second capacitor, the second end of the third resistor, the second end of the first capacitor and the second end of the fifth resistor are commonly connected to the power ground.

[0028] In one embodiment, the integration circuit includes a first amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and a third capacitor;

[0029] The first end of the sixth resistor is used as the frequency signal input end of the integration circuit and is connected to the signal shaping circuit to input the frequency signal; the first end of the tenth resistor is used as the voltage signal input end of the integration circuit and is connected to the gain adjustment circuit to input the voltage signal; the second end of the sixth resistor is connected to the A channel positive phase input end of the first amplifier, the A channel negative phase input end of the first amplifier is connected to the first end of the seventh resistor and the first end of the third capacitor, the A channel output end of the first amplifier is connected to the B channel positive phase input end of the first amplifier and the second end of the third capacitor, the B channel negative phase input end of the first amplifier is connected to the second end of the tenth resistor, the first end of the eighth resistor and the first end of the ninth resistor, the B channel output end of the first amplifier and the second end of the eighth resistor are commonly used as the triangular wave pulse output end of the integration circuit and are connected to the pulse width adjustment circuit to output the triangular wave pulse; the second end of the seventh resistor and the second end of the ninth resistor are commonly connected to the power ground.

[0030] In one embodiment, the current detection circuit includes:

[0031] A voltage transformation circuit, connected to the square wave inverter circuit, configured to transform the output square wave to output a first square wave;

[0032] a preprocessing circuit, connected to the voltage transformation circuit, and configured to adjust the amplitude of the first square wave to output a second square wave;

[0033] a rectifier circuit, connected to the preprocessing circuit, configured to rectify the second square wave to output a DC square wave pulse;

[0034] a pulse width compensation circuit, connected to the rectifier circuit and the control circuit, and configured to perform voltage compensation on the DC square wave pulse to output the current sampling signal;

[0035] The current sampling signal is direct current and has the same amplitude as the direct current square wave pulse.

[0036] In one of the embodiments, the voltage transformation circuit includes a first current transformer, an eleventh resistor and a fourth capacitor;

[0037] The first input end of the first current transformer serves as the output square wave input end of the transformer circuit, and is connected to the square wave inverter circuit to input the output square wave; the second input end of the first current transformer, the first end of the eleventh resistor, and the first end of the fourth capacitor are commonly connected to the signal ground; the first output end of the first current transformer serves as the output square wave output end of the transformer circuit to output the output square wave; the second output end of the first current transformer, the second end of the eleventh resistor, and the second end of the fourth capacitor serve as the first square wave output end of the transformer circuit, and are connected to the preprocessing circuit to output the first square wave.

[0038] In one embodiment, the pre-processing circuit includes a second operational amplifier, a twelfth resistor and a thirteenth resistor;

[0039] The non-phase input terminal of the second operational amplifier serves as the first square wave input terminal of the pre-processing circuit and is connected to the voltage transformer circuit to input the first square wave; the inverting input terminal of the second operational amplifier is connected to the first end of the twelfth resistor and the first end of the thirteenth resistor, the output terminal of the second operational amplifier and the second end of the twelfth resistor jointly serve as the second square wave output terminal of the pre-processing circuit and are connected to the rectifier circuit to output the second square wave; the second end of the thirteenth resistor is connected to the signal ground.

[0040] In one embodiment, the rectifier circuit includes a third operational amplifier, a first diode, a second diode, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a twentieth resistor;

[0041] The first end of the sixteenth resistor and the first end of the seventeenth resistor are jointly used as the second square wave input end of the rectifier circuit, and are connected to the preprocessing circuit to input the second square wave; the second end of the sixteenth resistor is connected to the first end of the eighteenth resistor, the cathode of the second diode and the A channel inverting input end of the third operational amplifier, the second end of the eighteenth resistor is connected to the anode of the first diode and the first end of the nineteenth resistor, the B channel inverting input end of the third operational amplifier is connected to the second end of the seventeenth resistor, the second end of the nineteenth resistor and the first end of the twentieth resistor, the A channel output end of the third operational amplifier is connected to the anode of the second diode and the cathode of the first diode, the second end of the twentieth resistor and the B channel output end of the third operational amplifier are jointly used as the DC square wave pulse output end of the rectifier circuit, and are connected to the pulse width compensation circuit to output the DC square wave pulse; the A channel positive input end of the third operational amplifier and the B channel positive input end of the third operational amplifier are jointly connected to the signal ground.

[0042] In one embodiment, the pulse width compensation circuit includes a first comparator, a fourth operational amplifier, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor and a fifth capacitor;

[0043] The positive phase input terminal of the first comparator and the first end of the twenty-first resistor are jointly used as the DC square wave pulse input terminal of the pulse width compensation circuit, and are connected to the rectifier circuit to input the DC square wave pulse; the inverting input terminal of the first comparator is connected to the first end of the thirty-third resistor and the first end of the thirty-fourth resistor, the output terminal of the first comparator is connected to the first end of the twenty-second resistor, the second end of the twenty-second resistor is connected to the A channel positive phase input terminal of the fourth operational amplifier, the A channel output terminal of the fourth operational amplifier is connected to the first end of the twenty-seventh resistor and the first end of the twenty-third resistor, the A channel inverting input terminal of the fourth operational amplifier is connected to the second end of the twenty-third resistor and the first end of the twenty-fourth resistor, and the B channel of the fourth operational amplifier is connected to the first end of the twenty-second resistor. The inverting input terminal of the channel of the fourth operational amplifier is connected to the second end of the twenty-seventh resistor, the first end of the twenty-fifth resistor and the first end of the twenty-sixth resistor, the non-inverting input terminal of the B channel of the fourth operational amplifier is connected to the second end of the twenty-first resistor, the first end of the thirty-fifth resistor and the first end of the fifth capacitor, the second end of the twenty-sixth resistor and the B channel output terminal of the fourth operational amplifier are jointly used as the current sampling signal output terminal of the pulse width compensation circuit, and are connected to the control circuit to output the current sampling signal; the second end of the thirty-third resistor is connected to the second power supply, the second end of the twenty-fifth resistor is connected to the third power supply, and the second end of the thirty-fifth resistor, the second end of the fifth capacitor, the second end of the thirty-fourth resistor and the second end of the twenty-fourth resistor are jointly connected to the signal ground.

[0044] In one of the embodiments, the driving signal includes a first driving signal and a second driving signal;

[0045] The pulse width adjustment circuit comprises:

[0046] a clamping circuit connected to the control circuit and configured to output a first reference voltage and a second reference voltage based on the regulated voltage; the first reference voltage is positively correlated with the regulated voltage and an upper limit of the first reference voltage is clamped, and the second reference voltage is negatively correlated with the regulated voltage and a lower limit of the second reference voltage is clamped;

[0047] A comparison circuit is connected to the clamp circuit and the square wave inverter circuit, and is configured to compare the first reference voltage and the triangular wave pulse to output the first drive signal, and to compare the second reference voltage and the triangular wave pulse to output the second drive signal.

[0048] In one embodiment, the clamping circuit includes a fifth operational amplifier, a fourteenth resistor, a fifteenth resistor, a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor, a thirty-sixth resistor, a thirty-seventh resistor, and a sixth capacitor;

[0049] The first end of the fifteenth resistor is used as the adjustment voltage input end of the clamp circuit and is connected to the control circuit to input the adjustment voltage; the A channel positive input end of the fifth operational amplifier is connected to the second end of the fifteenth resistor, the A channel inverting input end of the fifth operational amplifier is connected to the first end of the fourteenth resistor, the first end of the thirty-third resistor and the first end of the sixth capacitor, the A channel output end of the fifth operational amplifier and the second end of the thirty-third resistor, the second end of the sixth capacitor and the first end of the thirty-fifth resistor are used together as the first reference voltage output end of the clamp circuit and are connected to the comparison circuit to output the reference voltage. The first reference voltage is outputted from the clamp circuit; the B channel inverting input terminal of the fifth operational amplifier is connected to the second end of the thirty-fifth resistor and the first end of the thirty-fourth resistor, the B channel output terminal of the fifth operational amplifier and the second end of the thirty-fourth resistor are jointly used as the second reference voltage output terminal of the clamp circuit, and are connected to the comparison circuit to output the second reference voltage; the B channel non-inverting input terminal of the fifth operational amplifier is connected to the first end of the thirty-sixth resistor and the first end of the thirty-seventh resistor, the second end of the thirty-seventh resistor is connected to the first power supply, and the second end of the fourteenth resistor and the second end of the thirty-sixth resistor are jointly connected to the power ground.

[0050] In one embodiment, the comparison circuit includes a second comparator, a thirty-eighth resistor, a thirty-ninth resistor, a fortieth resistor, a forty-first resistor, a forty-second resistor, and a seventh capacitor;

[0051] The B channel positive phase input terminal of the second comparator and the first end of the thirty-ninth resistor are jointly used as the first reference voltage input terminal of the comparison circuit, and are connected to the clamp circuit to input the first reference voltage; the A channel negative phase input terminal of the second comparator and the first end of the thirty-eighth resistor are jointly used as the second reference voltage input terminal of the comparison circuit, and are connected to the clamp circuit to input the second reference voltage; the A channel positive phase input terminal of the second comparator and the B channel negative phase input terminal of the second comparator, the first end of the fortieth resistor, the first end of the forty-second resistor and the first end of the seventh capacitor are connected, and the first end of the forty-first resistor is connected to the first end of the forty-eighth resistor. The second ends of the seven capacitors are commonly used as the triangular wave pulse input end of the comparison circuit to input the triangular wave pulse; the A channel output end of the second comparator is used as the second drive signal output end of the comparison circuit, connected to the square wave inverter circuit to output the second drive signal; the B channel output end of the second comparator is used as the first drive signal output end of the comparison circuit, connected to the square wave inverter circuit to output the first drive signal; the second end of the thirty-eighth resistor and the second end of the forty-second resistor are commonly connected to the first power supply; the second end of the thirty-ninth resistor, the second end of the fortieth resistor and the second end of the forty-first resistor are commonly connected to the power ground.

[0052] In one embodiment, the control circuit includes a digital signal controller, a digital-to-analog converter, a sixth operational amplifier, an optical isolation amplifier, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor, a thirty-second resistor, and a second capacitor;

[0053] The first input and output terminal of the digital signal controller is connected to the chip selection terminal of the digital-to-analog converter, the second input and output terminal of the digital signal controller is connected to the digital serial clock input terminal of the digital-to-analog converter, the third input and output terminal of the digital signal controller is connected to the digital serial data input terminal of the digital-to-analog converter, the analog voltage output terminal of the group B of the digital-to-analog converter serves as the adjustment voltage output terminal of the control circuit, and is connected to the pulse width adjustment circuit to output the adjustment voltage; the fourth input and output terminal of the digital signal controller is connected to the output terminal of the sixth operational amplifier and the first end of the thirty-second resistor, the non-inverting input terminal of the sixth operational amplifier is connected to the first end of the twenty-ninth resistor and the first end of the thirty-first resistor The inverting input terminal of the sixth operational amplifier is connected to the second end of the thirty-second resistor and the first end of the thirtieth resistor, the second end of the thirtieth resistor is connected to the negative output terminal of the optical isolation amplifier, the second end of the twenty-ninth resistor is connected to the positive output terminal of the optical isolation amplifier, the non-inverting input terminal of the optical isolation amplifier is connected to the first end of the twenty-eighth resistor and the first end of the second capacitor, the second end of the twenty-eighth resistor serves as the current sampling signal input terminal of the control circuit, and is connected to the current detection circuit to input the current sampling signal; the second end of the thirty-first resistor is connected to the power ground, and the inverting input terminal of the optical isolation amplifier and the second end of the second capacitor are commonly connected to the signal ground.

[0054] An embodiment of the present application further provides an electronic device, which includes the above-mentioned square wave generating circuit.

[0055] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the pulse width adjustment circuit outputs a driving signal based on a triangular wave pulse and an adjustment voltage, and since the corresponding triangular wave pulse can be input according to demand, real-time dynamic adjustment of the output square wave is achieved, thereby improving the flexibility of the square wave generating circuit; at the same time, a current feedback loop for the output square wave is established, which reduces the risk of arc instability after the plasma power supply starts the arc, improves the stability of the arc, and when applied to a plasma knife, reduces the risk of tissue carbonization and improves safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical application in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 A schematic diagram of a square wave generating circuit provided in one embodiment of the present application;

[0058] Figure 2 Another structural schematic diagram of a square wave generating circuit provided in an embodiment of the present application;

[0059] Figure 3 Another structural schematic diagram of a square wave generating circuit provided in an embodiment of the present application;

[0060] Figure 4 A schematic diagram of the structure of a high-frequency isolation transformer provided in one embodiment of the present application;

[0061] Figure 5 Another structural schematic diagram of a square wave generating circuit provided in an embodiment of the present application;

[0062] Figure 6 Another structural schematic diagram of a square wave generating circuit provided in an embodiment of the present application;

[0063] Figure 7 Another structural schematic diagram of a square wave generating circuit provided in an embodiment of the present application;

[0064] Figure 8 Another structural schematic diagram of a square wave generating circuit provided in an embodiment of the present application;

[0065] Fig. 9 A partial exemplary circuit schematic diagram of a square wave generating circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0067] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0068] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0069] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0070] Figure 1 The structural diagram of the square wave generating circuit provided in one embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0071] The square wave generating circuit includes a square wave inverter circuit 100 , a current detection circuit 200 , a control circuit 300 and a pulse width adjustment circuit 400 .

[0072] The square wave inverter circuit 100 is configured to receive a first direct current and invert the first direct current to output an output square wave.

[0073] The current detection circuit 200 is connected to the square wave inverter circuit 100 and is configured to detect the current of the output square wave to output a current sampling signal.

[0074] The control circuit 300 is connected to the current detection circuit 200 and is configured to output a regulating voltage according to the current sampling signal.

[0075] The pulse width adjustment circuit 400 is connected to the control circuit 300 and the square wave inverter circuit 100, and is configured to output a driving signal based on a triangular wave pulse and a regulation voltage.

[0076] The square wave inverter circuit 100 is further configured to invert the first direct current based on the driving signal to output an output square wave.

[0077] The pulse width adjustment circuit 400 may be a linear circuit, and its control accuracy is only related to the resolution of the digital-to-analog conversion module in the control circuit 300 .

[0078] The pulse width adjustment circuit 400 outputs a driving signal based on a triangular wave pulse and an adjustment voltage, thereby realizing real-time dynamic adjustment of the output square wave, reducing the risk of arc instability after the plasma power supply starts the arc, realizing arc stability at a relatively low average power, reducing tissue heating, reducing the risk of tissue carbonization, and improving the safety of the circuit.

[0079] By way of example and not limitation, Figure 2 As shown, the square wave generating circuit also includes a voltage-controlled DC power supply circuit 500 .

[0080] The voltage-controlled DC power supply circuit 500 is configured to receive an input voltage and convert the input voltage to output a first DC power.

[0081] The voltage-controlled DC power supply circuit 500 is used to achieve rapid regulation of the first DC voltage between zero and the maximum design voltage, thereby satisfying the requirement for rapid switching between the high voltage of electrocuting and the low voltage of electrocoagulation.

[0082] By way of example and not limitation, Figure 3 As shown, the square wave generating circuit further includes an isolation conversion circuit 600 .

[0083] The isolation conversion circuit 600 is connected to the square wave inverter circuit 100 and the current detection circuit 200 and is configured to isolate and convert the output square wave;

[0084] The current detection circuit 200 is specifically configured to detect the current of the output square wave after isolation and conversion to output a current sampling signal.

[0085] In a specific implementation, the isolation conversion circuit 600 may include a high-frequency isolation transformer.

[0086] The leakage inductance of the transformer affects the coupling degree between the primary and secondary sides of the transformer, restricting the energy transmission between the primary and secondary sides in the power circuit. In severe cases, it will form a spike voltage in the circuit, affecting the safe operation of the circuit. After selecting the core material and structure, the installation and winding form of the transformer winding and the air gap of the core are the main sources of the transformer leakage inductance.

[0087] For this, Figure 4 As shown, the high-frequency isolation transformer in the present application may include a primary winding, a secondary winding and a shielding layer, and may also include a balanced winding 1 and a balanced winding 2. The balanced winding 1 and the balanced winding 2 are two sets of windings with the same parameters and connected in series. When the primary winding and the secondary winding are not coupled tightly enough, a large leakage flux will be generated. At this time, the magnetic flux passing through the two side arms of the magnetic core is not equal. The balanced winding 1 and the balanced winding 2 will generate the same or opposite magnetic flux through the unbalanced magnetic flux, thereby strengthening or offsetting the unbalanced magnetic flux, achieving the purpose of reducing the leakage magnetic flux, thereby constraining the leakage magnetic flux, and effectively reducing the high voltage isolation between the primary winding and the secondary winding and the transformer leakage inductance.

[0088] Using high-frequency transformers to replace traditional dedicated industrial frequency transformers can meet the safety standards for medical electrical equipment, and is small in size, low in cost and high in reliability.

[0089] By way of example and not limitation, Figure 5 As shown, the square wave generating circuit further includes a reference circuit 700 .

[0090] The reference circuit 700 is connected to the control circuit 300 and the pulse width adjustment circuit 400 , and is configured to output a triangular wave pulse based on a reference pulse.

[0091] The amplitude of the triangular wave pulse is constant and has the same frequency as the reference pulse.

[0092] In a specific implementation, the reference pulse may be generated by the control circuit 300 .

[0093] The reference pulse is converted into a triangular wave pulse that can be directly connected to the pulse width adjustment circuit 400 through the reference circuit 700, and the triangular wave pulse has the same frequency as the reference pulse, so that the frequency of the triangular wave pulse is adjustable and the flexibility of the square wave generating circuit is improved.

[0094] By way of example and not limitation, Figure 6 As shown, the reference circuit 700 includes a signal shaping circuit 710 , a gain adjustment circuit 720 , and an integration circuit 730 .

[0095] The signal shaping circuit 710 is connected to the control circuit 300 and is configured to output a frequency signal based on a reference pulse; wherein the amplitude of the frequency signal is constant and has the same frequency as the reference pulse.

[0096] The gain adjustment circuit 720 is connected to the signal shaping circuit 710 and is configured to convert the frequency signal into a voltage signal; the voltage of the voltage signal is positively correlated with the frequency of the frequency signal.

[0097] The integration circuit 730 is connected to the signal shaping circuit 710, the gain adjustment circuit 720 and the pulse width adjustment circuit 400, and is configured to integrate the frequency signal and amplify the integrated frequency signal based on the voltage signal to output a triangular wave pulse; the amplification factor is positively correlated with the voltage of the voltage signal.

[0098] Since the integration circuit 730 amplifies the integrated frequency signal based on the voltage signal to output a triangular wave pulse, and the amplitude of the integrated frequency signal is negatively correlated with the frequency, and the amplification factor is positively correlated with the voltage of the voltage signal, and the voltage of the voltage signal is positively correlated with the frequency of the frequency signal, that is, the amplification factor is positively correlated with the frequency, the amplitude of the triangular wave pulse is constant.

[0099] By way of example and not limitation, Figure 7 As shown, the current detection circuit 200 includes a voltage transformation circuit 210 , a pre-processing circuit 220 , a rectification circuit 230 and a pulse width compensation circuit 240 .

[0100] The voltage transformation circuit 210 is connected to the square wave inverter circuit 100 and is configured to transform the output square wave to output a first square wave.

[0101] The preprocessing circuit 220 is connected to the voltage transformation circuit 210 and is configured to adjust the amplitude of the first square wave to output a second square wave.

[0102] The rectifier circuit 230 is connected to the preprocessing circuit 220 and is configured to rectify the second square wave to output a DC square wave pulse.

[0103] The pulse width compensation circuit 240 is connected to the rectifier circuit 230 and the control circuit 300 , and is configured to perform voltage compensation on the DC square wave pulse to output a current sampling signal.

[0104] The current sampling signal is direct current and has the same amplitude as the direct current square wave pulse.

[0105] The pre-processing circuit 220 can adjust the high-frequency output square wave to a first square wave with a suitable amplitude and equal-proportion attenuation.

[0106] The rectifier circuit 230 can rectify the first square wave into a high-fidelity, unipolar DC square wave pulse.

[0107] The pulse width compensation circuit 240 can generate a voltage gain compensation signal according to the duty cycle of the DC square wave pulse, and at the same time perform low-pass filtering on the input DC square wave pulse, and multiply the filtered DC square wave pulse with the voltage gain compensation signal to obtain a current sampling signal proportional to the high-frequency square wave output amplitude.

[0108] The conventional current detection circuit 200 obtains a DC current sampling signal through filtering, which has a different amplitude from the DC square wave pulse. It can no longer meet the measurement requirements in scenarios where the pulse width changes rapidly and dynamically. The measurement error is large and the error is not fixed. The pulse width compensation circuit 240 is used to make the circuit compensation coefficient dynamically and linearly change with the pulse width, thereby achieving rapid measurement of the pulse amplitude and single coefficient calibration of the current detection circuit 200.

[0109] By way of example and not limitation, Figure 8 As shown, the driving signal includes a first driving signal and a second driving signal, which are respectively used to drive different bridge arms of the square wave inverter circuit.

[0110] The pulse width modulation circuit 400 includes a clamp circuit 410 and a comparison circuit 420 .

[0111] The clamping circuit 410 is connected to the control circuit 300 and is configured to output a first reference voltage and a second reference voltage based on the regulated voltage; the first reference voltage is positively correlated with the regulated voltage and the upper limit of the first reference voltage is clamped, and the second reference voltage is negatively correlated with the regulated voltage and the lower limit of the second reference voltage is clamped.

[0112] The comparison circuit 420 is connected to the clamp circuit 410 and the square wave inverter circuit 100, and is configured to compare the first reference voltage and the triangular wave pulse to output a first driving signal, and to compare the second reference voltage and the triangular wave pulse to output a second driving signal.

[0113] The clamping circuit 410 is used to clamp the minimum duty cycle and the maximum duty cycle of the two driving signals within a specific range to ensure that the circuit works normally.

[0114] Fig. 9 A partial exemplary circuit structure of a square wave generating circuit provided in an embodiment of the present application is shown. For the sake of convenience, only the part related to the embodiment of the present application is shown, which is described in detail as follows:

[0115] The signal shaping circuit 710 includes a D flip-flop U1 , a third diode D3 , a first resistor R1 , a second resistor R2 , and an eighth capacitor C8 .

[0116] The clock input terminal CLK of the D flip-flop U1 serves as the reference pulse input terminal of the signal shaping circuit 710 to input the reference pulse; the clear terminal CLR of the D flip-flop U1 is connected to the first end of the eighth capacitor C8, the reverse output terminal \Q of the D flip-flop U1 is connected to the positive electrode of the third diode D3 and the first end of the first resistor R1, the negative electrode of the third diode D3 is connected to the first end of the second resistor R2, the output terminal Q of the D flip-flop U1 serves as the frequency signal output terminal of the signal shaping circuit 710, and is connected to the gain adjustment circuit 720 to output the frequency signal; the preset terminal PRE of the D flip-flop U1 and the input terminal D of the D flip-flop U1 are commonly connected to the first power supply; the second end of the eighth capacitor C8, the second end of the first resistor R1 and the second end of the second resistor R2 are commonly connected to the power ground.

[0117] The D flip-flop U1 has high stability, good reliability and fast response speed.

[0118] The gain adjustment circuit 720 includes a frequency-to-voltage converter U2 , a third resistor R3 , a fourth resistor R4 , a fifth resistor R5 , a first capacitor C1 , and a second capacitor C2 .

[0119] The first end of the fourth resistor R4 serves as the frequency signal input end of the gain adjustment circuit 720 and is connected to the signal shaping circuit 710 to input the frequency signal; the second end of the fourth resistor R4 is connected to the positive input signal end TACH+ of the frequency voltage converter U2, the first capacitor C1 connection end CP1 of the voltage converter U2 is connected to the first end of the second capacitor C2, the second capacitor C2 connection end CP2 of the voltage converter U2 is connected to the first end of the third resistor R3 and the first end of the first capacitor C1, the inverting input end IN- of the voltage converter U2, the emitter EMIT of the voltage converter U2 and the first end of the fifth resistor R5 are collectively used as the voltage signal output end of the gain adjustment circuit 720, and are connected to the integration circuit 730 to output the voltage signal; the collector COL of the voltage converter U2 is connected to the first power supply; the second end of the second capacitor C2, the second end of the third resistor R3, the second end of the first capacitor C1 and the second end of the fifth resistor R5 are collectively connected to the power ground.

[0120] The frequency-to-voltage converter U2 has high conversion accuracy and high operating frequency.

[0121] The integration circuit 730 includes a first amplifier U3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and a third capacitor C3.

[0122] The first end of the sixth resistor R6 is used as the frequency signal input end of the integration circuit 730, and is connected to the signal shaping circuit 710 to input the frequency signal; the first end of the tenth resistor R10 is used as the voltage signal input end of the integration circuit 730, and is connected to the gain adjustment circuit 720 to input the voltage signal; the second end of the sixth resistor R6 is connected to the A channel positive input end +INA of the first amplifier U3, the A channel inverting input end -INA of the first amplifier U3 is connected to the first end of the seventh resistor R7 and the first end of the third capacitor C3, and the A channel output end OUT of the first amplifier U3 is connected to the first end of the seventh resistor R7 and the first end of the third capacitor C3. A is connected to the positive input terminal +INB of the B channel of the first amplifier U3 and the second end of the third capacitor C3, the inverting input terminal -INB of the B channel of the first amplifier U3 is connected to the second end of the tenth resistor R10, the first end of the eighth resistor R8 and the first end of the ninth resistor R9, the B channel output terminal OUTB of the first amplifier U3 and the second end of the eighth resistor R8 are jointly used as the triangular wave pulse output terminal of the integration circuit 730, and are connected to the pulse width adjustment circuit 400 to output a triangular wave pulse; the second end of the seventh resistor R7 and the second end of the ninth resistor R9 are jointly connected to the power ground.

[0123] The circuit is simple and reliable.

[0124] The voltage transformation circuit 210 includes a first current transformer CT1 , an eleventh resistor R11 , and a fourth capacitor C4 .

[0125] The first input end of the first current transformer CT1 serves as the output square wave input end of the transformer circuit 210, and is connected to the square wave inverter circuit 100 to input and output square waves; the second input end of the first current transformer CT1, the first end of the eleventh resistor R11, and the first end of the fourth capacitor C4 are commonly connected to the signal ground; the first output end of the first current transformer CT1 serves as the output square wave output end of the transformer circuit 210 to output the output square wave; the second output end of the first current transformer CT1, the second end of the eleventh resistor R11, and the second end of the fourth capacitor C4 serve as the first square wave output end of the transformer circuit 210, and are connected to the preprocessing circuit 220 to output the first square wave.

[0126] The first current transformer CT1 has high precision.

[0127] The pre-processing circuit 220 includes a second operational amplifier U4, a twelfth resistor R12, and a thirteenth resistor R13.

[0128] The non-inverting input terminal VIN+ of the second operational amplifier U4 serves as the first square wave input terminal of the pre-processing circuit 220, and is connected to the voltage transformer circuit 210 to input the first square wave; the inverting input terminal VIN- of the second operational amplifier U4 is connected to the first end of the twelfth resistor R12 and the first end of the thirteenth resistor R13, and the output terminal VO of the second operational amplifier U4 and the second end of the twelfth resistor R12 serve together as the second square wave output terminal of the pre-processing circuit 220, and are connected to the rectifier circuit 230 to output the second square wave; the second end of the thirteenth resistor R13 is connected to the signal ground.

[0129] The circuit is simple and reliable.

[0130] The rectifier circuit 230 includes a third operational amplifier U5 , a first diode D1 , a second diode D2 , a sixteenth resistor R16 , a seventeenth resistor R17 , an eighteenth resistor R18 , a nineteenth resistor R19 , and a twentieth resistor R20 .

[0131] The first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17 are used together as the second square wave input end of the rectifier circuit 230, and are connected to the preprocessing circuit 220 to input the second square wave; the second end of the sixteenth resistor R16 is connected to the first end of the eighteenth resistor R18, the cathode of the second diode D2 and the A channel inverting input end -INA of the third operational amplifier U5, the second end of the eighteenth resistor R18 is connected to the anode of the first diode D1 and the first end of the nineteenth resistor R19, the B channel inverting input end -INB of the third operational amplifier U5 and the second end of the seventeenth resistor R17, the cathode of the second diode D2 and the A channel inverting input end -INA of the third operational amplifier U5 The second end of the nineteenth resistor R19 and the first end of the twentieth resistor R20 are connected, the A channel output terminal OUTA of the third operational amplifier U5 is connected to the anode of the second diode D2 and the cathode of the first diode D1, the second end of the twentieth resistor R20 and the B channel output terminal OUTB of the third operational amplifier U5 are jointly used as the DC square wave pulse output terminal of the rectifier circuit 230, and are connected to the pulse width compensation circuit 240 to output a DC square wave pulse; the A channel positive phase input terminal +INA of the third operational amplifier U5 and the B channel positive phase input terminal +INB of the third operational amplifier U5 are jointly connected to the signal ground.

[0132] The circuit has simple structure and high efficiency.

[0133] The pulse width compensation circuit 240 includes a first comparator U6, a fourth operational amplifier U7, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35 and a fifth capacitor C5.

[0134] The positive phase input terminal +IN of the first comparator U6 and the first end of the twenty-first resistor R21 are used together as the DC square wave pulse input terminal of the pulse width compensation circuit 240, and are connected to the rectifier circuit 230 to input the DC square wave pulse; the inverting input terminal -IN of the first comparator U6 is connected to the first end of the thirty-third resistor R33 and the first end of the thirty-fourth resistor R34, the output terminal OUT of the first comparator U6 is connected to the first end of the twenty-second resistor R22, the second end of the twenty-second resistor R22 is connected to the A channel positive phase input terminal +INA of the fourth operational amplifier U7, the A channel output terminal OUTA of the fourth operational amplifier U7 is connected to the first end of the twenty-seventh resistor R27 and the first end of the twenty-third resistor R23, the A channel inverting input terminal -INA of the fourth operational amplifier U7 is connected to the second end of the twenty-third resistor R23 and the first end of the twenty-fourth resistor R24, and the fourth operational amplifier U The B channel inverting input terminal -INB of the fourth operational amplifier U7 is connected to the second end of the twenty-seventh resistor R27, the first end of the twenty-fifth resistor R25 and the first end of the twenty-sixth resistor R26, the B channel non-inverting input terminal +INB of the fourth operational amplifier U7 is connected to the second end of the twenty-first resistor R21, the first end of the thirty-fifth resistor R35 and the first end of the fifth capacitor C5, the second end of the twenty-sixth resistor R26 and the B channel output terminal OUTB of the fourth operational amplifier U7 are jointly used as the current sampling signal output terminal of the pulse width compensation circuit 240, and are connected to the control circuit 300 to output the current sampling signal; the second end of the thirty-third resistor R33 is connected to the second power supply, the second end of the twenty-fifth resistor R25 is connected to the third power supply, and the second end of the thirty-fifth resistor R35, the second end of the fifth capacitor C5, the second end of the thirty-fourth resistor R34 and the second end of the twenty-fourth resistor R24 ​​are jointly connected to the signal ground.

[0135] Among them, the thirty-fifth resistor R35 and the third capacitor C3 can form a low-pass filter.

[0136] The pulse width compensation circuit 240 is constructed using discrete components, which makes it easy to change component parameters according to actual needs and improves the flexibility of use.

[0137] The clamp circuit 410 includes a fifth operational amplifier U12, a fourteenth resistor R14, a fifteenth resistor R15, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37 and a sixth capacitor C6.

[0138] The first end of the fifteenth resistor R15 is used as the adjustment voltage input end of the clamp circuit 410, and is connected to the control circuit 300 to input the adjustment voltage; the A channel positive input end +INA of the fifth operational amplifier U12 is connected to the second end of the fifteenth resistor R15, the A channel inverting input end -INA of the fifth operational amplifier U12 is connected to the first end of the fourteenth resistor R14, the first end of the thirty-third resistor R33 and the first end of the sixth capacitor C6, the A channel output end OUTA of the fifth operational amplifier U12 and the second end of the thirty-third resistor R33, the second end of the sixth capacitor C6 and the first end of the thirty-fifth resistor R35 are used together as the first reference voltage output end of the clamp circuit 410, and are connected to the comparison circuit 420 to output a first reference voltage; an inverting input terminal -INB of the B channel of the fifth operational amplifier U12 is connected to the second end of the thirty-fifth resistor R35 and the first end of the thirty-fourth resistor R34, an output terminal OUTB of the B channel of the fifth operational amplifier U12 and the second end of the thirty-fourth resistor R34 are jointly used as a second reference voltage output terminal of the clamp circuit 410, and are connected to the comparison circuit 420 to output a second reference voltage; a non-inverting input terminal +INB of the B channel of the fifth operational amplifier U12 is connected to the first end of the thirty-sixth resistor R36 and the first end of the thirty-seventh resistor R37, a second end of the thirty-seventh resistor R37 is connected to the first power supply, and a second end of the fourteenth resistor R14 and a second end of the thirty-sixth resistor R36 are jointly connected to the power ground.

[0139] The circuit has a simple structure and a fast response speed.

[0140] The comparison circuit 420 includes a second comparator U13, a thirty-eighth resistor R38, a thirty-ninth resistor R39, a fortieth resistor R40, a forty-first resistor R41, a forty-second resistor R42 and a seventh capacitor C7.

[0141] The B channel positive input terminal +INB of the second comparator U13 and the first end of the thirty-ninth resistor R39 are used together as the first reference voltage input terminal of the comparison circuit 420, which is connected to the clamp circuit 410 to input the first reference voltage; the A channel inverting input terminal -INA of the second comparator U13 and the first end of the thirty-eighth resistor R38 are used together as the second reference voltage input terminal of the comparison circuit 420, which is connected to the clamp circuit 410 to input the second reference voltage; the A channel positive input terminal +INA of the second comparator U13 and the B channel inverting input terminal -INB of the second comparator U13, the first end of the fortieth resistor R40, the first end of the forty-second resistor R42 and the first end of the seventh capacitor C7 are connected, and the first end of the forty-first resistor R41 is connected. The second end of the thirty-eighth resistor R38 and the second end of the forty-second resistor R42 are commonly connected to the first power supply; the second end of the thirty-ninth resistor R39, the second end of the fortieth resistor R40 and the second end of the forty-first resistor R41 are commonly connected to the power ground.

[0142] The second comparator U13 has high stability and high sensitivity.

[0143] The control circuit 300 includes a digital signal controller U8, a digital-to-analog converter U9, a sixth operational amplifier U10, an optical isolation amplifier U11, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32 and a second capacitor C2.

[0144] The first input-output terminal RD5 of the digital signal controller U8 is connected to the chip selection terminal CS of the digital-to-analog converter U9, the second input-output terminal RD6 of the digital signal controller U8 is connected to the digital serial clock input terminal SCLK of the digital-to-analog converter U9, the third input-output terminal RD7 of the digital signal controller U8 is connected to the digital serial data input terminal DIN of the digital-to-analog converter U9, the analog voltage output terminal OUTB of the group B of the digital-to-analog converter U9 serves as the adjustment voltage output terminal of the control circuit 300, and is connected to the pulse width adjustment circuit 400 to output the adjustment voltage; the fourth input-output terminal RB6 of the digital signal controller U8 is connected to the output terminal VO of the sixth operational amplifier U10 and the first end of the thirty-second resistor R32, the non-inverting input terminal VIN+ of the sixth operational amplifier U10 is connected to the first end of the twenty-ninth resistor R29 and the first end of the thirty-first resistor R31 The inverting input terminal VIN- of the sixth operational amplifier U10 is connected to the second end of the thirty-second resistor R32 and the first end of the thirtieth resistor R30, the second end of the thirtieth resistor R30 is connected to the negative output terminal VOUT- of the optical isolation amplifier U11, the second end of the twenty-ninth resistor R29 is connected to the positive output terminal VOUT+ of the optical isolation amplifier U11, the non-inverting input terminal VIN+ of the optical isolation amplifier U11 is connected to the first end of the twenty-eighth resistor R28 and the first end of the second capacitor C2, the second end of the twenty-eighth resistor R28 serves as the current sampling signal input terminal of the control circuit 300, and is connected to the current detection circuit 200 to input the current sampling signal; the second end of the thirty-first resistor R31 is connected to the power ground, the inverting input terminal VIN- of the optical isolation amplifier U11 and the second end of the second capacitor C2 are commonly connected to the signal ground.

[0145] The circuit includes integrated chips such as a digital signal controller U8, a digital-to-analog converter U9, a sixth operational amplifier U10, and an optical isolation amplifier U11, which reduce the circuit volume, simplify the assembly process, and reduce the possibility of connection errors and signal loss.

[0146] The following is a combination of working principles Fig. 9 As shown for further explanation:

[0147] The voltage-controlled DC power supply circuit 500 converts the input voltage into a first DC power, the square wave inverter circuit 100 inverts the first DC power into an output square wave, the isolation conversion circuit 600 isolates and converts the output square wave, and outputs the isolated and converted output square wave to the first input terminal of the first current transformer CT1, the first current transformer CT1 outputs the first square wave from the second output terminal of the first current transformer CT1, the second terminal of the eleventh resistor R11, and the second terminal of the fourth capacitor C4 to the non-inverting input terminal VIN+ of the second operational amplifier U4 according to the isolated and converted output square wave, the second operational amplifier U4 adjusts the amplitude of the first square wave, and outputs the first square wave from the output terminal VO of the second operational amplifier U4 and the twelfth resistor R11. The second end of R12 outputs the second square wave to the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17. The rectifier circuit 230 rectifies the second square wave into a unipolar DC square wave pulse, and outputs the DC square wave pulse from the second end of the twentieth resistor R20 and the B channel output terminal OUTB of the third operational amplifier U5 to the positive phase input terminal +IN of the first comparator U6 and the first end of the twenty-first resistor R21. The second end of the thirty-third resistor R33 is connected to the second power supply. The thirty-third resistor R33 and the thirty-fourth resistor R34 divide the voltage of the second power supply, and output the divided voltage of the second power supply from the first end of the thirty-third resistor R33 and the first end of the thirty-fourth resistor R34 to the first comparator U6. The inverting input terminal -IN of the comparator U6, the first comparator U6 generates a voltage gain compensation signal according to the DC square wave pulse and the voltage output of the second power supply after the voltage division, and outputs the voltage gain compensation signal from the output terminal OUT of the first comparator U6, which is transmitted to the A channel positive input terminal +INA of the fourth operational amplifier U7 through the twenty-second resistor R22, and the B channel positive input terminal +INB of the fourth operational amplifier U7 is connected to the DC square wave pulse filtered by the fifth capacitor C5 and the thirty-fifth resistor R35. The fourth operational amplifier U7 multiplies the filtered DC square wave pulse and the output voltage gain compensation signal, and outputs the voltage gain compensation signal from the second end of the twenty-sixth resistor R26 and the B channel output of the fourth operational amplifier U7. The terminal OUTB outputs the amplitude sampling signal to the second end of the twenty-eighth resistor R28, the optical isolation amplifier U11 isolates and converts the amplitude sampling signal, and outputs a differential output voltage proportional to the amplitude sampling signal from the positive output terminal VOUT+ of the optical isolation amplifier U11 and the negative output terminal VOUT- of the optical isolation amplifier U11 to the non-inverting input terminal VIN+ of the sixth operational amplifier U10 and the inverting input terminal VIN- of the sixth operational amplifier U10, and the sixth operational amplifier U10 outputs an adjustment signal from the output terminal VO of the sixth operational amplifier U10 and the first end of the thirty-second resistor R32 to the fourth input-output terminal RB6 of the digital signal controller U8 according to the differential output voltage,The digital signal controller U8 outputs a digital signal from the third input / output terminal RD7 of the digital signal controller U8 to the digital serial data input terminal DIN of the digital-to-analog converter U9 according to the adjustment signal, and the digital-to-analog converter U9 performs digital-to-analog conversion on the digital signal, and outputs the adjustment voltage from the B channel analog voltage output terminal OUTB of the digital-to-analog converter U9 to the first end of the fifteenth resistor R15, the second end of the thirty-seventh resistor R37 is connected to the first power supply, the thirty-sixth resistor R36 and the thirty-seventh resistor R37 divide the voltage of the first power supply, and output the divided first voltage from the first end of the thirty-sixth resistor R36 and the first end of the thirty-seventh resistor R37 The voltage of the power supply is supplied to the B channel positive input terminal +INB of the fifth operational amplifier U12. The fifth operational amplifier U12 outputs a first reference voltage from the A channel output terminal OUTA of the fifth operational amplifier U12 and the second end of the thirty-third resistor R33, the second end of the sixth capacitor C6 and the first end of the thirty-fifth resistor R35 to the B channel positive input terminal +INB of the second comparator U13 and the first end of the thirty-ninth resistor R39 according to the adjustment voltage. The second reference voltage is output from the B channel output terminal OUTB of the fifth operational amplifier U12 and the second end of the thirty-fourth resistor R34 to the A channel inverting input terminal -INA of the second comparator U13 and the third The first end of the eighteenth resistor R38 and the clock input end CLK of the D flip-flop U1 are connected to the reference pulse. The D flip-flop U1 outputs a frequency signal from the output end Q of the D flip-flop U1 to the first end of the fourth resistor R4 and the first end of the sixth resistor R6 according to the reference pulse. The frequency-to-voltage converter U2 converts the frequency signal into a voltage signal, and outputs the voltage signal from the inverting input end IN- of the voltage converter U2, the emitter EMIT of the voltage converter U2 and the first end of the fifth resistor R5 to the first end of the tenth resistor R10. The first amplifier U3 integrates the frequency signal, amplifies the integrated frequency signal based on the voltage signal, and outputs the frequency signal from the first amplifier U3. The B channel output terminal OUTB and the second end of the eighth resistor R8 output a triangular wave pulse to the first end of the forty-first resistor R41 and the second end of the seventh capacitor C7. The second comparator U13 compares the first reference voltage with the triangular wave pulse to output a first drive signal from the B channel output terminal OUTB of the second comparator U13 to the square wave inverter circuit 100, and compares the second reference voltage with the triangular wave pulse to output a second drive signal from the A channel output terminal OUTA of the second comparator U13 to the square wave inverter circuit 100. The square wave inverter circuit 100 inverts the first direct current based on the first drive signal and the second drive signal to output an output square wave.

[0148] An embodiment of the present application also provides an electronic device, which includes the above-mentioned square wave generating circuit.

[0149] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0150] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A square wave generating circuit, characterized in that: include: A square wave inverter circuit is configured to receive a first direct current and invert the first direct current to output an output square wave; A current detection circuit, connected to the square wave inverter circuit, configured to detect the current of the output square wave to output a current sampling signal; a control circuit connected to the current detection circuit and configured to output a regulating voltage according to the current sampling signal; a pulse width adjustment circuit connected to the control circuit and the square wave inverter circuit and configured to output a driving signal based on a triangular wave pulse and the adjustment voltage; The square wave inverter circuit is further configured to invert the first direct current based on the drive signal to output the output square wave; The square wave generating circuit also includes: a reference circuit, connected to the pulse width adjustment circuit, configured to output the triangular wave pulse based on a reference pulse; Wherein, the amplitude of the triangular wave pulse is constant and has the same frequency as the reference pulse; The reference circuit comprises: a signal shaping circuit connected to the control circuit and configured to output a frequency signal based on the reference pulse; wherein the amplitude of the frequency signal is constant and has the same frequency as the reference pulse; a gain adjustment circuit connected to the signal shaping circuit and configured to convert the frequency signal into a voltage signal; the voltage of the voltage signal is positively correlated with the frequency of the frequency signal; an integration circuit connected to the signal shaping circuit, the gain adjustment circuit and the pulse width adjustment circuit, configured to integrate the frequency signal and amplify the integrated frequency signal based on the voltage signal to output the triangular wave pulse; the amplification factor is positively correlated with the voltage of the voltage signal; The current detection circuit comprises: A voltage transformation circuit, connected to the square wave inverter circuit, configured to transform the output square wave to output a first square wave; a preprocessing circuit, connected to the voltage transformation circuit, and configured to adjust the amplitude of the first square wave to output a second square wave; a rectifier circuit, connected to the preprocessing circuit, configured to rectify the second square wave to output a DC square wave pulse; a pulse width compensation circuit, connected to the rectifier circuit and the control circuit, and configured to perform voltage compensation on the DC square wave pulse to output the current sampling signal; The current sampling signal is direct current and has the same amplitude as the direct current square wave pulse.

2. The square wave generating circuit according to claim 1, characterized in that: Also includes: The voltage-controlled DC power supply circuit is configured to receive an input voltage and convert the input voltage to output the first DC power.

3. The square wave generating circuit according to claim 1, characterized in that: Also includes: an isolation conversion circuit, connected to the square wave inverter circuit and the current detection circuit, and configured to isolate and convert the output square wave; The current detection circuit is specifically configured to detect the current of the output square wave after isolation and conversion to output a current sampling signal.

4. The square wave generating circuit according to claim 1, characterized in that: The signal shaping circuit includes a D trigger, a third diode, a first resistor, a second resistor and an eighth capacitor; The clock input terminal of the D flip-flop serves as the reference pulse input terminal of the signal shaping circuit to input the reference pulse; The clear end of the D flip-flop is connected to the first end of the eighth capacitor, the reverse output end of the D flip-flop is connected to the anode of the third diode and the first end of the first resistor, the cathode of the third diode is connected to the first end of the second resistor, the output end of the D flip-flop serves as the frequency signal output end of the signal shaping circuit, and is connected to the gain adjustment circuit to output the frequency signal; the preset end of the D flip-flop and the input end of the D flip-flop are commonly connected to the first power supply; the second end of the eighth capacitor, the second end of the first resistor and the second end of the second resistor are commonly connected to the power ground.

5. The square wave generating circuit according to claim 1, characterized in that: The gain adjustment circuit includes a frequency-to-voltage converter, a third resistor, a fourth resistor, a fifth resistor, a first capacitor and a second capacitor; The first end of the fourth resistor serves as the frequency signal input end of the gain adjustment circuit and is connected to the signal shaping circuit to input the frequency signal; the second end of the fourth resistor is connected to the positive input signal end of the frequency-to-voltage converter, the first capacitor connection end of the voltage converter is connected to the first end of the second capacitor, the second capacitor connection end of the voltage converter is connected to the first end of the third resistor and the first end of the first capacitor, the inverting input end of the voltage converter, the emitter of the voltage converter and the first end of the fifth resistor serve together as the voltage signal output end of the gain adjustment circuit and are connected to the integration circuit to output the voltage signal; the collector of the voltage converter is connected to the first power supply; the second end of the second capacitor, the second end of the third resistor, the second end of the first capacitor and the second end of the fifth resistor are commonly connected to the power ground.

6. The square wave generating circuit according to claim 1, characterized in that: The integration circuit includes a first amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and a third capacitor; The first end of the sixth resistor is used as the frequency signal input end of the integration circuit and is connected to the signal shaping circuit to input the frequency signal; the first end of the tenth resistor is used as the voltage signal input end of the integration circuit and is connected to the gain adjustment circuit to input the voltage signal; the second end of the sixth resistor is connected to the A channel positive phase input end of the first amplifier, the A channel negative phase input end of the first amplifier is connected to the first end of the seventh resistor and the first end of the third capacitor, the A channel output end of the first amplifier is connected to the B channel positive phase input end of the first amplifier and the second end of the third capacitor, the B channel negative phase input end of the first amplifier is connected to the second end of the tenth resistor, the first end of the eighth resistor and the first end of the ninth resistor, the B channel output end of the first amplifier and the second end of the eighth resistor are commonly used as the triangular wave pulse output end of the integration circuit and are connected to the pulse width adjustment circuit to output the triangular wave pulse; the second end of the seventh resistor and the second end of the ninth resistor are commonly connected to the power ground.

7. The square wave generating circuit according to claim 1, characterized in that: The voltage transformation circuit includes a first current transformer, an eleventh resistor and a fourth capacitor; The first input end of the first current transformer serves as the output square wave input end of the voltage conversion circuit and is connected to the square wave inverter circuit to input the output square wave; The second input terminal of the first current transformer, the first terminal of the eleventh resistor, and the first terminal of the fourth capacitor are commonly connected to a signal ground; The first output end of the first current transformer serves as an output square wave output end of the voltage transformation circuit to output the output square wave; The second output end of the first current transformer, the second end of the eleventh resistor, and the second end of the fourth capacitor together serve as the first square wave output end of the voltage transformation circuit, and are connected to the preprocessing circuit to output the first square wave.

8. The square wave generating circuit according to claim 1, characterized in that: The pre-processing circuit includes a second operational amplifier, a twelfth resistor and a thirteenth resistor; The non-phase input terminal of the second operational amplifier is used as the first square wave input terminal of the pre-processing circuit and is connected to the voltage transformation circuit to input the first square wave; The inverting input terminal of the second operational amplifier is connected to the first end of the twelfth resistor and the first end of the thirteenth resistor. The output terminal of the second operational amplifier and the second end of the twelfth resistor together serve as the second square wave output terminal of the preprocessing circuit and are connected to the rectifier circuit to output the second square wave. The second end of the thirteenth resistor is connected to the signal ground.

9. The square wave generating circuit according to claim 1, characterized in that: The rectifier circuit includes a third operational amplifier, a first diode, a second diode, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor and a twentieth resistor; The first end of the sixteenth resistor and the first end of the seventeenth resistor are used together as the second square wave input end of the rectifier circuit, and are connected to the preprocessing circuit to input the second square wave; The second end of the sixteenth resistor is connected to the first end of the eighteenth resistor, the cathode of the second diode and the inverting input end of the A channel of the third operational amplifier, the second end of the eighteenth resistor is connected to the anode of the first diode and the first end of the nineteenth resistor, the inverting input end of the B channel of the third operational amplifier is connected to the second end of the seventeenth resistor, the second end of the nineteenth resistor and the first end of the twentieth resistor, the A channel output end of the third operational amplifier is connected to the anode of the second diode and the cathode of the first diode, the second end of the twentieth resistor and the B channel output end of the third operational amplifier are used together as the DC square wave pulse output end of the rectifier circuit, and are connected to the pulse width compensation circuit to output the DC square wave pulse; The A channel non-inverting input terminal of the third operational amplifier and the B channel non-inverting input terminal of the third operational amplifier are commonly connected to the signal ground.

10. The square wave generating circuit according to claim 1, characterized in that: The pulse width compensation circuit includes a first comparator, a fourth operational amplifier, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor and a fifth capacitor; The positive phase input terminal of the first comparator and the first end of the twenty-first resistor are jointly used as the DC square wave pulse input terminal of the pulse width compensation circuit, and are connected to the rectifier circuit to input the DC square wave pulse; the inverting input terminal of the first comparator is connected to the first end of the thirty-third resistor and the first end of the thirty-fourth resistor, the output terminal of the first comparator is connected to the first end of the twenty-second resistor, the second end of the twenty-second resistor is connected to the A channel positive phase input terminal of the fourth operational amplifier, the A channel output terminal of the fourth operational amplifier is connected to the first end of the twenty-seventh resistor and the first end of the twenty-third resistor, the A channel inverting input terminal of the fourth operational amplifier is connected to the second end of the twenty-third resistor and the first end of the twenty-fourth resistor, and the B channel of the fourth operational amplifier is connected to the first end of the twenty-second resistor. The inverting input terminal of the channel of the fourth operational amplifier is connected to the second end of the twenty-seventh resistor, the first end of the twenty-fifth resistor and the first end of the twenty-sixth resistor, the non-inverting input terminal of the B channel of the fourth operational amplifier is connected to the second end of the twenty-first resistor, the first end of the thirty-fifth resistor and the first end of the fifth capacitor, the second end of the twenty-sixth resistor and the B channel output terminal of the fourth operational amplifier are jointly used as the current sampling signal output terminal of the pulse width compensation circuit, and are connected to the control circuit to output the current sampling signal; the second end of the thirty-third resistor is connected to the second power supply, the second end of the twenty-fifth resistor is connected to the third power supply, and the second end of the thirty-fifth resistor, the second end of the fifth capacitor, the second end of the thirty-fourth resistor and the second end of the twenty-fourth resistor are jointly connected to the signal ground.

11. The square wave generating circuit according to claim 1, characterized in that: The driving signal includes a first driving signal and a second driving signal; The pulse width adjustment circuit comprises: a clamping circuit connected to the control circuit and configured to output a first reference voltage and a second reference voltage based on the regulated voltage; the first reference voltage is positively correlated with the regulated voltage and an upper limit of the first reference voltage is clamped, and the second reference voltage is negatively correlated with the regulated voltage and a lower limit of the second reference voltage is clamped; A comparison circuit is connected to the clamp circuit and the square wave inverter circuit, and is configured to compare the first reference voltage and the triangular wave pulse to output the first drive signal, and to compare the second reference voltage and the triangular wave pulse to output the second drive signal.

12. The square wave generating circuit according to claim 11, characterized in that: The clamping circuit includes a fifth operational amplifier, a fourteenth resistor, a fifteenth resistor, a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor, a thirty-sixth resistor, a thirty-seventh resistor and a sixth capacitor; The first end of the fifteenth resistor is used as an adjustment voltage input end of the clamp circuit and is connected to the control circuit to input the adjustment voltage; The A channel non-inverting input terminal of the fifth operational amplifier is connected to the second end of the fifteenth resistor, the A channel inverting input terminal of the fifth operational amplifier is connected to the first end of the fourteenth resistor, the first end of the thirty-third resistor and the first end of the sixth capacitor, the A channel output terminal of the fifth operational amplifier and the second end of the thirty-third resistor, the second end of the sixth capacitor and the first end of the thirty-fifth resistor are commonly used as the first reference voltage output terminal of the clamp circuit, and are connected to the comparison circuit to output the first reference voltage; The B channel inverting input terminal of the fifth operational amplifier is connected to the second end of the thirty-fifth resistor and the first end of the thirty-fourth resistor, and the B channel output terminal of the fifth operational amplifier and the second end of the thirty-fourth resistor serve together as the second reference voltage output terminal of the clamping circuit, and are connected to the comparison circuit to output the second reference voltage; The B channel non-inverting input terminal of the fifth operational amplifier is connected to the first end of the thirty-sixth resistor and the first end of the thirty-seventh resistor, the second end of the thirty-seventh resistor is connected to the first power supply, and the second end of the fourteenth resistor and the second end of the thirty-sixth resistor are commonly connected to the power ground.

13. The square wave generating circuit according to claim 11, characterized in that: The comparison circuit includes a second comparator, a thirty-eighth resistor, a thirty-ninth resistor, a fortieth resistor, a forty-first resistor, a forty-second resistor and a seventh capacitor; The B channel non-inverting input terminal of the second comparator and the first end of the thirty-ninth resistor are used together as the first reference voltage input terminal of the comparison circuit, and are connected to the clamping circuit to input the first reference voltage; The A channel inverting input terminal of the second comparator and the first end of the thirty-eighth resistor are used together as the second reference voltage input terminal of the comparison circuit, and are connected to the clamping circuit to input the second reference voltage; The A channel positive phase input terminal of the second comparator is connected to the B channel negative phase input terminal of the second comparator, the first end of the 40th resistor, the first end of the 42nd resistor and the first end of the seventh capacitor, and the first end of the 41st resistor and the second end of the seventh capacitor are used together as the triangular wave pulse input terminal of the comparison circuit to input the triangular wave pulse; the A channel output terminal of the second comparator is used as the second drive signal output terminal of the comparison circuit, connected to the square wave inverter circuit, to output the second drive signal; the B channel output terminal of the second comparator is used as the first drive signal output terminal of the comparison circuit, connected to the square wave inverter circuit, to output the first drive signal; The second end of the thirty-eighth resistor and the second end of the forty-second resistor are commonly connected to the first power supply; the second end of the thirty-ninth resistor, the second end of the fortieth resistor and the second end of the forty-first resistor are commonly connected to the power ground.

14. The square wave generating circuit according to any one of claims 1 to 13, characterized in that: The control circuit includes a digital signal controller, a digital-to-analog converter, a sixth operational amplifier, an optical isolation amplifier, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor, a thirty-second resistor and a second capacitor; The first input and output terminal of the digital signal controller is connected to the chip selection terminal of the digital-to-analog converter, the second input and output terminal of the digital signal controller is connected to the digital serial clock input terminal of the digital-to-analog converter, the third input and output terminal of the digital signal controller is connected to the digital serial data input terminal of the digital-to-analog converter, the analog voltage output terminal of the group B of the digital-to-analog converter serves as the adjustment voltage output terminal of the control circuit, and is connected to the pulse width adjustment circuit to output the adjustment voltage; the fourth input and output terminal of the digital signal controller is connected to the output terminal of the sixth operational amplifier and the first end of the thirty-second resistor, and the non-inverting input terminal of the sixth operational amplifier is connected to the The first end of the 29th resistor is connected to the first end of the 31st resistor, the inverting input end of the sixth operational amplifier is connected to the second end of the 32nd resistor and the first end of the 30th resistor, the second end of the 30th resistor is connected to the negative output end of the optical isolation amplifier, the second end of the 29th resistor is connected to the positive output end of the optical isolation amplifier, the non-inverting input end of the optical isolation amplifier is connected to the first end of the 28th resistor and the first end of the second capacitor, and the second end of the 28th resistor is used as the current sampling signal input end of the control circuit and is connected to the current detection circuit to input the current sampling signal; The second end of the thirty-first resistor is connected to the power ground, and the inverting input end of the optical isolation amplifier and the second end of the second capacitor are commonly connected to the signal ground.

15. An electronic device, characterized in that: Comprising the square wave generating circuit as described in any one of claims 1 to 14.

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