A method for preparing a back contact cell, a back contact cell and a photovoltaic module

Abstract

The invention discloses a method for preparing a back-contact cell, a back-contact cell and a photovoltaic module, and relates to the field of photovoltaic technology. The method for preparing the back-contact cell forms a tunneling polysilicon structure by first depositing on the front and back sides of a silicon wafer, and then forms a silicon nitride layer on the front and back sides of the silicon wafer by low-pressure chemical vapor deposition, so as to achieve the deposition of silicon nitride layers on both sides of the silicon wafer at one time, improve deposition efficiency, reduce equipment cost, shorten production cycle, and the deposition temperature of low-pressure chemical vapor deposition is high, which can play the role of annealing at the same time, save subsequent annealing steps, and further improve deposition efficiency, and can make the prepared silicon nitride layer have better corrosion resistance and film density, and better protect the tunneling polysilicon structure in the subsequent wet cleaning process to ensure its high passivation level.

Description

Technical Field

[0001] The present invention belongs to the field of photovoltaic technology, and in particular relates to a method for preparing a back-contact cell, a back-contact cell and a photovoltaic module. Background Art

[0002] At present, in the preparation process of back-contact batteries, an anti-reflection layer and a mask layer are generally formed on the front and back sides of the silicon wafer respectively, wherein the anti-reflection layer and the mask layer are both silicon nitride layers. The current method of growing and preparing the silicon nitride layer is generally through tubular PECVD (plasma enhanced chemical vapor deposition) or plate PECVD. Tubular PECVD or plate PECVD can only coat one side at a time, so two depositions are required to complete the coating of the front and back sides of the silicon wafer. The deposition efficiency is low, the equipment cost is high, and the PECVD deposition temperature is low, resulting in the prepared silicon nitride layer having poor corrosion resistance and film density, which is easily damaged during the subsequent wet cleaning process, affecting the passivation level.

[0003] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0004] The purpose of the present invention is to overcome the defects of the prior art that the front and back sides of the silicon wafer need to be deposited sequentially during the preparation process of the back-contact cell, resulting in low deposition efficiency, high equipment cost and long production cycle. A preparation method of a back-contact cell, a back-contact cell and a photovoltaic module are provided. The preparation method of the back-contact cell forms a tunneling polysilicon structure by first depositing on the front and back sides of the silicon wafer, and then forms a silicon nitride layer on the front and back sides of the silicon wafer at the same time by low-pressure chemical vapor deposition, so as to realize the deposition of silicon nitride layers on both sides of the silicon wafer at one time, improve deposition efficiency, reduce equipment cost and shorten production cycle. In addition, the deposition temperature of the low-pressure chemical vapor deposition is relatively high. On the one hand, it can also play the role of annealing, eliminating the subsequent annealing step and further improving the deposition efficiency. On the other hand, it can make the prepared silicon nitride layer have better corrosion resistance and film density, better protect the tunneling polysilicon structure during the subsequent wet cleaning process, and ensure its high passivation level.

[0005] In order to achieve the above object, in a first aspect, the present invention provides a method for preparing a back contact battery, comprising the following steps:

[0006] S1. Provide double-sided polished silicon wafers;

[0007] S2. The front side of the silicon wafer is subjected to a velvet rinse to form a velvet surface on the front side of the silicon wafer;

[0008] S3. forming a first semiconductor layer on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling oxide layer and a first doping layer disposed in sequence;

[0009] S4. forming a second semiconductor layer on the front side of the silicon wafer, wherein the second semiconductor layer comprises a second tunneling oxide layer and a second doping layer arranged in sequence, and the carbon doping concentration of the second doping layer is 1e19cm -3 -4e21cm -3 The phosphorus doping concentration of the second doping layer is 1e19cm -3 -5e20cm -3 ;

[0010] S5. forming a mask layer on the first doped layer and an anti-reflection layer on the second doped layer by low pressure chemical vapor deposition, and annealing the first semiconductor layer and the second semiconductor layer, wherein the thickness of the mask layer and the anti-reflection layer are both 100 nm-120 nm;

[0011] S6. Etching an opening on the first tunneling oxide layer, the first doping layer and the mask layer to form a first opening region;

[0012] S7. Cleaning and removing the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region, and then cleaning and removing the mask layer outside the first opening region;

[0013] S8. Deposit a third semiconductor layer on the back side of the silicon wafer so that a portion of the third semiconductor layer covers the side of the first semiconductor layer away from the silicon wafer, and another portion extends into the first opening area and covers the silicon wafer, the third semiconductor layer includes an intrinsic amorphous silicon layer and a third doped layer arranged in sequence.

[0014] Preferably, in S2, the texturing rinsing liquid used is a mixed solution of potassium hydroxide, texturing additives and water, wherein the mass percentage of potassium hydroxide is 1%-5%, the mass percentage of texturing additives is 0.5%-1%, the texturing time is 8min-40min, and the texturing temperature is 65℃-85℃.

[0015] Preferably, S3 includes:

[0016] Laughing gas is introduced and reacted to form a first tunneling oxide layer under the condition of turning on the glow, wherein the thickness of the first tunneling oxide layer is 1 nm-2 nm;

[0017] Silane, phosphine and hydrogen are introduced and reacted under the condition of turning on the glow to form a first doping layer, and the thickness of the first doping layer is 150nm-300nm.

[0018] Preferably, in S3, the reaction conditions for forming the first tunneling oxide layer are: the laughing gas flow rate is 2000sccm-4000sccm, the reaction temperature is 400°C-450°C, the reaction pressure is 100mtorr-2000mtorr, and the reaction time is 10s-60s;

[0019] And / or, the reaction conditions for forming the first doping layer are: silane flow rate is 600sccm-1000sccm, phosphine flow rate is 300sccm-600sccm, hydrogen flow rate is 1000sccm-3000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 500s-1500s.

[0020] Preferably, S4 includes:

[0021] Laughing gas is introduced and reacted to form a second tunneling oxide layer under the condition of turning on the glow, wherein the thickness of the second tunneling oxide layer is 4nm-6nm;

[0022] Silane, phosphine, methane and hydrogen are introduced and reacted under the condition of turning on the glow to form a second doping layer, and the thickness of the second doping layer is 10nm-15nm.

[0023] Preferably, in S4, the reaction conditions for forming the second tunneling oxide layer are: a laughing gas flow rate of 5000sccm-8000sccm, a reaction temperature of 400°C-450°C, a reaction pressure of 100mtorr-2000mtorr, and a reaction time of 10s-60s;

[0024] And / or, the reaction conditions for forming the second doping layer are: silane flow rate is 200sccm-300sccm, phosphine flow rate is 100sccm-150sccm, methane flow rate is 200sccm-500sccm, hydrogen flow rate is 1000sccm-2000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 30s-200s.

[0025] Preferably, in S5, the reaction conditions for forming the mask layer and the anti-reflection layer are: introducing silane and ammonia, the silane flow rate is 300sccm-600sccm, the ammonia flow rate is 700sccm-1000sccm, the reaction temperature is 800-850°C, the reaction pressure is 100pa-150pa, and the reaction time is 30-50min.

[0026] Preferably, after S8, the method for preparing a back contact battery further comprises:

[0027] S9. Etching openings on the third semiconductor layer to form second opening regions that are alternately arranged with the first opening regions and spaced apart;

[0028] S10. forming a conductive film layer on the back side of the silicon wafer;

[0029] S11. An isolation groove is formed on the conductive film layer so that a portion of the conductive film layer separated from each other extends into the first opening region and covers the third semiconductor layer, and another portion extends into the second opening region and covers the first semiconductor layer;

[0030] S12. Form a first electrode on the portion of the conductive film layer extending into the first opening region, and form a second electrode on the portion of the conductive film layer extending into the second opening region.

[0031] In a second aspect, the present invention provides a back-contact battery, which is prepared by the above-mentioned method for preparing a back-contact battery.

[0032] In a third aspect, the present invention provides a photovoltaic module comprising the above-mentioned back contact cell.

[0033] Beneficial effects:

[0034] It has been found through research that in the preparation process of back-contact cells, silicon nitride layers need to be deposited on both the front and back sides of the silicon wafer, and it is well known that the current tubular PECVD or plate PECVD can only achieve single-sided deposition, with low deposition efficiency and high equipment cost, and the PECVD deposition temperature is low, resulting in poor corrosion resistance and film density of the prepared silicon nitride layer, which is easily damaged during the subsequent wet cleaning process, affecting the passivation level. Based on this, further research was conducted and the present invention was proposed.

[0035] The preparation method of the back contact battery provided by the present invention adopts the above-mentioned technical scheme, especially first depositing a tunneling polysilicon structure (tunneling oxide layer + doping layer) on the front and back of the silicon wafer, and then forming a silicon nitride layer on the front and back of the silicon wafer at the same time through low-pressure chemical vapor deposition (LPCVD) (the front of the silicon wafer is an anti-reflection layer, and the back of the silicon wafer is a mask layer), so as to realize the deposition of silicon nitride layers on both sides of the silicon wafer at one time, improve deposition efficiency, reduce equipment cost, shorten production cycle, and the deposition temperature of low-pressure chemical vapor deposition is relatively high. On the one hand, it can also play the role of annealing, eliminating the subsequent annealing step and further improving the deposition efficiency. On the other hand, it can make the prepared silicon nitride layer have better corrosion resistance and film density, and better protect the tunneling polysilicon structure in the subsequent wet cleaning process to ensure its high passivation level.

[0036] The back contact battery provided by the present invention is prepared by the above-mentioned back contact battery preparation method, has a better deposition effect, and has good product quality.

[0037] The photovoltaic module provided by the present invention includes the above-mentioned back contact cell, has better photoelectric conversion efficiency and high photovoltaic power generation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is a schematic diagram of the structure of a silicon wafer after double-sided polishing and cleaning according to an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of a structure in which a velvet surface is formed on the front side of a silicon wafer according to an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of a structure in which a first semiconductor layer is formed on the back side of a silicon wafer and a second semiconductor layer is formed on the front side according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of a structure in which a mask layer is formed on the back side of a silicon wafer and an anti-reflection layer is formed on the front side according to an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a structure in which a first opening area is formed on the back side of a silicon wafer according to an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of a structure in which a third semiconductor layer and a second opening area are formed on the back side of a silicon wafer according to an embodiment of the present invention;

[0045] Figure 7 This is a schematic diagram of the structure of forming a conductive film layer and an isolation groove on the back side of a silicon wafer according to an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of the structure of forming a first electrode and a second electrode on the back side of a silicon wafer according to an embodiment of the present invention.

[0047] Description of reference numerals:

[0048] 1-silicon wafer; 2-first tunneling oxide layer; 3-first doping layer; 4-second tunneling oxide layer; 5-second doping layer; 6-mask layer; 7-anti-reflection layer; 8-intrinsic amorphous silicon layer; 9-third doping layer; 10-conductive film layer; 11-first electrode; 12-second electrode. DETAILED DESCRIPTION

[0049] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0051] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0052] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0053] In the first aspect, the present invention provides a method for preparing a back-contact battery, which first deposits a tunneling polysilicon structure (tunneling oxide layer + doping layer) on the front and back sides of a silicon wafer, and then forms a silicon nitride layer on the front and back sides of the silicon wafer at the same time through low-pressure chemical vapor deposition (LPCVD) (the front side of the silicon wafer is an anti-reflection layer, and the back side of the silicon wafer is a mask layer), so as to achieve the deposition of silicon nitride layers on both sides of the silicon wafer at one time, improve deposition efficiency, reduce equipment cost, shorten production cycle, and the deposition temperature of low-pressure chemical vapor deposition is relatively high. On the one hand, it can also play the role of annealing, eliminating the subsequent annealing step and further improving the deposition efficiency. On the other hand, it can make the prepared silicon nitride layer have better corrosion resistance and film density, and better protect the tunneling polysilicon structure during the subsequent wet cleaning process to ensure its high passivation level.

[0054] The method for preparing a back contact battery comprises the following steps:

[0055] S1. Provide double-sided polished silicon wafers;

[0056] S2. The front side of the silicon wafer is subjected to a velvet rinse to form a velvet surface on the front side of the silicon wafer;

[0057] S3. forming a first semiconductor layer on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling oxide layer and a first doping layer disposed in sequence;

[0058] S4. forming a second semiconductor layer on the front side of the silicon wafer, wherein the second semiconductor layer comprises a second tunneling oxide layer and a second doping layer arranged in sequence, and the carbon doping concentration of the second doping layer is 1e19cm -3 -4e21cm -3 The phosphorus doping concentration of the second doping layer is 1e19cm -3 -5e20cm -3 ;

[0059] S5. forming a mask layer on the first doped layer and an anti-reflection layer on the second doped layer by low pressure chemical vapor deposition, and annealing the first semiconductor layer and the second semiconductor layer, wherein the thickness of the mask layer and the anti-reflection layer are both 100 nm-120 nm;

[0060] S6. Etching an opening on the first tunneling oxide layer, the first doping layer and the mask layer to form a first opening region;

[0061] S7. Cleaning and removing the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region, and then cleaning and removing the mask layer outside the first opening region;

[0062] S8. Deposit a third semiconductor layer on the back side of the silicon wafer so that a portion of the third semiconductor layer covers the side of the first semiconductor layer away from the silicon wafer, and another portion extends into the first opening area and covers the silicon wafer, the third semiconductor layer includes an intrinsic amorphous silicon layer and a third doped layer arranged in sequence.

[0063] It should be noted that, in S1, the silicon wafer is preferably an N-type single crystal silicon wafer, and the silicon wafer can be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0064] In S2, the front side of the silicon wafer is single-sidedly textured by water rinsing to form a pyramid texture surface on the front side to reduce the reflectivity. The texture rinsing liquid used is a mixed solution of potassium hydroxide, a texture additive and water, wherein the mass percentage of potassium hydroxide is 1%-5%, the mass percentage of the texture additive is 0.5%-1%, the texture time is 8min-40min, the texture temperature is 65℃-85℃, and the texture additive contains at least one of benzoic acid, aminotri(methylene)phosphoric acid, polyepoxysuccinic acid and polyaspartic acid.

[0065] S3 consists of two stages:

[0066] The first stage: introducing laughing gas and reacting to form a first tunneling oxide layer under the condition of turning on the glow, and the thickness of the first tunneling oxide layer is 1nm-2nm. Preferably, in the first stage, the reaction conditions for forming the first tunneling oxide layer are: laughing gas flow rate is 2000sccm-4000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 10s-60s;

[0067] The second stage: introducing silane, phosphine and hydrogen, and reacting to form a first doped layer under the condition of turning on the glow, the first doped layer is an N-type doped polysilicon layer, and the thickness of the first doped layer is 150nm-300nm. Preferably, in the second stage, the reaction conditions for forming the first doped layer are: silane flow rate is 600sccm-1000sccm, phosphine flow rate is 300sccm-600sccm, hydrogen flow rate is 1000sccm-3000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 500s-1500s.

[0068] S4 consists of two stages:

[0069] The first stage: introduce laughing gas and react to form a second tunneling oxide layer under the condition of turning on the glow, and the thickness of the second tunneling oxide layer is 4nm-6nm. Preferably, in the first stage, the reaction conditions for forming the second tunneling oxide layer are: laughing gas flow rate is 5000sccm-8000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 10s-60s.

[0070] The second stage: introducing silane, phosphine, methane and hydrogen, and reacting to form a second doped layer under the condition of turning on the glow, the second doped layer is a carbon-doped or oxygen-doped N-type doped polycrystalline layer, and the thickness of the second doped layer is 10nm-15nm. Preferably, in the second stage, the reaction conditions for forming the second doped layer are: silane flow rate is 200sccm-300sccm, phosphine flow rate is 100sccm-150sccm, methane flow rate is 200sccm-500sccm, hydrogen flow rate is 1000sccm-2000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 30s-200s.

[0071] In S5, a mask layer and an anti-reflection layer are formed simultaneously by low-pressure chemical vapor deposition. In this process, since the deposition temperature of low-pressure chemical vapor deposition is relatively high, on the one hand, it can simultaneously play the role of annealing, eliminating the subsequent annealing step, and further improving the deposition efficiency. On the other hand, it can make the prepared silicon nitride layer (mask layer and anti-reflection layer) have better corrosion resistance and film density, and better protect the tunneling polysilicon structure during the subsequent wet cleaning process to ensure its high passivation level. Preferably, the reaction conditions for forming the mask layer and the anti-reflection layer are: introducing silane and ammonia, the silane flow rate is 300sccm-600sccm, the ammonia flow rate is 700sccm-1000sccm, the reaction temperature is 800℃-850℃, the reaction pressure is 100pa-150pa, and the reaction time is 30-50min.

[0072] In S6, laser or mask etching is used to etch an opening on the mask layer, the first doping layer and the first tunneling oxide layer on the back of the silicon wafer to form a first opening area, and the mask layer, the first doping layer and the first tunneling oxide layer in the first opening area are etched away. The width of the first opening area W1 is 0.3 mm-0.6 mm. Laser etching is preferred, and the etching laser is an ultraviolet laser or a green laser, and the pulse width is less than 100 ns.

[0073] In S7, the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region are removed by alkaline solution cleaning; and then the mask layer outside the first opening region is removed by hydrofluoric acid water rinsing.

[0074] In S8, a third semiconductor layer is deposited on the back side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the third doped layer is a P-type doped amorphous or microcrystalline silicon layer, the thickness of the intrinsic amorphous silicon layer is 5nm-15nm, the thickness of the third doped layer is 10nm-35nm, and the boron doping concentration of the third doped layer is 1e19cm -3 -4e20cm -3 .

[0075] Preferably, after S8, the method for preparing a back contact battery further comprises:

[0076] S9. Etching openings on the third semiconductor layer to form second opening regions that are alternately arranged with the first opening regions and spaced apart;

[0077] S10. forming a conductive film layer on the back side of the silicon wafer;

[0078] S11. An isolation groove is formed on the conductive film layer so that a portion of the conductive film layer separated from each other extends into the first opening region and covers the third semiconductor layer, and another portion extends into the second opening region and covers the first semiconductor layer;

[0079] S12. Form a first electrode on the portion of the conductive film layer extending into the first opening region, and form a second electrode on the portion of the conductive film layer extending into the second opening region.

[0080] It should be noted that in S9, an opening is etched on the third semiconductor layer on the back of the silicon wafer by laser or mask etching to form a second opening area, and the third semiconductor layer in the second opening area is etched away. The width of the second opening area W2 is 0.1 mm-0.3 mm. Laser etching is preferred, and the laser used for etching is an ultraviolet laser or a green laser, and the pulse width is less than 50 ns.

[0081] In S10, a conductive film layer is deposited on the back of the silicon wafer using physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD). The thickness of the conductive film layer is 40nm-80nm. The material of the conductive film layer can be an indium oxide film doped with tin oxide, titanium oxide, zinc oxide or gallium oxide, or a zinc oxide film doped with aluminum oxide, gallium oxide or boron oxide.

[0082] In S11, an isolation groove is formed on the conductive film layer by laser or etching. The isolation groove is used to achieve the insulation function between two adjacent conductive film layers. The isolation groove is located between the first opening area and the second opening area. The width of the isolation groove W3 is 30μm-200μm.

[0083] In S12, the silver gate electrode can be formed by screen printing and low temperature sintering, or the gate line electrode can be formed by electroplating. Preferably, the gate line electrode is formed by electroplating (the first electrode and the second electrode are both formed by electroplating).

[0084] In a second aspect, the present invention provides a back-contact battery, which is prepared by the above-mentioned method for preparing a back-contact battery.

[0085] In a third aspect, the present invention provides a photovoltaic module comprising the above-mentioned back contact cell.

[0086] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0087] Example 1

[0088] A back contact battery is prepared by the following steps:

[0089] S1. Figure 1 As shown, the N-type single crystal silicon wafer 1 is double-sided polished and cleaned, and the silicon wafer 1 is a Czochralski single crystal silicon wafer 1.

[0090] S2. Figure 2As shown, a velvet surface is formed on the front side of the silicon wafer 1 by velveting rinsing, and the velveting rinsing liquid used is a mixed solution of potassium hydroxide, velveting additives and water, wherein the mass percentage of potassium hydroxide is 2%, the mass percentage of the velveting additive is 0.7%, the velveting time is 20 minutes, the velveting temperature is 75°C, and the velveting additive contains benzoic acid and aminotri(methylene)phosphoric acid.

[0091] S3. Figure 3 As shown, a first tunneling oxide layer 2 and a first doping layer 3 are sequentially deposited on the back side of a silicon wafer 1 by tubular PECVD, and the deposition process is as follows:

[0092] In the first stage, laughing gas is introduced and reacted to form a first tunneling oxide layer 2 under the condition of turning on the glow, the laughing gas flow rate is 3000sccm, the reaction temperature is 420°C, the reaction pressure is 1000mtorr, the reaction time is 30s, and the thickness of the formed first tunneling oxide layer 2 is 1.5nm;

[0093] In the second stage, silane, phosphine and hydrogen are introduced and reacted under the condition of turning on the glow to form the first doping layer 3. The silane flow rate is 800sccm, the phosphine flow rate is 400sccm, the hydrogen flow rate is 2000sccm, the reaction temperature is 420°C, the reaction pressure is 1000mtorr, the reaction time is 1000s, and the thickness of the formed first doping layer 3 is 200nm.

[0094] S4. Figure 3 As shown, a second tunneling oxide layer 4 and a second doping layer 5 are sequentially deposited on the back of the silicon wafer 1 by tubular PECVD, and the deposition process is as follows:

[0095] In the first stage, laughing gas is introduced and reacted to form a second tunneling oxide layer 4 under the condition of turning on the glow, the laughing gas flow rate is 6000sccm, the reaction temperature is 420°C, the reaction pressure is 1000mtorr, the reaction time is 30s, and the thickness of the formed second tunneling oxide layer 4 is 5nm;

[0096] In the second stage, silane, phosphine, methane and hydrogen are introduced and reacted under the condition of turning on the glow to form the second doping layer 5. The silane flow rate is 250sccm, the phosphine flow rate is 125sccm, the methane flow rate is 300sccm, the hydrogen flow rate is 1500sccm, the reaction temperature is 420°C, the reaction pressure is 1000mtorr, the reaction time is 100s, and the thickness of the formed second doping layer 5 is 12nm. The carbon doping concentration of the second doping layer 5 is 2e21cm -3 The phosphorus doping concentration of the second doping layer 5 is 3e20cm -3 .

[0097] S5. Figure 4As shown, the mask layer 6 and the anti-reflection layer 7 are formed simultaneously by low-pressure chemical vapor deposition. The deposition process is: introducing silane and ammonia, the silane flow rate is 400sccm, the ammonia flow rate is 8000sccm, the reaction temperature is 820°C, the reaction pressure is 120pa, the reaction time is 40min, and the thickness of the formed mask layer 6 and the anti-reflection layer 7 are both 110nm.

[0098] S6. Figure 5 As shown, an opening is etched on the mask layer 6, the first doping layer 3 and the first tunneling oxide layer 2 to form a first opening area. The width of the first opening area W1 is 0.4 mm. The laser used for etching is a green laser with a pulse width of 50 ns.

[0099] S7. The first tunneling oxide layer 2, the first doping layer 3 and the mask layer 6 remaining in the first opening region are removed by alkaline cleaning, and then the mask layer 6 outside the first opening region is removed by hydrofluoric acid water rinsing.

[0100] S8. Figure 6 As shown, a third semiconductor layer is deposited on the back of the silicon wafer 1. The third semiconductor layer includes an intrinsic amorphous silicon layer 8 and a third doped layer 9 arranged in sequence. The intrinsic amorphous silicon layer 8 has a thickness of 10 nm, the third doped layer 9 has a thickness of 20 nm, and the boron doping concentration in the third doped layer 9 is 3e20 cm -3 .

[0101] S9. Figure 6 As shown, an opening is etched on the third semiconductor layer to form a second opening area that is alternately arranged with the first opening area and spaced apart. The width of the second opening area W2 is 0.2 mm. The laser used for etching is a green laser with a pulse width of 20 ns.

[0102] S10. Figure 7 As shown, a conductive film layer 10 is formed on the back of a silicon wafer 1 by using physical vapor deposition technology (PVD). The thickness of the conductive film layer 10 is 60 nm, and the material of the conductive film layer 10 is a tin oxide-doped indium oxide thin film.

[0103] S11. Figure 7 As shown, an isolation groove W3 is opened on the conductive film layer 10 by laser, and the width of the isolation groove W3 is 100 μm.

[0104] S12. Figure 8 As shown, a first electrode 11 is formed on a portion of the conductive film layer 10 extending into the first opening region by electroplating, and a second electrode 12 is formed on a portion of the conductive film layer 10 extending into the second opening region.

[0105] Example 2

[0106] The method of Example 1 is followed, except that the reaction conditions for forming the first doping layer 3 in S3 are adjusted so that the silane flow rate is 1000 sccm, the phosphine flow rate is 600 sccm, the hydrogen flow rate is 1000 sccm, the reaction temperature is 400°C, the reaction pressure is 100 mtorr, the reaction time is 500 s, and the thickness of the formed first doping layer 3 is 150 nm.

[0107] Example 3

[0108] The method of Example 1 is referred to, except that the reaction conditions for forming the second doping layer 5 in S4 are adjusted so that the silane flow rate is 300 sccm, the phosphine flow rate is 100 sccm, the methane flow rate is 200 sccm, the hydrogen flow rate is 1000 sccm, the reaction temperature is 400°C, the reaction pressure is 100 mtorr, the reaction time is 30 s, the thickness of the formed second doping layer 5 is 10 nm, and the carbon doping concentration of the second doping layer 5 is 1e19 cm -3 The phosphorus doping concentration of the second doping layer 5 is 1e19 cm -3 .

[0109] Example 4

[0110] The method of Example 1 is followed, except that the reaction conditions for forming the mask layer 6 and the anti-reflection layer 7 in S5 are adjusted so that the silane flow rate is 300 sccm, the ammonia flow rate is 700 sccm, the reaction temperature is 800°C, the reaction pressure is 100 Pa, the reaction time is 30 min, and the thickness of the mask layer 6 and the anti-reflection layer 7 formed are both 100 nm.

[0111] Comparative Example 1

[0112] The method of Example 1 is followed, except that the reaction conditions for forming the first doping layer 3 in S3 are adjusted so that the silane flow rate is 500 sccm, the phosphine flow rate is 250 sccm, the hydrogen flow rate is 800 sccm, the reaction temperature is 300°C, the reaction pressure is 50 mtorr, the reaction time is 300 s, and the thickness of the formed first doping layer 3 is 80 nm.

[0113] Comparative Example 2

[0114] The method of Example 1 is referred to, except that the reaction conditions for forming the second doping layer 5 in S4 are adjusted so that the silane flow rate is 150 sccm, the phosphine flow rate is 80 sccm, the methane flow rate is 100 sccm, the hydrogen flow rate is 800 sccm, the reaction temperature is 300°C, the reaction pressure is 50 mtorr, the reaction time is 20 s, the thickness of the formed second doping layer 5 is 8 nm, and the carbon doping concentration of the second doping layer 5 is 1e18 cm -3The phosphorus doping concentration of the second doping layer 5 is 1e18 cm -3 .

[0115] Comparative Example 3

[0116] The method of Example 1 is followed, except that the reaction conditions for forming the mask layer 6 and the anti-reflection layer 7 in S5 are adjusted so that the silane flow rate is 200 sccm, the ammonia flow rate is 500 sccm, the reaction temperature is 600°C, the reaction pressure is 80 Pa, the reaction time is 20 min, and the thickness of the mask layer 6 and the anti-reflection layer 7 formed are both 80 nm.

[0117] Test Case

[0118] The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in the following performance index comparison table.

[0119] Performance index comparison table:

[0120]

[0121] It can be seen from the above performance index comparison table that, relative to the comparative example, the embodiment scheme of the present invention is adopted to first deposit a tunneling polysilicon structure (tunneling oxide layer + doping layer) on the front and back sides of the silicon wafer 1, and then a silicon nitride layer is simultaneously formed on the front and back sides of the silicon wafer 1 by low-pressure chemical vapor deposition (LPCVD) (the front side of the silicon wafer 1 is an anti-reflection layer 7, and the back side of the silicon wafer 1 is a mask layer 6), so as to achieve the deposition of silicon nitride layers on both sides of the silicon wafer 1 at one time, improve deposition efficiency, reduce equipment cost, shorten production cycle, and the deposition temperature of low-pressure chemical vapor deposition is relatively high. On the one hand, it can also play the role of annealing, eliminating the subsequent annealing step, and further improving the deposition efficiency. On the other hand, it can make the prepared silicon nitride layer have better corrosion resistance and film density, and better protect the tunneling polysilicon structure in the subsequent wet cleaning process to ensure its high passivation level.

[0122] Furthermore, according to Example 1 and Examples 2-4, it can be seen that the solution of the preferred battery structure of the present invention has a better deposition effect, better product quality, and is more conducive to reducing optical absorption while ensuring conductivity, improving passivation effect, improving battery conversion efficiency, and improving photovoltaic power generation efficiency.

[0123] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for preparing a back contact battery, characterized in that: The following steps are involved: S1. Provide double-sided polished silicon wafers; S2. The front side of the silicon wafer is subjected to a velvet rinse to form a velvet surface on the front side of the silicon wafer; S3. forming a first semiconductor layer on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling oxide layer and a first doping layer disposed in sequence; S4. forming a second semiconductor layer on the front side of the silicon wafer, wherein the second semiconductor layer comprises a second tunneling oxide layer and a second doping layer arranged in sequence, and the carbon doping concentration of the second doping layer is 1e19cm -3 -4e21cm -3 The phosphorus doping concentration of the second doping layer is 1e19cm -3 -5e20cm -3 ; S5. forming a mask layer on the first doped layer and an anti-reflection layer on the second doped layer by low-pressure chemical vapor deposition, and annealing the first semiconductor layer and the second semiconductor layer at the same time, wherein the mask layer has the same thickness as the anti-reflection layer, and the thickness of the mask layer and the anti-reflection layer are both 100nm-120nm, and the reaction conditions for forming the mask layer and the anti-reflection layer are: introducing silane and ammonia, the silane flow rate is 300sccm-600sccm, the ammonia flow rate is 700sccm-1000sccm, the reaction temperature is 800-850°C, the reaction pressure is 100Pa-150Pa, and the reaction time is 30-50min; S6. Etching an opening on the first tunneling oxide layer, the first doping layer and the mask layer to form a first opening region; S7. Cleaning and removing the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region, and then cleaning and removing the mask layer outside the first opening region; S8. Deposit a third semiconductor layer on the back side of the silicon wafer so that a portion of the third semiconductor layer covers the side of the first semiconductor layer away from the silicon wafer, and another portion extends into the first opening area and covers the silicon wafer, wherein the third semiconductor layer includes an intrinsic amorphous silicon layer and a third doping layer arranged in sequence.

2. The method for preparing a back contact battery according to claim 1, characterized in that: In S2, the texturing rinsing liquid used is a mixed solution of potassium hydroxide, texturing additives and water, wherein the mass percentage of potassium hydroxide is 1%-5%, the mass percentage of texturing additives is 0.5%-1%, the texturing time is 8min-40min, and the texturing temperature is 65℃-85℃.

3. The method for preparing a back contact battery according to claim 1, characterized in that: S3 includes: Passing laughing gas, and reacting to form the first tunneling oxide layer under the condition of turning on the glow, wherein the thickness of the first tunneling oxide layer is 1nm-2nm; Silane, phosphine and hydrogen are introduced and reacted under the condition of turning on the glow to form the first doping layer, and the thickness of the first doping layer is 150nm-300nm.

4. The method for preparing a back contact battery according to claim 3, characterized in that: In S3, the reaction conditions for forming the first tunneling oxide layer are: a laughing gas flow rate of 2000sccm-4000sccm, a reaction temperature of 400°C-450°C, a reaction pressure of 100mtorr-2000mtorr, and a reaction time of 10s-60s; And / or, the reaction conditions for forming the first doping layer are: silane flow rate is 600sccm-1000sccm, phosphine flow rate is 300sccm-600sccm, hydrogen flow rate is 1000sccm-3000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 500s-1500s.

5. The method for preparing a back contact battery according to claim 1, characterized in that: S4 includes: The second tunneling oxide layer is formed by reacting the second tunneling oxide layer under the condition of turning on the glow, wherein the thickness of the second tunneling oxide layer is 4 nm to 6 nm; Silane, phosphine, methane and hydrogen are introduced and reacted under the condition of turning on the glow to form the second doping layer, and the thickness of the second doping layer is 10nm-15nm.

6. The method for preparing a back contact battery according to claim 5, characterized in that: In S4, the reaction conditions for forming the second tunneling oxide layer are: a laughing gas flow rate of 5000sccm-8000sccm, a reaction temperature of 400°C-450°C, a reaction pressure of 100mtorr-2000mtorr, and a reaction time of 10s-60s; And / or, the reaction conditions for forming the second doping layer are: silane flow rate is 200sccm-300sccm, phosphine flow rate is 100sccm-150sccm, methane flow rate is 200sccm-500sccm, hydrogen flow rate is 1000sccm-2000sccm, reaction temperature is 400℃-450℃, reaction pressure is 100mtorr-2000mtorr, and reaction time is 30s-200s.

7. The method for preparing a back contact battery according to claim 1, characterized in that: After S8, the method for preparing the back contact battery further includes: S9. Etching openings on the third semiconductor layer to form second opening regions that are alternately and spaced apart from the first opening regions; S10 forming a conductive film layer on the back side of the silicon wafer; S11. An isolation groove is formed on the conductive film layer so that a portion of the conductive film layer separated from each other extends into the first opening area and covers the third semiconductor layer, and another portion extends into the second opening area and covers the first semiconductor layer; S12. Form a first electrode on the portion of the conductive film layer extending into the first opening region, and form a second electrode on the portion of the conductive film layer extending into the second opening region.

8. A back contact battery, characterized in that: The back contact battery is prepared by the method for preparing a back contact battery as described in any one of claims 1 to 7.

9. A photovoltaic module, characterized in that: Comprising a back contact cell as claimed in claim 8.

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