A method for quickly evaluating the power consumption of parallel port IO simulation circuits

Abstract

The purpose of the present invention is to provide a method for quickly evaluating the power consumption of a parallel port IO analog circuit, the method comprising: configuring the circuit to a preset working mode for simulation, testing the internal DC power consumption of the circuit; configuring the circuit to a preset working mode for simulation, testing the internal flip power consumption of the circuit; obtaining the external DC power consumption of the circuit by calculation; obtaining the external switching power consumption of the circuit by calculation. The present invention can greatly reduce the computing resources and time required to obtain power consumption data, and provides a method for accurately evaluating the power consumption changes of IO analog circuits caused by process migration.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit power consumption testing, and in particular to a method for rapidly evaluating the power consumption of a parallel port IO analog circuit. Background Art

[0002] In the research and development process of high-speed parallel transmission interface (IO) protocol IPs such as DDR, LPDDR, and ONFI, for projects that have been developed, circuit simulation is required to obtain the circuit power consumption under different working modes, configurations, and working speeds. However, the entire IO circuit is often very large, and the simulation time required each time is very long. It takes a very long time to obtain the power consumption under a variety of different modes, configurations, and speeds, especially for high-speed interface IPs that often need to meet multiple protocols today. For projects that have not yet been developed, if you want to evaluate the IO circuit power consumption after migrating from an existing project to a new process, you can only make a rough estimate based on the technicians' experience with different processes, and the power consumption values ​​obtained often have large deviations.

[0003] In the prior art, a large amount of computing resources is required to obtain the power consumption of IO circuits under different working modes, different configurations, and different working rates. For example, for an IO simulation circuit for the LPDDR4 protocol, it is necessary to obtain the power consumption of the three modes that are usually required, namely low power consumption, high-speed writing, and high-speed reading. Each mode needs to be configured under three different configuration combinations of drive strength and termination resistance. The high-speed mode needs to provide power consumption at three different working rates, so at least 21 simulations are required. The time for each simulation will vary depending on the scale of the IO circuit and the amount of computing resources. Assuming that each simulation takes 5 hours (the typical simulation time required for a medium-sized IO circuit using medium-sized computing resources), then plus the time required to build 21 different simulation environments, it takes about 7 days to obtain all the power consumption results, that is, it takes 1.5 weeks to obtain all the required power consumption data. The simulation development cycle of an IO project is often 3 to 6 months, that is, it takes about 6% to 12% of the time just to collect power consumption data, which is a huge consumption of time and computing resources. When we have an IO circuit under a certain process and need to migrate it to a new process, we often need to evaluate the power consumption of the new project. Under current circumstances, this evaluation is usually based on the engineer's experience and estimation of the new process. This has two disadvantages. First, this method is very dependent on the personal experience of the specific engineer; second, this evaluation can only be very rough, and there is often a large deviation from the final IO circuit power consumption after migration. Summary of the invention

[0004] The purpose of the present invention is to provide a method for quickly evaluating the power consumption of a parallel port IO analog circuit, which can greatly reduce the computing resources and time required to obtain power consumption data, and provide a method for accurately evaluating the power consumption changes of the IO analog circuit caused by process migration.

[0005] A method for quickly evaluating the power consumption of a parallel port IO simulation circuit includes:

[0006] Configure the circuit to the preset working mode for simulation and test the internal DC power consumption of the circuit;

[0007] Configure the circuit to the preset working mode for simulation and test the internal flip power consumption of the circuit;

[0008] The external DC power consumption of the circuit is obtained by calculation;

[0009] The external switching power consumption of the circuit is obtained by calculation;

[0010] The power consumption value of the circuit is calculated according to the internal DC power consumption, the internal flipping power consumption, the external DC power consumption and the external switching power consumption.

[0011] Preferably, configuring the circuit to a preset working mode for simulation and testing the internal DC power consumption of the circuit includes:

[0012] In low power mode, turn off all transmitter circuit drivers and termination resistor circuits, simulate the circuit under given high or low static data input, and obtain the internal DC power consumption of the circuit in low power mode;

[0013] In the high-speed write mode, all the transmitter circuit drivers and termination resistor circuits are turned off, and the circuit is simulated under a given high or low static data input to obtain the internal DC power consumption of the circuit in the high-speed write mode;

[0014] In the high-speed read mode, all transmitter circuit drivers and termination resistor circuits are turned off, and the circuit is simulated under a given high or low static data input to obtain the internal DC power consumption of the circuit in the high-speed read mode.

[0015] Preferably, configuring the circuit to a preset working mode for simulation and testing the internal flip power consumption of the circuit includes:

[0016] In the high-speed write mode, all the transmitting circuit drivers and the terminating resistor circuits are turned off, and simulation is performed at a preset working rate. The internal DC power consumption value in the corresponding mode is subtracted from the obtained power consumption value to obtain the internal flip power consumption in the high-speed write mode;

[0017] In the high-speed read mode, all the transmitting circuit drivers and the termination resistor circuits are turned off, and simulation is performed at a preset operating rate. The internal DC power consumption value in the corresponding mode is subtracted from the obtained power consumption value to obtain the internal flip power consumption in the high-speed read mode.

[0018] Preferably, the power consumption value of the circuit calculated according to the internal DC power consumption, the internal flip power consumption, the external DC power consumption and the external switching power consumption includes:

[0019] In the low power consumption mode, the power consumption in the low power consumption mode is obtained by adding the external DC power consumption and the internal DC power consumption;

[0020] In the high-speed write mode, the high-speed write internal flip power consumption at the rate DR1 obtained by simulation, the high-speed write external DC power consumption obtained by ideal circuit simulation, the high-speed write external switching power consumption and the high-speed write internal DC power consumption obtained by simulation are added to obtain the high-speed write mode power consumption at any data rate;

[0021] In the high-speed read mode, the high-speed read internal flip power consumption at the simulated rate DR1 is added to the calculated high-speed read external DC power consumption and the simulated high-speed read internal DC power consumption to obtain the high-speed read mode power consumption at any data rate.

[0022] Preferably, obtaining the external switching power consumption of the circuit by calculation includes:

[0023] By estimating the circuit's parasitic capacitance at the output;

[0024] Calculate the external switching power consumption;

[0025] If the parasitic capacitance of the circuit at the output end cannot be estimated, the capacitance value under the current process is used to calculate the external switching power consumption.

[0026] Preferably, configuring the circuit to a preset working mode for simulation and testing the internal DC power consumption of the circuit includes:

[0027] If there is no bias current in the circuit, compare the leakage of an inverter circuit under different processes and calculate the value of the internal DC power consumption under the new process through proportional conversion;

[0028] If there is bias current in the circuit, the internal DC power consumption is divided into leakage power consumption and bias power consumption for calculation;

[0029] The leakage power consumption is evaluated using an inverter circuit, the bias power consumption is used with the original value, and the leakage power consumption and bias power consumption are added together to obtain the internal DC power consumption under the new process.

[0030] Preferably, configuring the circuit to a preset working mode for simulation and testing the internal flip power consumption of the circuit includes:

[0031] Internal flip power consumption in high-speed write mode, simulated and tested using a level converter circuit;

[0032] Internal flip power consumption in high-speed read mode. If the circuit does not have internal flip power consumption, there is no need to evaluate the internal flip power consumption;

[0033] If the circuit has internal upset power consumption, the circuit modules are specifically selected for internal upset power consumption testing according to the characteristics of each circuit architecture.

[0034] Preferably, the internal DC power consumption includes the power consumption generated by the static current inside the circuit when the input data is not flipped;

[0035] Internal flip power consumption includes the additional power consumption caused by data flipping inside the circuit when the input data flips;

[0036] External DC power consumption includes the power consumption generated by the circuit supplying power to the external circuit;

[0037] External switching power consumption includes the additional power consumption caused by data flipping when the circuit is powered externally.

[0038] A system for quickly evaluating the power consumption of a parallel port IO simulation circuit, comprising:

[0039] An internal DC power consumption test module is used to configure the circuit to a preset working mode for simulation and test the internal DC power consumption of the circuit;

[0040] An internal flip power consumption test module is used to configure the circuit to a preset working mode for simulation and test the internal flip power consumption of the circuit;

[0041] An external DC power consumption test module is used to obtain the external DC power consumption of the circuit by calculation;

[0042] An external switching power consumption test module is used to obtain the external switching power consumption of the circuit by calculation;

[0043] The circuit power consumption test module is used to calculate the power consumption value of the circuit according to the internal DC power consumption, the internal flip power consumption, the external DC power consumption and the external switching power consumption.

[0044] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program codes, the computer program codes comprise computer instructions, and the electronic device executes a method for rapidly evaluating the power consumption of a parallel port IO analog circuit.

[0045] The beneficial effects of the present invention are as follows: 1. The present invention functionally deconstructs the power consumption of the IO analog circuit and divides it into four unique parts. Each part can be directly obtained through theoretical calculation or can be reused simulation data. By combining and utilizing these four parts of data, the accurate value of the power consumption of the IO analog circuit under various working modes, configurations, and rates can be obtained. The division of these four power consumption parts is the best division method. The continued division of any part is redundant, and the merging of any two parts cannot achieve a reasonable estimate of the total power consumption; 2. The present invention provides a module for simulating power consumption conversion for the power consumption of the process-related parts when the circuit is migrated to a new process. For internal DC power consumption, an inverter circuit should be selected; for internal flip power consumption of high-speed writing, a level converter circuit should be selected. The selection of these two circuits follows two important principles. First, the selected circuit module should be simple enough to be quickly built and quickly obtain simulation results; second, the power consumption ratio obtained can accurately reflect the ratio of the power consumption of the corresponding part of the entire circuit under different processes. The selection of these two modules meets these two requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0048] Figure 1 A flow chart of a method for quickly evaluating power consumption of a parallel port IO analog circuit according to the present invention;

[0049] Figure 2 A schematic diagram of a method for calculating power consumption of a parallel port IO analog circuit according to the present invention;

[0050] Figure 3 It is a schematic diagram of the internal DC power consumption flow of the test circuit of the present invention;

[0051] Figure 4 It is a schematic diagram of the internal flip power consumption flow of the test circuit of the present invention;

[0052] Figure 5 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0055] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0056] In the prior art, a large amount of computing resources is required to obtain the power consumption of IO circuits under different working modes, different configurations, and different working rates. For example, for an IO simulation circuit for the LPDDR4 protocol, it is necessary to obtain the power consumption of the three modes that are usually required, namely low power consumption, high-speed writing, and high-speed reading. Each mode needs to be configured under three different configuration combinations of drive strength and termination resistance. The high-speed mode needs to provide power consumption at three different working rates, so at least 21 simulations are required. The time for each simulation will vary depending on the scale of the IO circuit and the amount of computing resources. Assuming that each simulation takes 5 hours (the typical simulation time required for a medium-sized IO circuit using medium-sized computing resources), then plus the time required to build 21 different simulation environments, it takes about 7 days to obtain all the power consumption results, that is, it takes 1.5 weeks to obtain all the required power consumption data. The simulation development cycle of an IO project is often 3 to 6 months, that is, it takes about 6% to 12% of the time just to collect power consumption data, which is a huge consumption of time and computing resources. When we have an IO circuit under a certain process and need to migrate it to a new process, we often need to evaluate the power consumption of the new project. Under current circumstances, this evaluation is usually based on the engineer's experience and estimation of the new process. This has two disadvantages. First, this method is very dependent on the personal experience of the specific engineer; second, this evaluation can only be very rough, and there is often a large deviation from the final IO circuit power consumption after migration.

[0057] The present invention functionally deconstructs the power consumption of the IO analog circuit and divides it into four unique parts. Each part can be directly obtained through theoretical calculation or can be reused simulation data. By combining the four parts of data, the accurate value of the power consumption of the IO analog circuit under various working modes, configurations, and rates can be obtained. The division of these four power consumption parts is the best division method. The continued division of any part is redundant, and the merging of any two parts cannot achieve a reasonable estimate of the total power consumption; the present invention provides a module for simulating power consumption conversion for the power consumption of the process-related parts when the circuit is migrated to a new process. For internal DC power consumption, an inverter circuit should be selected; for internal flip power consumption of high-speed writing, a level converter circuit should be selected. The selection of these two circuits follows two important principles. First, the selected circuit module should be simple enough to be quickly built and quickly obtain simulation results; second, the power consumption ratio obtained can accurately reflect the ratio of the power consumption of the corresponding part of the entire circuit under different processes. The selection of these two modules meets these two requirements.

[0058] Example 1

[0059] A method for quickly evaluating the power consumption of parallel port IO simulation circuits, refer to Figure 1,include:

[0060] S100, configuring the circuit to a preset working mode for simulation, and testing the internal DC power consumption of the circuit;

[0061] S200, configuring the circuit to a preset working mode for simulation, and testing the internal flip power consumption of the circuit;

[0062] S300, obtaining the external DC power consumption of the circuit by calculation;

[0063] S400, obtaining the external switching power consumption of the circuit by calculation;

[0064] S500, calculating the power consumption value of the circuit according to the internal DC power consumption, the internal flipping power consumption, the external DC power consumption and the external switching power consumption.

[0065] When the circuit works in low power mode, there is no signal flipping in the circuit, only internal DC power consumption and external DC power consumption. Internal DC power consumption is the static power consumption under the current configuration. External DC power consumption is related to the different configurations of the transmitting circuit drive strength and the external termination resistor, and has nothing to do with the process and circuit design.

[0066] When the circuit works in high-speed write mode, all four types of power consumption exist. Internal DC power consumption is the static power consumption under the current configuration and has nothing to do with the operating speed. Internal flip power consumption is proportional to the operating speed. External DC power consumption is related to the different configurations of the transmitting circuit drive strength and the external termination resistor, and has nothing to do with the speed, process and circuit design. External switching power consumption is related to the size of the output parasitic capacitance and load capacitance and the circuit operating speed, and has nothing to do with the process.

[0067] When the circuit operates in high-speed read mode, there may be two or three types of power consumption. Internal DC power consumption is the static power consumption under the current configuration and has nothing to do with the operating rate. Depending on the different architectures used in the receiving circuit, internal flip power consumption may or may not exist. If it does exist, it is proportional to the operating rate. External DC power consumption is related to the drive strength of the external transmitting circuit and the different configurations of the internal termination resistors, and has nothing to do with the rate, process, and circuit design. In high-speed read mode, there is no external switching power consumption.

[0068] It can be seen that no matter which working mode is used, there is a part of power consumption that is unrelated to the process and circuit design. External DC power consumption has nothing to do with the process and circuit design, but only with the protocol and working mode. External switching power consumption is only related to the total capacitance of the circuit at the output end, and the total capacitance is dominated by the load capacitance, which has nothing to do with the process and design of the IO circuit. Therefore, even if we don’t have any circuits at hand, we can accurately calculate the values ​​of external DC power consumption and external switching power consumption. For the external DC power consumption and external switching power consumption of the high-speed write circuit, we can build an ideal model for simulation to quickly obtain the sum of these two parts of power consumption under different emission circuit drive strengths and external termination resistor configurations and different load capacitance sizes. The simulation time of the ideal model is very fast and can be ignored.

[0069] Preferably, reference Figure 3 , S100, configure the circuit to a preset working mode for simulation, and test the internal DC power consumption of the circuit including:

[0070] S110, turning off all transmitting circuit drivers and termination resistor circuits in the low power consumption mode, simulating the circuit under a given high or low static data input, and obtaining the internal DC power consumption of the circuit in the low power consumption mode;

[0071] S120, turning off all transmitter circuit drivers and termination resistor circuits in the high-speed write mode, simulating the circuit under a given high or low static data input, and obtaining the internal DC power consumption of the circuit in the high-speed write mode;

[0072] S130, turning off all transmitter circuit drivers and termination resistor circuits in the high-speed read mode, simulating the circuit under a given high or low static data input, and obtaining the internal DC power consumption of the circuit in the high-speed read mode.

[0073] For internal DC power consumption, we need to perform circuit simulation. Configure the circuit to the corresponding operating mode, turn off all the transmitter circuit drivers and termination resistor circuits, and simulate under given high or low static data input to get the internal DC power consumption. The internal DC power consumption has nothing to do with the configuration combination of drive strength and termination resistors and the operating rate. Therefore, if we continue to use the example given above, we only need to simulate once in low power consumption, high-speed write, and high-speed read modes, that is, simulate 3 different internal DC power consumption values.

[0074] Preferably, reference Figure 4 , S200, configure the circuit to the preset working mode for simulation, and test the internal flip power consumption of the circuit including:

[0075] S210, turning off all transmitting circuit drivers and termination resistor circuits in the high-speed write mode, performing simulation at a preset working rate, and subtracting the internal DC power consumption value in the corresponding mode from the obtained power consumption value to obtain the internal flip power consumption in the high-speed write mode;

[0076] S220, turning off all transmitting circuit drivers and termination resistor circuits in the high-speed read mode, performing simulation at a preset working rate, subtracting the internal DC power consumption value in the corresponding mode from the obtained power consumption value, and obtaining the internal flip power consumption in the high-speed read mode.

[0077] We also need to perform circuit simulation for internal flip power consumption. Configure the circuit to the corresponding working mode, turn off all the transmitting circuit drivers and termination resistor circuits, simulate at a certain working rate, and subtract the internal DC power consumption value in the corresponding mode from the power consumption value to get the internal flip power consumption. The internal flip power consumption has nothing to do with the configuration combination of the drive strength and the termination resistor, and is proportional to the working rate. In other words, we only need to simulate the internal flip power consumption at one rate to calculate the internal flip power consumption at all working rates. If we continue with the example given above, we only need to simulate once in the high-speed write and high-speed read (according to the circuit architecture, high-speed reading does not necessarily require internal flip power consumption) modes at one working rate, that is, a maximum of 2 different internal flip power consumption values ​​can be simulated.

[0078] Preferably, in S500, calculating the power consumption value of the circuit according to the internal DC power consumption, the internal flip power consumption, the external DC power consumption and the external switching power consumption includes:

[0079] In the low power consumption mode, the power consumption in the low power consumption mode is obtained by adding the external DC power consumption and the internal DC power consumption;

[0080] For the low power mode, the power consumption in the low power mode can be obtained by adding the calculated low power external DC power consumption and the simulated low power internal DC power consumption.

[0081] In the high-speed write mode, the high-speed write internal flip power consumption at the rate DR1 obtained by simulation, the high-speed write external DC power consumption obtained by ideal circuit simulation, the high-speed write external switching power consumption and the high-speed write internal DC power consumption obtained by simulation are added to obtain the high-speed write mode power consumption at any data rate;

[0082] For the high-speed write mode, assuming that the high-speed write internal flip power consumption at rate DR1 is simulated, the high-speed write external DC power consumption and high-speed write external switching power consumption obtained through ideal circuit simulation, the high-speed write internal flip power consumption at rate DR1 obtained through simulation, and the high-speed write internal DC power consumption obtained through simulation can be added to obtain the high-speed write mode power consumption at rate DR1. The high-speed write mode power consumption at any other rate can also be obtained. It is only necessary to perform a simple calculation on the high-speed write internal flip power consumption at rate DR1 obtained through simulation, and then add it to the high-speed write external DC power consumption and high-speed write external switching power consumption obtained through ideal circuit simulation, and the high-speed write internal DC power consumption obtained through simulation to obtain the high-speed write mode power consumption at any other data rate.

[0083] In the high-speed read mode, the high-speed read internal flip power consumption at the simulated rate DR1 is added to the calculated high-speed read external DC power consumption and the simulated high-speed read internal DC power consumption to obtain the high-speed read mode power consumption at any data rate.

[0084] For the high-speed read mode, the internal flip power consumption may or may not exist depending on the different architectures of the receiving circuit. When the high-speed read internal flip power consumption does not exist, the high-speed read mode power consumption at any rate is a fixed value, which is the sum of the high-speed read external DC power consumption obtained by theoretical calculation and the high-speed read internal DC power consumption obtained by simulation. When the high-speed read internal flip power consumption exists, the high-speed read mode power consumption is related to the data rate. Assuming that the high-speed read internal flip power consumption at rate DR1 is simulated, the high-speed read mode power consumption at rate DR1 can be obtained by simply adding the high-speed read external DC power consumption obtained by calculation, the high-speed read internal flip power consumption at rate DR1 obtained by simulation, and the high-speed read internal DC power consumption obtained by simulation. For the high-speed read mode power consumption at any other rate, it can be obtained. It is only necessary to perform a simple calculation on the high-speed read internal flip power consumption at rate DR1 obtained by simulation, and then add it to the high-speed read external DC power consumption obtained by calculation and the high-speed read internal DC power consumption obtained by simulation, to obtain the high-speed read mode power consumption at any other data rate.

[0085] Preferably, in S400, obtaining the external switching power consumption of the circuit by calculation includes:

[0086] By estimating the circuit's parasitic capacitance at the output;

[0087] Calculate the external switching power consumption;

[0088] If the parasitic capacitance of the circuit at the output end cannot be estimated, the capacitance value under the current process is used to calculate the external switching power consumption.

[0089] Parasitic capacitance refers to the unintentional capacitance in a circuit or component, also known as secondary capacitance or stray capacitance. This capacitance is due to the mutual capacitance between wirings, which is like parasitic between wirings, hence the name. Parasitic capacitance itself is not a capacitor, but due to the mutual capacitance between wirings or components, they exhibit the characteristics of capacitance. Parasitic capacitance cannot be avoided, and generally has a greater impact on the circuit in high-frequency circuits, so special consideration is required when wiring the circuit. Parasitic capacitance generally refers to the capacitance characteristics of inductors, resistors, chip pins, etc. at high frequencies. In fact, a resistor is equivalent to a capacitor, an inductor and a resistor in series, which is not obvious at low frequencies, but at high frequencies, the equivalent value will increase and cannot be ignored. The causes of parasitic capacitance include the capacitance formed between wires in the circuit, the mutual capacitance between inductor windings, between chip pins, and between power semiconductor pins. These parasitic capacitances will cause charge accumulation and storage, thereby affecting the performance and working characteristics of the circuit. Especially at high frequencies, the performance of parasitic capacitance is more significant, which may cause signal delays, reduce switching speeds, and may cause signal waveform distortion.

[0090] In order to reduce the impact of parasitic capacitance on the circuit, a series of measures can be taken, such as optimizing layout and wiring, reducing wire length and area, using appropriate packaging and ground wire design, using low dielectric constant insulating materials, optimizing MOS structure design, etc., to reduce the impact of parasitic capacitance and improve circuit performance and reliability.

[0091] In PCB design, the parasitic capacitance of a trace can be calculated by determining the parasitic capacitance between the two conductors to be calculated, then determining the effective length and relative position between the two conductors, and then using the appropriate formula to calculate the value of the parasitic capacitance.

[0092] The external switching power consumption can be calculated by estimating the parasitic capacitance of the circuit at the output end. If it cannot be estimated, we can use the capacitance value under the current process because this part of the power consumption will be dominated by the external load capacitance.

[0093] Preferably, S100, configuring the circuit to a preset working mode for simulation, and testing the internal DC power consumption of the circuit further includes:

[0094] If there is no bias current in the circuit, compare the leakage of an inverter circuit under different processes and calculate the value of the internal DC power consumption under the new process through proportional conversion;

[0095] If there is bias current in the circuit, the internal DC power consumption is divided into leakage power consumption and bias power consumption for calculation;

[0096] The leakage power consumption is evaluated using an inverter circuit, the bias power consumption is used with the original value, and the leakage power consumption and bias power consumption are added together to obtain the internal DC power consumption under the new process.

[0097] Bias current is the base DC current of the amplifier input transistor, which ensures that the amplifier operates in the linear range and provides a DC operating point for the amplifier. In an op amp (operational amplifier), bias current involves the performance of the op amp and circuit design considerations. An op amp is a transistor amplifier integrated on a chip, and its bias current is usually provided by an external circuit, because it is impossible for the op amp itself to integrate a current source that provides bias current on the chip. The value of the bias current is usually very small, and the input resistor and feedback resistor of a general operational circuit can provide this current. However, the bias current value of the op amp also limits the input resistor and feedback resistor values ​​to not be too large, so as to avoid the voltage drop on the resistor being comparable to the operational voltage and affecting the operational accuracy. If the design requires the use of large feedback resistors and input resistors, you can consider using an op amp with J-FET input, because J-FET is a voltage-controlled device, and its input bias current parameter refers to the reverse leakage current of the input PN junction, which is in the order of pA. Similarly, MOSFET devices can also provide smaller input leakage currents. The existence of bias current has an important impact on circuit design. In actual amplifiers, a small amount of current will flow into the two input terminals. The average value of these currents is defined as the input bias current (Ib), and the difference between the currents flowing through the two input terminals is defined as the input offset current (Ios). Input bias current and offset current are key parameters that need to be considered when designing op amps because they directly affect the performance of the op amp and the accuracy of the circuit. Especially in low-level signal amplification or precision measurement applications, the errors caused by bias current must be carefully considered and controlled.

[0098] Internal DC power consumption is related to the process. In order to obtain this value, we need to distinguish different circuit designs. If there is no bias current in the circuit, we only need to compare the leakage of an inverter circuit under different processes, and we can use this ratio to calculate the value of the internal DC power consumption under the new process. If there is a bias current in the circuit, the internal DC power consumption is divided into leakage power consumption and bias power consumption for calculation. The leakage power consumption is also evaluated using a simple inverter circuit, and the bias power consumption is the original value. The addition of the two gives the internal DC power consumption under the new process.

[0099] Preferably, S200, configuring the circuit to a preset working mode for simulation, and testing the internal flip power consumption of the circuit includes:

[0100] Internal flip power consumption in high-speed write mode, simulated and tested using a level converter circuit;

[0101] Internal flip power consumption in high-speed read mode. If the circuit does not have internal flip power consumption, there is no need to evaluate the internal flip power consumption;

[0102] If the circuit has internal upset power consumption, the circuit modules are specifically selected for internal upset power consumption testing according to the characteristics of each circuit architecture.

[0103] Internal flip power consumption is related to the process, and we can evaluate it by selecting typical modules in the circuit. For internal flip power consumption in high-speed write mode, a typical choice is a level converter circuit. In the IO transmission circuit, a level converter is required on the high-speed data path. Compare the internal flip power consumption of the level converter circuit under different processes, and then use this ratio to convert the internal flip power consumption in high-speed write mode under the new process. For internal flip power consumption in high-speed read mode, it is necessary to distinguish between different circuit designs. If the circuit structure determines that the circuit does not have internal flip power consumption (such as using an amplifier structure with a tail current source), there is no need to evaluate this part; if the circuit has internal flip power consumption, then select a typical module for evaluation. The architecture of the receiving circuit is often quite different, and it needs to be selected according to the characteristics of each architecture.

[0104] Preferably, reference Figure 2 ,The internal DC power consumption includes the power consumption generated by the static current inside the circuit when the input data is not flipped;

[0105] Internal flip power consumption includes the additional power consumption caused by data flipping inside the circuit when the input data flips;

[0106] External DC power consumption includes the power consumption generated by the circuit supplying power to the external circuit;

[0107] External switching power consumption includes the additional power consumption caused by data flipping when the circuit is powered externally.

[0108] According to the characteristics of the high-speed parallel transmission interface analog circuit, its power consumption can be divided into four components: internal DC power consumption, internal flip power consumption, external DC power consumption, and external switching power consumption. Internal DC power consumption refers to the power consumption generated by the static current inside the circuit when the input data is not flipped; internal flip power consumption refers to the additional power consumption caused by data flipping inside the circuit when the input data is flipped; external DC power consumption refers to the power consumption generated by the circuit supplying power to the external circuit; external switching power consumption refers to the additional power consumption caused by data flipping when the circuit supplies power to the outside.

[0109] In the present invention, the specific architecture of the IO simulation circuit is not given, and corresponding different evaluation methods are given for the architectures used by different IO circuits. This power consumption evaluation method can be used in all high-speed parallel transmission IO simulation circuits. The present invention divides the power consumption of the IO simulation circuit into four parts and gives relevant definitions. As long as the classification method of the power consumption is the same according to this definition, no matter what name is given to these four parts of power consumption, the power consumption evaluation method of the present invention can be used to solve it. Since the external DC power consumption and external switching power consumption have almost nothing to do with the process and circuit design, they can be obtained only by calculation. Therefore, no matter how the calculation is done, it not only includes manual estimation but also simulation.

[0110] The results of 5 simulations of the present invention can obtain the power consumption values ​​under all 21 different conditions, reducing the number of simulations required from 21 to 5. In this specific example, the configuration combination of the required drive strength and the termination resistance and the number of operating rate scenarios are arbitrarily specified. If these two requirements increase, the reduction in the number of simulations brought about by the method of the present invention will be more significant.

[0111] Example 2

[0112] A system for quickly evaluating the power consumption of a parallel port IO simulation circuit, comprising:

[0113] An internal DC power consumption test module is used to configure the circuit to a preset working mode for simulation and test the internal DC power consumption of the circuit;

[0114] An internal flip power consumption test module is used to configure the circuit to a preset working mode for simulation and test the internal flip power consumption of the circuit;

[0115] An external DC power consumption test module is used to obtain the external DC power consumption of the circuit by calculation;

[0116] An external switching power consumption test module is used to obtain the external switching power consumption of the circuit by calculation;

[0117] The circuit power consumption test module is used to calculate the power consumption value of the circuit according to the internal DC power consumption, internal flip power consumption, external DC power consumption and external switching power consumption.

[0118] The present invention functionally deconstructs the power consumption of the IO analog circuit, analyzes and calculates according to the characteristics of each part, obtains the maximum amount of power consumption information from the least simulation data, greatly reduces the computing resources and time required to collect power consumption data, and summarizes the methodology for accurately estimating the power consumption evaluation of the IO analog circuit when migrating to the new process, so that reasonable power consumption evaluation can be achieved. By adding the power consumption of each part in the manner described above, the power consumption value of the new process under different conditions can be obtained.

[0119] Example 3

[0120] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program codes, the computer program codes include computer instructions, and the electronic device executes a method for rapidly evaluating the power consumption of a parallel port IO analog circuit.

[0121] refer to Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0122] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0123] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0124] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0125] The present invention functionally deconstructs the power consumption of the IO analog circuit and divides it into four unique parts. Each part can be directly obtained through theoretical calculation or can be reused simulation data. By combining the four parts of data, the accurate value of the power consumption of the IO analog circuit under various working modes, configurations, and rates can be obtained. The division of these four power consumption parts is the best division method. The continued division of any part is redundant, and the merging of any two parts cannot achieve a reasonable estimate of the total power consumption; the present invention provides a module for simulating power consumption conversion for the power consumption of the process-related parts when the circuit is migrated to a new process. For internal DC power consumption, an inverter circuit should be selected; for internal flip power consumption of high-speed writing, a level converter circuit should be selected. The selection of these two circuits follows two important principles. First, the selected circuit module should be simple enough to be quickly built and quickly obtain simulation results; second, the power consumption ratio obtained can accurately reflect the ratio of the power consumption of the corresponding part of the entire circuit under different processes. The selection of these two modules meets these two requirements.

[0126] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for quickly evaluating the power consumption of a parallel port IO analog circuit, characterized in that: include: Configure the circuit to the preset working mode for simulation and test the internal DC power consumption of the circuit; The circuit is configured to a preset working mode for simulation, and the internal DC power consumption of the test circuit also includes: If there is no bias current in the circuit, compare the leakage of an inverter circuit under different processes and calculate the value of the internal DC power consumption under the new process through proportional conversion; If there is bias current in the circuit, the internal DC power consumption is divided into leakage power consumption and bias power consumption for calculation; The leakage power consumption is evaluated using an inverter circuit, the bias power consumption is taken as the original value, and the leakage power consumption and bias power consumption are added together to obtain the internal DC power consumption under the new process; Configure the circuit to the preset working mode for simulation and test the internal flip power consumption of the circuit; The circuit is configured to a preset working mode for simulation, and the internal flip power consumption of the test circuit includes: Internal flip power consumption in high-speed write mode, simulated and tested using a level converter circuit; Internal flip power consumption in high-speed read mode. If the circuit does not have internal flip power consumption, there is no need to evaluate the internal flip power consumption; If the circuit has internal flip power consumption, the circuit module is selected according to the characteristics of each circuit architecture to perform internal flip power consumption test; The external DC power consumption of the circuit is obtained by calculation; The external switching power consumption of the circuit is obtained by calculation; Calculating the power consumption value of the circuit according to the internal DC power consumption, the internal flipping power consumption, the external DC power consumption and the external switching power consumption; The power consumption value of the circuit calculated according to the internal DC power consumption, the internal flip power consumption, the external DC power consumption and the external switching power consumption includes: In the low power consumption mode, the power consumption in the low power consumption mode is obtained by adding the external DC power consumption and the internal DC power consumption; In the high-speed write mode, the high-speed write internal flip power consumption at the rate DR1 obtained by simulation, the high-speed write external DC power consumption obtained by ideal circuit simulation, the high-speed write external switching power consumption and the high-speed write internal DC power consumption obtained by simulation are added to obtain the high-speed write mode power consumption at any data rate; In the high-speed read mode, the high-speed read internal flip power consumption at the simulated rate DR1 is added to the calculated high-speed read external DC power consumption and the simulated high-speed read internal DC power consumption to obtain the high-speed read mode power consumption at any data rate.

2. A method for quickly evaluating power consumption of a parallel port IO analog circuit according to claim 1, characterized in that: The circuit is configured to a preset working mode for simulation, and the internal DC power consumption of the test circuit includes: In low power mode, turn off all transmitter circuit drivers and termination resistor circuits, simulate the circuit under given high or low static data input, and obtain the internal DC power consumption of the circuit in low power mode; In the high-speed write mode, all the transmitter circuit drivers and termination resistor circuits are turned off, and the circuit is simulated under a given high or low static data input to obtain the internal DC power consumption of the circuit in the high-speed write mode; In the high-speed read mode, all transmitter circuit drivers and termination resistor circuits are turned off, and the circuit is simulated under a given high or low static data input to obtain the internal DC power consumption of the circuit in the high-speed read mode.

3. The method for quickly evaluating the power consumption of a parallel port IO analog circuit according to claim 1, characterized in that: The circuit is configured to a preset working mode for simulation, and the internal flip power consumption of the test circuit includes: In the high-speed write mode, all the transmitting circuit drivers and the terminating resistor circuits are turned off, and simulation is performed at a preset working rate. The internal DC power consumption value in the corresponding mode is subtracted from the obtained power consumption value to obtain the internal flip power consumption in the high-speed write mode; In the high-speed read mode, all the transmitting circuit drivers and the termination resistor circuits are turned off, and simulation is performed at a preset operating rate. The internal DC power consumption value in the corresponding mode is subtracted from the obtained power consumption value to obtain the internal flip power consumption in the high-speed read mode.

4. The method for quickly evaluating the power consumption of a parallel port IO analog circuit according to claim 1, characterized in that: The external switching power consumption of the circuit obtained by calculation also includes: By estimating the circuit's parasitic capacitance at the output; Calculate the external switching power consumption; If the parasitic capacitance of the circuit at the output end cannot be estimated, the capacitance value under the current process is used to calculate the external switching power consumption.

5. The method for quickly evaluating the power consumption of a parallel port IO analog circuit according to claim 1, characterized in that: The internal DC power consumption includes the power consumption generated by the static current inside the circuit when the input data is not flipped; Internal flip power consumption includes the additional power consumption caused by data flipping inside the circuit when the input data flips; External DC power consumption includes the power consumption generated by the circuit supplying power to the external circuit; External switching power consumption includes the additional power consumption caused by data flipping when the circuit is powered externally.

6. A system for quickly evaluating the power consumption of a parallel port IO analog circuit, characterized in that: include: An internal DC power consumption test module is used to configure the circuit to a preset working mode for simulation and test the internal DC power consumption of the circuit; The circuit is configured to a preset working mode for simulation, and the internal DC power consumption of the test circuit also includes: If there is no bias current in the circuit, compare the leakage of an inverter circuit under different processes and calculate the value of the internal DC power consumption under the new process through proportional conversion; If there is bias current in the circuit, the internal DC power consumption is divided into leakage power consumption and bias power consumption for calculation; The leakage power consumption is evaluated using an inverter circuit, the bias power consumption is taken as the original value, and the leakage power consumption and bias power consumption are added together to obtain the internal DC power consumption under the new process; An internal flip power consumption test module is used to configure the circuit to a preset working mode for simulation and test the internal flip power consumption of the circuit; The circuit is configured to a preset working mode for simulation, and the internal flip power consumption of the test circuit includes: Internal flip power consumption in high-speed write mode, simulated and tested using a level converter circuit; Internal flip power consumption in high-speed read mode. If the circuit does not have internal flip power consumption, there is no need to evaluate the internal flip power consumption; If the circuit has internal flip power consumption, the circuit module is selected according to the characteristics of each circuit architecture to perform internal flip power consumption test; An external DC power consumption test module is used to obtain the external DC power consumption of the circuit by calculation; An external switching power consumption test module is used to obtain the external switching power consumption of the circuit by calculation; A circuit power consumption test module, used for calculating the power consumption value of the circuit according to the internal DC power consumption, the internal flip power consumption, the external DC power consumption and the external switching power consumption; The power consumption value of the circuit calculated according to the internal DC power consumption, the internal flip power consumption, the external DC power consumption and the external switching power consumption includes: In the low power consumption mode, the power consumption in the low power consumption mode is obtained by adding the external DC power consumption and the internal DC power consumption; In the high-speed write mode, the high-speed write internal flip power consumption at the rate DR1 obtained by simulation, the high-speed write external DC power consumption obtained by ideal circuit simulation, the high-speed write external switching power consumption and the high-speed write internal DC power consumption obtained by simulation are added to obtain the high-speed write mode power consumption at any data rate; In the high-speed read mode, the high-speed read internal flip power consumption at the simulated rate DR1 is added to the calculated high-speed read external DC power consumption and the simulated high-speed read internal DC power consumption to obtain the high-speed read mode power consumption at any data rate.

7. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for quickly evaluating the power consumption of a parallel port IO analog circuit as described in any one of claims 1 to 5.

Images