A method and system for manufacturing a semiconductor memory chip

Abstract

The present invention relates to the field of chip manufacturing, and proposes a method and system for realizing the preparation of semiconductor memory chips, the method comprising: first obtaining chip parameters, selecting semiconductor materials and pre-processing, determining the area to be deposited, and then depositing insulating layers and conductive layers to build a multi-layer structure framework, and then determining the optimal thickness and layout of each layer and calculating the expected reading and writing values, then determining the performance indicators according to the expected reading and writing values, evaluating the feasibility of preparation to obtain preparation evaluation data, querying the influencing factors to calculate the influence degree value, and then configuring the packaging materials according to the influence degree value to build a curing environment, monitoring the curing process state and tracing the abnormality, and finally analyzing the target concentrated in the abnormal source, identifying the abnormal storage factor, and generating a chip preparation plan based on this monitoring feedback data. The present invention can improve the preparation stability of semiconductor memory chips.

Description

Technical Field

[0001] The present invention relates to the field of chip manufacturing, and in particular to a method and system for manufacturing a semiconductor memory chip. Background Art

[0002] In today's electronic information field, the importance of semiconductor memory chips is becoming increasingly prominent, and they are widely used in many fields such as computers, smart phones, data centers, etc. In the preparation method of semiconductor memory chips, advanced technical means are crucial and have great significance for improving the performance, capacity and reliability of memory chips.

[0003] At present, the traditional preparation of semiconductor memory chips mainly relies on established process flows and relatively single technologies. This approach has gradually revealed its limitations in the face of growing storage needs and increasingly complex application scenarios. On the one hand, the production efficiency of traditional preparation methods is relatively low, which consumes a lot of time and resource costs, and it is difficult to ensure the consistency and stability of the chips. On the other hand, conventional preparation methods are difficult to meet some emerging application requirements, such as high-speed data transmission, low-power operation, etc., resulting in the inability to accurately prepare semiconductor memory chips that meet the needs of new electronic devices. Therefore, a method for preparing semiconductor memory chips is needed to improve the preparation stability of semiconductor memory chips. Summary of the invention

[0004] The present invention provides a method and system for manufacturing a semiconductor memory chip, the main purpose of which is to improve the manufacturing stability of the semiconductor memory chip.

[0005] Obtaining chip parameters corresponding to the memory chip to be prepared, selecting semiconductor materials corresponding to the memory chip to be prepared according to the chip parameters, and performing material pretreatment on the semiconductor materials to obtain pretreated semiconductor materials;

[0006] Determine a region to be deposited corresponding to the pretreated semiconductor material, and after depositing an insulating layer and a conductive layer on the region to be deposited, construct a multi-layer structural framework corresponding to the memory chip to be prepared, determine the optimal thickness and layout of each layer of the memory chip to be prepared based on the multi-layer structural framework, and calculate the expected read and write values ​​corresponding to the memory chip to be prepared according to the optimal thickness and layout;

[0007] Based on the expected read / write values, determining the performance index of the memory chip to be prepared, based on the performance index, evaluating the feasibility of preparing the memory chip to be prepared, obtaining preparation evaluation data, querying the preparation influencing factors existing in the preparation evaluation data, and calculating the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factors;

[0008] Based on the impact degree value, configuring the packaging material corresponding to the storage chip to be prepared, constructing the curing environment corresponding to the storage chip to be prepared based on the packaging material, monitoring the curing process state of the chip in the curing environment, extracting the process parameters corresponding to the curing process state, tracing the abnormality of the process parameters, and obtaining the abnormality source set;

[0009] Analyze the abnormal targets in the abnormal source set, identify abnormal storage factors in the abnormal targets, monitor the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factors, and generate a chip preparation plan corresponding to the storage chip to be prepared based on the preparation feedback data.

[0010] Optionally, the pre-processing the semiconductor material to obtain the processed semiconductor material includes:

[0011] Analyzing material properties corresponding to the semiconductor material;

[0012] Based on the material properties, determining surface distribution characteristics corresponding to the semiconductor material;

[0013] extracting key impurity factors in the surface distribution characteristics;

[0014] Based on the key impurity factors, analyzing the potential defect types corresponding to the semiconductor material;

[0015] Based on the potential defect type, the semiconductor material is subjected to defect treatment to obtain a treated semiconductor material.

[0016] Optionally, determining the area to be deposited corresponding to the processed semiconductor material includes:

[0017] Analyzing the physical structural characteristics of the processed semiconductor material;

[0018] Based on the physical structural characteristics, querying the potential deposition sites on the surface of the processed semiconductor material corresponding to the material;

[0019] Performing data evaluation on the potential deposition site to obtain deposition evaluation data;

[0020] extracting dominant deposition sites from the deposition assessment data;

[0021] Based on the advantageous deposition sites, a region to be deposited corresponding to the pretreated semiconductor material is determined.

[0022] Optionally, the calculating, according to the optimal thickness and layout, the expected read / write values ​​corresponding to the memory chip to be prepared includes:

[0023] The expected read / write value corresponding to the memory chip to be prepared is calculated using the following formula:

[0024]

[0025] in, Indicates the read time corresponding to the storage chip to be prepared, represents the length of the interconnect in the layout, Indicates that the resistivity of the memory chip to be prepared varies with temperature The change function of represents the optimum thickness, represents the line width in the layout, represents the line spacing in the layout, represents the driving voltage of the read / write circuit in the memory chip to be prepared, Indicates the length of the interconnect line The length of the differential element when performing the integration, represents a function of the signal transmission delay factor in the memory chip to be prepared varying with temperature, represents the capacitance value of the storage unit in the storage chip to be prepared, represents a function of the read current in the memory chip to be prepared varying with temperature, Indicates the writing time corresponding to the storage chip to be prepared, represents a function of the change of the write power in the memory chip to be prepared with the temperature, Indicates the expected read and write values ​​corresponding to the storage chip to be prepared.

[0026] Optionally, determining the performance index of the memory chip to be prepared based on the expected read / write value includes:

[0027] Based on the expected read and write values, evaluating the read and write speed level of the memory chip to be prepared;

[0028] extracting key speed features in the read and write speed levels;

[0029] Analyze the impact of the key speed characteristics on the overall performance of the chip;

[0030] Querying key factors in the influencing data;

[0031] Comparing the key factors with a preset performance influencing factor library to obtain a comparison result;

[0032] Filtering a performance impact subset that meets a preset performance threshold in the comparison result;

[0033] Based on the performance impact subset, a performance indicator of the memory chip to be manufactured is determined.

[0034] Optionally, the calculating, based on the preparation influencing factors, the influence degree value corresponding to the memory chip to be prepared includes:

[0035] The impact value corresponding to the memory chip to be prepared is calculated using the following formula:

[0036]

[0037] in, represents the impact value corresponding to the memory chip to be prepared, represents the number of factors influencing the preparation, represents the quantitative index of the preparation influencing factors, Indicates The influence weight of each preparation influencing factor is Indicates Actual measured values ​​of the factors affecting the preparation, Indicates Standard values ​​of preparation influencing factors.

[0038] Optionally, configuring packaging materials corresponding to the memory chip to be prepared based on the impact degree value includes:

[0039] Determine the packaging material performance requirements corresponding to the impact degree value;

[0040] Constructing a candidate set of packaging materials that meet the performance requirements of the packaging materials;

[0041] Analyze the material properties of the materials in the packaging material candidate set;

[0042] Query the packaging material type that meets the material characteristics;

[0043] Based on the packaging material type, packaging materials corresponding to the memory chip to be prepared are configured.

[0044] Optionally, constructing a curing environment corresponding to the memory chip to be prepared based on the packaging material includes:

[0045] Determining the curing condition parameters required for the packaging material;

[0046] Collecting basic environmental data related to the curing condition parameters;

[0047] Analyzing available environmental resources corresponding to the environmental basic data;

[0048] Based on the resource options, preliminarily build a curing environment framework corresponding to the memory chip to be prepared;

[0049] Based on the curing environment framework, a curing environment corresponding to the memory chip to be prepared is constructed.

[0050] Optionally, tracing the exception source of the process parameter to obtain the exception source set includes:

[0051] Performing data classification on the process parameters to obtain process classification parameters;

[0052] Draw a process change trend graph corresponding to the process classification parameter;

[0053] Identify the change fluctuation point in the process change trend graph;

[0054] Analyze the fluctuation change gradient corresponding to the change fluctuation point;

[0055] Anomaly source tracing is performed on the gradient parameters in the fluctuation gradient to obtain an anomaly source set.

[0056] Optionally, in order to solve the above problem, the present invention provides a system for manufacturing a semiconductor memory chip, the system comprising:

[0057] A material processing module, used for obtaining chip parameters corresponding to the memory chip to be prepared, selecting semiconductor materials corresponding to the memory chip to be prepared according to the chip parameters, and performing material pretreatment on the semiconductor materials to obtain pretreated semiconductor materials;

[0058] A read / write expected value calculation module, used to determine a to-be-deposited area corresponding to the pre-treated semiconductor material, and after depositing an insulating layer and a conductive layer on the to-be-deposited area, construct a multi-layer structural framework corresponding to the to-be-prepared memory chip, determine the optimal thickness and layout of each layer of the to-be-prepared memory chip based on the multi-layer structural framework, and calculate the read / write expected value corresponding to the to-be-prepared memory chip according to the optimal thickness and layout;

[0059] An influence degree value calculation module is used to determine the performance index of the memory chip to be prepared based on the expected read and write values, evaluate the preparation feasibility of the memory chip to be prepared based on the performance index, obtain preparation evaluation data, query the preparation influencing factors existing in the preparation evaluation data, and calculate the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factors;

[0060] an abnormality tracing module, configured to configure the packaging material corresponding to the storage chip to be prepared based on the impact degree value, construct a curing environment corresponding to the storage chip to be prepared based on the packaging material, monitor the curing process state of the chip in the curing environment, extract the process parameters corresponding to the curing process state, perform abnormality tracing on the process parameters, and obtain an abnormality source set;

[0061] A solution generation module is used to analyze the abnormal targets in the abnormal source set, identify the abnormal storage factors in the abnormal targets, monitor the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factors, and generate a chip preparation solution corresponding to the storage chip to be prepared based on the preparation feedback data.

[0062] Firstly, by obtaining chip parameters corresponding to the memory chip to be prepared, the present invention can make the preparation process more accurate and controllable, ensure that the performance and quality of the chip meet the expected requirements, optimize the preparation process, help to discover potential problems in advance and make adjustments, reduce production costs and risks, and provide an important basis for subsequent chip applications, so that it can better meet specific functional requirements. At the same time, by determining the area to be deposited corresponding to the pretreated semiconductor material, the present invention can ensure that the insulating layer and the conductive layer are accurately deposited at the most suitable position, improve the performance and stability of the memory chip, avoid unnecessary deposition waste, and make the use of materials more efficient. Secondly, it is helpful to optimize the layout design of the memory chip. Based on the expected read and write values, the present invention determines the area to be deposited of the memory chip to be prepared. Performance indicators can clearly understand the actual performance capabilities of the chip in data storage and reading, provide a clear direction for subsequent optimization and improvement, and help to accurately predict its final performance in the early stages of chip design. The present invention configures the packaging materials corresponding to the storage chip to be prepared based on the impact value, which can maximize the performance and stability of the storage chip, ensure that the chip can achieve the expected performance indicators when working, and reduce performance degradation or failures caused by improper packaging. Furthermore, the present invention can analyze the abnormal targets in the abnormal source concentration to clarify which specific factors cause the abnormality of the curing process, so as to take targeted measures to solve it, avoid blind investigation and adjustment, and enhance the stability and reliability of the curing process. Therefore, the method and system for preparing semiconductor storage chips proposed by the present invention can improve the preparation stability of semiconductor storage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of a process for implementing a method for preparing a semiconductor memory chip provided by an embodiment of the present invention;

[0064] Figure 2 A schematic diagram of a module of a system for manufacturing a semiconductor memory chip provided by an embodiment of the present invention.

[0065] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0066] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0067] The embodiment of the present application provides a method for preparing a semiconductor memory chip. The execution subject of the method for preparing a semiconductor memory chip includes but is not limited to at least one of the electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the method for preparing a semiconductor memory chip can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc. The server can be an independent server, or it can be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

[0068] Reference Figure 1 FIG. 1 is a flow chart of a method for preparing a semiconductor memory chip according to an embodiment of the present invention. In this embodiment, the method for preparing a semiconductor memory chip includes:

[0069] S1. Obtain chip parameters corresponding to the memory chip to be prepared, select semiconductor materials corresponding to the memory chip to be prepared according to the chip parameters, and perform material pretreatment on the semiconductor materials to obtain pretreated semiconductor materials.

[0070] By obtaining chip parameters corresponding to the memory chip to be prepared, the present invention can make the preparation process more accurate and controllable, ensure that the performance and quality of the chip meet the expected requirements, optimize the preparation process, help to discover potential problems in advance and make adjustments, reduce production costs and risks, and provide an important basis for subsequent chip applications, so that it can better meet specific functional requirements.

[0071] Among them, the chip parameters refer to the specific numerical values ​​or descriptive information of various characteristics and specifications related to the storage chip to be prepared, which may include the following aspects: storage capacity, that is, the amount of data that the chip can store; read and write speed, indicating the speed of the chip reading and writing data; power consumption, reflecting the amount of electrical energy consumed by the chip when working; working voltage, the voltage range required for the normal operation of the chip; chip size, the size of the physical size; process technology, the level of process technology used to manufacture the chip; reliability indicators, such as service life, error rate, etc.; stability parameters, indicating the ability of the chip to maintain stable performance under different environmental conditions; and other specific parameters related to chip performance, function and quality. Optionally, the acquisition of chip parameters corresponding to the storage chip to be prepared can be achieved through a chip testing tool, such as: using a chip tester, the chip's read and write speed, power consumption and other performance parameters can be tested.

[0072] Furthermore, the present invention selects the semiconductor material corresponding to the memory chip to be prepared according to the chip parameters, which can provide the required electrical properties, such as high conductivity, low resistance, etc., so as to meet the performance indicators of the chip in terms of storage capacity, read and write speed, etc., and can also enhance the stability and reliability of the chip so that it can work normally under different environmental conditions. This helps to improve the quality of the chip, reduce the failure rate, and extend the service life.

[0073] Among them, the semiconductor material refers to a material with semiconductor properties, that is, a material with conductivity between that of a conductor and an insulator at room temperature. Common semiconductor materials include silicon (Si), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), etc. The conductivity of these materials can be adjusted by controlling their doping concentration, temperature, light and other conditions. In semiconductor memory chips, semiconductor materials are used to manufacture key components such as memory cells and transistors, and their performance directly affects the storage capacity, read and write speed, power consumption and other parameters of the chip. Optionally, the selection of the semiconductor material corresponding to the memory chip to be prepared can be achieved through a material performance database, such as: by querying the material performance database, understanding the conductivity, band structure, thermal stability and other parameters of different semiconductor materials, matching them with the storage capacity, read and write speed, operating temperature and other requirements of the chip, thereby selecting a suitable material.

[0074] Furthermore, the present invention obtains pretreated semiconductor material by pretreating the semiconductor material, thereby removing impurities and pollutants on the surface of the semiconductor material, ensuring the purity of the material, and laying a good foundation for the subsequent storage chip preparation process. Pure semiconductor material can improve the performance stability and reliability of the chip and reduce adverse phenomena such as leakage and short circuit caused by impurities.

[0075] The processed semiconductor material refers to a semiconductor material that has undergone targeted defect processing for potential defect types, removed key impurities, and repaired potential defects, and can better adapt to the requirements of the memory chip preparation process.

[0076] As an embodiment of the present invention, the material pretreatment of the semiconductor material to obtain the processed semiconductor material includes: analyzing the material properties corresponding to the semiconductor material; determining the surface distribution characteristics corresponding to the semiconductor material based on the material properties; extracting key impurity factors in the surface distribution characteristics; based on the key impurity factors, analyzing the potential defect types corresponding to the semiconductor material; based on the potential defect types, performing defect treatment on the semiconductor material to obtain the processed semiconductor material.

[0077] Among them, the material properties refer to the comprehensive properties of semiconductor materials such as physical properties (such as crystal structure, hardness, melting point, etc.), chemical properties (such as chemical stability, redox properties, etc.) and electrical properties (such as conductivity, carrier concentration, etc.); the surface distribution characteristics refer to the microscopic morphology, roughness, impurity distribution and possible crystal defect distribution of the surface of semiconductor materials; the key impurity factors refer to the factors such as the type, content and distribution position of impurities that have a greater impact on the performance of semiconductor materials in the surface distribution characteristics of semiconductor materials; the potential defect types refer to the defect types that may affect the performance of semiconductor materials and the subsequent chip preparation process, which are obtained based on the analysis of key impurity factors and material properties of semiconductor materials, such as crystal defects (dislocations, voids, etc.), chemical defects (uneven oxide layer, etc.), etc.

[0078] Furthermore, the analysis of the material properties corresponding to the semiconductor material can be achieved through a material composition analysis method, such as: using an X-ray fluorescence spectrometer to perform material composition analysis to determine the elemental composition of the semiconductor material; the determination of the surface distribution characteristics corresponding to the semiconductor material can be achieved through an electron beam exposure system, such as: the electron beam can be precisely controlled to scan the surface of the semiconductor material to obtain surface distribution information; the extraction of key impurity factors in the surface distribution characteristics can be achieved through a principal component analysis algorithm, such as: performing principal component analysis on data such as energy spectrum analysis to extract key impurity factors that have a greater impact on the performance of semiconductor materials; the analysis of potential defect types corresponding to the semiconductor material can be achieved through defect detection experiments, such as: hot carrier injection experiments, stress tests, etc., to observe whether performance degradation or failure occurs, thereby analyzing potential defect types; the defect treatment of the semiconductor material can be achieved through chemical treatment methods, such as: using a specific chemical solution to soak and clean the semiconductor material to remove surface impurities and contaminants.

[0079] S2. Determine the area to be deposited corresponding to the processed semiconductor material, and after depositing an insulating layer and a conductive layer on the area to be deposited, construct a multi-layer structural framework corresponding to the memory chip to be prepared, and based on the multi-layer structural framework, determine the optimal thickness and layout of each layer of the memory chip to be prepared, and calculate the expected read and write values ​​corresponding to the memory chip to be prepared according to the optimal thickness and layout.

[0080] By determining the area to be deposited corresponding to the pretreated semiconductor material, the present invention can ensure that the insulating layer and the conductive layer are accurately deposited at the most suitable position, thereby improving the performance and stability of the memory chip, avoiding unnecessary deposition waste, making the use of materials more efficient, and secondly, helping to optimize the layout design of the memory chip.

[0081] The area to be deposited refers to a specific area on the surface of the semiconductor material that is finally determined and used for depositing the insulating layer and the conductive layer.

[0082] As an embodiment of the present invention, determining the area to be deposited corresponding to the processed semiconductor material includes: analyzing the physical structural characteristics corresponding to the processed semiconductor material; based on the physical structural characteristics, querying the potential deposition sites on the surface of the material corresponding to the processed semiconductor material; performing data evaluation on the potential deposition sites to obtain deposition evaluation data; extracting the dominant deposition sites in the deposition evaluation data; and determining the area to be deposited corresponding to the pretreated semiconductor material based on the dominant deposition sites.

[0083] Among them, the physical structural characteristics refer to the physical characteristics of the processed semiconductor material, such as crystal structure, surface morphology, size, etc.; the potential deposition site refers to the position on the surface of the processed semiconductor material that may be suitable for subsequent deposition of insulating layers and conductive layers; the deposition evaluation data refers to the data results obtained after a multi-faceted analysis and evaluation of the potential deposition site, including but not limited to evaluation information on the flatness, chemical activity, and correlation with surrounding structures of the site; the advantageous deposition site refers to a specific position among the potential deposition sites that is considered to be most conducive to the subsequent deposition process and can maximize the performance and stability of the memory chip after evaluation.

[0084] Further, the analysis of the physical structural characteristics corresponding to the treated semiconductor material can be achieved by an optical microscope, such as: using an optical microscope to preliminarily observe the appearance and larger-scale structural characteristics of the material; the query of the potential deposition sites on the surface of the treated semiconductor material can be achieved by a contact angle meter, such as: measuring the contact angle of the liquid on the material surface to infer the hydrophilicity or hydrophobicity of the surface, thereby determining the potential deposition sites; the data evaluation of the potential deposition sites can be achieved by a simulated deposition experiment, such as: conducting a simulated deposition experiment, observing the effects of deposition on different potential deposition sites, such as flatness, bonding strength, etc., to obtain evaluation data; the extraction of the dominant deposition sites in the deposition evaluation data can be achieved by a data analysis tool, such as: using data analysis software to process and analyze the deposition evaluation data to extract the dominant deposition sites; the determination of the area to be deposited corresponding to the pretreated semiconductor material can be achieved by a regional division and merging method, such as: dividing the semiconductor material surface into regions according to the distribution of the dominant deposition sites, and merging adjacent dominant deposition sites into one area to be deposited.

[0085] The present invention constructs a multi-layer structural frame corresponding to the storage chip to be prepared after depositing an insulating layer and a conductive layer on the area to be deposited, thereby providing better electrical isolation and signal transmission performance, ensuring normal operation of various components inside the chip, reducing signal interference and leakage, and improving the reliability and stability of the chip.

[0086] Among them, the insulating layer refers to a material layer with good insulating properties, which is used to separate different conductive layers to prevent current leakage and signal interference, and is usually made of materials such as oxides and nitrides; the conductive layer refers to a material layer that can conduct current, which is usually composed of materials such as metals (such as copper, aluminum, etc.) or conductive polymers, and is used to realize circuit connections inside the chip; the multi-layer structure frame refers to a frame with a multi-layer structure formed by alternating deposition of insulating layers and conductive layers. It is the basic structure of the memory chip and provides support and connection for various functional components of the chip, so that the chip can realize functions such as data storage, reading and processing. Optionally, the conductor is injected into the The deposition of insulating layers and conductive layers can be achieved through PVD methods and CVD methods, such as: by bombarding the target material with high-energy particles in a vacuum environment, the target atoms are sputtered out and deposited on the surface of the injected conductor to form a uniform insulating layer, and in the reaction chamber, a reaction gas is introduced, and the gas reaction is excited by plasma to deposit a conductive layer on the injected conductor; the construction of the multi-layer structural framework corresponding to the storage chip to be prepared can be achieved through thin film deposition and planarization technology, such as: continuously and alternately depositing insulating layers and conductive layers, and using chemical mechanical planarization (CMP) technology to planarize the surface to ensure the flatness and connectivity between the layers to construct a multi-layer structural framework.

[0087] Furthermore, the present invention determines the optimal thickness and layout of each layer of the storage chip to be prepared based on the multi-layer structural framework, which can improve the storage density of the chip, enable the chip to store more data at the same size, and meet the growing storage demand. Secondly, reasonable thickness and layout design can improve the performance of the chip, such as increasing the reading and writing speed, reducing power consumption, etc., thereby improving the overall performance of the chip.

[0088] Among them, the optimal thickness refers to the most suitable thickness that each layer of material should have under the premise of meeting the performance requirements of the memory chip. This thickness can make the chip achieve the best balance in terms of storage capacity, read and write speed, power consumption, etc., while ensuring the reliability and stability of the chip; the layout refers to the spatial arrangement and organization of each layer structure and each component in the memory chip, which includes the relative position of each layer, the connection method and the distribution of circuit elements, etc., aiming to maximize the function, optimize the performance and minimize the size of the chip. Optionally, the determination of the optimal thickness and layout of each layer of the memory chip to be prepared can be achieved through simulation software, such as: using finite element analysis software to model the multi-layer structure of the memory chip, and by simulating physical processes such as electric field distribution and heat conduction under different thicknesses and layouts, the performance of the chip is evaluated, thereby determining the optimal thickness and layout.

[0089] Furthermore, the present invention calculates the expected read and write values ​​corresponding to the storage chip to be prepared based on the optimal thickness and layout, which can better evaluate the feasibility and potential performance of the design scheme, thereby performing optimization adjustments in the design stage to avoid performance failures in the later stage. Secondly, accurate expected read and write values ​​can help determine the performance of the chip under different working conditions.

[0090] The expected read / write value refers to an indicator for measuring the read / write performance of a chip obtained by comprehensively considering the read time and write time of the storage chip.

[0091] As an embodiment of the present invention, the calculating of the expected read / write values ​​corresponding to the memory chip to be prepared according to the optimal thickness and layout includes:

[0092] The expected read / write value corresponding to the memory chip to be prepared is calculated using the following formula:

[0093]

[0094] in, Indicates the read time corresponding to the storage chip to be prepared, represents the length of the interconnect in the layout, Indicates that the resistivity of the memory chip to be prepared varies with temperature The change function of represents the optimum thickness, represents the line width in the layout, represents the line spacing in the layout, represents the driving voltage of the read / write circuit in the memory chip to be prepared, Indicates the length of the interconnect line The length of the differential element when performing the integration, represents a function of the signal transmission delay factor in the memory chip to be prepared varying with temperature, represents the capacitance value of the storage unit in the storage chip to be prepared, represents a function of the read current in the memory chip to be prepared varying with temperature, Indicates the writing time corresponding to the storage chip to be prepared, represents a function of the change of the write power in the memory chip to be prepared with the temperature, Indicates the expected read and write values ​​corresponding to the storage chip to be prepared.

[0095] In detail, the read time refers to the time required for the memory chip to complete a read operation; the interconnect length refers to the length of the signal transmission path in the layout of the memory chip; the drive voltage refers to the voltage provided by the read / write circuit in the memory chip to drive the current for read / write operations; the signal transmission delay factor refers to a coefficient that comprehensively considers the impact of the memory chip layout on the signal transmission delay; the memory cell capacitance value refers to the ability of the memory cell to store charge; the write time refers to the time taken for the memory chip to complete a write operation; and the write power refers to the power required for the memory chip to perform a write operation.

[0096] S3. Based on the expected read and write values, determine the performance indicators of the storage chip to be prepared, evaluate the preparation feasibility of the storage chip to be prepared based on the performance indicators, obtain preparation evaluation data, query the preparation influencing factors existing in the preparation evaluation data, and calculate the influence degree value corresponding to the storage chip to be prepared based on the preparation influencing factors.

[0097] The present invention determines the performance indicators of the memory chip to be prepared based on the expected read and write values, which can clearly understand the actual performance capabilities of the chip in data storage and reading, provide a clear direction for subsequent optimization and improvement, and help to accurately predict the final performance of the chip in the early stages of chip design.

[0098] The performance indicators refer to specific parameters and standards used to measure and describe the performance of the memory chip to be manufactured in various aspects.

[0099] As an embodiment of the present invention, determining the performance indicators of the storage chip to be prepared based on the expected read and write values ​​includes: evaluating the read and write speed level of the storage chip to be prepared based on the expected read and write values; extracting key speed features in the read and write speed levels; analyzing the impact data of the key speed features on the overall performance of the chip; querying the key factors in the impact data; comparing the key factors with a preset performance impact factor library to obtain comparison results; screening a performance impact subset in the comparison results that meets a preset performance threshold; and determining the performance indicators of the storage chip to be prepared based on the performance impact subset.

[0100] Among them, the read and write speed level refers to the speed at which the storage chip completes the read and write operations in a unit of time; the key speed feature refers to the speed-related characteristics that are significantly representative and important in the read and write speed level; the influencing data refers to the specific numerical value or quantitative information of the impact of the key speed feature on the overall performance of the chip; the key factor refers to the factor that plays a dominant role in the influencing data and has an important impact on the chip performance; the comparison result refers to the result of the consistency or difference obtained by comparing the key factor with the preset performance influencing factor library; the preset performance threshold refers to the standard value used to screen the performance influencing subset in the comparison result, which is a boundary for measuring whether the performance influencing factors meet the requirements; the performance influencing subset refers to a set of partial factors that are highly important and have a significant impact on chip performance that are screened out from the comparison results.

[0101] Furthermore, the evaluation of the read and write speed level of the storage chip to be prepared can be achieved through the CrystalDiskMark tool, such as: performing multiple read and write tests on the chip through CrystalDiskMark to obtain read and write speed data under different data block sizes, thereby evaluating its read and write speed level; the extraction of key speed features in the read and write speed level can be achieved through feature selection algorithms, such as: ReliefF algorithm, information gain algorithm, etc.; the analysis of the impact of the key speed features on the overall performance of the chip can be achieved through the SPICE tool, such as: inputting key speed feature parameters in SPICE, simulating the working conditions of the chip, and obtaining the impact data on the overall performance; the query The key factors affecting the data can be implemented by an algorithm based on a decision tree, such as: using the C4.5 algorithm to build a decision tree, classifying and screening the various factors in the affecting data, and finding the key factors; the comparison of the key factors with the preset performance influencing factor library can be implemented by a pattern matching algorithm, such as: a KMP algorithm; the screening of the performance influencing subset that meets the preset performance threshold in the comparison results can be implemented by a principal component analysis method, such as: performing principal component analysis on multiple factors in the comparison results, extracting the main components, and thus screening out important performance influencing subsets; the determination of the performance indicators of the storage chip to be prepared can be implemented by performance benchmarking tools, such as: IOMeter, FIO and other tools.

[0102] The present invention evaluates the feasibility of preparing the memory chip to be prepared based on the performance index to obtain preparation evaluation data, and can comprehensively and accurately predict the success possibility of the entire project before the chip is prepared, can discover potential technical difficulties and bottlenecks in advance, and can perform real-time monitoring and adjustment against the evaluation data to ensure that the chip finally prepared can meet the expected performance requirements.

[0103] Among them, the preparation evaluation data refers to relevant data and information used to measure and describe the feasibility of the memory chip to be prepared in terms of technology, process, cost, market, etc. Optionally, the evaluation of the preparation feasibility of the memory chip to be prepared can be achieved through simulation tools, such as ANSYS, COMSOL and other tools.

[0104] Furthermore, by querying the preparation influencing factors existing in the preparation evaluation data, the present invention can formulate targeted response strategies and solutions, thereby avoiding potential risks in advance and improving the success rate of preparation. Secondly, it helps to optimize the preparation process and resource allocation, and after clarifying the influencing factors, the preparation process can be reasonably adjusted to more effectively concentrate resources on key links and reduce unnecessary waste and delays.

[0105] Among them, the preparation influencing factors refer to various factors that may have an adverse effect on the quality, performance, cost, production efficiency, etc. of the chip during the process of preparing the memory chip, including but not limited to technical bottlenecks, raw material supply problems, production process defects, equipment failures, personnel operating errors, market demand changes, etc. Optionally, the query of the preparation influencing factors existing in the preparation evaluation data can be achieved through a fault tree analysis method, such as: taking a certain fault or problem in the preparation process as the top event, and gradually analyzing the causes of the fault downward to form a tree structure, so as to find out the influencing factors.

[0106] Furthermore, the present invention calculates the impact degree value corresponding to the storage chip to be prepared based on the preparation influencing factors, which can provide a clear and quantitative understanding of the importance and degree of harm of each influencing factor, and can be used for subsequent processing, thereby rationally allocating resources and energy, and secondly, helping to formulate more accurate and effective response strategies.

[0107] The impact degree value refers to a numerical value used to quantify the degree of impact on the memory chip to be manufactured under the combined effect of various manufacturing influencing factors.

[0108] As an embodiment of the present invention, the calculating the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factor includes:

[0109] The impact value corresponding to the memory chip to be prepared is calculated using the following formula:

[0110]

[0111] in, represents the impact value corresponding to the memory chip to be prepared, represents the number of factors influencing the preparation, represents the quantitative index of the preparation influencing factors, Indicates The influence weight of each preparation influencing factor is Indicates Actual measured values ​​of the factors affecting the preparation, Indicates Standard values ​​of preparation influencing factors.

[0112] In detail, the influence weight refers to the numerical value of the relative importance assigned to each preparation influencing factor, which reflects the contribution ratio of different influencing factors to the overall influence. The larger the weight, the more important the influence of the factor on the final result; the actual measured value refers to the specific numerical value of the preparation influencing factor obtained through actual detection, experiment, observation or evaluation; the standard value refers to the expected or normal numerical range of the preparation influencing factor under ideal conditions or set according to industry specifications, design requirements and previous experience of similar projects.

[0113] S4. Based on the impact degree value, configure the packaging material corresponding to the storage chip to be prepared, build a curing environment corresponding to the storage chip to be prepared based on the packaging material, monitor the curing process status of the chip in the curing environment, extract the process parameters corresponding to the curing process status, trace the abnormality of the process parameters, and obtain an abnormality source set.

[0114] The present invention configures the packaging material corresponding to the memory chip to be prepared based on the impact degree value, which can maximize the performance and stability of the memory chip, ensure that the chip can achieve the expected performance indicators when working, and reduce performance degradation or failures caused by improper packaging.

[0115] The packaging material refers to the specific material actually used for packaging the memory chip to be prepared, and is a specific substance determined to be used after screening and configuration from a candidate set.

[0116] As an embodiment of the present invention, configuring the packaging material corresponding to the storage chip to be prepared based on the impact degree value includes: determining the packaging material performance requirement corresponding to the impact degree value; constructing a packaging material candidate set that meets the packaging material performance requirement; analyzing the material properties of the materials in the packaging material candidate set; querying the packaging material type that meets the material properties; and configuring the packaging material corresponding to the storage chip to be prepared based on the packaging material type.

[0117] Among them, the packaging material performance requirements refer to the various performance indicators and parameters that the packaging material should have determined according to the impact degree value, such as specific requirements in terms of thermal conductivity, electrical conductivity, mechanical strength, corrosion resistance, etc.; the packaging material candidate set refers to a collection of a series of optional packaging materials that meet the determined packaging material performance requirements; the material properties refer to the inherent physical, chemical and mechanical properties of the packaging material itself, such as the composition, structure, hardness, melting point, etc. of the material; the packaging material type refers to the category of packaging materials classified according to different characteristics and uses, such as plastic packaging, ceramic packaging, metal packaging, etc.

[0118] Furthermore, the determination of the packaging material performance requirements corresponding to the impact degree value can be achieved through a multi-objective optimization algorithm, such as: using a multi-objective optimization algorithm such as NSGA-II, while considering multiple factors such as the impact degree value, cost, and performance, to determine the optimal packaging material performance requirements; the construction of a packaging material candidate set that meets the packaging material performance requirements can be achieved through a database query method, such as: in a packaging material database, querying according to the set performance requirements to screen out candidate materials that meet the requirements; the analysis of the material properties of the materials in the packaging material candidate set can be achieved through a material analysis and testing instrument, such as: using an X-ray diffractometer (XRD), a scanning electron microscope (SEM) and other equipment to analyze the candidate materials to obtain their microstructure and composition and other properties; the query of the packaging material type that meets the material properties can be achieved through a classification algorithm, such as: a decision tree, a support vector machine and other classification algorithms; the configuration of the packaging material corresponding to the storage chip to be prepared can be achieved through a risk assessment method, such as: assessing the risks that may be faced by using different packaging materials, such as supply stability, technology maturity, etc., and selecting materials with lower risks for configuration.

[0119] The present invention constructs a curing environment corresponding to the memory chip to be prepared based on the packaging material, which can ensure that the packaging material reaches an optimal performance state during the curing process, and can promote the chemical reaction or physical change of the material, so that it has better mechanical strength, thermal stability and sealing, thereby providing more reliable protection for the memory chip.

[0120] The curing environment refers to the overall environment that is finally constructed, can fully meet the curing requirements of the packaging material, and has stable and precise curing condition parameters.

[0121] As an embodiment of the present invention, constructing a curing environment corresponding to the memory chip to be prepared based on the packaging material includes: determining the curing condition parameters required for the packaging material; collecting basic environmental data related to the curing condition parameters; analyzing the available environmental resources corresponding to the basic environmental data; based on the resource options, preliminarily building a curing environment framework corresponding to the memory chip to be prepared; based on the curing environment framework, constructing a curing environment corresponding to the memory chip to be prepared.

[0122] Among them, the curing condition parameters refer to a series of specific conditions and indicators necessary for the packaging materials to achieve a good curing effect, such as temperature, humidity, pressure, time, etc.; the basic environmental data refers to various original information and data related to the curing condition parameters, including the temperature and humidity ranges that existing equipment can provide, adjustable pressure values, available time intervals, etc.; the available environmental resources refer to various specific resources that can be used to meet the curing condition parameters under the current actual situation, such as specific temperature and humidity control equipment, pressure regulating devices, timing tools, etc.; the curing environment framework refers to the basic environmental structure and layout that is preliminarily planned and built according to the available environmental resources and can roughly meet the curing condition parameters.

[0123] Furthermore, the determination of the curing condition parameters required for the packaging material can be achieved through experimental testing and data analysis methods, such as: conducting small batch curing experiments, measuring the curing effects under different conditions, and determining the optimal curing condition parameters through data analysis; the collection of basic environmental data related to the curing condition parameters can be achieved through a sensor monitoring system, such as: using temperature sensors, humidity sensors, pressure sensors, etc. to collect environmental data in real time; the analysis of available environmental resources corresponding to the basic environmental data can be achieved through a feasibility analysis matrix, such as: taking each parameter in the basic environmental data as a row, and the characteristics of existing resources as a column, and evaluating each combination of parameters and resources to determine its feasibility; the preliminary construction of the curing environment framework corresponding to the storage chip to be prepared can be achieved through virtual modeling tools, such as: SolidWork and other tools; the construction of the curing environment corresponding to the storage chip to be prepared can be achieved through an automated control system, such as: PLC, DCS and other systems.

[0124] The present invention monitors the curing process status of the chip in the curing environment and extracts the process parameters corresponding to the curing process status, so as to grasp the progress and situation of chip curing in real time and ensure that the curing process proceeds as planned. The continuous monitoring of the curing process status can timely discover any abnormal situation, such as too slow curing speed, temperature fluctuation, etc., so as to take corresponding measures to make adjustments and avoid affecting the quality and performance of the chip.

[0125] Among them, the curing process state refers to the specific curing stage and various characteristic conditions exhibited by the storage chip to be prepared in the curing environment, including but not limited to the degree of curing, the state of chemical reaction, changes in physical form, etc.; the process parameters refer to specific numerical indicators that can quantitatively describe the curing process state, such as curing time, temperature change curve, humidity change value, pressure fluctuation range, etc. Optionally, the monitoring of the curing process state of the chip in the curing environment can be achieved by an infrared thermal imager, such as: the temperature distribution on the surface of the chip can be detected by an infrared thermal imager to determine whether the curing is uniform; the extraction of process parameters corresponding to the curing process state can be achieved by image processing technology, such as: for image data obtained by optical monitoring, using image processing algorithms to extract useful process parameters.

[0126] The present invention traces the abnormality of the process parameters to obtain an abnormality source set, and can timely discover and locate the root cause of the problem in the curing process so that targeted measures can be taken quickly to correct it, thereby reducing waste and rework, improving production efficiency, and reducing energy and material waste, thereby achieving effective cost control.

[0127] The abnormal source set refers to a collection of various factors that may cause abnormal curing process after analyzing and tracing the gradient parameters in the fluctuating gradient, including equipment failure, environmental changes, material problems, etc.

[0128] As an embodiment of the present invention, the process parameters are subjected to abnormal tracing to obtain an abnormal source set, including: data classification of the process parameters to obtain process classification parameters; drawing a process change trend graph corresponding to the process classification parameters; identifying change fluctuation points in the process change trend graph; analyzing the fluctuation change gradient corresponding to the change fluctuation points; and abnormal tracing of gradient parameters in the fluctuation change gradient to obtain an abnormal source set.

[0129] Among them, the process classification parameters refer to the parameter set obtained after classifying the monitored process parameters of the curing process status according to different characteristics or attributes, for example, it can be classified according to temperature-related parameters, humidity-related parameters, time-related parameters, etc.; the process change trend chart refers to a chart with time as the horizontal axis and various process classification parameters as the vertical axis, which is used to intuitively display the change trends of different parameters in the curing process; the change fluctuation point refers to the point in the process change trend chart where the parameter value changes significantly and deviates from the normal trend; the fluctuation change gradient refers to the measurement of the rate and direction of change of the parameter value at the change fluctuation point, reflecting the severity of the parameter change.

[0130] Furthermore, the data classification of the process parameters can be achieved through rule-based classification, such as: setting specific rules to classify according to the nature and source of the process parameters; the drawing of the process change trend graph corresponding to the process classification parameters can be achieved through data visualization tools, such as: using Excel, Python's Matplotlib library and other tools to draw the changes of the classified process parameters over time into trend graphs in the form of line graphs, bar graphs, etc.; the identification of change fluctuation points in the process change trend graph can be achieved through a sliding window algorithm, such as: setting a sliding window of a fixed size and moving the window on the trend graph, Calculate the standard deviation or variance of the parameters in the window. When the standard deviation or variance exceeds the set threshold, the time point corresponding to the center of the window is considered to be a change fluctuation point. The analysis of the fluctuation change gradient corresponding to the change fluctuation point can be achieved through a regression analysis method, such as: performing local regression analysis near the change fluctuation point, fitting a curve of parameter change, and then calculating the slope of the curve at this point as the fluctuation change gradient. The abnormal tracing of the gradient parameters in the fluctuation change gradient can be achieved through a fault tree analysis method, such as: taking the gradient parameter abnormality as the top event, gradually analyzing the various factors that may cause the abnormality, establishing a fault tree, and determining the abnormal source set through analysis of the fault tree.

[0131] S5. Analyze the abnormal targets in the abnormal source set, identify abnormal storage factors in the abnormal targets, monitor the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factors, and generate a chip preparation plan corresponding to the storage chip to be prepared based on the preparation feedback data.

[0132] By analyzing the abnormal targets in the abnormal source set, the present invention can clarify which specific factors lead to the abnormality of the curing process, so as to take targeted measures to solve the problem, avoid blind investigation and adjustment, and enhance the stability and reliability of the curing process.

[0133] Among them, the abnormal target refers to the key factor or object in the abnormal source set that specifically causes the abnormality of the solidification process. Optionally, the analysis of the abnormal targets in the abnormal source set can be achieved through a correlation analysis method, such as: by analyzing the correlation between process parameters, finding the factor with the highest correlation with the abnormal phenomenon as the abnormal target.

[0134] By identifying the abnormal storage factors in the abnormal target, the present invention can more deeply understand the root cause of the abnormal curing of the storage chip, and can clarify which specific factors play a negative role in the curing process of the storage chip, thereby providing key clues for targeted problem solving.

[0135] The abnormal storage factor refers to a specific factor that is finally determined to have an abnormal impact on storage performance during the storage chip curing process.

[0136] As an embodiment of the present invention, the identifying of abnormal storage factors in the abnormal target includes: performing target deconstruction on the abnormal target to obtain target deconstruction items; analyzing deconstruction features in the target deconstruction items; identifying risk factors corresponding to the deconstruction features; screening storage-related factors in the risk factors to obtain a risk storage candidate set; querying abnormal storage segments in the risk storage candidate set; and identifying abnormal storage factors in the abnormal storage segments.

[0137] Among them, the target deconstruction item refers to the specific component or element obtained after decomposing the abnormal target; the deconstruction feature refers to the specific attribute, characteristic or manifestation of the target deconstruction item; the risk factor refers to the potential factor that may cause problems in the storage chip curing process, which may have an adverse effect on the curing result; the risk storage candidate set refers to a set of storage-related factors screened out from a large number of risk factors, which are considered to pose risks to the storage performance of the storage chip; the abnormal storage segment refers to a specific part or fragment in the risk storage candidate set that is preliminarily judged to be abnormal.

[0138] Furthermore, the target deconstruction of the abnormal target can be achieved through a failure mode and impact analysis method, such as: decomposing the abnormal target according to different failure modes, analyzing the impact of each failure mode on the whole, and thus determining the target deconstruction item; the analysis of the deconstruction features in the target deconstruction item can be achieved through a feature extraction algorithm, such as: using algorithms such as principal component analysis (PCA) to extract key features from the data of the target deconstruction item as deconstruction features; the identification of the risk factors corresponding to the deconstruction features can be achieved through a risk matrix method, such as: constructing a risk matrix, taking the severity and probability of occurrence of the deconstruction features as two dimensions, evaluate the risk level corresponding to each deconstructed feature, so as to determine the risk factors; the screening of storage-related factors in the risk factors can be achieved through logical reasoning, such as: according to the working principle of the storage chip and the requirements of the solidification process, logical reasoning is performed to screen out the risk factors related to storage; the query of abnormal storage segments in the risk storage candidate set can be achieved through anomaly detection algorithms, such as: 3σ principle, box plot, etc.; the identification of abnormal storage factors in the abnormal storage segments can be achieved through a decision tree algorithm, such as: building a decision tree model, taking the characteristics of the abnormal storage segments as input, and predicting the abnormal storage factors.

[0139] The present invention monitors the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factor, and can timely discover and correct potential problems in the preparation process. By paying close attention to the feedback data related to the abnormal storage factor, measures can be taken when problems just appear to avoid further expansion of the problems, thereby ensuring the preparation quality of the storage chip.

[0140] The preparation feedback data refers to various data information reflecting the current state and performance of the memory chip during the preparation process of the memory chip to be prepared, including but not limited to environmental parameters such as temperature, pressure, humidity, physical and chemical property change data of the material, and electrical performance parameters of the memory chip, etc. Optionally, the monitoring of the preparation feedback data of the memory chip to be prepared during the preparation process can be achieved through machine learning algorithm monitoring, such as: (using a machine learning algorithm to learn historical preparation data, establish a prediction model, and then discover anomalies by real-time monitoring of the deviation between the new preparation data and the model, thereby obtaining feedback data.

[0141] Furthermore, the present invention generates a chip preparation plan corresponding to the storage chip to be prepared based on the preparation feedback data, which can achieve precise production. Through the analysis of the preparation feedback data, the actual situation and existing problems in the current preparation process can be deeply understood, so as to adjust and optimize the preparation plan in a targeted manner, so that each link can better adapt to actual needs and improve the quality and performance of the chip.

[0142] Among them, the chip preparation plan refers to the detailed plan and strategy formulated for the production process of the memory chip to be prepared, including various aspects such as the selection of raw materials, the design of process flow, the configuration and parameter setting of equipment, and quality control standards, so as to ensure that the memory chip can be produced efficiently and with high quality. Optionally, the generation of the chip preparation plan corresponding to the memory chip to be prepared can be achieved through visualization tools, such as Tableau, PowerBI and other tools.

[0143] Firstly, by obtaining chip parameters corresponding to the memory chip to be prepared, the present invention can make the preparation process more accurate and controllable, ensure that the performance and quality of the chip meet the expected requirements, optimize the preparation process, help to discover potential problems in advance and make adjustments, reduce production costs and risks, and provide an important basis for subsequent chip applications, so that it can better meet specific functional requirements. At the same time, by determining the area to be deposited corresponding to the pretreated semiconductor material, the present invention can ensure that the insulating layer and the conductive layer are accurately deposited at the most suitable position, improve the performance and stability of the memory chip, avoid unnecessary deposition waste, and make the use of materials more efficient. Secondly, it is helpful to optimize the layout design of the memory chip. Based on the expected read and write values, the present invention determines the area to be deposited of the memory chip to be prepared. Performance indicators can clearly understand the actual performance capabilities of the chip in data storage and reading, provide a clear direction for subsequent optimization and improvement, and help to accurately predict its final performance in the early stages of chip design. The present invention configures the packaging materials corresponding to the storage chip to be prepared based on the impact value, which can maximize the performance and stability of the storage chip, ensure that the chip can achieve the expected performance indicators when working, and reduce performance degradation or failures caused by improper packaging. Furthermore, the present invention can analyze the abnormal targets in the abnormal source concentration to clarify which specific factors cause the abnormality of the curing process, so as to take targeted measures to solve it, avoid blind investigation and adjustment, and enhance the stability and reliability of the curing process. Therefore, the method and system for preparing semiconductor storage chips proposed by the present invention can improve the preparation stability of semiconductor storage chips.

[0144] like Figure 2 1 is a functional module diagram of a system for manufacturing a semiconductor memory chip provided by an embodiment of the present invention.

[0145] The preparation system 200 for realizing a semiconductor storage chip described in the present invention can be installed in an electronic device. According to the functions to be realized, the preparation system 200 for realizing a semiconductor storage chip can include a material processing module 201, a read / write expected value calculation module 202, an impact value calculation module 203, an abnormality tracing module 204, and a solution generation module 205. The module described in the present invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0146] In this embodiment, the functions of each module / unit are as follows:

[0147] The material processing module 201 is used to obtain chip parameters corresponding to the memory chip to be prepared, select semiconductor materials corresponding to the memory chip to be prepared according to the chip parameters, and perform material pretreatment on the semiconductor materials to obtain pretreated semiconductor materials;

[0148] The expected read / write value calculation module 202 is used to determine the area to be deposited corresponding to the pre-treated semiconductor material, and after depositing the insulating layer and the conductive layer on the area to be deposited, construct a multi-layer structure framework corresponding to the memory chip to be prepared, determine the optimal thickness and layout of each layer of the memory chip to be prepared based on the multi-layer structure framework, and calculate the expected read / write value corresponding to the memory chip to be prepared according to the optimal thickness and layout;

[0149] The influence degree value calculation module 203 is used to determine the performance index of the memory chip to be prepared based on the expected read and write value, evaluate the feasibility of the preparation of the memory chip to be prepared based on the performance index, obtain preparation evaluation data, query the preparation influencing factors existing in the preparation evaluation data, and calculate the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factors;

[0150] The abnormality tracing module 204 is used to configure the packaging material corresponding to the storage chip to be prepared based on the impact degree value, build a curing environment corresponding to the storage chip to be prepared based on the packaging material, monitor the curing process state of the chip in the curing environment, extract the process parameters corresponding to the curing process state, and perform abnormality tracing on the process parameters to obtain an abnormality source set;

[0151] The solution generation module 205 is used to analyze the abnormal targets in the abnormal source set, identify the abnormal storage factors in the abnormal targets, monitor the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factors, and generate a chip preparation solution corresponding to the storage chip to be prepared based on the preparation feedback data.

[0152] In detail, the modules described in the system 200 for preparing semiconductor memory chips described in the embodiment of the present invention adopt the same technical means as the method for preparing semiconductor memory chips described in the accompanying drawings when used, and can produce the same technical effects, which will not be repeated here.

[0153] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for manufacturing a semiconductor memory chip, characterized in that: The method comprises: Obtaining chip parameters corresponding to the memory chip to be prepared, selecting semiconductor materials corresponding to the memory chip to be prepared according to the chip parameters, and performing material pretreatment on the semiconductor materials to obtain pretreated semiconductor materials; Determine a region to be deposited corresponding to the pretreated semiconductor material, and after depositing an insulating layer and a conductive layer on the region to be deposited, construct a multilayer structural framework corresponding to the memory chip to be prepared, determine the optimal thickness and layout of each layer of the memory chip to be prepared based on the multilayer structural framework, and calculate the expected read / write value corresponding to the memory chip to be prepared according to the optimal thickness and layout, wherein the calculation of the expected read / write value corresponding to the memory chip to be prepared according to the optimal thickness and layout includes: The expected read / write value corresponding to the memory chip to be prepared is calculated using the following formula: in, Indicates the read time corresponding to the storage chip to be prepared, represents the length of the interconnect in the layout, Indicates that the resistivity of the memory chip to be prepared varies with temperature The change function of represents the optimum thickness, represents the line width in the layout, represents the line spacing in the layout, represents the driving voltage of the read / write circuit in the memory chip to be prepared, Indicates the length of the interconnect line The length of the differential element when performing the integration, represents a function of the signal transmission delay factor in the memory chip to be prepared varying with temperature, represents the capacitance value of the storage unit in the storage chip to be prepared, represents a function of the read current in the memory chip to be prepared varying with temperature, Indicates the writing time corresponding to the storage chip to be prepared, represents a function of the change of the write power in the memory chip to be prepared with the temperature, Indicates the expected read and write values ​​corresponding to the storage chip to be prepared; Based on the expected read / write values, a performance index of the memory chip to be prepared is determined; based on the performance index, the feasibility of preparing the memory chip to be prepared is evaluated to obtain preparation evaluation data; preparation influencing factors existing in the preparation evaluation data are queried; based on the preparation influencing factors, an influence degree value corresponding to the memory chip to be prepared is calculated; wherein, the calculation of the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factors includes: The impact value corresponding to the memory chip to be prepared is calculated using the following formula: in, represents the impact value corresponding to the memory chip to be prepared, represents the number of factors influencing the preparation, represents the quantitative index of the preparation influencing factors, Indicates The influence weight of each preparation influencing factor is Indicates Actual measured values ​​of the factors affecting the preparation, Indicates Standard values ​​of factors affecting preparation; Based on the impact degree value, configuring the packaging material corresponding to the storage chip to be prepared, constructing the curing environment corresponding to the storage chip to be prepared based on the packaging material, monitoring the curing process state of the chip in the curing environment, extracting the process parameters corresponding to the curing process state, tracing the abnormality of the process parameters, and obtaining the abnormality source set; Analyze the abnormal targets in the abnormal source set, identify abnormal storage factors in the abnormal targets, monitor the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factors, and generate a chip preparation plan corresponding to the storage chip to be prepared based on the preparation feedback data.

2. A method for manufacturing a semiconductor memory chip according to claim 1, characterized in that: The step of pre-treating the semiconductor material to obtain the pre-treated semiconductor material comprises: Analyzing material properties corresponding to the semiconductor material; Based on the material properties, determining surface distribution characteristics corresponding to the semiconductor material; extracting key impurity factors in the surface distribution characteristics; Based on the key impurity factors, analyzing the potential defect types corresponding to the semiconductor material; Based on the potential defect type, the semiconductor material is subjected to defect treatment to obtain a pre-treated semiconductor material.

3. A method for manufacturing a semiconductor memory chip according to claim 1, characterized in that: The step of determining the area to be deposited corresponding to the pre-treated semiconductor material comprises: Analyzing physical structural characteristics corresponding to the pretreated semiconductor material; Based on the physical structural characteristics, querying the potential deposition sites on the surface of the corresponding material of the pretreated semiconductor material; Performing data evaluation on the potential deposition site to obtain deposition evaluation data; extracting dominant deposition sites from the deposition assessment data; Based on the advantageous deposition sites, a region to be deposited corresponding to the pretreated semiconductor material is determined.

4. A method for manufacturing a semiconductor memory chip according to claim 1, characterized in that: The step of determining the performance index of the memory chip to be prepared based on the expected read / write value includes: Based on the expected read and write values, evaluating the read and write speed level of the memory chip to be prepared; extracting key speed features in the read and write speed levels; Analyze the impact of the key speed characteristics on the overall performance of the chip; Querying key factors in the influencing data; Comparing the key factors with a preset performance influencing factor library to obtain a comparison result; Filtering a performance impact subset that meets a preset performance threshold in the comparison result; Based on the performance impact subset, a performance indicator of the memory chip to be manufactured is determined.

5. A method for manufacturing a semiconductor memory chip according to claim 1, characterized in that: The configuring packaging materials corresponding to the memory chip to be prepared based on the impact degree value includes: Determine the packaging material performance requirements corresponding to the impact degree value; Constructing a candidate set of packaging materials that meet the performance requirements of the packaging materials; Analyze the material properties of the materials in the packaging material candidate set; Query the packaging material type that meets the material characteristics; Based on the packaging material type, packaging materials corresponding to the memory chip to be prepared are configured.

6. A method for manufacturing a semiconductor memory chip according to claim 1, characterized in that: The step of constructing a curing environment corresponding to the memory chip to be prepared based on the packaging material includes: Determining the curing condition parameters required for the packaging material; Collecting basic environmental data related to the curing condition parameters; Analyzing available environmental resources corresponding to the environmental basic data; Based on the resource options, a curing environment framework corresponding to the memory chip to be prepared is preliminarily established; Based on the curing environment framework, a curing environment corresponding to the memory chip to be prepared is constructed.

7. A method for manufacturing a semiconductor memory chip according to claim 1, characterized in that: The abnormal source tracing of the process parameters to obtain an abnormal source set includes: Performing data classification on the process parameters to obtain process classification parameters; Draw a process change trend graph corresponding to the process classification parameter; Identify the change fluctuation point in the process change trend graph; Analyze the fluctuation change gradient corresponding to the change fluctuation point; Anomaly source tracing is performed on the gradient parameters in the fluctuation gradient to obtain an anomaly source set.

8. A system for manufacturing a semiconductor memory chip, characterized in that: A system for executing a method for manufacturing a semiconductor memory chip as claimed in any one of claims 1 to 7, the system comprising: A material processing module, used for obtaining chip parameters corresponding to the memory chip to be prepared, selecting semiconductor materials corresponding to the memory chip to be prepared according to the chip parameters, and performing material pretreatment on the semiconductor materials to obtain pretreated semiconductor materials; A read / write expected value calculation module is used to determine the area to be deposited corresponding to the pre-treated semiconductor material, and after depositing an insulating layer and a conductive layer on the area to be deposited, construct a multi-layer structure framework corresponding to the memory chip to be prepared, and determine the optimal thickness and layout of each layer of the memory chip to be prepared based on the multi-layer structure framework, and calculate the read / write expected value corresponding to the memory chip to be prepared according to the optimal thickness and layout, wherein the calculation of the read / write expected value corresponding to the memory chip to be prepared according to the optimal thickness and layout includes: The expected read / write value corresponding to the memory chip to be prepared is calculated using the following formula: in, Indicates the read time corresponding to the storage chip to be prepared, represents the length of the interconnect in the layout, Indicates that the resistivity of the memory chip to be prepared varies with temperature The change function of represents the optimum thickness, represents the line width in the layout, represents the line spacing in the layout, represents the driving voltage of the read / write circuit in the memory chip to be prepared, Indicates the length of the interconnect line The length of the differential element when performing the integration, represents a function of the signal transmission delay factor in the memory chip to be prepared varying with temperature, represents the capacitance value of the storage unit in the storage chip to be prepared, represents a function of the read current in the memory chip to be prepared varying with temperature, Indicates the writing time corresponding to the storage chip to be prepared, represents a function of the change of the write power in the memory chip to be prepared with the temperature, Indicates the expected read and write values ​​corresponding to the storage chip to be prepared; An influence degree value calculation module is used to determine the performance index of the memory chip to be prepared based on the expected read and write value, evaluate the preparation feasibility of the memory chip to be prepared based on the performance index, obtain preparation evaluation data, query the preparation influencing factors existing in the preparation evaluation data, and calculate the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factors, wherein the calculation of the influence degree value corresponding to the memory chip to be prepared based on the preparation influencing factors includes: The impact value corresponding to the memory chip to be prepared is calculated using the following formula: in, represents the impact value corresponding to the memory chip to be prepared, represents the number of factors influencing the preparation, represents the quantitative index of the preparation influencing factors, Indicates The influence weight of each preparation influencing factor is Indicates Actual measured values ​​of the factors affecting the preparation, Indicates Standard values ​​of factors affecting preparation; an abnormality tracing module, configured to configure the packaging material corresponding to the storage chip to be prepared based on the impact degree value, construct a curing environment corresponding to the storage chip to be prepared based on the packaging material, monitor the curing process state of the chip in the curing environment, extract the process parameters corresponding to the curing process state, perform abnormality tracing on the process parameters, and obtain an abnormality source set; A solution generation module is used to analyze the abnormal targets in the abnormal source set, identify the abnormal storage factors in the abnormal targets, monitor the preparation feedback data of the storage chip to be prepared during the preparation process based on the abnormal storage factors, and generate a chip preparation solution corresponding to the storage chip to be prepared based on the preparation feedback data.

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