DRAM test machine and method based on embedded logic analysis

Abstract

The present invention provides a DRAM test machine and method based on embedded logic analysis. An embedded logic analyzer is integrated in an ATE test control chip. The embedded logic analyzer is integrated in an ATE test control chip having a main control unit, a test vector generator, and a test result processor. The defects in the prior art are overcome, and the signals of the DRAM chip can be captured and analyzed in real time, so as to help test engineers quickly find problems and improve test efficiency. A plurality of signal channels can be monitored at the same time, so as to improve in-depth analysis capability, and specific trigger conditions can be set to capture key data. The complex timing behaviors of various DRAMs can be decoded and analyzed, so as to save test time. The machine is compactly integrated, does not occupy additional space, reduces costs, and improves benefits. The machine can quickly provide test results and feedback, and is helpful to shorten the test time of the DRAM chip and accelerate the test progress.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and more specifically, to a DRAM testing machine and method based on embedded logic analysis. Background Art

[0002] When testing DRAM (Dynamic Random Access Memory), it is usually tested through an external logic analyzer. When testing through an external logic analyzer, the test vector is often applied to the input pin of the DRAM chip through an ATE (Automated Test Equipment) machine, and the signal behavior of the DRAM chip output pin is collected in real time through the ATE test machine. The actual output data collected is then compared with the expected output data to determine whether the DRAM chip functions normally. However, this method has the following technical problems:

[0003] ① Difficulty in detection: DRAM chips are usually packaged in BGA, and the pins are located under the chip, making it difficult to directly connect the probe to the pins for measurement. To solve this problem, special detection methods may be required, such as back via adapters, DIMM serial resistors, or adapters, but these methods may introduce additional signal interference or complexity; ② Difficulty in distinguishing read and write bursts: The DRAM data bus is bidirectional, and it is necessary to distinguish the transmission bursts corresponding to read and write operations. In the case of large signal noise and reflection, it may be difficult to clearly distinguish only by observing the relationship between DQS and DQ data edges. Additional digital signal equipment may be required to collect the DRAM command bus and determine the read and write properties based on the command type. The oscilloscope may need to support more detection channels, which is difficult for general oscilloscopes to meet; ③ Unable to meet high-speed and high-precision requirements: In order to accurately measure high-speed DRAM signals, high-speed oscilloscopes need to have sufficient bandwidth, sampling rate, and measurement accuracy. At the same time, the probe of the oscilloscope also needs to have low load and good high-frequency response characteristics to avoid excessive attenuation or distortion of the signal. Therefore, DRAM testing has high requirements for oscilloscopes, and general oscilloscopes are difficult to meet the requirements; ④ Complex test settings: When performing DRAM testing, it is necessary to correctly set the parameters of the oscilloscope, such as trigger mode, sampling mode, measurement options, etc., to ensure that the required signal characteristics can be accurately captured and analyzed. In addition, it may be necessary to combine specific DRAM test software or analysis tools to perform standard-compliant tests and measurements; ⑤ High-speed oscilloscopes and DRAMATE testers are independent test equipment, and they cannot achieve perfect cooperation in realizing functions such as automation. They can only test single DRAM chips or DRAM bars, and cannot meet DRAMATE test requirements.

[0004] Therefore, there is an urgent need for a DRAM test machine and method based on embedded logic analysis that can achieve efficient real-time monitoring, perform multi-channel simultaneous analysis, improve in-depth analysis capabilities, be compactly integrated, flexibly configured, facilitate data analysis, and save test time. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a DRAM test machine based on embedded logic analysis to solve the following technical problems existing in the existing testing method through an external logic analyzer device: ① detection difficulty; ② reading and writing bursts are difficult to distinguish, and it may be difficult to clearly distinguish by observing the relationship between DQS and DQ data edges; ③ high speed and high precision requirements cannot be met; ④ test settings are complicated; ⑤ high-speed oscilloscopes and DRAM ATE test machines are independent test equipment, and cannot be perfectly coordinated in realizing functions such as automation. They can only test single DRAM chips or DRAM bars, and cannot meet DRAM ATE test requirements.

[0006] The present invention provides a DRAM test machine based on embedded logic analysis, which includes a test machine and various ATE test control chips arranged in the test machine; wherein,

[0007] The ATE test control chip integrates a main control unit, a test vector generator, a test result processor, and an embedded logic analyzer;

[0008] The main control unit is used to receive commands from the test machine to control the test vector generator, the test result processor, and the embedded logic analyzer;

[0009] The test vector generator is used to generate test vectors and expected outputs according to the specifications and test requirements of the DRAM to be tested;

[0010] The test result processor is used to collect the timing behavior information generated by the DRAM to be tested after receiving the test vector, and analyze and judge the timing behavior information based on the expected output to obtain the DRAM analysis result;

[0011] The embedded logic analyzer is used to lock the fault point of the DRAM to be tested according to the timing behavior information based on the DRAM analysis result, and analyze the timing behavior information of the fault point to obtain the test result.

[0012] Preferably, the embedded logic analyzer comprises a logic analyzer configuration module, a sampling module, a buffer, a trigger module and a logic output unit.

[0013] Preferably, the logic analyzer configuration module is connected to the main control unit, and is used to receive a logic analysis command issued by the main control unit, control or terminate the sampling module to sample the DRAM to be tested, control or terminate the buffer to cache data, and turn on or off the trigger module.

[0014] Preferably, the sampling module includes a preset number of sampling channels, and the sampling channels are used to perform real-time sampling on the DRAM to be tested through a preset sampling program to obtain a test vector input to the DRAM to be tested, an expected output, timing behavior information generated by the DRAM to be tested, and a DRAM analysis result;

[0015] The number of sampling channels is 2048.

[0016] Preferably, a test interface is also integrated on the ATE test control chip;

[0017] The test interface is communicatively connected with the test vector generator, the test result processor, the embedded logic analyzer, and the DRAM to be tested.

[0018] Preferably, the buffer is used to buffer all data information collected through the sampling channel within a preset time.

[0019] Preferably, the trigger module includes 16 groups of trigger logic units, and each trigger logic unit includes six types of signal transition edge trigger instructions.

[0020] Preferably, one of the signal transition edge trigger instructions is a fault trigger.

[0021] The fault trigger is: if the DRAM analysis result collected by the sampling channel is the DRAM fault to be tested, the logic output unit is triggered so that the logic output unit determines the timing behavior information corresponding to the fault trigger, forms a test digital waveform, and matches the corresponding test result according to the test digital waveform.

[0022] The present invention also provides a DRAM test method based on embedded logic analysis, wherein the DRAM test is implemented based on the DRAM test machine based on embedded logic analysis as described above, including:

[0023] Integrate an embedded logic analyzer into an ATE test control chip having a main control unit, a test vector generator, and a test result processor;

[0024] The main control unit receives a command from the test machine, and based on the command, generates a test vector and an expected output through the test vector generator according to the specification and test requirements of the DRAM to be tested;

[0025] Using the test result processor to collect the timing behavior information generated by the DRAM to be tested after receiving the test vector, and analyzing and judging the timing behavior information based on the expected output to obtain a DRAM analysis result;

[0026] The embedded logic analyzer locks the fault point of the DRAM to be tested based on the DRAM analysis result and the timing behavior information, and analyzes the timing behavior information of the fault point to obtain the test result.

[0027] Preferably, based on the DRAM analysis result, the fault point of the DRAM to be tested is locked according to the timing behavior information, and the timing behavior information of the fault point is analyzed to obtain the test result, including:

[0028] The DRAM to be tested is sampled in real time through a preset sampling program to obtain a test vector input to the DRAM to be tested, an expected output, timing behavior information generated by the DRAM to be tested, and a DRAM analysis result;

[0029] If the DRAM analysis result collected by the sampling channel is the DRAM fault to be tested, the logic output unit is triggered so that the logic output unit determines the timing behavior information corresponding to the fault trigger, forms a test digital waveform, and matches the corresponding test result according to the test digital waveform.

[0030] It can be seen from the above technical scheme that the DRAM test machine and method based on embedded logic analysis provided by the present invention integrate an embedded logic analyzer in an ATE test control chip, and integrate the embedded logic analyzer in an ATE test control chip having a main control unit, a test vector generator, and a test result processor, so that the main control unit receives commands from the test machine, and based on the commands, generates test vectors and expected outputs according to the specifications and test requirements of the DRAM to be tested through the test vector generator, and uses the test result processor to collect timing behavior information generated by the DRAM to be tested after receiving the test vector, and analyzes and judges the timing behavior information based on the expected output to obtain a DRAM analysis result, and locks the fault of the DRAM to be tested based on the DRAM analysis result and the timing behavior information through the embedded logic analyzer. This method overcomes the defects in the prior art and can achieve: efficient real-time monitoring: it can capture and analyze the signals of DRAM chips in real time, helping test engineers to quickly find problems and improve test efficiency; multi-channel simultaneous analysis: it can monitor multiple signal channels at the same time, which is very important for the synchronous analysis of multiple related signals in complex chips such as DRAM; improve in-depth analysis capabilities: it has powerful trigger functions and data parsing capabilities, can set specific trigger conditions to capture key data, and decode and analyze various complex timing behaviors of DRAM; save test time: compared with the use of multiple separate test equipment such as oscilloscopes, embedded logic analyzers are integrated in ATE In the tester, it reduces the time for equipment switching and connection; achieves system-level insight: helps ATE test engineers gain in-depth understanding of DRAM chip test conditions, including the interaction between hardware and software, so as to better perform system-level testing and verification; achieves flexible test settings: can be flexibly configured and programmed according to different test requirements, and adapts to a variety of chips and test scenarios; compact integration: does not take up additional space, the embedded logic analyzer is integrated inside the ATE test control chip, and is tightly integrated with other components of the ATE test control chip, making the entire test system more concise and efficient; reduces costs and improves benefits: since there is no need to purchase multiple independent logic analyzers, costs can be reduced to a certain extent; facilitates data analysis: directly provides test data to the main control system of the ATE tester, which facilitates unified data management and analysis; shortens feedback time: can quickly provide test results and feedback, which helps to shorten the test time of DRAM chips and speed up the test progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0032] Figure 1 A logic schematic diagram of a DRAM test machine based on embedded logic analysis according to an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of a specific embodiment of a DRAM test machine based on embedded logic analysis according to an embodiment of the present invention;

[0034] Figure 3 A logic schematic diagram of an embedded logic analyzer in a DRAM test machine based on embedded logic analysis according to an embodiment of the present invention;

[0035] Figure 4 4 is a flow chart of a DRAM testing method based on embedded logic analysis according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The existing testing method using an external logic analyzer is: ① difficult to detect; ② difficult to distinguish between read and write bursts, and it may be difficult to clearly distinguish by observing the relationship between DQS and DQ data edges; ③ unable to meet high-speed and high-precision requirements; ④ complex test settings; ⑤ high-speed oscilloscopes and DRAM ATE testers are independent test equipment, and cannot be perfectly coordinated in realizing functions such as automation. They can only test single DRAM chips or DRAM bars, and cannot meet DRAM ATE test requirements.

[0037] In view of the above problems, the present invention provides a DRAM test machine and method based on embedded logic analysis. The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] In order to illustrate the DRAM test machine and method based on embedded logic analysis provided by the present invention, Figure 1-Figure 4 The embodiments of the present invention are exemplarily indicated.

[0039] The following description of exemplary embodiments is merely illustrative in nature and is not intended to limit the present invention and its application or use. Technologies and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technologies and devices should be considered as part of the specification.

[0040] like Figure 1 , Figure 2As shown together, the DRAM test machine based on embedded logic analysis provided by the present invention includes a test machine and various ATE test control chips 100 arranged in the test machine; wherein, a main control unit 101, a test vector generator 102, a test result processor 103, and an embedded logic analyzer 104 are integrated in the ATE test control chip; the main control unit is used to receive commands from the test machine to control the test vector generator, the test result processor, and the embedded logic analyzer; the test vector generator is used to generate test vectors and expected outputs according to the specifications and test requirements of the DRAM to be tested 105; the test result processor is used to collect the timing behavior information generated by the DRAM to be tested 105 after receiving the test vector, and analyze and judge the timing behavior information based on the expected output to obtain a DRAM analysis result; the embedded logic analyzer is used to lock the fault point of the DRAM to be tested based on the DRAM analysis result according to the timing behavior information, and analyze the timing behavior information of the fault point to obtain a test result.

[0041] In this embodiment, a test interface 106 is also integrated on the ATE test control chip, and the test interface 106 is communicatively connected with the test vector generator 102, the test result processor 103, the embedded logic analyzer 104, and the DRAM to be tested 105. In other words, the embedded logic analyzer is integrated in the ATE test control chip, and the ATE test control chip also includes a main control unit, a test vector generator, a test result processor and a test interface, and the test interface is connected to the DRAM to be tested.

[0042] The test vector generator generates corresponding test vectors according to the specifications and test requirements of the DRAM to be tested. These test vectors contain a series of DRAM input timing signals and expected outputs, and apply these test vectors to the DRAM chip to be tested through the test interface.

[0043] The test result processor will collect the timing behavior information of the DRAM to be tested after the test vector is applied, and perform timing analysis to determine whether the timing behavior information it generates meets the expected results. If it does not meet the expected results, it is determined that the DRAM to be tested has a DRAM chip failure. For example, the test vector writes a certain value to a certain storage unit of the DRAM according to the DRAM specification requirements, and then reads the value of the corresponding storage unit. If the read data is inconsistent with the actual written data, or the actual output result is inconsistent with the expected output, it can be located as a DRAM chip failure.

[0044] The embedded logic analyzer has a signal acquisition trigger function. When the test result processor detects a chip fault, it will trigger the embedded logic analyzer to collect the timing behavior of the DRAM interface of the fault point, which will help testers to quickly understand the cause of the fault by analyzing the timing behavior of the fault point.

[0045] In this embodiment, the entire embedded logic analyzer is integrated into the ATE test control chip. The specific integration method is not limited here. It can be any method of integrating the functional module on the chip, as long as the chip satisfies the functional description of the above-mentioned embedded logic analyzer. The entire embedded logic analyzer is integrated into the ATE test control chip to capture and analyze the signals of the DRAM chip in real time, helping test engineers to quickly find problems and improve test efficiency. Compared with the use of multiple separate test equipment such as oscilloscopes, the embedded logic analyzer is integrated into the ATE test machine, which reduces the time for equipment switching and connection. In addition, the embedded logic analyzer is compactly integrated into the ATE test control chip and does not occupy additional space. The embedded logic analyzer is integrated inside the ATE test control chip and is tightly integrated with other components of the ATE test control chip, making the entire test system more concise and efficient, directly providing test data to the main control system of the ATE test machine, facilitating unified data management and analysis, and can quickly provide test results and feedback, which helps to shorten the test time of the DRAM chip and speed up the test progress. In addition, since there is no need to purchase multiple independent logic analyzers, the cost of the test equipment can be reduced to a certain extent.

[0046] Figure 2 The structure diagram of an ATE test control chip (ATE control chip) in a more specific embodiment is shown. The ATE test control chip includes the following functional units:

[0047] The main control unit (also known as the main controller unit or main control unit) is a RISC-V CPU, which is the core of the ATE test control chip and manages the operation of each internal functional module of the ATE test control chip. The ATE test vector generator (test vector generator) receives the instructions issued by the main control unit through the AXIi interface, generates ATE test vectors, and passes the test vectors to the PHY interface of DDR / LPDDR through the DFI test interface, and finally applies the test stimulus to the unit under test DDR / LPDDR for functional testing; the embedded logic analyzer, one end of the embedded logic analyzer is connected to the main control unit, communicates with the main control chip, receives the control of the main control chip, can configure the number of sampling channels, sampling depth, and the Trigger mode of the embedded logic analyzer, and can pass the sampling results or trigger information of the embedded logic analyzer to the main control unit, and the main control unit can process the sampling information or trigger information. The test result processor receives the test results of DDR / LPDDR DRAM through the DFI interface and processes the test results. The test vector generator and the ATE test result processor (test result processor) will generate a Trigger signal to the embedded logic analyzer at the appropriate time through the Trigger interface to trigger the DFI interface signal. The Trigger of the test vector generator (ATE test vector generator) is mainly used to observe whether the test vector generated by the ATE test vector generator is the correct test vector through the embedded logic analyzer. The Trigger interface of the test result processor is mainly used to observe and analyze the abnormal behavior of the DFI interface through the embedded logic analyzer when the DRAM test result is abnormal.

[0048] like Figure 3As shown, in this embodiment, the embedded logic analyzer includes a logic analyzer configuration module 1041, a sampling module 1043, a buffer 1042, a trigger module 1044 and a logic output unit (not shown in the figure). The logic analyzer configuration module 1041 is connected to the main control unit 101, and is used to receive the logic analysis command issued by the main control unit, control or terminate the sampling module 1043 to sample the DRAM to be tested, control or terminate the buffer to cache data, and turn on or off the trigger module. The sampling module includes a preset number of sampling channels, and the sampling channels are used to perform real-time sampling of the DRAM to be tested through a preset sampling program to obtain the test vector input to the DRAM to be tested, the expected output, the timing behavior information generated by the DRAM to be tested, and the DRAM analysis result; in a specific embodiment, the sampling channels are 2048. A test interface is also integrated on the ATE test control chip, and the test interface is connected to the test vector generator, the test result processor, the embedded logic analyzer, and the DRAM to be tested. The buffer is used to cache all data information collected by the sampling channel within a preset time; the trigger module includes 16 groups of trigger logic units, each of which contains six types of signal jump edge trigger instructions. One of the signal jump edge trigger instructions is a fault trigger, which is: if the DRAM analysis result collected by the sampling channel is the DRAM fault to be tested, then the logic output unit is triggered, so that the logic output unit determines the timing behavior information corresponding to the fault trigger, forms a test digital waveform, and matches the corresponding test result according to the test digital waveform.

[0049] The embedded logic analyzer configuration module can configure the entire embedded logic analyzer, including the number of sampling channels and sampling passband, DRAM trigger mode, etc., so that engineers can intervene in the test process at any time, increasing the convenience of testing. It helps ATE test engineers to have a deep understanding of DRAM chip testing, including the interaction between hardware and software, so as to better perform system-level testing and verification. It can also be flexibly configured and programmed according to different test requirements to adapt to a variety of chips and test scenarios.

[0050] The sampling channels of the sampling module are configurable, supporting the sampling of up to 2048 channels of signals at the same time. At the same time, different types of DRAM such as DDR4 / DDR5 / LPDD4 / LPDDR5 can be sampled according to the type of DRAM being tested, that is, multiple signal channels can be monitored at the same time, which is very important for the synchronous analysis of multiple related signals in complex chips such as DRAM, and improves the breadth and adaptability of DRAM testing.

[0051] In this embodiment, the trigger module implements 16 groups of trigger logic control units, each of which includes multiple trigger modes such as ==, !=, >, <, <=, >=, signal jump edge trigger, etc. At the same time, the 16 groups of trigger logic units can be combined in different ways to realize different trigger functions, which can meet the triggering of various timing behaviors of DRAM. The embedded buffer module can store the collected information in the buffer. The width and depth of the buffer can be configured to meet the sampling requirements of various sampling channel numbers and depths. The trigger module has powerful trigger functions and data parsing capabilities, and can set specific trigger conditions to capture key data, and decode and analyze various complex timing behaviors of DRAM. The embedded logic analyzer can be linked with the test vector generator and test result processor of the ATE test chip to start the functions of the embedded logic analyzer in real time as needed, thereby meeting the automated testing requirements of the ATE test machine.

[0052] As described above, the DRAM test machine based on embedded logic analysis provided by the present invention has an embedded logic analyzer integrated in the ATE test control chip, and the embedded logic analyzer is integrated in the ATE test control chip with a main control unit, a test vector generator, and a test result processor, which overcomes the defects in the prior art and can achieve: efficient real-time monitoring: it can capture and analyze the signals of the DRAM chip in real time, helping test engineers to quickly find problems and improve test efficiency; multi-channel simultaneous analysis: it can monitor multiple signal channels at the same time, which is very important for the synchronous analysis of multiple related signals in complex chips such as DRAM; improve in-depth analysis capabilities: it has powerful trigger functions and data parsing capabilities, can set specific trigger conditions to capture key data, and decode and analyze various complex timing behaviors of DRAM; save test time: compared with the use of multiple separate test equipment such as oscilloscopes, the embedded logic analyzer is integrated in the ATE In the tester, it reduces the time for equipment switching and connection; achieves system-level insight: helps ATE test engineers gain in-depth understanding of DRAM chip test conditions, including the interaction between hardware and software, so as to better perform system-level testing and verification; achieves flexible test settings: can be flexibly configured and programmed according to different test requirements, and adapts to a variety of chips and test scenarios; compact integration: does not take up additional space, the embedded logic analyzer is integrated inside the ATE test control chip, and is tightly integrated with other components of the ATE test control chip, making the entire test system more concise and efficient; reduces costs and improves efficiency: since there is no need to purchase multiple independent logic analyzers, costs can be reduced to a certain extent; facilitates data analysis: directly provides test data to the main control system of the ATE tester, which facilitates unified data management and analysis; shortens feedback time: can quickly provide test results and feedback, which helps to shorten the test time of DRAM chips and speed up the test progress.

[0053] In addition, if Figure 4 As shown, the present invention also provides a DRAM test method based on embedded logic analysis, which implements DRAM testing based on the aforementioned DRAM test machine based on embedded logic analysis, including:

[0054] S1: Integrate the embedded logic analyzer into an ATE test control chip having a main control unit, a test vector generator, and a test result processor;

[0055] S2: enabling the main control unit to receive a command from the test machine, and based on the command, generating a test vector and an expected output through the test vector generator according to the specification and test requirements of the DRAM to be tested;

[0056] S3: using the test result processor to collect timing behavior information generated after the DRAM to be tested receives the test vector, and analyzing and judging the timing behavior information based on the expected output to obtain a DRAM analysis result;

[0057] S4: locking the fault point of the DRAM to be tested based on the DRAM analysis result and the timing behavior information by the embedded logic analyzer, and analyzing the timing behavior information of the fault point to obtain the test result.

[0058] In one embodiment, based on the DRAM analysis result, the fault point of the DRAM to be tested is locked according to the timing behavior information, and the timing behavior information of the fault point is analyzed to obtain the test result, including:

[0059] The DRAM to be tested is sampled in real time through a preset sampling program to obtain a test vector input to the DRAM to be tested, an expected output, timing behavior information generated by the DRAM to be tested, and a DRAM analysis result;

[0060] If the DRAM analysis result collected by the sampling channel is the DRAM fault to be tested, the logic output unit is triggered so that the logic output unit determines the timing behavior information corresponding to the fault trigger, forms a test digital waveform, and matches the corresponding test result according to the test digital waveform.

[0061] The specific implementation example may refer to the specific implementation method of the DRAM test machine based on embedded logic analysis, which will not be described in detail again.

[0062] As shown above, the DRAM testing method based on embedded logic analysis provided by the present invention enables the main control unit to receive the command of the test machine, and based on the command, generates a test vector and an expected output according to the specifications and test requirements of the DRAM to be tested through the test vector generator, uses the test result processor to collect the timing behavior information generated by the DRAM to be tested after receiving the test vector, and analyzes and judges the timing behavior information based on the expected output to obtain a DRAM analysis result, and locks the fault point of the DRAM to be tested based on the DRAM analysis result according to the timing behavior information through the embedded logic analyzer, and performs timing behavior information analysis on the fault point. This method overcomes the defects of the existing technology and can achieve: efficient real-time monitoring: it can capture and analyze the signals of DRAM chips in real time, helping test engineers to quickly find problems and improve test efficiency; multi-channel simultaneous analysis: it can monitor multiple signal channels at the same time, which is very important for the synchronous analysis of multiple related signals in complex chips such as DRAM; improve in-depth analysis capabilities: it has powerful trigger functions and data parsing capabilities, can set specific trigger conditions to capture key data, and decode and analyze various DRAM complex timing behaviors; save test time: compared with the use of multiple separate test equipment such as oscilloscopes, embedded logic analyzers are integrated in ATE In the tester, it reduces the time for equipment switching and connection; achieves system-level insight: helps ATE test engineers gain in-depth understanding of DRAM chip test conditions, including the interaction between hardware and software, so as to better perform system-level testing and verification; achieves flexible test settings: can be flexibly configured and programmed according to different test requirements, and adapts to a variety of chips and test scenarios; compact integration: does not take up additional space, the embedded logic analyzer is integrated inside the ATE test control chip, and is tightly integrated with other components of the ATE test control chip, making the entire test system more concise and efficient; reduces costs and improves efficiency: since there is no need to purchase multiple independent logic analyzers, costs can be reduced to a certain extent; facilitates data analysis: directly provides test data to the main control system of the ATE tester, which facilitates unified data management and analysis; shortens feedback time: can quickly provide test results and feedback, which helps to shorten the test time of DRAM chips and speed up the test progress.

[0063] As described above with reference to the accompanying drawings, the DRAM test machine and method based on embedded logic analysis proposed according to the present invention are described by way of example. However, those skilled in the art should understand that various improvements can be made to the DRAM test machine and method based on embedded logic analysis proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A DRAM test machine based on embedded logic analysis, characterized in that: It includes a test machine and various ATE test control chips arranged in the test machine; wherein, The ATE test control chip integrates a main control unit, a test vector generator, a test result processor, and an embedded logic analyzer; The main control unit is used to receive commands from the test machine to control the test vector generator, the test result processor, and the embedded logic analyzer; the main control unit is a RISC-V CPU; the embedded logic analyzer includes a logic analyzer configuration module, a sampling module, a buffer, a trigger module and a logic output unit; the logic analyzer configuration module is connected to the main control unit, and is used to receive a logic analysis command issued by the main control unit, control or terminate the sampling module to sample the DRAM to be tested, control or terminate the buffer to cache data, and turn on or off the trigger module; the sampling module includes a preset number of sampling channels, and the sampling channels are used to perform real-time sampling of the DRAM to be tested through a preset sampling program to obtain the test vector input to the DRAM to be tested, the expected output, the timing behavior information generated by the DRAM to be tested, and the DRAM analysis result; the number of sampling channels is 2048; The test vector generator is used to receive instructions issued by the main control unit through the AXIi interface, and generate test vectors and expected outputs according to the specifications and test requirements of the DRAM to be tested; the test vectors are ATE test vectors; wherein the ATE test vectors are transmitted to the PHY interface of the DRAM to be tested through the DFI test interface; The test result processor is used to collect the timing behavior information generated by the DRAM to be tested after receiving the test vector, and analyze and judge the timing behavior information based on the expected output to obtain the DRAM analysis result; The embedded logic analyzer is used to lock the fault point of the DRAM to be tested according to the timing behavior information based on the DRAM analysis result, and analyze the timing behavior information of the fault point to obtain the test result; A test interface is also integrated on the ATE test control chip; The test interface is communicatively connected with the test vector generator, the test result processor, the embedded logic analyzer, and the DRAM to be tested.

2. The DRAM tester based on embedded logic analysis as claimed in claim 1, characterized in that: The buffer is used to buffer all data information collected through the sampling channel within a preset time.

3. The DRAM test machine based on embedded logic analysis as claimed in claim 2, characterized in that: The trigger module includes 16 groups of trigger logic units, and each trigger logic unit includes six types of signal jump edge trigger instructions.

4. The DRAM test machine based on embedded logic analysis as claimed in claim 3, characterized in that: One of the signal transition edge trigger instructions is fault trigger. The fault trigger is: if the DRAM analysis result collected by the sampling channel is the DRAM fault to be tested, the logic output unit is triggered so that the logic output unit determines the timing behavior information corresponding to the fault trigger, forms a test digital waveform, and matches the corresponding test result according to the test digital waveform.

5. A DRAM testing method based on embedded logic analysis, characterized in that: Implementing DRAM testing based on the DRAM testing machine based on embedded logic analysis as described in any one of claims 1 to 4, comprising: An embedded logic analyzer is integrated into an ATE test control chip having a main control unit, a test vector generator, a test result processor, and a test interface; the main control unit is a RISC-V CPU; the test interface is communicatively connected with the test vector generator, the test result processor, the embedded logic analyzer, and the DRAM to be tested; The main control unit receives a command from a test machine, and based on the command, generates a test vector and an expected output through the test vector generator according to the specifications and test requirements of the DRAM to be tested; wherein the test vector generator receives an instruction issued by the main control unit through an AXIi interface, and generates a test vector and an expected output according to the specifications and test requirements of the DRAM to be tested; the test vector is an ATE test vector; wherein the ATE test vector is transmitted to the PHY interface of the DRAM to be tested through a DFI test interface; Using the test result processor to collect the timing behavior information generated by the DRAM to be tested after receiving the test vector, and analyzing and judging the timing behavior information based on the expected output to obtain a DRAM analysis result; The embedded logic analyzer is used to lock the fault point of the DRAM to be tested based on the DRAM analysis result and the timing behavior information, and analyze the timing behavior information of the fault point to obtain the test result; wherein, the embedded logic analyzer includes a logic analyzer configuration module, a sampling module, a buffer, a trigger module and a logic output unit; the logic analyzer configuration module is connected to the main control unit, and is used to receive the logic analysis command issued by the main control unit, control or terminate the sampling module to sample the DRAM to be tested, control or terminate the buffer to cache data, and turn on or off the trigger module; the sampling module includes a preset number of sampling channels, and the sampling channels are used to perform real-time sampling of the DRAM to be tested through a preset sampling program to obtain the test vector input to the DRAM to be tested, the expected output, the timing behavior information generated by the DRAM to be tested, and the DRAM analysis result; the sampling channels are 2048.

6. The DRAM testing method based on embedded logic analysis as claimed in claim 5, characterized in that: Based on the DRAM analysis result, the fault point of the DRAM to be tested is locked according to the timing behavior information, and the timing behavior information of the fault point is analyzed to obtain the test result, including: The DRAM to be tested is sampled in real time through a preset sampling program to obtain a test vector input to the DRAM to be tested, an expected output, timing behavior information generated by the DRAM to be tested, and a DRAM analysis result; If the DRAM analysis result collected by the sampling channel is the DRAM fault to be tested, the logic output unit is triggered so that the logic output unit determines the timing behavior information corresponding to the fault trigger, forms a test digital waveform, and matches the corresponding test result according to the test digital waveform.

Images