SR-IOV handshake system, method and device for PCIe and NVMe of SSD main control chip and medium

Abstract

The invention provides an SR-IOV handshake system, method and device for PCIe and NVMe of an SSD main control chip and a medium, and belongs to the technical field of storage virtualization control. The system comprises an NVMe subsystem and a PCIe controller; the NVMe subsystem comprises a plurality of NVMe controllers; the PCIe controller is provided with a plurality of PFs and a plurality of VFs; each VF is bound to a physical function interface PF; the PCIe controller is connected with the NVMe controller through an AXI bus; the AXI bus comprises an AxUSER signal line, and a sriov controller is arranged on the AxUSER signal line; and the sriov controller is used for carrying out PF and VF distribution of the PCIe controller and carrying out conversion between the address of each NVMe controller of the NVMe subsystem and the PF number and the VF number of the PCIe controller. According to the invention, handshake between each PCIe functional interface and the NVMe controller is realized.

Description

Background Art

[0002] SSD is the abbreviation of Solid State Drive.

[0003] SR-IOV is the abbreviation of Single-Root I / O Virtualization. Single-root I / O virtualization is a way of managing and sharing the IO of the server storage disk through the virtual layer. SR-IOV has two channel types: PF and VF. PF is the function of the PCIe device in the physical channel, and VF is the function of the PCIe device in the virtual channel.

[0004] AXI, short for Advanced eXtensible Interface, is a bus protocol.

[0005] PCIe, short for Peripheral Component Interconnect Express, is a high-speed serial computer expansion bus standard.

[0006] NVMe is the abbreviation of NonVolatile Memory express, which is non-volatile fast memory.

[0007] NVMe SSD can reduce the number of PCIe devices required by users with the help of SR-IOV virtualization technology, and can also achieve multi-namespace management to achieve data IO isolation. The NVMe subsystem that supports SR-IOV function has physical functions and multiple virtual functions under each physical function. Each virtual function needs to be bound to a physical function, and each function will correspond to an NVMe controller.

[0008] The data interaction between PCIe and NVMe controller is carried out through two groups of AXI buses. One group of PCIe is used as the master interface to send data to the NVMe controller, and the other group of PCIe is used as the slave interface to receive data sent by the NVMe controller. The design process requires that the data of each PCIe function be correctly transmitted to the corresponding NVMe controller. Incorrect transmission will lead to reduced system stability and reliability. In the PCIe system that supports SR-IOV, the PF and VF sideband signals are added to indicate whether the AXI data transmission is PF data or VF data, and the function number is increased to indicate which function the data on the AXI bus comes from. Nitrogen is mostly bound to multiple VFs by a single PF. The handshake between the PCIe function and the NVMe controller is generally carried out using the user signal of the AXI bus. For example, in a related method, the PF_NUM signal is always added to PCIe to indicate which PF, and the VF_NUM is added to indicate which VF. O_VF_ACTIVE indicates whether the AXI data transmitted by PCIe to NVMe is VF data, and I_VF_ACTIVE indicates whether the AXI data transmitted by NVMe to PCIe is VF data. The handshake method when PCIe is used as the main interface to transmit data to NVMe is as follows:

[0009] 1. When O_VF_ACTIVE = 0, AXI_user = PF_NUM;

[0010] 2. When O_VF_ACTIVE = 1, AXI_user = VF_NUM + 1;

[0011] The handshake mode of NVMe as the main interface to transmit data to PCIe is as follows:

[0012] 1. Determine whether AXI_User is greater than 0;

[0013] 2. When AIX_User is equal to 0, PF_NUM = 0, I_VF_ACTIVE = 0;

[0014] 3. When AIX_User is greater than 0, VF_NUM=AIX_User-1, I_VF_ACTIVE=1.

[0015] This is a shortcoming of the prior art. Therefore, in view of the above-mentioned defects in the prior art, it is very necessary to provide a SR-IOV handshake system, method, device and medium for SSD master control chip PCIe and NVMe. Summary of the invention

[0016] In view of the defect that in the communication process between PCIe and NVMe subsystem supporting SR-IOV function in the prior art, the current design method can only be used in a system in which each PF is bound to a fixed number of VFs, and cannot meet the handshake requirements for a system in which the number of bound VFs is uncertain, the present invention provides an SR-IOV handshake system, method, device and medium between SSD master control chip PCIe and NVMe to solve the above technical problems.

[0017] In a first aspect, the present invention provides an SR-IOV handshake system between an SSD master control chip PCIe and NVMe, including an NVMe subsystem and a PCIe controller;

[0018] The NVMe subsystem includes several NVMe controllers;

[0019] The PCIe controller is provided with a number of physical function interfaces PF and a number of virtual function interfaces VF; each virtual function interface VF is bound to a physical function interface PF;

[0020] The PCIe controller and NVMe controller are connected via the AXI bus;

[0021] The AXI bus includes an AxUSER signal line, on which a sriov controller is provided;

[0022] The NVMe subsystem represents each NVMe controller through the signal of the AxUSER signal line;

[0023] The sriov controller is used to allocate the physical function interface PF and the virtual function interface VF of the PCIe controller, and convert the addresses of each NVMe controller of the NVMe subsystem with the physical function interface PF number and the virtual function interface VF number of the PCIe controller.

[0024] Further, the AXI bus also includes a data transmission line, and the data transmission line includes a master transmission line and a slave transmission line;

[0025] The main transmission line uses the PCIe controller as the main interface and the NVMe controller as the slave interface for data transmission;

[0026] The slave transmission line uses the NVMe controller as the main interface and the PCIe controller as the slave interface for data transmission.

[0027] Further, the AxUSER signal line includes a master AxUSER signal line and a slave AxUSER signal line;

[0028] The main AxUSER signal line includes a front-end main write channel signal line, a rear-end main write channel signal line, a front-end main read channel signal line, and a rear-end main read channel signal line;

[0029] The front-end main write channel signal line connects the PCIe controller and the sirov controller, and the rear-end main write channel signal line connects the sirov controller and the NVMe controller;

[0030] The slave AxUSER signal lines include a front-end slave write channel signal line, a rear-end slave write channel signal line, a front-end slave read channel signal line, and a rear-end slave read channel signal line;

[0031] The front section connects the NVMe controller and the sirov controller through the write channel signal line, and the back section connects the sirov controller and the PCIe controller through the write channel signal line.

[0032] Furthermore, the sriov controller is provided with:

[0033] The first conversion module converts the VF active signal in the AxUSER signal line, the number of the current physical function interface PF, the required number of physical function interfaces PF, the number of virtual function interfaces VF required under each physical function interface PF, and the number of virtual function interfaces VF under the current physical function interface PF number into the number AxUSER of the user identification signal representing the NVMe controller when the PCIe controller transmits data to the NVMe subsystem as the main interface;

[0034] The second conversion module, when the PCIe controller acts as a slave interface to receive data transmitted by the NVMe subsystem, converts the required number of physical function interfaces PF, the required number of virtual function interfaces VF under each physical function interface PF, and the number AxUSER of the user identification signal representing the NVMe controller in the AxUSER signal line into a VF active signal, the current physical function interface PF number, and the current virtual function interface VF number.

[0035] Furthermore, the first conversion module includes:

[0036] A virtual interface active function identification unit, used to identify a VF active signal VF_ACTIVE in the AxUSER signal line when the PCIe controller transmits data to the NVMe subsystem as an AXI master interface;

[0037] A first user identification signal calculation unit, used for determining that the virtual function interface VF is not enabled when VF_ACTIVE=0, and the user identification signal number AxUSER=the number PF_NUM of the current virtual function interface PF;

[0038] The current physical function interface identification unit is used to determine that the virtual function interface VF is turned on when VF_ACTIVE=1, obtain the current PCIe descriptor in the AxUSER signal line, and identify the number PF_NUM of the current physical function interface PF;

[0039] The second user identification signal calculation unit sets the user identification signal number AxUSER=

[0040] The number of physical function interfaces PF_NUM_TOTAL required + the number of the current PF PF_NUM + the sum of the number of virtual function interfaces VF under each previous physical function interface PF + the number VF_NUM of the current virtual function interface VF under the current physical function interface PF;

[0041] The destination NVMe controller determining unit is used to determine to which NVMe controller the data is to be transmitted according to the number AxUSER of the user identification signal.

[0042] Furthermore, the second conversion module includes:

[0043] A user identification number identification unit, used to identify the number AxUSER of the user identification signal in the AxUSER signal line when the PCIe controller receives NVMe system transmission data as an AXI slave interface;

[0044] A unit for comparing the user identification signal number and the required physical function quantity, used to determine whether the user identification signal number AxUSER> the required physical function interface PF number PF_NUM_TOTAL-1 is established;

[0045] The virtual function start determination unit is used to determine that the VF active signal VF_ACTIVE=1 when the number of the user identification signal AxUSER> the number of the required physical function interface PF_NUM_TOTAL-1 is established;

[0046] The virtual function is not enabled. If the number AxUSER used for user identification signal > the number of required physical function interfaces PF_NUM_TOTAL-1 is not established, the VF active signal VF_ACTIVE = 0;

[0047] A physical function interface determination unit, used for setting the number PF_NUM of the current physical function interface PF to correspond to the number AxUSER of the user identification signal which is greater than the number PF*_VF_NUM of the virtual function interface VF corresponding to all the previous physical function interfaces PF of the current physical function interface PF plus the number PF_NUM_TOTAL of the required physical function interfaces PF-1 and less than the number PF*_VF_NUM of the virtual function interfaces VF required by the physical function interface PF and the sum of the number PF*_VF_NUM of the virtual function interfaces VF required by all the previous physical function interfaces PF plus the number PF_NUM_TOTAL of the required physical function interfaces PF;

[0048] A VF active signal determination unit, used to determine whether the VF active signal VF_ACTIVE is 0;

[0049] A virtual interface number determination unit, used for setting the number VF_NUM of the current virtual function interface VF to be equal to the number AxUSER of the user identification signal minus the number PF_NUM_TOTAL of the required physical function interfaces PF and the number PF*_VF_NUM of the virtual function interfaces VF required by the physical function interface PF preceding the number PF_NUM of the current physical function interface PF when the VF active signal VF_ACTIVE is 0;

[0050] The destination PCIe controller interface determination unit is used to determine, when the VF active signal VF_ACTIVE is not 0, according to the number PF_NUM of the current physical function interface PF and the number VF_NUM of the current virtual function interface VF to which interface of the PCIe controller the data is transmitted.

[0051] In a second aspect, the present invention provides an SR-IOV handshake method between an SSD master control chip PCIe and NVMe, comprising the following steps:

[0052] S1. Set up a sriov controller between the PCIe controller and the NVMe subsystem, and pre-configure the required number of physical function interfaces PF and the number of virtual function interfaces VF required under each physical function interface PF;

[0053] S2. When the PCIe controller transmits data to the NVMe subsystem as the main interface, the sriov controller converts the VF active signal in the AxUSER signal line, the number of the current physical function interface PF, the required number of physical function interfaces PF, the number of virtual function interfaces VF required under each physical function interface PF, and the number of virtual function interfaces VF under the current physical function interface PF number into the number AxUSER representing the user identification signal of the NVMe controller;

[0054] S3. When the PCIe controller receives data transmitted by the NVMe subsystem as a slave interface, the sriov controller converts the required number of physical function interfaces PF, the required number of virtual function interfaces VF under each physical function interface PF, and the number AxUSER of the user identification signal representing the NVMe controller in the AxUSER signal line into a VF active signal, the current physical function interface PF number, and the current virtual function interface VF number.

[0055] Furthermore, the specific steps of step S1 are as follows:

[0056] S11. Set a sriov controller on the AxUSER signal line of the AXI bus between the PCIe controller and each NVMe controller;

[0057] S12. Obtain the maximum number of physical function interfaces PF_NUM_MAX and the maximum number of virtual function interfaces VF_NUM_MAX supported by the PCIe controller, and configure them in the sriov controller;

[0058] S13. Configure the required number of physical function interfaces PF_NUM_TOTAL and the number PF_NUM of each physical function interface PF in the sriov controller, wherein the required number of physical function interfaces PF_NUM_TOTAL is less than or equal to the maximum number of physical function interfaces PF PF_NUM_MAX supported by the PCIe controller;

[0059] S14. Configure the number of virtual function interfaces VF PF*_VF_NUM required for each physical function interface PF and the number VF_NUM of each virtual function interface VF in the sriov controller, wherein the sum of the number of virtual function interfaces VF PF*_VF_NUM required for each physical function interface PF is less than or equal to the maximum number of virtual function interfaces VF VF_NUM_MAX supported by the PCIe controller.

[0060] Furthermore, the specific steps of step S2 are as follows:

[0061] S21. When the PCIe controller transmits data to the NVMe subsystem as the AXI master interface, the sriov controller identifies the VF active signal VF_ACTIVE in the AxUSER signal line;

[0062] When VF_ACTIVE=0, go to step S22;

[0063] When VF_ACTIVE=1, go to step S23;

[0064] S22. It is determined that the virtual function interface VF is not enabled, the user identification signal number AxUSER = the current virtual function interface PF number PF_NUM, and the process proceeds to step S25;

[0065] S23. Determine that the virtual function interface VF is turned on, obtain the current PCIe descriptor in the AxUSER signal line, and identify the number PF_NUM of the current physical function interface PF;

[0066] S24. User identification signal number AxUSER =

[0067] The number of physical function interfaces PF_NUM_TOTAL required + the number of the current PF PF_NUM + the sum of the number of virtual function interfaces VF under each previous physical function interface PF + the number VF_NUM of the current virtual function interface VF under the current physical function interface PF;

[0068] The S25.sriov controller determines to which NVMe controller the data is transmitted based on the number AxUSER of the user identification signal.

[0069] Furthermore, the specific steps of step S3 are as follows:

[0070] S31. When the PCIe controller receives data transmitted by the NVMe system as an AXI slave interface, it identifies the user identification signal number AxUSER in the AxUSER signal line;

[0071] S32. Determine whether the user identification signal number AxUSER> the required number of physical function interfaces PF_NUM_TOTAL-1 is established;

[0072] If so, determine that the VF active signal VF_ACTIVE=1, and go to step S33;

[0073] If not, it is determined that the VF active signal VF_ACTIVE=0, and the process goes to step S33;

[0074] S33. The number PF_NUM of the current physical function interface PF needs to correspond to the number AxUSER of the user identification signal greater than the virtual function interface VF number PF*_VF_NUM corresponding to all the previous physical function interfaces PF of the current physical function interface PF plus the number of required physical function interfaces PF PF_NUM_TOTAL-1 and less than the number of virtual function interfaces VF PF*_VF_NUM required for the physical function interface PF and the sum of the number of virtual function interfaces VF PF*_VF_NUM required for all the previous physical function interfaces PF plus the number of required physical function interfaces PF PF_NUM_TOTAL;

[0075] S34. Determine whether the VF active signal VF_ACTIVE is 0;

[0076] If yes, go to step S36;

[0077] If not, proceed to step S35;

[0078] S35. The number VF_NUM of the current virtual function interface VF is equal to the number AxUSER of the user identification signal minus the number PF_NUM_TOTAL of the required physical function interfaces PF and the number PF_NUM of the current physical function interface PF and the number PF*_VF_NUM of the required virtual function interfaces VF of the physical function interface PF in front of the number PF_NUM of the current physical function interface PF;

[0079] S36. The sriov controller determines to which interface of the PCIe controller the data is to be transmitted according to the number PF_NUM of the current physical function interface PF and the number VF_NUM of the current virtual function interface VF.

[0080] In a third aspect, the present invention provides an electronic device, including a processor and a memory;

[0081] The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the electronic device executes the method described in the second aspect above.

[0082] In a fourth aspect, the present invention provides a storage medium,

[0083] The storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the second aspect.

[0084] The beneficial effects of the present invention are:

[0085] The present invention provides an SR-IOV handshake system, method, device and medium for SSD master chip PCIe and NVMe. An SR-IOV controller is designed in the SSD master chip supporting the SR-IOV function, and a handshake between each functional interface of PCIe and the NVMe controller is realized. At the same time, a handshake mechanism with the NVMe controller can be dynamically configured according to different PFs and VFs allocated according to PCIe. Compared with the previous PCIe each VF must be bound to a fixed NVMe controller, the waste of NVMe controller resources is avoided, so that resource utilization is more reasonable, and dynamic allocation can make the system more flexible.

[0086] In addition, the invention has a reliable design principle, a simple structure and a very broad application prospect.

[0087] It can be seen that compared with the prior art, the present invention has outstanding substantive features and significant progress, and the beneficial effects of its implementation are also obvious. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0089] Figure 1 It is a schematic diagram of the SR-IOV handshake system of the SSD master control chip PCIe and NVMe of the present invention.

[0090] Figure 2 It is a flow chart of the SR-IOV handshake method between the SSD master control chip PCIe and NVMe of the present invention.

[0091] Figure 3 It is a schematic diagram of the correspondence between the functional interfaces of the NVMe controller and the PCIe controller of the present invention. DETAILED DESCRIPTION

[0092] Since the number of controllers owned by NVMe is fixed, but the number of physical functions supported by PCIe is not fixed, the present invention performs a two-way handshake design based on the number of physical functions PF configured by PCIe and the number of virtual interfaces VF bound to each physical interface PF, thereby rationally utilizing the number of controllers owned by NVMe and avoiding waste of resources.

[0093] The SR-IOV handshake method between the SSD main control chip PCIe and NVMe can be applied to one or more devices, wherein the device is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASIC), programmable gate arrays (FPGA), digital signal processors (DSP), embedded devices, etc.

[0094] An electronic device can be any electronic product that can interact with a user, such as a personal computer, a tablet computer, a smart phone, a personal digital assistant (PDA), an interactive network television (IPTV), etc. The network in which the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (VPN), etc.

[0095] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0096] See also Figure 1 The figure shows a SR-IOV handshake system between an SSD master control chip PCIe and NVMe in a specific implementation, including an NVMe subsystem and a PCIe controller;

[0097] The NVMe subsystem includes several NVMe controllers;

[0098] The PCIe controller is provided with a number of physical function interfaces PF and a number of virtual function interfaces VF; each virtual function interface VF is bound to a physical function interface PF;

[0099] The PCIe controller and NVMe controller are connected via the AXI bus;

[0100] The AXI bus includes an AxUSER signal line, on which a sriov controller is provided;

[0101] The NVMe subsystem represents each NVMe controller through the signal of the AxUSER signal line;

[0102] The sriov controller is used to allocate the physical function interface PF and the virtual function interface VF of the PCIe controller, and convert the addresses of each NVMe controller of the NVMe subsystem with the physical function interface PF number and the virtual function interface VF number of the PCIe controller.

[0103] In this embodiment, the AXI bus further includes data transmission lines, and the data transmission lines include a master transmission line AXIMST and a slave transmission line AXI SLV;

[0104] The main transmission line AXI MST uses the PCIe controller as the main interface and the NVMe controller as the slave interface for data transmission;

[0105] The slave transmission line AXI SLV uses the NVMe controller as the master interface and the PCIe controller as the slave interface for data transmission;

[0106] The AxUSER signal line includes a master AxUSER signal line and a slave AxUSER signal line;

[0107] The main AxUSER signal line includes a front-end main write channel signal line M-AW USER1, a rear-end main write channel signal line M-AW USER2, a front-end main read channel signal line M-AR USER1, and a rear-end main read channel signal line M-AR USER2;

[0108] The front-end main write channel signal line M-AW USER1 connects the PCIe controller and the sirov controller, and the back-end main write channel signal line M-AR USER2 connects the sirov controller and the NVMe controller;

[0109] The slave AxUSER signal lines include a front-end slave write channel signal line S-AW USER1, a rear-end slave write channel signal line S-AW USER2, a front-end slave read channel signal line S-AR USER1, and a rear-end slave read channel signal line S-AR USER2;

[0110] The front section connects the NVMe controller and the sirov controller from the write channel signal line S-AW USER1, and the back section connects the sirov controller and the PCIe controller from the write channel signal line S-AW USER2.

[0111] In some embodiments, the sriov controller is provided with a first conversion module and a second conversion module;

[0112] The first conversion module converts the VF active signal in the AxUSER signal line, the number of the current physical function interface PF, the required number of physical function interfaces PF, the number of virtual function interfaces VF required under each physical function interface PF, and the number of virtual function interfaces VF under the current physical function interface PF number into the number AxUSER of the user identification signal representing the NVMe controller when the PCIe controller transmits data to the NVMe subsystem as the main interface;

[0113] The first conversion module includes:

[0114] A virtual interface active function identification unit, used to identify a VF active signal VF_ACTIVE in the AxUSER signal line when the PCIe controller transmits data to the NVMe subsystem as an AXI master interface;

[0115] A first user identification signal calculation unit, used for determining that the virtual function interface VF is not enabled when VF_ACTIVE=0, and the user identification signal number AxUSER=the number PF_NUM of the current virtual function interface PF;

[0116] The current physical function interface identification unit is used to determine that the virtual function interface VF is turned on when VF_ACTIVE=1, obtain the current PCIe descriptor in the AxUSER signal line, and identify the number PF_NUM of the current physical function interface PF;

[0117] The second user identification signal calculation unit sets the user identification signal number AxUSER=

[0118] The number of physical function interfaces PF_NUM_TOTAL required + the number of the current PF PF_NUM + the sum of the number of virtual function interfaces VF under each previous physical function interface PF + the number VF_NUM of the current virtual function interface VF under the current physical function interface PF;

[0119] A destination NVMe controller determining unit, used to determine to which NVMe controller the data is to be transmitted according to the number AxUSER of the user identification signal;

[0120] The second conversion module converts the required number of physical function interfaces PF, the required number of virtual function interfaces VF under each physical function interface PF, and the number AxUSER of the user identification signal representing the NVMe controller in the AxUSER signal line into a VF active signal, the current physical function interface PF number, and the current virtual function interface VF number when the PCIe controller receives the NVMe subsystem transmission data as a slave interface;

[0121] The second conversion module includes:

[0122] A user identification number identification unit, used to identify the number AxUSER of the user identification signal in the AxUSER signal line when the PCIe controller receives NVMe system transmission data as an AXI slave interface;

[0123] A unit for comparing the user identification signal number and the required physical function quantity, used to determine whether the user identification signal number AxUSER> the required physical function interface PF number PF_NUM_TOTAL-1 is established;

[0124] The virtual function start determination unit is used to determine that the VF active signal VF_ACTIVE=1 when the number of the user identification signal AxUSER> the number of the required physical function interface PF_NUM_TOTAL-1 is established;

[0125] The virtual function is not enabled. If the number AxUSER used for user identification signal > the number of required physical function interfaces PF_NUM_TOTAL-1 is not established, the VF active signal VF_ACTIVE = 0;

[0126] A physical function interface determination unit, used for setting the number PF_NUM of the current physical function interface PF to correspond to the number AxUSER of the user identification signal which is greater than the number PF*_VF_NUM of the virtual function interface VF corresponding to all the previous physical function interfaces PF of the current physical function interface PF plus the number PF_NUM_TOTAL of the required physical function interfaces PF-1 and less than the number PF*_VF_NUM of the virtual function interfaces VF required by the physical function interface PF and the sum of the number PF*_VF_NUM of the virtual function interfaces VF required by all the previous physical function interfaces PF plus the number PF_NUM_TOTAL of the required physical function interfaces PF;

[0127] A VF active signal determination unit, used to determine whether the VF active signal VF_ACTIVE is 0;

[0128] A virtual interface number determination unit, used for setting the number VF_NUM of the current virtual function interface VF to be equal to the number AxUSER of the user identification signal minus the number PF_NUM_TOTAL of the required physical function interfaces PF and the number PF*_VF_NUM of the virtual function interfaces VF required by the physical function interface PF preceding the number PF_NUM of the current physical function interface PF when the VF active signal VF_ACTIVE is 0;

[0129] The destination PCIe controller interface determination unit is used to determine, when the VF active signal VF_ACTIVE is not 0, according to the number PF_NUM of the current physical function interface PF and the number VF_NUM of the current virtual function interface VF to which interface of the PCIe controller the data is transmitted.

[0130] The number of NVMe controllers in an NVMe subsystem is generally fixed, but the number of functions supported by a PCIe controller is flexibly configurable, such as Figure 3 As shown in the figure, the number of NVMe controllers is 7, which correspond to ctrl0, ctrl1, ctrl2, ctrl3, ctrl4, ctrl5, and ctrl6 respectively. Among them, ctrl0, ctrl1, and ctrl2 have relatively strong support capabilities, and the physical function interface PF corresponding to the PCIe controller needs to be mapped to them. The number of virtual function interfaces VF supported by each physical function PF is not fixed. Due to the limitation of the number of NVMe controllers, PF supports a maximum of 3 and VF supports a maximum of 4. When the SR-IOV function supports 3 physical function interfaces PF and 4 virtual function interfaces VF, the physical function interface PF0 supports 2 virtual function interfaces VF, the physical function interface PF1 supports 1 virtual function interface VF, and the physical function interface PF2 supports 1 virtual function interface VF, the handshake relationship between the PCIe function and the NVMe controller is as follows Figure 3 As shown in (a), when the SR-IOV function supports 2 physical function interfaces PF and 3 virtual function interfaces VF, where physical function interface PF0 supports 1 virtual function interface VF, physical function interface PF1 supports 1 virtual function interface VF, and physical function interface PF2 supports 1 virtual function interface VF, the handshake relationship between the PCIe function and the NVMe controller is as follows: Figure 3 as shown in (b).

[0131] First, you need to configure the supported PF number PF_NUM_TOTAL through the configuration register, and configure the supported VF number PF*_VF_NUM for each PF. PF_NUM_TOTAL needs to be less than or equal to the maximum number of controllers provided by NVMe for PF, and the configured PF*_VF_NUM needs to be less than or equal to the maximum number of controllers provided by NVMe for VF. VF_ACTIVE is used to determine whether the data indicated in the PCIe descriptor for transmission is a VF signal.

[0132] Taking three physical function interfaces as an example, when PCIe transmits data to NVMe as the AXI master interface, the handshake process is as follows:

[0133] 1. When VF_ACTIVE = 0, AxUSER = PF_NUM;

[0134] 2. When VF_ACTIVE = 1, determine which VF the current PCIe descriptor corresponds to.

[0135] If PF_NUM=0, AxUSER=PF_NUM_TOTAL+VF_NUM

[0136] If PF_NUM=1, AxUSER=PF_NUM_TOTAL+PF0_VF_NUM+VF_NUM

[0137] If PF_NUM=2, AxUSER=PF_NUM_TOTAL+

[0138] PF0_VF_NUM+PF1_VF_NUM+VF_NUM

[0139] According to the above rules, when VF_ACTIVE = 1, AxUSER is calculated as PF_NUM_TOTAL plus the PF_VF_NUM owned by all PFs before this PF and the VF_NUM transmitted by the current PF.

[0140] When PCIe receives NVMe transmission data as an AXI slave interface, the handshake process is as follows:

[0141] Data transmission in this direction requires telling PCIe through descriptors that three signals are VF_ACTIVE, PF_NUM, and VF_NUM.

[0142] VF_ACTIVE: When AxUSER>PF_NUM_TOTAL-1, VF_ACTIVE=1, otherwise VF_ACTIVE=0;

[0143] PF_NUM:PF_NUM_TOTAL+PF0_VF_NUM>AxUSER>PF_NUM_TOTAL-1,PF_NUM=0

[0144] PF_NUM_TOTAL+PF0_VF_NUM+PF1_VF_NUM>AxUSER>

[0145] PF_NUM_TOTAL-1+PF0_VF_NUM,PF_NUM=1

[0146] According to the above rules, the AxUSER corresponding to each PF_NUM needs to be greater than the PF_VF_NUM corresponding to all the PFs before it plus PF_NUM_TOTAL-1 and less than the sum of the PF_VF_NUM owned by this PF and the PF_VF_NUM corresponding to all the previous PFs plus PF_NUM_TOTAL.

[0147] VF_NUM: When PF_NUM=0, VF_NUM=AxUSER-PF_NUM_TOTAL;

[0148] When PF_NUM=1, VF_NUM=AxUSER-PF_NUM_TOTAL-PF0_VF_NUM;

[0149] According to the above rules, we must first determine the PF_NUM value. The VF_NUM value is AxUSER minus PF_NUM_TOTAL and all PF_VF_NUMs owned by the PF in front of the PF_NUM.

[0150] The following is an embodiment of the SR-IOV handshake method between the SSD master control chip PCIe and NVMe provided in an embodiment of the present disclosure. This method and the SR-IOV handshake system between the SSD master control chip PCIe and NVMe in the above-mentioned embodiments belong to the same inventive concept. For details not described in detail in the embodiment of the SR-IOV handshake method between the SSD master control chip PCIe and NVMe, please refer to the embodiment of the SR-IOV handshake system between the SSD master control chip PCIe and NVMe.

[0151] like Figure 2As shown, the method comprises the following steps:

[0152] S1. Set up a sriov controller between the PCIe controller and the NVMe subsystem, and pre-configure the required number of physical function interfaces PF and the number of virtual function interfaces VF required under each physical function interface PF;

[0153] S2. When the PCIe controller transmits data to the NVMe subsystem as the main interface, the sriov controller converts the VF active signal in the AxUSER signal line, the number of the current physical function interface PF, the required number of physical function interfaces PF, the number of virtual function interfaces VF required under each physical function interface PF, and the number of virtual function interfaces VF under the current physical function interface PF number into the number AxUSER representing the user identification signal of the NVMe controller;

[0154] S3. When the PCIe controller receives data transmitted by the NVMe subsystem as a slave interface, the sriov controller converts the required number of physical function interfaces PF, the required number of virtual function interfaces VF under each physical function interface PF, and the number AxUSER of the user identification signal representing the NVMe controller in the AxUSER signal line into a VF active signal, the current physical function interface PF number, and the current virtual function interface VF number.

[0155] In this embodiment, the specific steps of step S1 are as follows:

[0156] S11. Set a sriov controller on the AxUSER signal line of the AXI bus between the PCIe controller and each NVMe controller;

[0157] S12. Obtain the maximum number of physical function interfaces PF_NUM_MAX and the maximum number of virtual function interfaces VF_NUM_MAX supported by the PCIe controller, and configure them in the sriov controller;

[0158] S13. Configure the required number of physical function interfaces PF_NUM_TOTAL and the number PF_NUM of each physical function interface PF in the sriov controller, wherein the required number of physical function interfaces PF_NUM_TOTAL is less than or equal to the maximum number of physical function interfaces PF PF_NUM_MAX supported by the PCIe controller;

[0159] S14. Configure the number of virtual function interfaces VF PF*_VF_NUM required for each physical function interface PF and the number VF_NUM of each virtual function interface VF in the sriov controller, wherein the sum of the number of virtual function interfaces VF PF*_VF_NUM required for each physical function interface PF is less than or equal to the maximum number of virtual function interfaces VF VF_NUM_MAX supported by the PCIe controller;

[0160] The specific steps of step S2 are as follows:

[0161] S21. When the PCIe controller transmits data to the NVMe subsystem as the AXI master interface, the sriov controller identifies the VF active signal VF_ACTIVE in the AxUSER signal line;

[0162] When VF_ACTIVE=0, go to step S22;

[0163] When VF_ACTIVE=1, go to step S23;

[0164] S22. It is determined that the virtual function interface VF is not enabled, the user identification signal number AxUSER = the current virtual function interface PF number PF_NUM, and the process proceeds to step S25;

[0165] S23. Determine that the virtual function interface VF is turned on, obtain the current PCIe descriptor in the AxUSER signal line, and identify the number PF_NUM of the current physical function interface PF;

[0166] S24. User identification signal number AxUSER =

[0167] The number of physical function interfaces PF_NUM_TOTAL required + the number of the current PF PF_NUM + the sum of the number of virtual function interfaces VF under each previous physical function interface PF + the number VF_NUM of the current virtual function interface VF under the current physical function interface PF;

[0168] S25.sriov controller determines which NVMe controller to transmit data to based on the number AxUSER of the user identification signal;

[0169] The specific steps of step S3 are as follows:

[0170] S31. When the PCIe controller receives data transmitted by the NVMe system as an AXI slave interface, it identifies the user identification signal number AxUSER in the AxUSER signal line;

[0171] S32. Determine whether the user identification signal number AxUSER> the required number of physical function interfaces PF_NUM_TOTAL-1 is established;

[0172] If so, determine that the VF active signal VF_ACTIVE=1, and go to step S33;

[0173] If not, it is determined that the VF active signal VF_ACTIVE=0, and the process goes to step S33;

[0174] S33. The number PF_NUM of the current physical function interface PF needs to correspond to the number AxUSER of the user identification signal greater than the virtual function interface VF number PF*_VF_NUM corresponding to all the previous physical function interfaces PF of the current physical function interface PF plus the number of required physical function interfaces PF PF_NUM_TOTAL-1 and less than the number of virtual function interfaces VF PF*_VF_NUM required for the physical function interface PF and the sum of the number of virtual function interfaces VF PF*_VF_NUM required for all the previous physical function interfaces PF plus the number of required physical function interfaces PF PF_NUM_TOTAL;

[0175] S34. Determine whether the VF active signal VF_ACTIVE is 0;

[0176] If yes, go to step S36;

[0177] If not, proceed to step S35;

[0178] S35. The number VF_NUM of the current virtual function interface VF is equal to the number AxUSER of the user identification signal minus the number PF_NUM_TOTAL of the required physical function interfaces PF and the number PF_NUM of the current physical function interface PF and the number PF*_VF_NUM of the required virtual function interfaces VF of the physical function interface PF in front of the number PF_NUM of the current physical function interface PF;

[0179] S36. The sriov controller determines to which interface of the PCIe controller the data is to be transmitted according to the number PF_NUM of the current physical function interface PF and the number VF_NUM of the current virtual function interface VF.

[0180] The present invention designs a handshake method for each direction based on the fact that the data between the PCIe controller and the NVMe subsystem is bidirectional. When PCIe is used as the main interface to transmit data to NVMe, AxUSER = PF_NUM when VF_ACTIVE = 0, and AxUSER is calculated as PF_NUM_TOTAL plus the PF_VF_NUM owned by all PFs before the PF and the VF_NUM transmitted by the current PF when VF_ACTIVE = 1;

[0181] When PCIe receives NVMe data transmission as a slave interface, VF_ACTIVE, PF_NUM, and VF_NUM need to be determined and passed to PCIe;

[0182] VF_ACTIVE: When AxUSER>PF_NUM_TOTAL-1, VF_ACTIVE=1, otherwise VF_ACTIVE=0;

[0183] PF_NUM: The corresponding AxUSER needs to be greater than the PF_VF_NUM corresponding to all the PFs in front of this PF plus PF_NUM_TOTAL-1 and less than the sum of the PF_VF_NUM owned by this PF and the PF_VF_NUM corresponding to all the previous PFs plus PF_NUM_TOTAL;

[0184] VF_NUM: First determine the PF_NUM value. The VF_NUM value is AxUSER minus PF_NUM_TOTAL and all PF_VF_NUMs owned by the PFs preceding this PF.

[0185] It should be understood that the order of execution of the steps in the above embodiment does not mean that the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0186] The SR-IOV handshake method between the SSD master chip PCIe and NVMe provided by the present invention is a module and algorithm step of each example described in combination with the embodiments disclosed herein, and can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0187] Those skilled in the art will appreciate that the various aspects of the SR-IOV handshake method for the SSD master chip PCIe and NVMe provided by the present invention can be implemented as a system, method or program product. Therefore, various aspects of the present disclosure can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software, which can be collectively referred to as a "circuit", "module" or "system" here.

[0188] In the non-transitory computer-readable storage medium storing the SR-IOV handshake method of the SSD master chip PCIe and NVMe, it can be but not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0189] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person of ordinary skill in the art may easily think of changes or substitutions within the technical scope disclosed by the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. An SR-IOV handshake system between PCIe and NVMe SSD master chip, It is characterized in that Includes NVMe subsystem and PCIe controller; The NVMe subsystem includes several NVMe controllers; The PCIe controller is provided with a number of physical function interfaces PF and a number of virtual function interfaces VF; each virtual function interface VF is bound to a physical function interface PF; The PCIe controller and NVMe controller are connected via the AXI bus; The AXI bus includes an AxIUSER signal line, on which a sriov controller is provided; The NVMe subsystem represents each NVMe controller through the signal of the AxIUSER signal line; The sriov controller is used to allocate the physical function interface PF and the virtual function interface VF of the PCIe controller, and convert the addresses of each NVMe controller of the NVMe subsystem with the physical function interface PF number and the virtual function interface VF number of the PCIe controller.

2. The SR-IOV handshake system of the SSD master control chip PCIe and NVMe as claimed in claim 1, It is characterized in that The AXI bus also includes data transmission lines, which include master transmission lines and slave transmission lines. The master transmission line uses the PCIe controller as the main interface and the NVMe controller as the slave interface for data transmission. The slave transmission line uses the NVMe controller as the main interface and the PCIe controller as the slave interface for data transmission.

3. The SR-IOV handshake system between the SSD master control chip PCIe and NVMe as claimed in claim 2, It is characterized in that The AxIUSER signal line includes a master AxUSER signal line and a slave AxUSER signal line; The main AxUSER signal line includes a front-end main write channel signal line, a rear-end main write channel signal line, a front-end main read channel signal line, and a rear-end main read channel signal line; The front-end main write channel signal line connects the PCIe controller and the sirov controller, and the rear-end main write channel signal line connects the sirov controller and the NVMe controller; The slave AxUSER signal line includes a front-end slave write channel signal line, a rear-end slave write channel signal line, a front-end slave read channel signal line, and a rear-end slave read channel signal line; The front section connects the NVMe controller and the sirov controller through the write channel signal line, and the back section connects the sirov controller and the PCIe controller through the write channel signal line.

4. The SR-IOV handshake system between the SSD master control chip PCIe and NVMe as claimed in claim 3, It is characterized in that The sriov controller is provided with a first conversion module and a second conversion module; The first conversion module converts the VF active signal in the AxUSER signal line, the number of the current physical function interface PF, the required number of physical function interfaces PF, the number of virtual function interfaces VF required under each physical function interface PF, and the number of virtual function interfaces VF under the current physical function interface PF number into the number AxUSER of the user identification signal representing the NVMe controller when the PCIe controller transmits data to the NVMe subsystem as the main interface; The second conversion module, when the PCIe controller acts as a slave interface to receive data transmitted by the NVMe subsystem, converts the required number of physical function interfaces PF, the required number of virtual function interfaces VF under each physical function interface PF, and the number AxUSER of the user identification signal representing the NVMe controller in the AxUSER signal line into a VF active signal, the current physical function interface PF number, and the current virtual function interface VF number.

5. A SR-IOV handshake method between PCIe and NVMe of SSD master control chip, It is characterized in that The steps include: S1. Set up a sriov controller between the PCIe controller and the NVMe subsystem, and pre-configure the required number of physical function interfaces PF and the number of virtual function interfaces VF required under each physical function interface PF; S2. When the PCIe controller transmits data to the NVMe subsystem as the main interface, the sriov controller converts the VF active signal in the AxUSER signal line, the number of the current physical function interface PF, the required number of physical function interfaces PF, the number of virtual function interfaces VF required under each physical function interface PF, and the number of virtual function interfaces VF under the current physical function interface PF number into the number AxUSER representing the user identification signal of the NVMe controller; S3. When the PCIe controller receives data transmitted by the NVMe subsystem as a slave interface, the sriov controller converts the required number of physical function interfaces PF, the required number of virtual function interfaces VF under each physical function interface PF, and the number AxUSER of the user identification signal representing the NVMe controller in the AxUSER signal line into a VF active signal, the current physical function interface PF number, and the current virtual function interface VF number.

6. The SR-IOV handshake method between the SSD master control chip PCIe and NVMe as claimed in claim 5, It is characterized in that The specific steps of step S1 are as follows: S11. Set a sriov controller on the AxUSER signal line of the AXI bus between the PCIe controller and each NVMe controller; S12. Obtain the maximum number of physical function interfaces PF_NUM_MAX and the maximum number of virtual function interfaces VF_NUM_MAX supported by the PCIe controller, and configure them in the sriov controller; S13. Configure the required number of physical function interfaces PF_NUM_TOTAL and the number PF_NUM of each physical function interface PF in the sriov controller, wherein the required number of physical function interfaces PF_NUM_TOTAL is less than or equal to the maximum number of physical function interfaces PF PF_NUM_MAX supported by the PCIe controller; S14. Configure the number of virtual function interfaces VF PF*_VF_NUM required for each physical function interface PF and the number VF_NUM of each virtual function interface VF in the sriov controller, wherein the sum of the number of virtual function interfaces VF PF*_VF_NUM required for each physical function interface PF is less than or equal to the maximum number of virtual function interfaces VF VF_NUM_MAX supported by the PCIe controller.

7. The SR-IOV handshake method between the SSD master control chip PCIe and NVMe as claimed in claim 6, It is characterized in that The specific steps of step S2 are as follows: S21. When the PCIe controller transmits data to the NVMe subsystem as the AXI master interface, the sriov controller identifies the VF active signal VF_ACTIVE in the AxUSER signal line; When VF_ACTIVE=0, go to step S22; When VF_ACTIVE=1, go to step S23; S22. It is determined that the virtual function interface VF is not enabled, the user identification signal number AxUSER = the current virtual function interface PF number PF_NUM, and the process proceeds to step S25; S23. Determine that the virtual function interface VF is turned on, obtain the current PCIe descriptor in the AxUSER signal line, and identify the number PF_NUM of the current physical function interface PF; S24. User identification signal number AxUSER = The number of physical function interfaces PF_NUM_TOTAL required + the number of the current PF PF_NUM + the sum of the number of virtual function interfaces VF under each previous physical function interface PF + the number VF_NUM of the current virtual function interface VF under the current physical function interface PF; The S25.sriov controller determines to which NVMe controller the data is transmitted based on the number AxUSER of the user identification signal.

8. The SR-IOV handshake method between the SSD master control chip PCIe and NVMe as claimed in claim 7, It is characterized in that The specific steps of step S3 are as follows: S31. When the PCIe controller receives data transmitted by the NVMe system as an AXI slave interface, it identifies the user identification signal number AxUSER in the AxUSER signal line; S32. Determine whether the user identification signal number AxUSER> the required number of physical function interfaces PF_NUM_TOTAL-1 is established; If so, determine that the VF active signal VF_ACTIVE=1, and go to step S33; If not, it is determined that the VF active signal VF_ACTIVE=0, and the process goes to step S33; S33. The number PF_NUM of the current physical function interface PF needs to correspond to the number AxUSER of the user identification signal greater than the virtual function interface VF number PF*_VF_NUM corresponding to all the previous physical function interfaces PF of the current physical function interface PF plus the number of required physical function interfaces PF PF_NUM_TOTAL-1 and less than the number of virtual function interfaces VF PF*_VF_NUM required for the physical function interface PF and the sum of the number of virtual function interfaces VF PF*_VF_NUM required for all the previous physical function interfaces PF plus the number of required physical function interfaces PF PF_NUM_TOTAL; S34. Determine whether the VF active signal VF_ACTIVE is 0; If yes, go to step S36; If not, proceed to step S35; S35. The number VF_NUM of the current virtual function interface VF is equal to the number AxUSER of the user identification signal minus the number PF_NUM_TOTAL of the required physical function interfaces PF and the number PF_NUM of the current physical function interface PF and the number PF*_VF_NUM of the required virtual function interfaces VF of the physical function interface PF in front of the number PF_NUM of the current physical function interface PF; S36. The sriov controller determines to which interface of the PCIe controller the data is to be transmitted according to the number PF_NUM of the current physical function interface PF and the number VF_NUM of the current virtual function interface VF.

9. An electronic device, It is characterized in that including a processor and a memory; The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the electronic device executes the method described in any one of claims 5 to 8.

10. A storage medium, It is characterized in that The storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in any one of claims 5 to 8.

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