Chip design layout optimization method
By collecting and encoding the feature parameters of the chip design layout and using the optimization model for automated optimization, the problem of traditional methods being difficult to improve chip performance and reduce power consumption and area at the same time, achieving a more efficient chip design.
Patent Information
- Application Number
- CN202411019453.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-29
- Publication Date
- 2024-12-06
AI Technical Summary
Traditional chip design layout methods are difficult to simultaneously improve chip performance, reduce power consumption and area, and meet the multiple needs of complex chip designs.
By collecting the characteristic parameters of the chip design layout, encoding and generating digital data, inputting the trained chip design layout optimization model, obtaining optimization suggestions, and adjusting the optimization strategy and model parameters according to the evaluation results until the preset optimization goals are met.
It realizes the optimization of chip performance, power consumption and area, reduces design workload, improves design efficiency, and meets the needs of practical applications.
Smart Images
Figure CN119089853A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip design layout optimization, and in particular to a chip design layout optimization method. Background Art
[0002] With the rapid development of science and technology, chip design is becoming more and more complex, and the amount of data that needs to be processed is also growing rapidly. Therefore, the requirements for chip performance, power consumption, area, and reliability are also constantly increasing.
[0003] Traditional chip design layout methods often find it difficult to meet these requirements at the same time, so they need to be optimized. The main goal of the layout optimization method is to improve the performance and efficiency of the chip while reducing power consumption and area to meet the needs of practical applications. Therefore, a chip design layout optimization method is proposed to solve the above problems. Summary of the invention
[0004] The purpose of the present invention is to provide a chip design layout optimization method to solve the problems mentioned in the background technology.
[0005] The purpose of the present invention can be achieved through the following technical solutions:
[0006] A chip design layout optimization method, comprising:
[0007] Collect characteristic parameters of the chip design layout to be optimized;
[0008] Encoding the characteristic parameters according to a specific format to generate digital data;
[0009] Inputting the digital data into a trained chip design layout optimization model to obtain corresponding optimization suggestions;
[0010] The design layout of the chip to be optimized is adjusted according to the optimization suggestion, and the adjusted chip layout is evaluated, and the optimization strategy is adjusted according to the evaluation result.
[0011] Preferably, the process of adjusting the optimization strategy according to the evaluation result includes:
[0012] If the evaluation result meets the preset optimization goal, the optimization strategy is completed;
[0013] Otherwise, the parameters of the chip design layout optimization model are adjusted according to the evaluation results, and the adjusted chip is input into the trained chip design layout optimization model again until the evaluation results meet the preset optimization goals.
[0014] Preferably, the process of encoding the characteristic parameters in a specific format to generate digital data includes:
[0015] According to the type of the characteristic parameter, a corresponding encoding method is selected to implement encoding;
[0016] Combining the encoded feature parameters to generate a feature parameter group;
[0017] The characteristic parameter group is organized into a specific data structure according to an input format corresponding to the chip design layout optimization model.
[0018] Preferably, the process of evaluating the adjusted chip layout includes:
[0019] Obtain various chip performance indicators of the adjusted chip layout;
[0020] Compare each of the chip performance indicators with the corresponding preset indicator constraints:
[0021] If all preset indicator constraints are met, the chip comprehensive performance indicator is calculated according to each of the chip performance indicators, and the chip comprehensive performance indicator is evaluated;
[0022] Otherwise, it is determined that the adjusted chip layout does not meet the preset optimization goal.
[0023] Preferably, the process of calculating the chip comprehensive performance index according to each of the chip performance indexes includes:
[0024] By formula;
[0025]
[0026] Calculate the comprehensive performance index Z of the j-th optimized chip j ;
[0027] Where n is the number of chip performance indicators, i∈[1,n]; α i is the weight coefficient of the i-th chip performance indicator, β i is the application coefficient of the i-th chip performance indicator, and g is the comprehensive performance indicator conversion function.
[0028] Preferably, the process of evaluating the comprehensive performance index of the chip includes:
[0029] The j-th optimized chip comprehensive performance index Z j Compare with the preset comprehensive performance index constraints [Z1, Z2]:
[0030] If Z j ∈[Z1, Z2], then the adjusted chip layout is judged to meet the preset optimization goal;
[0031] Otherwise, it is determined that the adjusted chip layout does not meet the preset optimization goal.
[0032] Preferably, the process of adjusting the parameters of the chip design layout optimization model according to the evaluation results includes:
[0033] If there are items in the chip performance indicators that do not meet the preset indicator constraints, the formula is:
[0034]
[0035] Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 , and then input the adjusted chip into the chip design layout optimization model again until the evaluation result meets the preset optimization target;
[0036] Wherein, m is the number of items in the chip performance index that do not meet the preset index constraint conditions, r∈[1,m]; γ r is the weight coefficient of the chip performance index of the rth item that does not meet the preset index constraint condition, Δδ r is the difference between the chip performance index of the rth item that does not meet the preset index constraint and the preset index constraint, Δδ r0 is the preset standard deviation value between the chip performance index of the rth item that does not meet the preset index constraint condition and the preset index constraint condition, and y1 is the first index model parameter influence function.
[0037] Preferably, the process of adjusting the parameters of the chip design layout optimization model according to the evaluation results further includes:
[0038] If all the chip performance indicators meet the preset indicator constraints but the chip comprehensive performance indicators do not meet the preset comprehensive performance indicator constraints, the formula is:
[0039]
[0040] Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 , and then input the adjusted chip into the chip design layout optimization model again until the evaluation result meets the preset optimization target;
[0041] Among them, ΔZ j is the comprehensive performance index Z of the chip optimized for the jth time j The difference between the preset comprehensive performance index constraint condition, ΔZ j0 is the comprehensive performance index Z of the chip optimized for the jth time j The preset standard deviation value of the preset comprehensive performance indicator constraint condition, y2 is the second indicator model parameter influence function.
[0042] Beneficial effects of the present invention:
[0043] The chip design layout optimization method collects characteristic parameters of the chip design layout to be optimized, thereby extracting key features in the layout, such as layout, wiring, component type, etc., according to the characteristic parameters, and then encodes the characteristic parameters in a specific format to generate digital data, thereby converting these characteristic parameters into digital data that can be understood and processed by the chip design layout optimization model, providing a basis for subsequent optimization work, and then inputting the digital data into the trained chip design layout optimization model to obtain corresponding optimization suggestions. The model uses deep learning technology to learn how to automatically optimize the chip design layout through training. It can extract key features in the layout and generate corresponding optimization suggestions or adjustment plans based on the learned optimization strategy. Then, the layout can be modified according to these suggestions to improve the chip performance, power consumption, area and other indicators; then, the design layout of the chip to be optimized is adjusted according to the optimization suggestion, and the adjusted chip layout is evaluated, and the optimization strategy is adjusted according to the evaluation result, and the chip design layout that meets the preset optimization goal is further obtained, which reduces the workload of chip design, improves the chip design efficiency, and meets the needs of practical applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The present invention will be further described below in conjunction with the accompanying drawings.
[0045] Figure 1 The figure is a schematic block diagram of the method flow of the present invention. DETAILED DESCRIPTION
[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0047] See also Figure 1 As shown, the present invention is a chip design layout optimization method, comprising:
[0048] Collect characteristic parameters of the chip design layout to be optimized;
[0049] Encode the characteristic parameters in a specific format to generate digital data;
[0050] Input the digital data into the trained chip design layout optimization model to obtain corresponding optimization suggestions;
[0051] Adjust the design layout of the chip to be optimized according to the optimization suggestions, evaluate the adjusted chip layout, and adjust the optimization strategy based on the evaluation results.
[0052] Through the above technical scheme, this embodiment proposes a chip design layout optimization method. Specifically, by collecting the characteristic parameters of the chip design layout to be optimized, the key features in the layout, such as layout, wiring, component type, etc., are extracted according to the characteristic parameters, and then the characteristic parameters are encoded in a specific format to generate digital data, so as to convert these characteristic parameters into digital data that can be understood and processed by the chip design layout optimization model, which provides a basis for subsequent optimization work. Then, the digital data is input into the trained chip design layout optimization model to obtain corresponding optimization suggestions. The model uses deep learning technology to learn how to automatically optimize the chip design layout through training. It can extract the key features in the layout and generate corresponding optimization suggestions or adjustment plans according to the learned optimization strategy. Then, according to these suggestions, the layout can be modified to improve the chip performance, power consumption, area and other indicators; then, the design layout of the chip to be optimized is adjusted according to the optimization suggestion, and the adjusted chip layout is evaluated. The optimization strategy is adjusted according to the evaluation result, and the chip design layout that meets the preset optimization goal is further obtained, which reduces the workload of chip design, improves the chip design efficiency, and meets the needs of practical applications.
[0053] In the above technical solution, the chip design layout optimization model and the generation and processing of training samples are implemented through conventional machine learning algorithms in the prior art and will not be described in detail here.
[0054] The process of adjusting the optimization strategy based on the evaluation results includes:
[0055] If the evaluation results meet the preset optimization goals, the optimization strategy is completed;
[0056] Otherwise, the parameters of the chip design layout optimization model are adjusted according to the evaluation results, and the adjusted chip is input into the trained chip design layout optimization model again until the evaluation results meet the preset optimization goals.
[0057] Through the above technical scheme, this embodiment proposes a method for adjusting the optimization strategy according to the evaluation results. Specifically, if the evaluation results meet the preset optimization goals, that is, meet the needs of actual applications, the optimization strategy is completed. Otherwise, the parameters of the chip design layout optimization model are adjusted according to the evaluation results, and the adjusted chip is input into the trained chip design layout optimization model again until the evaluation results meet the preset optimization goals. That is, after the initial optimization, the results are evaluated. If they do not meet the requirements, the parameters of the model will be adjusted according to the evaluation results and the optimization will continue. This process may require multiple iterations until satisfactory results are achieved, thereby improving the accuracy of the optimization.
[0058] The process of encoding the characteristic parameters in a specific format and generating digital data includes:
[0059] According to the type of characteristic parameters, select the corresponding encoding method to implement encoding;
[0060] Combining the encoded feature parameters to generate a feature parameter group;
[0061] The characteristic parameter groups are organized into a specific data structure according to the input format corresponding to the chip design layout optimization model.
[0062] Through the above technical scheme, this embodiment proposes a method for encoding feature parameters in a specific format to generate digital data. Specifically, according to the type of feature parameters, the corresponding encoding method is selected to implement encoding. For example, component type, layout mode, etc., one-hot encoding or label encoding can be used. For numerical features, such as component size, electrical characteristics, etc., they can be directly digitized or standardized; then the encoded feature parameters are combined to generate a feature parameter group. For example, different features can be combined together to produce more meaningful features. Finally, the feature parameter group is organized into a specific data structure according to the input format corresponding to the chip design layout optimization model, thereby providing a basis for subsequent optimization work.
[0063] The process of evaluating the adjusted chip layout includes:
[0064] Obtain various chip performance indicators of the adjusted chip layout;
[0065] Compare each chip performance indicator with the corresponding preset indicator constraints:
[0066] If all preset indicator constraints are met, the chip comprehensive performance indicators are calculated based on the various chip performance indicators, and the chip comprehensive performance indicators are evaluated;
[0067] Otherwise, it is determined that the adjusted chip layout does not meet the preset optimization goal.
[0068] Through the above technical scheme, this embodiment proposes a method for evaluating the adjusted chip layout. Specifically, each chip performance indicator is compared with the corresponding preset indicator constraint conditions. Obviously, if there are chip performance indicators that do not meet the preset indicator constraints, it is judged that the adjusted chip layout does not meet the preset optimization goals; if all the preset indicator constraints are met, the chip comprehensive performance indicators are calculated according to each chip performance indicator, and the chip comprehensive performance indicators are evaluated, so that while considering each individual indicator, the comprehensive performance indicators of the detection chip are increased, thereby improving the accuracy of the chip layout optimization evaluation.
[0069] The process of calculating the chip comprehensive performance index based on various chip performance indicators includes:
[0070] By formula;
[0071]
[0072] Calculate the comprehensive performance index Z of the j-th optimized chip j ;
[0073] Where n is the number of chip performance indicators, i∈[1,n]; α i is the weight coefficient of the i-th chip performance indicator, β i is the application coefficient of the i-th chip performance indicator, and g is the comprehensive performance indicator conversion function.
[0074] Through the above technical solution, this embodiment proposes a method for calculating the chip comprehensive performance index according to various chip performance indicators. Specifically, through the formula Calculate the comprehensive performance index Z of the j-th optimized chip j , where the weight coefficient α of the i-th chip performance indicator is i and the application coefficient β of the i-th chip performance indicator i According to the different selectivities of the impact of different chip performance indicators on chip layout design, the comprehensive performance indicator conversion function g is obtained after BIM analysis and fitting based on the experimental data, which will not be described in detail here.
[0075] The process of evaluating the comprehensive performance indicators of a chip includes:
[0076] The j-th optimized chip comprehensive performance index Z j Compare with the preset comprehensive performance index constraints [Z1, Z2]:
[0077] If Z j ∈[Z1, Z2], then the adjusted chip layout is judged to meet the preset optimization goal;
[0078] Otherwise, it is determined that the adjusted chip layout does not meet the preset optimization goal.
[0079] The process of adjusting the parameters of the chip design layout optimization model based on the evaluation results includes:
[0080] If there are items in each chip performance index that do not meet the preset index constraint conditions, the formula is:
[0081]
[0082] Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 , and then input the adjusted chip into the chip design layout optimization model again until the evaluation result meets the preset optimization goal;
[0083] Where m is the number of items in the chip performance index that do not meet the preset index constraint conditions, r∈[1,m]; γ r is the weight coefficient of the chip performance index of the rth item that does not meet the preset index constraint condition, Δδ r is the difference between the chip performance index of the rth item that does not meet the preset index constraint and the preset index constraint, Δδ r0 is the preset standard deviation value between the chip performance index of the rth item that does not meet the preset index constraint condition and the preset index constraint condition, and y1 is the first index model parameter influence function.
[0084] The process of adjusting the parameters of the chip design layout optimization model based on the evaluation results also includes:
[0085] If all chip performance indicators meet the preset indicator constraints but the chip comprehensive performance indicators do not meet the preset comprehensive performance indicator constraints, the formula is:
[0086]
[0087] Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 , and then input the adjusted chip into the chip design layout optimization model again until the evaluation result meets the preset optimization goal;
[0088] Among them, ΔZ j is the comprehensive performance index Z of the chip optimized for the jth time j The difference between the preset comprehensive performance index constraint condition, ΔZ j0 is the comprehensive performance index Z of the chip optimized for the jth time j The preset standard deviation value of the preset comprehensive performance indicator constraint condition, y2 is the second indicator model parameter influence function.
[0089] Through the above technical solution, this embodiment proposes a method for adjusting the parameters of the chip design layout optimization model according to the evaluation results. Specifically, if there are items in each chip performance indicator that do not meet the preset indicator constraint conditions, the formula Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 ; If all chip performance indicators meet the preset indicator constraints but the chip comprehensive performance indicators do not meet the preset comprehensive performance indicator constraints, the formula Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1, thereby increasing the comprehensive performance indicators of the detection chip while considering each individual indicator, thereby improving the accuracy of the chip layout optimization evaluation; then the adjusted chip is input into the chip design layout optimization model again until the evaluation result meets the preset optimization goal, that is, after the initial optimization, the result is evaluated. If it does not meet the requirements, the parameters of the model will be adjusted according to the evaluation results, and the optimization will continue. After multiple iterations, a satisfactory result is achieved, thereby improving the accuracy of the optimization.
[0090] It should be noted that the weight coefficient γ of the chip performance index that does not meet the preset index constraint condition is r According to the different effects of chip performance indicators that do not meet the preset indicator constraints on the parameter adjustment coefficients of the chip design layout optimization model, the difference Δδ between the chip performance indicator that does not meet the preset indicator constraints and the preset indicator constraints is selected. r , the preset standard deviation Δδ between the chip performance index of the rth item that does not meet the preset index constraint and the preset index constraint r0 , the j-th optimized chip comprehensive performance index Z j The difference ΔZ from the preset comprehensive performance index constraint condition j and the j-th optimized chip comprehensive performance index Z j The preset standard deviation value ΔZ of the preset comprehensive performance index constraint condition j0 The first index model parameter influence function y1 and the second index model parameter influence function are obtained after fitting the experimental data through BIM analysis and fitting, which will not be described in detail here.
[0091] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.
Claims
1. A chip design layout optimization method, It is characterized in that include: Collect characteristic parameters of the chip design layout to be optimized; Encoding the characteristic parameters according to a specific format to generate digital data; Inputting the digital data into a trained chip design layout optimization model to obtain corresponding optimization suggestions; The design layout of the chip to be optimized is adjusted according to the optimization suggestion, and the adjusted chip layout is evaluated, and the optimization strategy is adjusted according to the evaluation result.
2. The chip design layout optimization method according to claim 1, It is characterized in that The process of adjusting the optimization strategy based on the evaluation results includes: If the evaluation result meets the preset optimization goal, the optimization strategy is completed; Otherwise, the parameters of the chip design layout optimization model are adjusted according to the evaluation results, and the adjusted chip is input into the trained chip design layout optimization model again until the evaluation results meet the preset optimization goals.
3. The chip design layout optimization method according to claim 1, It is characterized in that The process of encoding the characteristic parameters in a specific format to generate digital data includes: According to the type of the characteristic parameter, a corresponding encoding method is selected to implement encoding; Combining the encoded feature parameters to generate a feature parameter group; The characteristic parameter group is organized into a specific data structure according to an input format corresponding to the chip design layout optimization model.
4. The chip design layout optimization method according to claim 1, It is characterized in that The process of evaluating the adjusted chip layout includes: Obtain various chip performance indicators of the adjusted chip layout; Compare each of the chip performance indicators with the corresponding preset indicator constraints: If all preset indicator constraints are met, the chip comprehensive performance indicator is calculated according to each of the chip performance indicators, and the chip comprehensive performance indicator is evaluated; Otherwise, it is determined that the adjusted chip layout does not meet the preset optimization goal.
5. The chip design layout optimization method according to claim 1, It is characterized in that The process of calculating the chip comprehensive performance index according to each of the chip performance indexes includes: By formula; Calculate the comprehensive performance index Z of the j-th optimized chip j ; Where n is the number of chip performance indicators, i∈[1,n]; α i is the weight coefficient of the i-th chip performance indicator, β i is the application coefficient of the i-th chip performance indicator, and g is the comprehensive performance indicator conversion function.
6. The chip design layout optimization method according to claim 5, It is characterized in that The process of evaluating the comprehensive performance indicators of the chip includes: The j-th optimized chip comprehensive performance index Z j And the preset comprehensive performance index constraints [Z 1 , Z 2 ] for comparison: If Z j ∈[Z 1 , Z 2 ], it is judged that the adjusted chip layout meets the preset optimization goal; Otherwise, it is determined that the adjusted chip layout does not meet the preset optimization goal.
7. The chip design layout optimization method according to claim 6, It is characterized in that The process of adjusting the parameters of the chip design layout optimization model according to the evaluation results includes: If there are items in the chip performance indicators that do not meet the preset indicator constraints, the formula is: Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 , and then input the adjusted chip into the chip design layout optimization model again until the evaluation result meets the preset optimization target; Wherein, m is the number of items in the chip performance index that do not meet the preset index constraint conditions, r∈[1,m]; γ r is the weight coefficient of the chip performance index of the rth item that does not meet the preset index constraint condition, Δδ r is the difference between the chip performance index of the rth item that does not meet the preset index constraint and the preset index constraint, Δδ r0 is the preset standard deviation between the chip performance index of the rth item that does not meet the preset index constraint and the preset index constraint, y 1 is the first indicator model parameter influence function.
8. The chip design layout optimization method according to claim 7, It is characterized in that The process of adjusting the parameters of the chip design layout optimization model according to the evaluation results also includes: If all the chip performance indicators meet the preset indicator constraints but the chip comprehensive performance indicators do not meet the preset comprehensive performance indicator constraints, the formula is: Calculate the parameter adjustment coefficient X of the j+1th optimization of the chip design layout optimization model j+1 , and then input the adjusted chip into the chip design layout optimization model again until the evaluation result meets the preset optimization target; Among them, ΔZ j is the comprehensive performance index Z of the chip optimized for the jth time j The difference between the preset comprehensive performance index constraint condition, ΔZ j0 is the comprehensive performance index Z of the chip optimized for the jth time j The preset standard deviation value of the preset comprehensive performance index constraint condition, y 2 is the influence function of the second indicator model parameter.