Double-injection avalanche transistor and preparation method thereof

Abstract

The invention provides a double-injection avalanche transistor and a preparation method thereof, which can solve the problems that the conduction voltage drop and loss of the existing avalanche transistor are relatively high because the existing avalanche transistor needs to maintain a high field intensity collision ionization region, and the performance of the existing avalanche transistor is influenced by temperature rise caused by conduction loss under repetition frequency operation. The transistor comprises a collector region n + substrate layer, a collector region n0 epitaxial layer, a p-type base region layer, an n + emitter region layer, a plurality of p + field rings and a collector region p + injection layer arranged between the collector region n + substrate layer and the collector region n0 epitaxial layer, a plurality of first ring grooves are formed in the top of the collector region n0 epitaxial layer, the p + field rings are arranged in the first ring grooves, and the tops of the p + field rings are flush with the top of the collector region n0 epitaxial layer. The p + doping concentration of the collector region p + injection layer is greater than the n + doping concentration of the collector region n + substrate layer, the n + doping concentration of the n + emitter region layer is greater than the p-type doping concentration of the p-type base region layer, and the n + doping concentration of the n + emitter region layer and the p + doping concentration of the p + field ring are the same order of magnitude as the n + doping concentration of the collector region n + substrate layer.

Description

Technical Field

[0001] The invention relates to a transistor, in particular to a double-injection avalanche transistor and a preparation method thereof. Background Art

[0002] High repetition rate ultra-fast semiconductor switches are the core devices for generating high repetition rate ultra-wide spectrum pulses, and determine the performance level of high repetition rate ultra-wide spectrum systems. Ultra-wide spectrum pulse sources based on solid-state pulse power devices have the characteristics of high repetition rate, compact size, light weight, and high reliability, so they can be modularized, miniaturized, and arrayed. Compared with gas switches, semiconductor switches can provide higher operating frequencies, higher stability, higher controllability, and smaller size.

[0003] At present, the following semiconductor switch devices are mainly used in the construction of solid-state high repetition rate ultra-wide spectrum pulse sources: drift step recovery diode (DSRD), silicon avalanche steepening switch (SAS), photoconductive switch (PCSS), fast discharge switch (FID), avalanche transistor switch (ABJT). Among them, when the avalanche transistor switch is used to construct the Marx circuit, the output pulse front reaches hundreds of picoseconds, the repetition frequency is more than hundreds of kilohertz, and it is easy to modularize and array synthesis. Therefore, the avalanche transistor switch is currently the preferred choice for the construction of solid-state high repetition rate ultra-wide spectrum pulse sources.

[0004] The structure of traditional avalanche transistors is mostly NPN type, and its conduction process is that the electrons injected into the emitter region are collided and ionized in the collector region, thereby generating electron-hole plasma. During the conduction process, the avalanche transistor needs to maintain a high field strength collision ionization zone, resulting in high conduction voltage drop and conduction loss. The temperature rise caused by the conduction loss under repetitive operation causes the performance of the avalanche transistor to degrade or even fail, which seriously limits the repetitive frequency increase and performance improvement of the avalanche transistor. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problems that the existing avalanche transistor needs to maintain a high field strength collision ionization zone during the conduction process, resulting in high conduction voltage drop and conduction loss, and the temperature rise caused by the conduction loss under heavy frequency operation causes the avalanche transistor performance to degrade or even fail, and to provide a double injection avalanche transistor and a preparation method thereof.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] A double injection avalanche transistor comprises a collector region electrode, a collector region n arranged in sequence from bottom to top + Substrate layer, collector region n0 epitaxial layer, and p-type base layer, n +The emitter layer, the ring-shaped base electrode, and the plate-shaped emitter electrode; a first cavity is provided at the top middle position of the collector region n0 epitaxial layer, the p-type base layer is a plate layer structure with a second cavity, and the p-type base layer is arranged in the first cavity; the n + The emission region layer is arranged in the second cavity, n + The tops of the emitter layer and the p-type base layer are flush with the top of the collector region n0 epitaxial layer; the base electrode is arranged on the top of the p-type base layer; the emitter electrode is arranged on the n + The top of the emitter layer; it is special in that:

[0008] It also includes the collector region p + injection layer and multiple p + Field ring;

[0009] The collector region p + The injection layer is set in the collector region n + Between the substrate layer and the collector region n0 epitaxial layer;

[0010] The top of the collector region n0 epitaxial layer is located outside the p-type base layer and is coaxially provided with a plurality of first annular grooves. + The field rings are respectively arranged in a plurality of first ring grooves, and the p + The top of the field ring is flush with the top of the n0 epitaxial layer in the collector region;

[0011] The collector region p + The p of the injection layer + The doping concentration is greater than the collector region n + n of the substrate layer + doping concentration; the n0 doping concentration of the collector region n0 epitaxial layer is less than the collector region n + n of the substrate layer + doping concentration; the p-type doping concentration of the p-type base layer is greater than the n0 doping concentration of the collector region n0 epitaxial layer and less than the collector region n + n of the substrate layer + Doping concentration; the n + n of the emitter layer + The doping concentration is greater than the p-type doping concentration of the p-type base layer; + n of the emitter layer + Doping concentration and p + Field ring p + The doping concentration is related to the collector region n + n of the substrate layer + The doping concentration is of the same order of magnitude.

[0012] Furthermore, the collector region p + There is an n layer between the injection layer and the collector region n0 epitaxial layer. +Epitaxial layer;

[0013] The + The n of the epitaxial layer + Doping concentration and collector region p + The p of the injection layer + The doping concentration is of the same order of magnitude; the n + The thickness of the epitaxial layer is smaller than the collector region p + The thickness of the implanted layer.

[0014] Furthermore, the collector region p + The injection layer consists of multiple discrete ring-shaped + The injection region is composed of a plurality of second annular grooves coaxially arranged on the top of the collector region n+ substrate layer, a plurality of discrete annular p+ injection regions are respectively arranged in the plurality of second annular grooves, and the top of the collector region p+ injection layer is flush with the top of the collector region n+ substrate layer.

[0015] Furthermore, the collector region n + n of the substrate layer + Doping concentration, n + n of the emitter layer + Doping concentration and p + Field ring p + The doping concentration is 1×10 19 cm -3 ~9×10 19 cm -3 The collector region p + The p of the injection layer + The doping concentration is the collector region n + Substrate layer + The doping concentration of n0 in the collector region n0 epitaxial layer is 2 to 10 times of that in the collector region n0 epitaxial layer. 14 cm -3 ~9×10 14 cm -3 The p-type doping concentration of the p-type base layer is 1×10 17 cm -3 ~9×10 17 cm -3 .

[0016] Furthermore, the width of the base electrode is smaller than the width of the top of the p-type base layer; the width of the emitter electrode is smaller than the width of the n-type base layer. + The width of the emitter layer.

[0017] Furthermore, the base electrode, emitter electrode, and collector electrode are all made of metal; + The substrate layer is made of silicon wafer.

[0018] The present invention also provides a method for preparing the above-mentioned dual injection avalanche transistor, which is special in that it comprises the following steps:

[0019] Step 1: Select a collector region n whose doping element is an n-type doping element. + Substrate layer; in collector region n + P-type doping ions are injected into the substrate layer to form a collector region p + injection layer; the collector region p + The p of the injection layer + The doping concentration is greater than the collector region n + n of the substrate layer + Doping concentration;

[0020] Step 2: Using epitaxial process, in the collector region p + The collector region n0 epitaxial layer is prepared on the top of the injection layer; the doping element of the collector region n0 epitaxial layer is an n-type doping element, and the n0 doping concentration is less than the collector region n + n of the substrate layer + Doping concentration;

[0021] Step 3: Inject p-type doping ions into the collector region n0 epitaxial layer prepared in step 2 by mask implantation to sequentially form a p-type base layer, a plurality of p-type base layers located outside the p-type base layer and coaxially. + Field ring; p-type base layer and p + The top of the field ring is flush with the top of the n0 epitaxial layer in the collector region;

[0022] The p-type doping concentration of the p-type base layer is greater than the n0 doping concentration of the collector region n0 epitaxial layer and less than the collector region n0 epitaxial layer. + n of the substrate layer + Doping concentration; the p + Field ring p + Doping concentration and collector region n + n of the substrate layer + The doping concentration is of the same order of magnitude;

[0023] Step 4: Inject n-type doping ions into the p-type base layer formed in step 3 by mask implantation to form n + Emission zone layer; said n + The top of the emitter layer is flush with the top of the collector region n0 epitaxial layer; + n of the emitter layer + Doping concentration and collector region n + n of the substrate layer + The doping concentration is of the same order of magnitude;

[0024] Step 5: Prepare an electrode layer on the top of the collector region n0 epitaxial layer prepared in step 2, and use a mask to etch to form a ring-shaped emitter region electrode located on the top of the p-type base layer. + Plate-shaped base electrode on top of the emitter layer; thinned collector region n + The bottom of the substrate layer until the preset thickness is met;

[0025] Step 6: After thinning, the collector region n + A collector region electrode is prepared at the bottom of the substrate layer, and the substrate is sliced ​​to obtain separated double-injection avalanche transistors.

[0026] Furthermore, step 2 also includes the step of preparing an n+ epitaxial layer;

[0027] Step 2 is as follows:

[0028] Using epitaxial process, in the collector region p + The top of the injection layer is prepared from bottom to top + epitaxial layer, collector region n0 epitaxial layer; the n + The doping element of the epitaxial layer is an n-type doping element. + Doping concentration and collector region p + The p of the injection layer + The doping concentration is of the same order of magnitude, and its thickness is smaller than that of the collector region p + The thickness of the injection layer; the doping element of the collector region n0 epitaxial layer is an n-type doping element, and the n0 doping concentration is less than the collector region n + n of the substrate layer + Doping concentration.

[0029] Further, step 1 is specifically: selecting a collector region n whose doping element is an n-type doping element + Substrate layer; through mask injection, in the collector region n + P-type doping ions are injected into the interior of the substrate layer to form multiple discrete ring-shaped p + injection region; the annular p + The top of the injection region and the collector region n + The top of the substrate layer is flush with the + The doping concentration is greater than the collector region n + n of the substrate layer + Doping concentration.

[0030] Furthermore, in step 1 and step 2, the n-type doping element is arsenic;

[0031] In step 1 and step 3, the p-type doping ions are boron ions;

[0032] In step 4, the n-type doping ions are arsenic ions;

[0033] In step 5, an electrode layer is prepared on top of the collector region n0 epitaxial layer prepared in step 2 by using a metallization process;

[0034] In step 6, a metallization process is used to thin the collector region n + The collector region electrode is prepared at the bottom of the substrate layer.

[0035] Beneficial effects of the present invention:

[0036] 1. The present invention provides a double-injection avalanche transistor and a method for preparing the same, wherein in the collector region n + A collector region p+ injection layer is added between the substrate layer and the collector region n0 epitaxial layer to form a hole injection region. Compared with the traditional avalanche transistor, which needs to rely on the electron-hole plasma generated by electron impact ionization after being turned on to maintain the low-field strength quasi-neutral region, the avalanche transistor of the present invention relies on the added hole injection region to provide holes after being turned on, and maintains the low-field strength quasi-neutral region together with the electrons provided by the emission region. Therefore, the high electric field distribution in the collector region can be effectively reduced, thereby reducing the on-state voltage of the transistor (i.e., the on-state voltage drop is low), reducing switching losses, improving the problem of large temperature rise under heavy frequency operation, and improving the working reliability of the transistor. The hole injection region can also provide more initial holes for impact ionization during the conduction process of the avalanche transistor, thereby accelerating the conduction speed of the avalanche transistor.

[0037] 2. In the present invention, the collector region p + n is set between the injection layer and the collector region n0 epitaxial layer + The epitaxial layer can increase the operating voltage of the double-injection avalanche transistor.

[0038] 3. In the present invention, the discrete annular p + The implanted region can increase the operating voltage of the double-injection avalanche transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic cross-sectional view of a double-injection avalanche transistor in Embodiment 1 of the present invention;

[0040] Figure 2 is a schematic cross-sectional view of a double-injection avalanche transistor in Embodiment 2 of the present invention;

[0041] Figure 3 is a schematic cross-sectional view of a double-injection avalanche transistor in Embodiment 3 of the present invention;

[0042] Figure 4 1 is an example diagram of a conduction performance test application circuit of a double-injection avalanche transistor embodiment of the present invention;

[0043] Figure 5 is an output pulse curve diagram of the double injection avalanche transistor in the third embodiment of the present invention and the traditional avalanche transistor;

[0044] Figure 6 is a graph of conduction characteristics of a double-injection avalanche transistor in Embodiment 3 of the present invention and a conventional avalanche transistor;

[0045] Figure 7 is a switching power consumption curve diagram of the double-injection avalanche transistor in the third embodiment of the present invention and the traditional avalanche transistor;

[0046] Figure 8 is a switching energy loss curve diagram of the double-injection avalanche transistor in the third embodiment of the present invention and the traditional avalanche transistor;

[0047] Fig. 9 It is a device temperature rise curve diagram of the double injection avalanche transistor in the third embodiment of the present invention and the traditional avalanche transistor.

[0048] Description of reference numerals:

[0049] 1-Collector area n + Substrate layer, 2-collector region p + Injection layer, 20-ring p + Injection region, 3- collector region n0 epitaxial layer, 4- p-type base layer, 5-n + Emitting layer, 6-p + Field ring, 7-base electrode, 8-emitter electrode, 9-collector electrode, 10-n + Epitaxial layer. DETAILED DESCRIPTION

[0050] Embodiment 1

[0051] like Figure 1 As shown, a double injection avalanche transistor includes a collector region electrode 9, a collector region n arranged in sequence from bottom to top. + Substrate layer 1, collector region n0 epitaxial layer 3, p-type base layer 4, n + The emitter layer 5, the ring-shaped base electrode 7, the plate-shaped emitter electrode 8, the collector region p + Injection layer 2 and three p + Field ring 6. Specifically, a first cavity is provided at the top middle position of the collector region n0 epitaxial layer 3, and the p-type base layer 4 is a plate layer structure with a second cavity. The p-type base layer 4 is provided in the first cavity of the collector region n0 epitaxial layer 3. + The emitter layer 5 is arranged in the second cavity. + The tops of the emitter layer 5 and the p-type base layer 4 are flush with the top of the collector region n0 epitaxial layer 3. The base electrode 7 is arranged on the top of the p-type base layer 4, and the width of the base electrode 7 is smaller than the width of the top of the p-type base layer 4. The emitter electrode 8 is arranged on the n + The top of the emitter layer 5, the width of the emitter electrode 8 is less than n+ The width of the emitter layer 5. The collector region p + The injection layer 2 is arranged in the collector region n + The top of the collector region n0 epitaxial layer 3 is located outside the p-type base layer 4 and is coaxially provided with three first annular grooves. + The field rings 6 are respectively arranged in the three first ring grooves of the collector region n0 epitaxial layer 3. + The top of the field ring 6 is flush with the top of the collector region n0 epitaxial layer 3. In this embodiment, the base region electrode 7, the emitter region electrode 8, and the collector region electrode 9 are all made of metal; + The substrate layer 1 is made of silicon wafer; the collector region n + Substrate layer 1 n + doping concentration, n+ emitter layer 5 + Doping concentration and p + Field ring 6 p + The doping concentration is 1×10 19 cm -3 ; Collector region p + The p-type of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1n + The doping concentration of n0 in the collector region n0 epitaxial layer 3 is 1×10 14 cm -3 ; The p-type doping concentration of the p-type base layer 4 is 1×10 17 cm -3 .

[0052] This embodiment also provides a method for preparing the above-mentioned dual injection avalanche transistor, comprising the following steps:

[0053] Step 1: Select arsenic as the doping element, n + The doping concentration is 1×10 19 cm -3 The silicon wafer is used as the collector region n + Substrate layer 1; in collector region n + Boron ions are implanted into the substrate layer 1 to form a collector region p + Injection layer 2; collector region p + The p-type of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1n + The doping concentration is twice that of the previous step, and the implantation thickness is about 1μm to 3μm.

[0054] Step 2: Using an epitaxial process, prepare a collector region n0 epitaxial layer 3 on top of the collector region p+ injection layer 2; the doping element of the collector region n0 epitaxial layer 3 is arsenic, and the n0 doping concentration is 1×1014 cm -3 , and its thickness is about 20μm~25μm.

[0055] Step 3: Inject boron ions into the collector region n0 epitaxial layer 3 prepared in step 2 by mask implantation to sequentially form a p-type base layer 4, three p-type base layers 4 located outside the p-type base layer 4 and coaxially connected to the collector region n0 epitaxial layer 3, and a p-type base layer 4 formed by mask implantation. + Field ring 6; p-type base layer 4 and p + The top of the field ring 6 is flush with the top of the collector region n0 epitaxial layer 3;

[0056] The side length of the p-type base layer 4 is about 260 μm, the depth is about 5 μm, and the p-type doping concentration is 1×10 17 cm -3 ;p + Field ring 6 p + The doping concentration is 1×10 19 cm -3 ; Each p + The width of the field ring 6 is about 10 μm, the depth is about 5 μm, and the adjacent p + The interval between the field rings 6 is about 10 μm, and the p-type base layer 4 and the p-type base layer near the p-type base layer 4 are + The spacing between the field rings 6 is about 10 μm.

[0057] Step 4: By means of mask implantation, arsenic ions are implanted into the p-type base layer 4 formed in step 3 to form an n-type base layer. + Emitting layer 5; n + The top of the emitter layer 5 is flush with the top of the collector region n0 epitaxial layer 3; + The side length of the emitter layer 5 is about 170 μm, the depth is about 2 μm, and n + The doping concentration is 1×10 19 cm -3 .

[0058] Step 5: Using a metallization process, an electrode layer is prepared on the top of the collector region n0 epitaxial layer 3 prepared in step 2, and a ring-shaped emitter region electrode 7 is formed on the top of the p-type base region layer 4 through mask etching. + The plate-shaped base electrode 8 on the top of the emitter layer 5; the thinned collector region n + The bottom of the substrate layer 1, until the top of the collector region n0 epitaxial layer 3 to the collector region n + The thickness of the substrate layer 1 between the bottoms is 150 μm to 250 μm.

[0059] Step 6: Use metallization process to thin the collector area n + The collector region electrode 9 is prepared at the bottom of the substrate layer 1 and sliced ​​to obtain separated double-injection avalanche transistors with a size of 620 μm×620 μm.

[0060] Embodiment 2

[0061] like Figure 2 As shown, the structure of the double injection avalanche transistor in this embodiment is similar to that of the double injection avalanche transistor in the first embodiment, except that:

[0062] Collector region p + There is also an n layer between the injection layer 2 and the collector region n0 epitaxial layer 3. + Epitaxial layer 10, n + The n of epitaxial layer 10 + The doping concentration is the collector region n + Substrate layer 1n + 10 times the doping concentration, n + The thickness of the epitaxial layer 10 is smaller than that of the collector region p + The thickness of the injection layer 2, n + The thickness of the epitaxial layer 10 is 0.9 μm. + Substrate layer 1 n + doping concentration, n+ emitter layer 5 + Doping concentration and p + Field ring 6 p + The doping concentration is 9×10 19 cm -3 ; Collector region p + The p-type of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1n + The doping concentration of n0 in the collector region n0 epitaxial layer 3 is 9×10 14 cm -3 ; The p-type doping concentration of the p-type base layer 4 is 9×10 17 cm -3 .

[0063] The steps of the preparation method of the double injection avalanche transistor in this embodiment are similar to those of the double injection avalanche transistor in the first embodiment, except that:

[0064] In step 1, the doping element is arsenic, n + The doping concentration is 9×10 19 cm -3 The silicon wafer is used as the collector region n + Substrate layer 1; collector region p + The p-type of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1n + 10 times the doping concentration.

[0065] Step 2 is as follows: using an epitaxial process, n + Epitaxial layer 10, collector region n0 epitaxial layer 3; n + The doping element of the epitaxial layer 10 is arsenic, n + The doping concentration is the collector region n + Substrate layer 1n + The doping concentration is 10 times that of the collector region, and its thickness is less than that of the collector region p + The thickness of the injection layer 2 is 0.9 μm; the doping element of the collector region n0 epitaxial layer 3 is arsenic, and the n0 doping concentration is 9×10 14 cm -3 , and its thickness is about 20μm~25μm.

[0066] In step 3, the p-type doping concentration of the p-type base layer 4 is 9×10 17 cm -3 ;p + Field ring 6 p + The doping concentration is 9×10 19 cm -3 .

[0067] In step 4, the n+ emitter layer 5 has n + The doping concentration is 9×10 19 cm -3 .

[0068] Embodiment 3

[0069] like Figure 3 As shown, the structure of the double injection avalanche transistor in this embodiment is similar to that of the double injection avalanche transistor in the first embodiment, except that:

[0070] Collector region p + The injection layer 2 consists of four discrete ring-shaped + The top of the collector region n+ substrate layer 1 is coaxially provided with four second annular grooves, and four discrete annular p+ injection regions 20 are respectively arranged in the four second annular grooves, and the top of the collector region p+ injection layer 2 is flush with the top of the collector region n+ substrate layer 1. + Substrate layer 1 n + doping concentration, n+ emitter layer 5 + Doping concentration and p + Field ring 6 p + The doping concentration is 5×10 19 cm -3 ; Ring p + The p-type of the implanted region 20 + The doping concentration is the collector region n + Substrate layer 1n +5 times the doping concentration; the n0 doping concentration of the collector region n0 epitaxial layer 3 is 5×10 14 cm -3 ; The p-type doping concentration of the p-type base layer 4 is 5×10 17 cm -3 .

[0071] This embodiment also provides a method for preparing the above-mentioned dual injection avalanche transistor, which is characterized by comprising the following steps:

[0072] Step 1: Select arsenic as the doping element, n + The doping concentration is 5×10 19 cm -3 The silicon wafer is used as the collector region n + Substrate layer 1; through mask injection, in the collector region n + Boron ions are implanted into the interior of the substrate layer 1 to form four discrete and coaxial annular p + Implantation region 20; annular p + The top of the injection region 20 and the collector region n + The top of the substrate layer 1 is flush with the + The doping concentration is the collector region n + Substrate layer 1n + 5 times the doping concentration, the implant thickness is about 1μm to 3μm, and each ring p + The width of the implantation region 20 and the width of the two adjacent ring-shaped regions p + The intervals between the implanted regions 20 are all about 15 μm.

[0073] Step 2: Using an epitaxial process, prepare a collector region n0 epitaxial layer 3 on top of the collector region p+ injection layer 2; the doping element of the collector region n0 epitaxial layer 3 is arsenic, and the n0 doping concentration is 5×10 14 cm -3 , and its thickness is about 20μm~25μm.

[0074] Step 3: Inject boron ions into the collector region n0 epitaxial layer 3 prepared in step 2 by mask implantation to sequentially form a p-type base layer 4, three p-type base layers 4 located outside the p-type base layer 4 and coaxially connected to the collector region n0 epitaxial layer 3, and a p-type base layer 4 formed by mask implantation. + Field ring 6; p-type base layer 4 and p + The top of the field ring 6 is flush with the top of the collector region n0 epitaxial layer 3;

[0075] The side length of the p-type base layer 4 is about 260 μm, the depth is about 5 μm, and the p-type doping concentration is 5×10 17 cm -3 ;p + Field ring 6 p + The doping concentration is 5×10 19 cm -3; Each p + The width of the field ring 6 is about 10 μm, the depth is about 5 μm, and the adjacent p + The interval between the field rings 6 is about 10 μm, and the p-type base layer 4 and the p-type base layer near the p-type base layer 4 are + The spacing between the field rings 6 is about 10 μm.

[0076] Step 4: By means of mask implantation, arsenic ions are implanted into the p-type base layer 4 formed in step 3 to form an n-type base layer. + Emitting layer 5; n + The top of the emitter layer 5 is the top of the collector region n0 epitaxial layer 3; the side length of the n+ emitter layer 5 is about 170 μm, the depth is about 2 μm, and the n + The doping concentration is 5×10 19 cm -3 .

[0077] Step 5: Using a metallization process, an electrode layer is prepared on the top of the collector region n0 epitaxial layer 3 prepared in step 2, and a ring-shaped emitter region electrode 7 is formed on the top of the p-type base region layer 4 through mask etching. + The plate-shaped base electrode 8 on the top of the emitter layer 5; the thinned collector region n + The bottom of the substrate layer 1, until the top of the collector region n0 epitaxial layer 3 to the collector region n + The thickness of the substrate layer 1 between the bottoms is 150 μm to 250 μm.

[0078] Step 6: Use metallization process to thin the collector area n + The collector region electrode 9 is prepared at the bottom of the substrate layer 1 and diced to obtain separated double-injection avalanche transistors with a size of 620 μm×620 μm.

[0079] In order to verify that the double-injection avalanche transistor provided in this embodiment can achieve the effect of reducing conduction loss and accelerating conduction speed, the double-injection avalanche transistor device of this embodiment is simulated and analyzed using TCAD simulation software. Figure 4The application circuit shown includes a DC bias voltage source Vcc, an energy storage capacitor C0, a charging isolation resistor Rc, a discharge load transmission line TL3, a dual-injection avalanche transistor T1 of this embodiment, an emitter voltage divider resistor Re, a trigger pulse feeding transmission line TL1, and an emitter voltage measurement transmission line TL2, wherein the base and emitter of the avalanche transistor T1 are configured to be short-circuited. Using the capacitor energy storage method, the DC bias voltage source Vcc applies a voltage to the dual-injection avalanche transistor T1 through the charging isolation resistor Rc, and the energy storage capacitor C0, the dual-injection avalanche transistor T1, the emitter voltage divider resistor Re and the discharge load transmission line TL3 form a discharge loop. When a negative polarity pulse is applied to the base-emitter terminal through TL1, the dual-injection avalanche transistor T1 is turned on and outputs a pulse to the discharge load transmission line TL3, and the voltage is u L ,u e is the emitter voltage after the emitter voltage divider resistor Re is measured by u e The on-state voltage drop, switching power consumption and energy loss of the double-injection avalanche transistor T1 can be calculated.

[0080] Figure 5 The output pulse curves of the double-injection avalanche transistor of the embodiment of the present invention and the traditional avalanche transistor are shown in FIG. 1 , wherein curve T1 is the output pulse curve of the double-injection avalanche transistor provided in the embodiment, and curve T2 is the output pulse curve of the traditional avalanche transistor, which serves as a control group. It can be seen from curves T1 and T2 in the figure that the double-injection avalanche transistor provided in the embodiment is substantially the same as the traditional avalanche transistor in terms of output pulse width and output pulse amplitude.

[0081] Figure 6 is a turn-on characteristic curve diagram of the double-injection avalanche transistor according to an embodiment of the present invention and a conventional avalanche transistor, wherein: Figure 6 The middle curve T1 is a turn-on characteristic curve of the double injection avalanche transistor provided in this embodiment. Figure 6 The middle curve T2 is the turn-on characteristic curve of the conventional avalanche transistor, serving as a control group. It can be seen from the curves T1 and T2 in the figure that the double-injection avalanche transistor provided by this embodiment has a faster turn-on speed than the conventional avalanche transistor and a lower conduction voltage drop after turn-on.

[0082] Figure 7 : is a switching power consumption curve diagram of the double-injection avalanche transistor according to an embodiment of the present invention and the traditional avalanche transistor, wherein: Figure 7 The middle curve T1 is a switching power consumption curve of the double injection avalanche transistor according to an embodiment of the present invention. Figure 7 The middle curve T2 is the switch power consumption curve of the traditional avalanche transistor, which is used as the control group. It can be seen from the curves T1 and T2 in the figure that the switch power consumption of the double injection avalanche transistor of the embodiment of the present invention is high before being turned on, but the switch power consumption and peak power consumption after being turned on are significantly reduced.

[0083] Figure 8 is a switching energy loss curve diagram of the double-injection avalanche transistor according to an embodiment of the present invention and a conventional avalanche transistor, wherein: Figure 8 The middle curve T1 is a switching energy loss curve of the double injection avalanche transistor according to an embodiment of the present invention. Figure 8 The middle curve T2 is the switching energy loss curve of the conventional avalanche transistor, which is used as the control group. It can be seen from the curves T1 and T2 in the figure that the switching energy loss of the double injection avalanche transistor of the embodiment of the present invention is significantly reduced.

[0084] Fig. 9 : is a device temperature rise curve diagram of the double injection avalanche transistor of the embodiment of the present invention and the traditional avalanche transistor, wherein: Fig. 9 The middle curve T1 is a device temperature rise curve of the double injection avalanche transistor according to an embodiment of the present invention. Fig. 9 The middle curve T2 is the device temperature rise curve of the traditional avalanche transistor, which is used as the control group. It can be seen from the curves T1 and T2 in the figure that the device temperature rise of the double injection avalanche transistor in the embodiment of the present invention is significantly reduced.

[0085] It should be noted that the relevant performance characterization diagrams of the dual-injection avalanche transistor in the first and second embodiments are similar to those in the third embodiment, and reference may be made to the relevant performance characterization diagrams of the dual-injection avalanche transistor in the third embodiment.

[0086] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A double-injection avalanche transistor, comprising a collector region electrode (9), a collector region n + Substrate layer (1), collector region n0 epitaxial layer (3), and p-type base layer (4), n + An emitter region layer (5), a ring-shaped base region electrode (7), and a plate-shaped emitter region electrode (8); a first cavity is provided at the top middle position of the collector region n0 epitaxial layer (3); the p-type base region layer (4) is a plate layer structure with a second cavity, and the p-type base region layer (4) is arranged in the first cavity; the n + The emission region layer (5) is arranged in the second cavity, + The tops of the emitter region layer (5) and the p-type base region layer (4) are both flush with the top of the collector region n0 epitaxial layer (3); the base region electrode (7) is arranged on the top of the p-type base region layer (4); the emitter region electrode (8) is arranged on the top of the n0 epitaxial layer (3) + The top of the emission region layer (5); characterized in that: It also includes the collector region p + injection layer (2) and multiple p + Field ring (6); The collector region p + The injection layer (2) is arranged in the collector region n + Between the substrate layer (1) and the collector region n0 epitaxial layer (3); The top of the collector region n0 epitaxial layer (3) is located outside the p-type base region layer (4) and is coaxially provided with a plurality of first annular grooves. + The field rings (6) are respectively arranged in a plurality of first ring grooves, and the p + The top of the field ring (6) is flush with the top of the collector region n0 epitaxial layer (3); The collector region p + The p of the injection layer (2) + The doping concentration is greater than the collector region n + The substrate layer (1) + doping concentration; the n0 doping concentration of the collector region n0 epitaxial layer (3) is less than the collector region n + The substrate layer (1) + doping concentration; the p-type doping concentration of the p-type base layer (4) is greater than the n0 doping concentration of the collector region n0 epitaxial layer (3) and less than the collector region n0 doping concentration. + The substrate layer (1) + Doping concentration; the n + The n of the emitter layer (5) + The doping concentration is greater than the p-type doping concentration of the p-type base layer (4); the n + The n of the emitter layer (5) + Doping concentration and p + Field ring (6) p + The doping concentration is related to the collector region n + The substrate layer (1) + The doping concentration is of the same order of magnitude.

2. The dual injection avalanche transistor according to claim 1, characterized in that: The collector region p + An n is provided between the injection layer (2) and the collector region n0 epitaxial layer (3) + Epitaxial layer (10); The + The epitaxial layer (10) has n + Doping concentration and collector region p + The p of the injection layer (2) + The doping concentration is of the same order of magnitude; the n + The thickness of the epitaxial layer (10) is smaller than the collector region p + The thickness of the injection layer (2).

3. The dual injection avalanche transistor according to claim 1, characterized in that: The collector region p + The injection layer (2) consists of a plurality of discrete ring-shaped p + The injection region (20) is composed of the collector region n + The top of the substrate layer (1) is coaxially provided with a plurality of second annular grooves, a plurality of discrete annular grooves, and a plurality of + The injection regions (20) are respectively arranged in a plurality of second annular grooves, and the collector region p + The top of the injection layer (2) and the collector region n + The top of the substrate layer (1) is flush.

4. The double injection avalanche transistor according to claim 1, 2 or 3, characterized in that: The collector region n + The substrate layer (1) + Doping concentration, n + The n of the emitter layer (5) + Doping concentration and p + Field ring (6) p + The doping concentration is 1×10 19 cm -3 ~9×10 19 cm -3 The collector region p + The p of the injection layer (2) + The doping concentration is the collector region n + Substrate layer (1)n + The n0 doping concentration of the collector region n0 epitaxial layer (3) is 2 to 10 times of the doping concentration; the n0 doping concentration of the collector region n0 epitaxial layer (3) is 1×10 14 cm -3 ~9×10 14 cm -3 The p-type doping concentration of the p-type base layer (4) is 1×10 17 cm -3 ~9×10 17 cm -3 .

5. The double injection avalanche transistor according to claim 4, characterized in that: The width of the base region electrode (7) is smaller than the width of the top of the p-type base region layer (4); the width of the emitter region electrode (8) is smaller than the width of the n-type base region layer (4). + The width of the emission region layer (5).

6. The double-injection avalanche transistor according to claim 5, characterized in that: The base region electrode (7), the emitter region electrode (8), and the collector region electrode (9) are all made of metal; the collector region electrode n + The substrate layer (1) is made of silicon wafer material.

7. A method for preparing a dual-injection avalanche transistor according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1: Select a collector region n whose doping element is an n-type doping element. + Substrate layer (1); in collector region n + P-type doping ions are implanted into the interior of the substrate layer (1) to form a collector region p + injection layer (2); the collector region p + The p of the injection layer (2) + The doping concentration is greater than the collector region n + The substrate layer (1) + Doping concentration; Step 2: Using epitaxial process, in the collector region p + A collector region n0 epitaxial layer (3) is prepared on the top of the injection layer (2); the doping element of the collector region n0 epitaxial layer (3) is an n-type doping element, and the n0 doping concentration is less than the collector region n + The substrate layer (1) + Doping concentration; Step 3: Inject p-type doping ions into the collector region n0 epitaxial layer (3) prepared in step 2 by mask implantation to sequentially form a p-type base layer (4), a plurality of p-type base layers (4) located outside the p-type base layer (4) and coaxially connected to the p-type epitaxial layer (3). + Field ring (6); p-type base layer (4) and p + The top of the field ring (6) is flush with the top of the collector region n0 epitaxial layer (3); The p-type doping concentration of the p-type base layer (4) is greater than the n0 doping concentration of the collector region n0 epitaxial layer (3) and less than the n0 doping concentration of the collector region n0. + The substrate layer (1) + Doping concentration; the p + Field ring (6) p + Doping concentration and collector region n + The substrate layer (1) + The doping concentration is of the same order of magnitude; Step 4: Inject n-type doping ions into the p-type base layer (4) formed in step 3 by mask implantation to form n-type doping ions. + The emission region layer (5); the n + The top of the emitter region layer (5) is flush with the top of the collector region n0 epitaxial layer (3); + The n of the emitter layer (5) + Doping concentration and collector region n + The substrate layer (1) + The doping concentration is of the same order of magnitude; Step 5: Prepare an electrode layer on the top of the collector region n0 epitaxial layer (3) prepared in step 2, and use a mask to etch to form a ring-shaped emitter region electrode (7) located on the top of the p-type base region layer (4). + A plate-shaped base electrode (8) on the top of the emitter layer (5); a thinned collector region n + The bottom of the substrate layer (1) is formed until a preset thickness is met; Step 6: After thinning, the collector region n + A collector region electrode (9) is prepared at the bottom of the substrate layer (1), and the layer is sliced ​​to obtain a separated double-injection avalanche transistor.

8. The method for preparing a dual injection avalanche transistor according to claim 7, characterized in that: Step 2 also includes preparing n + The step of epitaxial layer (10); Step 2 is as follows: Using epitaxial process, in the collector region p + The top of the injection layer (2) is prepared from bottom to top + epitaxial layer (10), collector region n0 epitaxial layer (3); the n + The doping element of the epitaxial layer (10) is an n-type doping element. + Doping concentration and collector region p + The p of the injection layer (2) + The doping concentration is of the same order of magnitude, and its thickness is smaller than that of the collector region p + The thickness of the injection layer (2); the doping element of the collector region n0 epitaxial layer (3) is an n-type doping element, and the n0 doping concentration is less than the collector region n + The substrate layer (1) + Doping concentration.

9. The method for preparing a dual-injection avalanche transistor according to claim 7, characterized in that: Step 1 is as follows: The collector region n is selected to have an n-type doping element. + Substrate layer (1); by mask implantation, in collector region n + P-type doping ions are implanted into the interior of the substrate layer (1) to form a plurality of discrete annular p + injection region (20); the annular + The top of the injection region (20) and the collector region n + The top of the substrate layer (1) is flush with the + The doping concentration is greater than the collector region n + The substrate layer (1) + Doping concentration.

10. The method for preparing a dual injection avalanche transistor according to claim 8 or 9, characterized in that: In step 1 and step 2, the n-type doping element is arsenic; In step 1 and step 3, the p-type doping ions are boron ions; In step 4, the n-type doping ions are arsenic ions; In step 5, a metallization process is used to prepare an electrode layer on top of the collector region n0 epitaxial layer (3) prepared in step 2; In step 6, a metallization process is used to thin the collector region n + A collector region electrode (9) is prepared at the bottom of the substrate layer (1).

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